component counts. A prototype 0148V to 0.9V/50A VRM is built Fig. 1. LLC Resonant Converterfor48Vto0.9V VRM
to verify the result. in a larger load range. Nevertheless resonant converters needs
variablefrequency control, which cause difficulty to the
1. INTRODUCTION converter design such as gating of synchronous rectifier and
The computer industry has been quickly expanding for the power factor for tbe resonant loop, and the switching
last decade. The speed and integration density of frequency range of tb: convener.
microprocessors have increased rapidly. Now the processor In this paper, DC characteristics of the converter is
works with clock frequencies in the 23 GHz range. The next analyzed and the operation stages are presented Method to
generation of processors will work with even higher clock reduce the power factor angle is explored due to its important
frequencies. As a result, modem microprocessors are being influence on the converter performance. Secondary side
designed to work with lower levels of voltage in order to meet leakage inductance impairs the converter efficiency and FEA
the increasingly high demands for speed and integration method is used to end the optimal transformer winding
density. Now the Intel Pentium * microprocessors run at the configuration with least secondary side leakage inductance.
voltage of 1.3V1.7V, in the future the voltage will be below
IV. The requirements for the microprocessors’ power 11. LLC R.ESONANT CONVERTER ANALYSIS
supplies such as Voltage Regulator Modules (VRM) [I] are A. Operation Stage8
more and more critical. The output voltage of the VRM we
designed here in the paper is 0 . 9 ~ . The diagram of L K Resonant Converter is shown in Fig. I.
Today’s VRMs are mainly pulse width modulation (PWM) L~xp,L b l , LM are the leakage inductance at primary and
converters, such as the multiphase interleaving synchronous secondary side respectively. Since leakage inductance exists
buck [2], the pushpull buck [3], and the pushpull forward in the secondary :ride, there is overlapping time of
topology [4]. Utilizing external resonant method during the commutation between switch SR1 and switch SR2. As a result,
switch’s transition period, they realize ZVS. To increase the secondary current isll and is= conducts longer than half
effective switching frequency and dynamics multiphase period. When the cclnverter is working at frequency higher
converter stmcture has been implemented. However the than series resonant frequency f,, the operation can be divided
complexity of these converters is increased. into five stages. The operation stages and the steady state
For further increasing the switching frequency and keeping waveform are shown in Fig2 and Fig3 respectively.
high efficiency of the converter, resonant convertem attract Stagel (totl):
people’s attention once more. LLC resonant converter has Before this stage, icurrent i, through the resonant inductor
been successfully applied in the front end DC/DC conversion flows through switch S2, current isnl flows through switch
in Distributed Power System ([5][6]).Here LLC resonant SRI. At time 10, culrent isn2 begins to rise, since the gate
converter is introduced to VRM, as shown in Figl. In LLC signal of SR2 is not applied, current ism ilows through the
resonant converter, ZVS is realized due to series resonance parallel diode of switch SR2. This stage ends when gate signal
principle for switches in the half bridge. In traditional of switch S2 is removed.
twoorder LC resonant converter, output voltage regulation Stage2 (tl12):
ability is lost at light load condition. Thresorder LLC At time t l , switch S2 and SRI are turned off, current isnl
resonant converter owns both the advantages of series and begins to flow through the parallel diode of switch SRI. Since
parallel resonant circuit, and can regulate the output voltage the resonant circuit operates at induction mode, current i, is
negative at this moment, current i, begins to charge the
A td
U
(a) Stagel (10.11)
VO
RI +
Vi"
Ls cs
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2W4 351h Ai!nual IEEE Power Electronics Specialisls Conjerence Aachen, Germany, 2004
G
a<
= .A = R,,Ilj.w.L, (2)
1
E,. j.o.L,,+ iR,,,ll j . w . Lp
j.w.C,
We can derive
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2004 35th Annual IEEE Power Eleclronics Specinlisls Conference Aachen, Gemany, 2004
The input voltage range of the LLC resonant converter is 111. POWER FACTOR ANGLE OF PRIMARY SIDE
36V to 72V, the output voltage is 0.9V. Therefore, the DC The halfbridge output voltage vaband current i, are shown
voltage gain Gdcshould between 0.0125 and 0.025. in Fig7. It is assumed that resonant current i, is sinusoidal. td is
Too large transformer turn ratio increases the transformer the dead time in the gate signals of the main switches in the
design and manufacture difficulty. However, if transformer halfbridge. V, and I, are the input voltage and the peak value
turn ratio is too small, the primary side current and conduction of primary current respectively. Current i, is lagging the
loss increases and efficiency is impaired. voltage vsb with phase angle * t The turnoff current and
From Fig5, when Q=lOO, the DC voltage gain Gdois higher turnoff loss can be reduced if * i s smaller. In addition, with
than 0.0125 even at the maximum switching frequency, and
the situation is the same when Q is below 100. Thus, quality
factor Q below 100 is not considered. At the condition of

fixed output power the amplitude of ip is reduced with the
decrease of .because reactive power is reduced. Thus the
primary side conduction loss is reduced too. However, if * i s
Q>100 and ~ 2 0the , maximum DC voltage gain can’t reach
0.025. Therefore, transformer turn ratio n>20 is discarded close to zero, ZVS condition of the main switch is lost.
too. To realize Z V S for the switches ofthe halfbridge inverter,
The larger Q is, the more sensitive is the DC voltage gain to one capacitor parallel to the one switch should he completely
the change of switching frequency for the DC voltage gain charged while the other capacitor paralleled to other switch
between the range of 0.0125 and 0.025. Small change in need to be discharged by resonant current i, during dead time
switching frequency will induce dramatic change in DC t,+ The following equation can be derived from (I),
voltage gain, which may cause the control instability of the
converter.
sin 4 2 2c, ’ v, (7)
k is also an important parameter in LLC resonant converter.
I, . t d
Larger k means smaller current through parallel inductor Lp Considering that only fundamental element of the half bridge
when voltage cross L, is fixed at rated output voltage inverter output voltage transfers active power, the input
condition. Thus loss on inductor Lp is reduced. However, if k Dower of the converter Pi. can be written as
is too large, the LLC resonant converter degenerates to
twoorder LC resonant circuit and loses output voltage
regulation ability at light load condition. Substitute (8) to (7). the following results can then be
The final design results are: n=13, Q=2500, k=5. Then the derived,
circuit parameters can be calculated as: L.=14uH, C,=7nF,
L,=70uH. When the circuit parameters are selected, the DC
voltage gain Gdcas function of switching frequency f can then
be described as Fig6, where Q=500 and 2500 corresponds to From (9), MOSFET with smaller C , is favorable for
the light load and full load condition respectively. From Fig6
reducing primary power factor angle while at the same time
we can see that the converter can satisfy the DC voltage gain
keeping Z V S condition of the main switch.
requirement.
IV. SECONDARY SIDE LEAKAGE INDUCTANCE
In LLC resonant converter for VRM, the SR MOSFET
employs selfdriven method ([7][9]), as shown in Fig8. The
secondary side waveform is shown in Fig9. The secondary
current waveform is approximate half sine wave. Since
leakage inductance exists in the secondary side, there is
overlapping time of commutation between switch SR1 and
switch S E . As a result, secondary current isnl and isru
conducts longer than half period. An overlapping period is
produced between current isnl and current isw, as shown in
‘,NI
Fig. 6. E€ Characteistic(n=13. k=5)
Fig9. Assuming current is transferred from switch SR1 to
switch SR2, at time tO switch SRI is turned off, secondary
current isnl flows through the parallel diode of switch SRI,
therefore the voltage drop on switch SRI is around 0.7V from
time tO to t 1. Actually the synchronous rectification doesn’t
work and loss is increased significantly during this period.
Fig10 shows the simulation results of current iSRI,isR2 and the
voltage drop on switch SRI. Fig1 1 gives the experimental
waveforms of current isRl,isnl and the voltage drop on switch
SR1, and the waveforms are compared with different
secondary side leakage inductance. When the leakage
Fig. 7. Pnmary Voltage and Pimary Curreot inductance is larger, the seconday side current overlapping
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2004 35111Annual IEEE Power Elecrronics Specialists Conference Aachen. Gemiany, 2004
to tl
Fig. 9. Waveform of the SR MOSFET
V. EXPERIMENTALRESULTS
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2004 35th Annual IEEE Power Electronics Specialists Conference Aochen, Germany, 2004
Secondary
winding 1
Secondary
winding 2
(a) SIruCtUrel
Secondary
minding 1
winding
winding m
Secondary
III winding 2
@) Stmet"re2
Secondary 3
winding i
winding
0 Secondary (a)t: (500nddiv) @)t: (ZOOnddiv)
winding 2 Fig. 15. V8.mVa.ofS1, Vgs:(SV/div)Vds:(lOV/div)
(c) Stmshlre3
6
5
(a)t: (5OOoddiv) @p: (2OOOddi")
Leakage Fig. 16. V,,m Va.of S2, Vgs: (5V/div) Vds: (IOV/div)
Inductance3 IB Structure2
(nH) 2
I
0
Secondary Secondary
winding1 winding2
Fig. 13. Leakage hductanee Cornpaison ofDifferent Winding
Configuration (exciting frequency e500 m)
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2004 351h Annual IEEE Power Elecrrorrics Specialists Conference Aachen. Germany, 2004
VI. CONCLUSION
48V to 0.9V VRM using LLC resonant converter is
presented. The main switches work in ZVS condition. So the
converter can work at higher frequency, which is helpful for
the fast transient response and magnetic size reduction. How
to reduce the primary current amplitude by reducing the
power factor angle is investigated. The effect of secondary
leakage inductance of transformer is studied, and the winding
configuration design to minimize the secondary leakage
inductance is presented.
ACKNOWLEDGEMENT
This work was supported by Emerson Network Power Co.,
Ltd. It is also supported by National Natural Science
Foundation of China with Project Number 50237030.
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