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CHAPTER 2

LOW POWER DIGITAL CIRCUIT


DESIGN AND SOME CONCEPTS
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The major power dissipation mechanisms in digital logic circuits are described
in this chapter. To compensate for the performance loss that is caused by down scaling
in the supply voltage for reducing the dynamic power dissipation, the threshold voltage
of MOS transistors are also reduced, which results in an exponential increase in the
subthreshold leakage current. The tremendous increase in the standby subthreshold
leakage power dissipation, caused by down scaling in technology is also presented in
detail. Deep submicron and nanoscale device issues are discussed. The existing
subthreshold leakage reduction techniques are source biasing technique, stack
technique, dual VTH partitioning technique, variable threshold CMOS (VTCMOS)
technique, multi-threshold CMOS (MTCMOS) technique, sleepy keeper technique, and
super cutoff CMOS (SCCMOS) technique. These works on controlling subthreshold
standby leakage power dissipation are presented. Out of these existing techniques,
MTCMOS technique and SCCMOS technique are mainly used for reducing this
standby leakage power dissipation. However both MTCMOS and SCCMOS techniques
still suffer from higher standby leakage power dissipation. Hence new and effective
circuit design techniques are greatly needed for further reduction of this standby leakage
power dissipation. Finally, conclusion is provided in the end of this chapter.

2.1 SOURCES OF POWER DISSIPATION

There are two main classes of power dissipation in digital logic circuits. These
are dynamic power dissipation and static or leakage power dissipation. Dynamic power
dissipation in a logic circuit is mainly observed during its normal operation, especially
at high operating frequencies, whereas static or leakage power dissipation is more
evident during the long idle or standby period. An overview of different types of power
dissipation in digital circuits is shown in Fig. 2.1.
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Fig. 2.1 Power dissipation in digital logic circuits

2.1.1 DYNAMIC POWER DISSIPATION

Dynamic power dissipation in a digital logic circuit is mainly caused by the


current flow due to charging and discharging of parasitic capacitances. It consists of
three components: switching power dissipation, short circuit power dissipation, and
glitching power dissipation. In most digital circuits, the switching power dissipation is
the dominant component of dynamic power dissipation (Kang et al. 2003, Jie et al.
2014).

2.1.1.1 SWITCHING POWER DISSIPATION

In digital logic circuits, switching power dissipation occurs when current is


drawn from the power supply voltage, VDD to charge up the output node capacitance.
Fig. 2.2 shows a CMOS inverter circuit to illustrate this power dissipation. During the
switching event, the output node voltage typically makes a full transition from 0V to
VDD, and one-half of the energy drawn from the power supply is dissipated as heat in
the conducting pMOS transistor. The energy stored in the output node capacitance
during charge-up phase is dissipated as heat in the conducting nMOS transistor, when
the output voltage switches from VDD to 0V. The total capacitive load (Cload) at the
output of the inverter circuit consists of total drain diffusion capacitance, total
interconnect capacitance, and input gate oxide capacitance of the driven gates that are
connected to the output of the inverter circuit. The average switching power dissipation
of the inverter circuit can be calculated from the energy required to charge up the output
node capacitance to VDD and discharge to 0V.
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Fig. 2.2 Switching power dissipation in a CMOS inverter circuit

The generalized expression for the switching power dissipation can be written as
(Kang et al. 2003)

(2.1)

Here is the switching activity factor, represents the total load capacitance,
is the supply voltage, and represents the switching frequency.

Equation (2.1) indicates that the supply voltage is the dominant factor in the
switching power dissipation. Thus reducing is the most effective technique to
reduce this power dissipation.

2.1.1.2 SHORT CIRCUIT POWER DISSIPATION

Short circuit power dissipation occurs in a logic circuit that is driven by input
signal with finite rise and fall time. Fig. 2.3 shows a CMOS inverter circuit showing
short circuit power dissipation. This power dissipation occurs due to the short circuit
current flowing through both nMOS and pMOS transistors during switching (due to
finite rise and fall time of the input signal).
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Fig. 2.3 A CMOS inverter circuit showing short circuit power dissipation

Both nMOS and pMOS transistors in the circuit conduct simultaneously for a
short interval of time during switching, forming a direct current path between and
GND. This power dissipation is linearly proportional to rise and fall time of the input
signal (Veendrick 1984). Therefore, reducing the input rise and fall time will decrease
this power dissipation.

2.1.1.3 GLITCHING POWER DISSIPATION

Fig. 2.4 shows a simple multi-level network circuit showing glitching power
dissipation. This power dissipation occurs in the intermediate transitions during the
evaluation of the logic function of the logic circuit. In a multi-level logic circuit, the
propagation delay of input signals from one logic block to the next can cause the input
signals to change at different times. Thus, a node can exhibit multiple transitions in a
single clock cycle before settling to the correct logic level. These intermediate
erroneous outputs lead to a power loss in charging and discharging the output load
capacitance. Primarily, glitches occur due to a mismatch or imbalance in the path
lengths in the multi-level logic network (Raghunathan et al. 1996). Such a mismatch in
the path length results in mismatch in the signal timing with respect to the primary
inputs. In the multi-level network circuit shown in Fig. 2.4, if both NAND gates have
the same delay time and the three input signals (A, B, and C) arrive at the same time,
then this network will suffer from glitching power dissipation.
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Fig. 2.4 Multi-level network circuit showing glitching power dissipation

To avoid such power loss, circuit designers can use synchronous circuits in
which all the outputs are either latched or gated to synchronize the inputs to the next
stage. Also dynamic circuits avoid this type of power dissipation by synchronizing the
output with the clock signal. Finally, a careful layout can reduce the skew among the
input signals to each logic gate, leading to a lower glitching activity.

2.1.2 STATIC POWER DISSIPATION

Static power dissipation in a logic circuit is caused by leakage currents when the
circuit is in idle or standby state. Theoretically, a CMOS digital logic circuit should not
dissipate any power in the standby mode (Roy et al. 2000). This is due to the fact that
either pull-down network or pull-up network is turned off, thus preventing static or
leakage power dissipation. In reality, however, there is always some leakage current
passing through the transistors, indicating that the CMOS logic circuit consumes a
certain amount of power even in the standby state. Even though the static power
dissipation associated with an individual logic gate is extremely small, the total effect
becomes significant when millions of transistors are packed into a single chip.
Furthermore, as transistors shrink in size (due to down scaling in technology), the level
of doping has to be increased, thereby causing larger leakage currents. Leakage currents
come from a variety of sources within the transistor. Fig. 2.5 shows the leakage current
mechanism in a short-channel nMOS transistor (Roy et al. 2003).
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Fig. 2.5 Leakage current mechanism in a short-channel nMOS transistor

2.1.2.1 REVERSE DIODE LEAKAGE CURRENT (I1)

The reverse diode leakage current occurs when the pn-junction between the
drain and the bulk of the transistor is reverse-biased. The reverse-biased drain junction
conducts a reverse saturation current which is drawn from the power supply. This
leakage current in a pn-junction can be expressed as (Pierret 1996)

(2.2)

Here is the junction area, is the reverse bias voltage across the pn-junction, and
is the reverse saturation current density. Since this leakage current is proportional to
the junction area, it is advisable to minimize the area as much as possible in the layout
design to reduce this leakage current.

2.1.2.2 SUBTHRESHOLD LEAKAGE CURRENT (I2)

Subthreshold leakage current is the current flow between source and drain
region in a MOS transistor, even when the gate voltage (VGS) is below the threshold
voltage (VTH) of the MOS transistor. This leakage current is the most dominant
component among all leakage currents in small-channel MOS transistors. In
long-channel MOS transistors, the threshold voltage is considered as the boundary
between the cutoff and the active region. However, in a short channel MOS transistor,
this boundary is not abrupt and the transistor conducts even in weak inversion region
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below the threshold voltage of the MOS transistor. This leakage current is the dominant
source of static power dissipation in deep submicron and nanoscale technologies
(Deepaksubramanyan et al. 2007). This leakage current is discussed in more detail in
section 2.2.

2.1.2.3 DRAIN INDUCED BARRIER LOWERING EFFECT (I3)

In long-channel MOS transistors, the source and drain are separated far enough
that their depletion regions have no effect on the potential or field pattern in most part
of the device. Hence, for such devices, the threshold voltage is virtually independent of
the channel length and the drain bias voltage (VDS). For a long-channel device, the
barrier height is mainly controlled by the gate voltage and is not sensitive to VDS.
However, the barrier of a short-channel device reduces with an increase in the drain
voltage, which in turn increases the subthreshold leakage current due to a lower
threshold voltage. When a high drain voltage is applied to a short-channel MOS
transistor, it lowers the barrier height, resulting in further decrease of the threshold
voltage. Therefore, the threshold voltage and consequently the subthreshold leakage
current of short-channel MOS transistors vary with the drain bias voltage. This effect is
referred to as drain induced barrier lowering (DIBL). Due to this effect, the source
injects carriers into the channel surface even without the application of the gate voltage.
This effect is more enhanced at a higher drain voltage and shorter channel length (Leff)
in a MOS transistor (Deen et al. 1990).

2.1.2.4 GATE INDUCED DRAIN LEAKAGE (I4)

Gate induced drain leakage (GIDL) current arises in the high electric field under
the gate and drain overlap region causing deep depletion. This leakage current occurs at
a low VGS and a high VDS bias voltage and generates carriers into the substrate and drain
regions from surface traps or band-to-band tunneling.

2.1.2.5 PUNCHTHROUGH (I5)

Punchthrough occurs when the drain and the source depletion region approach
each other and electrically touch deep in the channel. This is a space-charge condition
that allows the channel current to exist deep in the subgate region, causing the gate to
lose control of the subgate channel region. This is regarded as a subsurface version of
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DIBL, and is obviously an undesirable condition and should be prevented in normal


circuit operation.

2.1.2.6 NARROW CHANNEL EFFECT (I6)

MOS transistors which have channel widths W of the same order of magnitude
as the maximum depletion region thickness are defined as narrow channel devices. The
most significant narrow channel effect is that it increases the actual threshold voltage of
MOS transistors.

2.1.2.7 GATE OXIDE TUNNELING (I7)

The gate oxide tunneling current arises due to the finite (non-zero) probability of
an electron directly tunneling through the insulating SiO2 layer. The electron tunneling
probability, and thus, the gate oxide tunneling current itself, is a strong exponential
function of the gate oxide layer thickness (tox) and the voltage potential across the gate
oxide. In a MOS transistor for tox ≥ 2nm the gate tunneling current is typically very
small in comparison with other forms of leakage currents (Lee et al. 2003).

2.1.2.8 HOT CARRIER INJECTION (I8)

Short-channel transistors are more susceptible to inject hot carriers (holes and
electrons) into the gate oxide. Reducing the device dimensions to the deep submicron
and nanoscale regime, accompanied by increasing the substrate doping densities, result
in a significant increase in the horizontal and vertical electrical fields in the channel
region. Electrons and holes that gain high kinetic energies (hot carriers) due to the
significant increase in the electric field can be injected into the gate oxide (Rosenbaum
et al. 1991). It causes permanent changes in the oxide-interface charge distribution,
thereby, degrading the current-voltage characteristics of the MOSFET.

Out of all these above mentioned leakage currents, the subthreshold leakage
current is highly critical for battery operated burst mode type systems. Gate oxide
tunneling or gate oxide leakage current can be significantly reduced by using high-k
dielectrics to better insulate the gate from the channel (Kim et al. 2003). Standby
subthreshold leakage power dissipation is the major concern for battery operated burst
mode type systems. These systems spend more than 90% of their time in the standby
mode (Hirabayashi et al. 2001). Thus, a larger percentage of total power is wasted in the
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standby period. This leakage power will become a large component in the total power
dissipation in future technologies. So, new and effective circuit techniques have to be
developed for further reduction of this leakage power dissipation. Hence, in this thesis
main focus is given on further reducing this standby leakage power dissipation in the
standby mode.

2.2 SUBTHRESHOLD LEAKAGE POWER DISSIPATION

Subthreshold leakage power dissipation occurs due to the flow of leakage


current between source and drain region in a MOS transistor, even when the gate
voltage (VGS) is below the threshold voltage (VTH) of the MOS transistor (Taur et al.
1998). In order to reduce the dynamic power dissipation in a logic circuit, the supply
voltage is reduced. However, with the reduction in the supply voltage, circuit
propagation delay also increases. So, threshold voltage of the MOS transistor is reduced
to overcome this problem. The reduction in the threshold voltage leads to an increase in
the subthreshold leakage current. This leakage current is caused by the inability to
completely turn off a MOS transistor, even when VGS is below VTH of the MOS
transistor.
In long-channel MOS transistors, the threshold voltage is considered as the
boundary between the cutoff and active inversion region. However, in short-channel
MOS transistor, this boundary is not abrupt and the transistor conducts even in weak
inversion region, below the threshold voltage of the MOS transistor (Roy et al. 2003).
This leakage current is mainly caused by the reduction in the threshold voltage of MOS
transistors and down scaling in technology. Fig. 2.6 shows the flow of subthreshold
leakage current in an nMOS transistor, when VGS is less than VTH of the transistor. This
leakage current is the most dominant component among all leakage currents in small-
channel MOS transistors. This leakage current is the main source of leakage power
dissipation, so this leakage current should be further minimized by utilizing effective
circuit techniques.
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Fig. 2.6 Subthreshold leakage current in an nMOS transistor

Subthreshold leakage current is highly undesirable in any logic circuits. Fig. 2.7
shows this leakage power dissipation trends according to the International Technology
Roadmap for Semiconductors. This figure shows that the leakage power dissipation
increases with the down scaling in technology generation. This leakage power
dissipation will dominate in the overall power dissipation in future technologies (Kim et
al. 2003).

Fig. 2.7 Subthreshold leakage power dissipation trends

Table 2.1 shows the dependence of subthreshold leakage current on MOS device
parameters (Deepaksubramanyan et al. 2007). From this table, it is observed that this
leakage current increases exponentially with the decrease in the threshold voltage and
increase in the input gate voltage of the MOS transistor. So, increasing the threshold
voltage of the MOS transistor and applying reverse gate voltage are effective ways to
reduce this leakage current.
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Table 2.1: Dependence of subthreshold leakage current on MOS transistor parameters

Transistor parameters Dependence of subthreshold current

Transistor channel width (W) Directly proportional

Transistor channel length (L) Inversely proportional

Temperature (T) Exponential increase

Transistor threshold voltage (VTH) Exponential increase with decrease in VTH

Input gate voltage (VGS) Exponential increase

According to BSIM4 MOSFET model, the equation governing the subthreshold


leakage current in deep submicron and nanoscale technologies can be expressed as
(Anis et al. 2003)


(2.3)

2
and (2.4)

Here , and are the gate to source, drain to source, and bulk to source
voltages respectively, denotes the carrier mobility, is the gate oxide capacitance
per unit area, W and L denote the channel width and channel length of the leaking MOS
transistor respectively, K is the Boltzmann constant, T is the absolute temperature, q is
the electrical charge of an electron, VT is the thermal voltage, VTH is the threshold
voltage, γ is body effect coefficient, η denotes the drain induced barrier lowering
coefficient, and n is the subthreshold swing coefficient.

The subthreshold leakage current can also be approximately formulated as


(Butzen et al. 2007)

(2.5)

The parameter n in equation (2.5) is the subthreshold swing coefficient and is given by

, where is the depletion layer capacitance per unit area, and Cox is the gate

oxide capacitance per unit area. This equation reveals that this leakage current is
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exponentially proportional to (VGS – VTH). Earlier, the threshold voltage of MOS


transistors was high enough that even with VGS = 0V, the subthreshold leakage current
was very small. However, in today's smaller geometry processes (90nm and below),
reduced power supply voltages require reduction in the threshold voltage of MOS
transistors, and thus, the subthreshold leakage current at VGS = 0V becomes significant.
This leakage current can be reduced by increasing VTH and n of MOS transistors and
reducing VGS.

In a digital logic circuit, the subthreshold leakage power dissipation can be


calculated as the product of the number of nMOS and pMOS transistors (NnMOS and
NpMOS), the average subthreshold leakage current per MOS transistor (ISUBAVG), and the
supply voltage (VDD). It is expressed as

(2.6)

Here ISUBAVG is calculated by computing the average leakage current per MOS transistor
for the given logic circuit using gate-level subthreshold leakage power estimation.

Fig. 2.8 shows the variation of minority carrier concentration along the length of
channel in an nMOS transistor biased in the weak inversion region (Roy et al. 2003).
This figure shows that the concentration of minority carriers in weak inversion region is
small, but not zero. Here, the source of the nMOS transistor is grounded, VDS > 0.1V,
and VGS < VTH. For such weak inversion condition, VDS drops almost entirely across the
reverse-biased substrate-drain pn-junction. As a result, the variation of the electrostatic
potential at the semiconductor surface along the channel (along y axis) is small. The

component of the electric field vector along y-direction (Ey), being equal to , is also

small. With smaller number of mobile carriers and lesser longitudinal electric field, the
drift component of the subthreshold drain-to-source current is negligible. Therefore,
unlike the strong inversion region in which the drift current dominates, the subthreshold
conduction is dominated by the diffusion current. The carriers move by diffusion along
the surface similar to charge transport across the base of bipolar transistors. Weak
inversion typically dominates modern device off-state leakage due to the low VTH of
MOS transistors. This leakage current dominates over other leakage components with
the down scaling in technology.
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Fig. 2.8 Variation of minority carrier in an nMOS transistor in weak inversion

The dependence of the subthreshold leakage current on the gate voltage in an


nMOS transistor is exponential, as illustrated in Fig. 2.9 (Rabaey 1996). The
subthreshold leakage current is the current flow between source and drain when V GS is
below VTH of the MOS transistor. So, when VGS < VTH, then the current flow between
the source and the drain region in an nMOS transistor is given as IDS = ISUB.

Fig. 2.9 Subthreshold leakage in an nMOS transistor


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The inverse of the slope of log10(IDS) versus VGS is called the subthreshold slope
(St) and is expressed as (Taur et al. 1998)

(2.7)

2.8)

(2.9)

(2.10)

Subthreshold slope indicates how effectively the transistor can be turned off
when VGS is decreased below VTH (Roy et al. 2002). A low value of subthreshold slope
is desirable for achieving low subthreshold leakage current. One way of reducing the
subthreshold slope is to operate the circuit at liquid nitrogen temperature (77 K).
Liquid nitrogen temperature (LNT) operation of CMOS devices offers speed,
density, and reliability for high performance VLSI logic systems. The performance
advantage of low temperature or LNT operation of MOSFETs has been recognized for
some time (Srivastava et al. 1995, Gaensslen et al., 1977, Sun et al. 1987). The benefit
is mainly derived from two aspects of the MOSFET characteristics at low temperature:
higher carrier mobilities and steeper subthreshold slope. The electron mobility improves
by a factor of 2-5, depending on the magnitude of the vertical electrical field from 300
K to 77 K (Gaensslen et al., 1977). Similarly, hole mobility also improves by a factor of
1.7- 4 from 300 K to 77 K (Gaensslen et al., 1977). Another important aspect of the
MOSFET characteristics at liquid nitrogen temperature is the steeper subthreshold
slope, making it much easier to turn off a MOS transistor than at room temperature.
This allows the threshold voltage, and therefore the supply voltage, to scale further
below their permissible values at room temperature.
Low temperature operation of silicon CMOS transistors is a promising way to
improve the circuit performance. The temperature reduction allows the increase of the
carrier mobility and saturation velocity, better turn-on capabilities, latch-up immunity,
reduction in activated degradation processes, lower power consumption, decrease of
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leakage current, reduced thermal noise, and increased thermal conductivity (Fang et al.
1970).

However, circuit operation at liquid nitrogen temperature (77 K) increases the


overall cost (Wang et al. 1991). Besides, for portable applications, room temperature
operation is essential. Also operation at liquid nitrogen temperature leads to problems
such as impurity freeze-out, kink phenomenon, and series resistance effects (Fang et al.
1970).

The silicon-on-insulator (SOI) device structure has the steep subthreshold slope
(Liu et al. 2011). Hence nowadays silicon-on-insulator (SOI) CMOS technology has
attracted considerable attention as a potential substitute in low power applications. In

this technology, is close to zero as the depletion capacitance is negligible (Park et

al. 1999). An important feature in using this technology is the steeper subthreshold
slope due to reduction in the substrate body effect (Sicard et al. 2007). A steep
subthreshold slope helps in achieving low leakage power dissipation. For a given Ioff
current, this technology has a much smaller threshold voltage, which means that the
circuit can operate at a lower supply voltage. This technology has lower DIBL, lesser
short channel effects, smaller subthreshold slope, and lesser junction and parasitic
capacitances in comparison with the bulk CMOS technology (Yan et al. 1992, Kado et
al. 1997, Cristoloveanu et al. 1998). Thus, the subthreshold leakage current in SOI
CMOS technology is much lower than the bulk CMOS technology for the same
threshold voltage. This technology makes an attractive option for proper and effective
reduction of the subthreshold leakage power dissipation (Fuse et al. 2003, Ning 2013).
Improved circuit techniques in SOI CMOS technology may be developed for efficient
reduction of this leakage power dissipation.

2.3 DEEP SUBMICRON AND NANOSCALE DEVICE ISSUES

Short-channel transistors require lower supply voltages to reduce their internal


electric fields and power dissipation. This forces reduction in the threshold voltage of a
MOS transistor, which causes an increase in the subthreshold leakage current. This
increase is due to the weak inversion state leakage and is a major function of VTH of
MOS transistors. Scaling down feature size is an important issue for the increase in this
power dissipation. However, second order effects such as threshold voltage roll-off and
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drain induced barrier lowering (DIBL) become serious for short-channel devices which
have to be considered while designing circuit techniques for reducing this leakage
power dissipation in deep submicron and nanoscale technologies (Chaudhry et al.
2004).

2.3.1 SHORT-CHANNEL THRESHOLD VOLTAGE ROLL-OFF

For a long channel MOS transistor, the surface potential barrier is constant.
Hence, the threshold voltage of the MOS transistor is not sensitive to the channel length
variation. However, for a short-channel MOS device, the surface potential barrier is
reduced along with scaling in the channel length. Therefore, the threshold voltage of the
MOS transistor decreases with the decrease in the channel length. Hence in deep
submicron and nanoscale technologies, the threshold voltages of MOS transistors are
smaller. This forces a tremendous increase in the subthreshold leakage current with the
down scaling in technology.

2.3.2 DRAIN INDUCED BARRIER LOWERING

Drain induced barrier lowering is discussed in section 2.1.2.3. This is an effect


which increases subthreshold leakage current in deep submicron and nanoscale devices.
In order to minimize these short channel effects, advanced MOSFET
technologies are found to be useful. It is found that short channel effects in MOS
transistors are much lesser in SOI CMOS technology in comparison with conventional
CMOS bulk technology. The use of this technology is bringing new possibilities in
reducing these short-channel effects.

2.4 CIRCUIT DESIGN TECHNIQUES

The most commonly used subthreshold leakage reduction techniques are source
biasing technique (Bellaouar et al. 1995), stack technique (Johnson et al. 2002), dual
VTH partitioning technique (Hirabayashi et al. 2001), variable threshold CMOS
(VTCMOS) technique (Hyunsik et al. 2001), multi-threshold CMOS (MTCMOS)
technique (Mutoh et al. 1995), sleepy keeper technique (Kim et al. 2006), and super
cutoff CMOS (SCCMOS) technique (Kawaguchi et al. 2000). Out of these leakage
reduction techniques, MTCMOS technique, and SCCMOS technique are the major
techniques available in the literature for reducing the standby subthreshold leakage
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power dissipation. However these techniques still dissipate a significant amount of this
standby leakage power. Minimizing this standby leakage power dissipation is highly
desirable for electronic systems that are powered with portable batteries. In burst mode
type systems, reduction of this standby leakage power greatly improves their battery
lifetime, as these systems spend majority of their time in the standby or idle mode
(Kunie et al. 2008). Hence nowadays researchers are focusing on the development of
effective and improved circuit techniques for further reduction of this standby leakage
power dissipation.

2.4.1 SOURCE BIASING TECHNIQUE

The concept of source biasing technique (Bellaouar et al. 1995) refers to the
application of a positive bias voltage to the source terminal in an off nMOS transistor
during the standby mode, which raises the threshold voltage of the transistor, as shown
in Fig. 2.10. By taking advantage of the body effect phenomenon, the subthreshold
leakage current can be reduced exponentially. In addition, the gate to source voltage
(VGS) becomes negative. The net effects are that the off transistor is turned off more
strongly and the leakage currents can be reduced effectively during the standby mode.

Fig. 2.10 Source biasing technique


2.4.2 STACK TECHNIQUE

Stack effect is the phenomenon where subthreshold leakage current decreases


due to two or more series connected turned off transistors (Johnson et al. 2002).
Stacking of MOS transistors in their cutoff state significantly reduces this leakage
current in the standby mode. In this technique, a MOS transistor is stacked by replacing
the transistor of width W with two series connected transistors, each of width W/2.
Fig. 2.11 shows stacking of an nMOS and a pMOS transistor of width W with two
series connected nMOS and pMOS transistors of width W/2 respectively.
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Fig. 2.11 Stacking of an nMOS and a pMOS transistor of width W

Fig. 2.12 shows the reduction in the leakage current due to the increase in the
barrier height and the reduction in VDS (= VDD – VN) after stacking of two cutoff nMOS
transistors in comparison with a single cutoff nMOS transistor. When both nMOS
transistors (Q1 and Q2) are turned off due to the application of VGS < VTH, then the
intermediate node voltage (VN) has a positive value due to the existence of a small drain
current. Thus, the gate to source voltage of Q1 is negative, due to which the
subthreshold leakage current reduces exponentially. The body effect of Q1
(due to VN > 0V) further increases VTH of Q1, thereby reduces this leakage current.
Drain induced barrier lowering (DIBL) is also reduced due to the positive value of node
voltage (VN). This increases VTH of Q2, which also contributes to the reduction of this
leakage current. Thus the subthreshold leakage current is reduced considerably due to
stacking effect in cutoff MOS transistors.

Fig. 2.12 Standby subthreshold leakage current differences between (a) a single cutoff
nMOS transistor and (b) a stack of two cutoff nMOS transistors
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2.4.3 DUAL VTH PARTITIONING TECHNIQUE

A dual VTH partitioning scheme (Hirabayashi et al. 2001) provides the designer
with transistors that are either fast (with a high leakage) or slow (with a low leakage). In
modern process technology, multiple threshold voltages are provided for each transistor.
Therefore, a circuit can be partitioned into high and low threshold voltage gates or
transistors, which is a trade-off between propagation delay and reduced leakage current.
Fig. 2.13 shows a dual VTH partitioning scheme. In this figure, the critical path within
the circuit should be implemented with low VTH MOS transistors to minimize the
propagation delay, whereas non-critical paths should be implemented with high VTH
MOS transistors to minimize the leakage current. As a result, the leakage current is
significantly reduced in both standby and active modes compared to all low VTH
implementation. At the same time, circuit performance in terms of switching speed is
maintained. A limitation of this technique is that CAD tools need to be developed and
integrated into the design flow to optimize the partitioning process.

Fig. 2.13 Dual VTH partitioning scheme

2.4.4 VARIABLE THRESHOLD CMOS (VTCMOS) TECHNIQUE

In variable threshold CMOS (VTCMOS) technique (Hyunsik et al. 2001), the


substrate bias voltage is dynamically varied to control the threshold voltage of MOS
transistors. Rather than employing multiple threshold voltage transistors, a VTCMOS
circuit inherently uses low threshold voltage transistors, and the substrate bias voltages
of the nMOS and pMOS transistors are generated by the variable substrate bias control
circuit.
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A CMOS inverter circuit using VTCMOS technique is shown in Fig. 2.14.


When the inverter circuit is operating in its active mode, the substrate bias voltage of
the nMOS transistor is VBn = 0V and the substrate bias voltage of the pMOS transistor is
VBp = VDD. Thus the transistors in the circuit do not experience any body effect. The
circuit operates with low-power dissipation (due to a low VDD) and a high switching
speed (due to a low VTH). When the circuit is in the standby mode, the substrate bias
control circuit generates a lower substrate bias voltage for the nMOS transistor and a
higher substrate bias voltage for the pMOS transistor. As a result, the magnitudes of the
threshold voltages (VTHn and VTHp) increase in the standby mode due to the body effect.
Since the subthreshold leakage current drops exponentially with increasing threshold
voltage, the leakage power dissipation in the standby state can be significantly reduced
with this circuit design technique.
However, with technology scaling, the effectiveness of VTCMOS technique
reduces as the channel length becomes smaller, or the VTH values are lowered. Also,
this technique is intrinsically more problematic for reliability since the high voltage
across the oxide decreases the lifetime of the device.

Fig. 2.14 A CMOS inverter circuit using VTCMOS technique


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2.4.5 MULTI-THRESHOLD CMOS (MTCMOS) TECHNIQUE

Multi-threshold CMOS is a very effective circuit technique to reduce the


leakage current of a logic circuit in the standby mode (Mutoh et al. 1995). In this
technique, low VTH transistors are used to design the logic circuit for which the
switching speed is essential and high VTH transistors (also called sleep transistors) are
used to effectively isolate the logic circuit from VDD and GND in the standby state and
thus effectively reduce the standby subthreshold leakage power dissipation. The circuit
structure of MTCMOS circuit technique is shown in Fig. 2.15.
In this technique, a high-threshold voltage pMOS transistor is inserted between
the power supply and the logic circuit (low VTH) and a high-threshold voltage nMOS
transistor is placed between the logic circuit (low VTH) and the ground. During active
mode of operation, the high threshold voltage MOS transistors (sleep transistors) are
turned on, thereby facilitating normal operation of the circuit as there exists a direct
path from the output to the ground and VDD. During standby mode, these high VTH
transistors are turned off, creating a virtual power supply and a virtual ground rail and
thus cutting off the logic circuit from the power supply and the ground. Since high VTH
transistors operating in the standby mode forces the logic circuit to go in sleep state, so
these high VTH transistors are also known as sleep transistors. In this technique both low
and high threshold voltage MOS transistors are fabricated on a single chip. From a
visual perspective, these high VTH sleep transistors act as a current gate to the designed
circuit (low VTH). For this reason, this technique is also referred to as power gating
circuit technique. The subthreshold leakage power dissipation in the standby mode can
be significantly reduced by using this circuit design technique.
The main disadvantage in using this technique is the increase in circuit delay
due to the use of high VTH MOS transistors (sleep transistors). Also this technique still
suffers from higher standby subthreshold leakage power dissipation, which can become
a great problem for portable systems, such as burst mode type systems, where a larger
amount of this leakage power is dissipated during the long standby period.
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Fig. 2.15 A CMOS logic circuit using MTCMOS technique

2.4.6 SLEEPY KEEPER TECHNIQUE

In sleepy keeper technique (Kim et al. 2006), an additional high threshold


voltage nMOS transistor is connected in parallel with the sleep pMOS transistor (high
VTH sleep pMOS transistor) and an additional high threshold voltage pMOS transistor is
connected in parallel with the sleep nMOS transistor (high VTH sleep nMOS transistor).
Fig. 2.16 shows a CMOS logic circuit using this technique. In sleep or standby mode of
operation, sleep transistors are in cutoff state. So, when sleep signal is active, then the
high threshold voltage nMOS transistor connected in parallel with the sleep pMOS
transistor provides a path to connect the pullup network of the CMOS logic circuit with
the power supply and the high threshold voltage pMOS transistor connected in parallel
with the sleep nMOS transistor provides a path to connect the pulldown network of the
CMOS logic circuit with ground. The major advantage in using this circuit technique is
that it retains the circuit present state even in the sleep mode. This circuit technique also
provides a significant method to reduce the subthreshold leakage power dissipation.
37

Fig. 2.16 A CMOS logic circuit using sleepy keeper technique

2.4.7 SUPER CUTOFF CMOS (SCCMOS) TECHNIQUE

Another technique, which is an alternate to MTCMOS technique, is the super


cutoff CMOS technique (Kawaguchi et al. 2000). In this scheme, sleep transistors are
under-driven (or over-driven) when in standby mode. Subthreshold leakage current in
the standby mode reduces exponentially due to the application of positive and negative
gate voltages to sleep pMOS and sleep nMOS transistors respectively. The key
difference between this technique and the MTCMOS technique lies in the use of sleep
transistors of having the same low threshold voltage as that of the designed logic circuit.
Fig. 2.17 shows a CMOS logic circuit using this technique.
The advantage of such a scheme is that the additional delay introduced due to
the use of high VTH sleep MOS transistors, as in MTCMOS technique, can be further
reduced during the active mode of operation because the transistor gets higher drive
current (due to the use of low VTH sleep MOS transistors). During active mode of
operation, sleep transistors (low VTH) are turned on, thereby facilitating normal
operation of the circuit as there exists a direct path from the output to the ground and
VDD. During standby mode, sleep transistors are completely cutoff due to the
application of positive and negative gate voltages (VGS1 and VGS2) to sleep pMOS
transistor and sleep nMOS transistor respectively. Hence the subthreshold leakage
current in the standby mode reduces exponentially. However the main disadvantage in
using this technique is the use of a complex controller circuit for providing both
38

negative and positive gate voltages to completely turn off sleep nMOS and sleep pMOS
transistors respectively.

Fig. 2.17 A CMOS logic circuit using SCCMOS technique

2.5 CONCLUSION

In this chapter, the main sources of power dissipation in digital logic circuits are
presented. Various phenomena associated with small size transistors, which result by
technology scaling, are also discussed. The subthreshold leakage current increases due
to down scaling in technology and reduction in the threshold voltage. The increase in
subthreshold standby leakage power dissipation seriously affects battery operated
portable electronic systems that spend their majority of time in the standby mode.
The most commonly used subthreshold leakage reduction techniques such as
source biasing technique, stack technique, dual VTH partitioning technique, VTCMOS
technique, MTCMOS technique, sleepy keeper technique, and SCCMOS technique are
described. Out of these existing techniques, MTCMOS technique and SCCMOS
technique are mainly used for the reduction of this standby leakage power dissipation.
The main disadvantage in using MTCMOS technique is the increase in circuit delay due
to the use of high threshold voltage MOS transistors (sleep transistors). In this
technique, the high VTH MOS transistors can limit the down scaling of the supply
voltage for ultra-low power applications. The main advantage in using SCCMOS
39

technique over MTCMOS technique is the reduction in the circuit delay due to the use
of low VTH sleep nMOS and sleep pMOS transistors. However in SCCMOS technique,
a complex controller circuit is used for providing both negative and positive gate
voltages to completely turn off nMOS and pMOS transistors respectively. Both of these
techniques still dissipate a significant amount of standby subthreshold leakage power
dissipation. Hence new and effective circuit design techniques have to be developed to
handle ever rising subthreshold standby leakage power dissipation.