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# Lecture 23 FSM design

## ◆ Logistics ■ FSM-design procedure

■ HW8 due Wednesday, March 11
■ Ant extra credit due Friday, March 13 1. State diagram
■ Final exam, Wednesday March 18, 2:30-4:20 pm here 2. state-transition table
■ Review session Monday, March 16, 4:30 pm, Place TBA
3. State minimization
◆ Last lecture 4. State encoding
■ General FSM Minimization
5. Next-state logic minimization
◆ Today 6. Implement the design
■ State encoding
µ One-hot encoding
µ Output encoding
■ State partitioning

## ◆ 15 cents for a cup of coffee

◆ Doesn’t take pennies or quarters Reset Reset present inputs next output
state D N state open
D' N' 0¢ 0 0 0¢ 0
◆ Doesn’t provide any change 0 1 5¢ 0
0¢ 1 0 10¢ 0
N 1 1 – –
Vending Open D' N' N 5¢ 0 0 5¢ 0
Coin Machine Release
Sensor FSM Mechanism D 0 1 10¢ 0
D 5¢ 1 0 15¢ 0
1 1 – –
N 10¢ 0 0 10¢ 0
0 1 15¢ 0
D 10¢ D' N' 1 0 15¢ 0
Clock 1 1 – –
N+D 15¢ – – 15¢ 1

[open]

## A vending machine: State encoding A vending machine: Logic minimization

Q1 Q1
D1 Q1 Open
D0
present state inputs next state output 0 0 1 1
0 1 1 0 0 0 1 0
Q1 Q0 D N D1 D0 open 0 1 1 1
0 0 0 0 0 0 0 N 1 0 1 1 N N
0 0 1 0
0 1 0 1 0 D X X X X
1 0 1 0 0 D X X X X D X X 1 X
1 1 – – – 1 1 1 1
0 1 1 1 0 0 1 0
0 1 0 0 0 1 0
0 1 1 0 0 Q0 Q0 Q0
1 0 1 1 0
1 1 – – –
1 0 0 0 1 0 0
0 1 1 1 0 D1 = Q1 + D + Q0 N
1 0 1 1 0
1 1 – – –
1 1 – – 1 1 1 D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D

OPEN = Q1 Q0

## CSE370, Lecture 23 5 CSE370, Lecture 23 6

A vending machine: Implementation State encoding

## ◆ Assume n state bits and m states

■ 2n! / (2n – m)! possible encodings
µ Example: 3 state bits, 4 states, 1680 possible state assignments

## ◆ Want to pick state encoding strategy that results in

■ FSM size (amount of logic and number of FFs)
■ FSM speed (depth of logic and fan-in/fan-out)
■ FSM ease of design or debugging

## ◆ No guarantee of optimality ◆ One-hot: Encode n states using n flip-flops

■ An intractable problem ■ Assign a single “1” for each state
µ Example: 0001, 0010, 0100, 1000
◆ Most common strategies ■ Propagate a single “1” from one flip-flop to the next
■ Binary (sequential) – number states as in the state table µ All other flip-flop outputs are “0”
■ Random – computer tries random encodings
■ Heuristic – rules of thumb that seem to work well ◆ The inverse: One-cold encoding
µ e.g. Gray-code – try to give adjacent states (states with an arc ■ Assign a single “0” for each state
between them) codes that differ in only one bit position µ Example: 1110, 1101, 1011, 0111
■ One-hot – use as many state bits as there are states ■ Propagate a single “0” from one flip-flop to the next
■ Output – use outputs to help encode states µ All other flip-flop outputs are “1”
■ Hybrid – mix of a few different ones (e.g. One-hot +
◆ “almost one-hot” encoding (modified one-hot encoding)
heuristic)
■ Use no-hot (000…0) for the initial (reset state)
■ Assumes you never revisit the reset state till reset again.

## CSE370, Lecture 23 9 CSE370, Lecture 23 10

Vending Machine:
One-hot encoding (con’t) One-hot encoded transition table

◆ Often the best/convenient approach for FPGAs present state inputs next state output
■ FPGAs have many flip-flops Q3Q2Q1Q0 D N D3 D2D1D0 open Reset
D' N'
0 0 0 1 0 0 0 0 0 1 0
◆ Draw FSM directly from the state diagram
0 1 0 0 1 0 0 0¢
■ + One product term per incoming arc 1 0 0 1 0 0 0
■ - Complex state diagram ⇒ complex design D' N' N
1 1 – – – – –
■ - Many states ⇒ many flip flops 0 0 1 0 0 0 0 0 1 0 0 5¢ D
0 1 0 1 0 0 0
1 0 1 0 0 0 0 N
1 1 – – – – – D 10¢ D' N'
0 1 0 0 0 0 0 1 0 0 0
0 1 1 0 0 0 0 N+D
1 0 1 0 0 0 0 15¢
[open] 1
1 1 – – – – –
1 0 0 0 – – 1 0 0 0 1

## CSE370, Lecture 23 11 CSE370, Lecture 23 12

Designing from the state diagram
Output encoding

## ◆ Reuse outputs as state bits

Reset D0 = Q0D’N’
■ Why create new functions when you can use outputs?
D' N' D1 = Q0N + Q1D’N’ ■ Bits from state assignments are the outputs for that state
0¢ D2 = Q0D + Q1N + Q2D’N’ µ Take outputs directly from the flip-flops
D' N' N D3 = Q1D + Q2D + Q2N + Q3
Inputs Combinational
D OPEN = Q3
5¢ Logic Outputs
N

## D 10¢ D' N' State Inputs State Outputs

Storage Elements
N+D
15¢
[open] 1 ◆ ad hoc - no tools
■ Yields small circuits for most FSMs

## CSE370, Lecture 23 13 CSE370, Lecture 23 14

Vending machine
FSM partitioning
--- already in output encoding form
◆ Break a large FSM into two or more smaller FSMs
Reset D0 = Q0D’N’
D' N' D1 = Q0N + Q1D’N’ ◆ Rationale
0¢ D2 = Q0D + Q1N + Q2D’N’ ■ Less states in each partition
µ Simpler minimization and state assignment
D' N' N D3 = Q1D + Q2D + Q2N + Q3
µ Smaller combinational logic
D OPEN = Q3 µ Shorter critical path

■ But more logic overall
N

10¢
■ Same clock!!!
N+D
15¢
[open] 1

## CSE370, Lecture 23 15 CSE370, Lecture 23 16

Example: Partition the machine Introduce idle states for each partition

## ◆ Partition into two halves ◆ SA and SB handoff control between machines

C1
S1 S6
C2

C1 S2 C3 S5
S1 S6
C2
S3 C4 C5 S4
C3
S2 S5
S1 C1 S6
C1•S1
(C2•S6)’
C2•S6 C2
S3 C4 C5 S4 (C1•S1+
C3•S2+ C3•S2+
S2 C3+C5 SA SB C4•S3
S5
C4•S3+
C5•S2)’

S3 C4 C5•S2 S4

## CSE370, Lecture 23 17 CSE370, Lecture 23 18

Partitioning rules Partitioning rules (con’t)

Rule #1: Source-state transformation Rule #3: Multiple transitions with same source or destination
Replace by transition to idle state (SA) Source ⇒ Replace by transitions to idle state (SA)
Destination ⇒ Replace with exit transitions from idle state
C1 C1 C3
S1 S6 S1 SA S2 C3+C5 C3•S2 + S5
S2 S5 C4•S3
SA SB

C4 C5 C4
Rule #2: Destination state transformation S3 S4 S3 C5•S2 S4
Replace with exit transition from idle state
Rule #4: Hold condition for idle state
C2 C2•S6 “OR exit conditions and invert”
S1 S6 S1 SA
C2•S6
C2•S6
S1 SA

## Example: Six-state up/down counter Example: 6 state up/down counter

◆ Break into 2 parts ◆ Count sequence S0, S1, S2, S3, S4, S5
■ S2 goes to SA and holds, leaves after S5
U ≡ count up ■ S5 goes to SB and holds, leaves after S2
D ≡ count down ■ Down sequence is similar
U
S0 S5
U U
D
D D S0 S5
U U•S5 U U
S1 S4
D D D D (D•S3 + (D•S0+ D•S0 D
U D S1 SA U•S5)’ U•S2)’ SB S4
U D•S3
S2 S3 D D D
U U U U•S2 U
S2 S3

## Example: 6 state up/down counter Example: 6 state up/down counter

Compare behavior U ◆ 4-state machines need 2 state bits each – total 4 state bits
S0 S5 Enough to represent 16 states, though the combination of the two
on UUUUUU: U U ■
D FSMs has only 6 different configurations
D D
S1 S4 ◆ Why do this?
D D ■ Each FSM may be much simpler to think about (and design logic for)
U D than the original FSM (not here, though)
U
S2 S3 ■ Essential to do this partitioning for large FSMs
U
S0 S5 S0 S5
U U•S5 U U U•S5 U
U U
D D (D•S3 + D•S0 D D D (D•S3 + D•S0 D
(D•S0+ (D•S0+
S1 SA U•S5)’ U•S2)’ SB S4 S1 SA U•S5)’ U•S2)’ SB S4
D•S3 D•S3
D D D D D D
U U U•S2 U U U U•S2 U
S2 S3 S2 S3

## CSE370, Lecture 23 23 CSE370, Lecture 23 24

Minimize communication between partitions Mealy versus Moore partitions

◆ Ideal world: Two machines handoff control ◆ Mealy machine partitioning is undesirable
■ Separate I/O, states, etc. ■ Inputs can affect outputs immediately
µ “output” can be a handoff to another machine!!!
◆ Real world: Minimize handoffs and common I/O
■ Minimize number of state bits that cross boundary ◆ Moore machine partitioning is desirable
■ Merge common outputs ■ Input-to-output path always broken by a flip-flop
■ But…may take several clock cycles for input to propagate to
output