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PREVIOUS QUESTION PAPERS AND IMPORTANT QUESTIONS UNIT-WISE

NOV-DEC 14 APR-MAY 15 UNIT-1 UNIT-2 UNIT-3 UNIT-4 UNIT-5


Part-A Part-A Part-A Part-A Part-A Part-A Part-A
1. Amdahl’s Law 1. 8 ideas 1. 8 ideas 1. ALU operations 1. measure CPU perform 1. strong/weak scaling 1. volatile / Non Volatile mem
2. Relative addressing 2. pipelining/parallelism 2. pipelining 2. block diag: FA 2. basic perf eqn 2. UMA/ NUMA 2. SRAM, DRAM
3. Little Endian 3. overflow in Sub 3. hardware comp 3. Booth’s Mult recoding Table 3. MIPS 3. Flynn’s classificatn 3. locality of reference
4. DMA 4. subword parallelism 4. CPU, ALU? 4. Merits-Booth’s algo 4. MIPS exec steps 4. Multi threading 4. LOR types
5. Speculation 5. R-Type instructions 5. Control Unit? 5.Exception- types 5. MIPS instrn formats 5. parallelism 5. techniques-improveCache
6. Exception? 6.BranchPrediction Buffer 6. ResponseTime/ThruPut 6. IEEE- single precision 6. datapath 6. ILP 6. CPU execution time
7. Flynn’s classification 7. strong,weak scaling 7. CPU Time 7. iEEE double precision 7. PC 7. LLP 7. VM
8. Multithreading 8. UMA / NUMA 8. Power Wall 8. represent a floating pt 8. Hazard? 8. types of dependencies 8. TLB
9. Programmed,Interrupt I/O 9. need-memory hierarchy 9. Multiprocessor s/ms 9. subword parallelism 9. Types of hazard 9. data hazard types 9. DMA
10. Dirty Bit 10. DMA-improve speed 10. Instrn, instrn Set 10. overflow in sub 10. exception? 10. IPC 10. interrupts
11. instruction format? 11. overflow, underflow 11. pipelining, stages 11. ways to implement HMT 11. Exception, types
12. logical instrns 12. big/ little endian 12. 12. Adv-Multithreading 12. functions of IOP
13. Control operations 13. CLA- advantages 13. multicore processors 13. programmed I/O, DMA
14. PC relative addressin
15. Moore’s Law
16. Amdahl’s Law
Part-B Part-B Part-B Part-B Part-B Part-B Part-B
11.a.i. AddressingMode 11.a. instructions 1. 8 ideas 1. n-bit adder 1. Datapath, its control 1. Flynn’s classification 1. memory technologies
11.a.ii.exec Time pblm 11.b. addressing modes 2. performance Eqn 2. CLA 2. hazard, types 2. HMT types 2. cache policies
11.b.i. components 12.a.sequential Multipln 3. instruction format? 3. sequential multiplicatn 3. except handlng in MIPS 3. ILP, enhance performance 3. cache mapping techniq
11.b.ii. perfrmnce eqn 12.b.Floating pt addition 4. logical instructions 4. booth’s recoding 4. pipelined datapath 4. Multicore processors 4. VM
12.a.i. booth bit pair recoding 13.a. Hazard types, Ex 5. addressing modes 5. booth’s multiplicatn 5. pipelined control 5. types ofdependences 5. TLB
12.a.ii. CLA 13.b.Exception handling 6. addressingmode-pblm 6. booth’s bit pair recoding 6. types of data hazards 6. programmed I/O
12.b. Restore/NonRestore Div 7. parallel processing challenges
14.a.Flynn’s classificatn 7.components of comptr 7. restoring/ NR division 7. DMA
13.a. Data path & Control 14.b. HMT,types 8. IEEE single, doubl precision 8. DMA transfer modes
13.b. Hazard? Types 15.a. memory technolog 9. bus arbitration tech
14.a. ILP, challenges 15.b.VM, addr translatn 10. interrupts
14.b.iMulticoreProcessor 11. IOP
14.b.ii. HMT
15.a.i. mapping functions
15.a.ii. bus arbitration
15.b.i. cache techniques
15.b.iiAny2 Std I/O i/face

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