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For systems based on Nettop Platform for ‘08 Revision 002 February 2009
Document Number: 320528-002
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1 Introduction ..............................................................................................................6 1.1 1.2 1.3 2 2.1 Intel® Atom™ Processor 300 Series Features ..........................................................6 Terminology .......................................................................................................7 References .........................................................................................................8 Clock Control and Low-power States .................................................................... 10 2.1.1 Thread Low-power State Descriptions........................................................ 11 18.104.22.168 Thread C0 State ....................................................................... 11 22.214.171.124 Thread C1/AutoHALT Powerdown State ........................................ 11 126.96.36.199 Thread C1/MWAIT Powerdown State............................................ 11 2.1.2 Package Low-power State Descriptions...................................................... 12 188.8.131.52 Normal State............................................................................ 12 2.1.3 Front Side Bus ....................................................................................... 12 FSB and GTLREF ............................................................................................... 14 Power and Ground Pins ...................................................................................... 14 Decoupling Guidelines ........................................................................................ 15 3.3.1 VCCP Decoupling .................................................................................... 15 3.3.2 FSB AGTL+ Decoupling ........................................................................... 15 Voltage Identification and Power Sequencing......................................................... 16 Catastrophic Thermal Protection .......................................................................... 17 Reserved and Unused Pins .................................................................................. 17 FSB Frequency Select Signals (BSEL[2:0]) ........................................................... 18 FSB Signal Groups ............................................................................................. 18 CMOS Asynchronous Signals ............................................................................... 20 Maximum Ratings.............................................................................................. 20 Processor DC Specifications ................................................................................ 21 AGTL+ FSB Specifications................................................................................... 25 Package Mechanical Specifications ....................................................................... 26 4.1.1 Package Mechanical Drawings .................................................................. 27 4.1.2 Package Loading Specifications ................................................................ 27 4.1.3 Processor Mass Specifications................................................................... 27 Processor Pinout Assignment............................................................................... 27 Signal Description ............................................................................................. 33 Thermal Specifications ....................................................................................... 42 5.1.1 Thermal Diode ....................................................................................... 43 5.1.2 Intel® Thermal Monitor........................................................................... 45 5.1.3 Digital Thermal Sensor ............................................................................ 47 5.1.4 Out of Specification Detection .................................................................. 47 5.1.5 PROCHOT# Signal Pin ............................................................................. 47
Low Power Features ................................................................................................ 10
Electrical Specifications ........................................................................................... 14 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12
Package Mechanical Specifications and Ball Information ......................................... 26 4.1
4.2 4.3 5 5.1
Thermal Specifications and Design Considerations .................................................. 42
Debug Tools Specifications ...................................................................................... 50
2-1 4-2 4-3 4-4 Thread Low-power States ........................................................................10 Package Mechanical Drawing ....................................................................27 Pinout Diagram (Top View, Left Side) ........................................................28 Pinout Diagram (Top View, Right Side) ......................................................29
2-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 4-12 4-13 5-14 5-15 5-16 Coordination of Thread Low-power States at the Package Level.....................11 Voltage Identification Definition ................................................................16 Processor VID Pin to VRD11 VID Pin Mapping .............................................17 BSEL[2:0] Encoding for BCLK Frequency ....................................................18 FSB Pin Groups ......................................................................................19 Processor Absolute Maximum Ratings ........................................................20 Voltage and Current Specifications for the processor....................................21 FSB Differential BCLK Specifications ..........................................................22 AGTL+/CMOS Signal Group DC Specifications .............................................23 Legacy CMOS Signal Group DC Specifications .............................................24 Open Drain Signal Group DC Specifications ................................................24 Pinout Arranged By Signal Name...............................................................30 Signal Description ...................................................................................33 Power Specifications for the Standard Voltage processor ..............................43 Thermal Diode Interface ..........................................................................44 Thermal Diode Parameters using Transistor Model.......................................44
Revision Number -001 -002 • Initial Release • Update pin-map • Add SSSE3 • Changed A[35:2] to A[32:2] • Changed Vboot • Changed Ron and Rodt • Removed L2 Dynamic Cache Sizing Description Date September 2008 February 2009
listen. • New dual-core processor for nettop PCs with enhanced performance • On die.1 Intel® Atom™ Processor 300 Series Features • Available at 1. primary 32-kB instructions cache and 24-kB write-back data cache. 8-way L2 cache.Introduction 1 Introduction The Intel® Atom™ processor 330 series is built on 45-nanometer Hi-k process technology. per core: total of 1 MB cache • Support for IA-32 and Intel® 64 architecture • Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3) support • Micro-FCBGA8 packaging technologies • Thermal management support using TM1 • FSB Lane Reversal for flexible routing • Supports C0 and C1 states only • Execute Disable Bit support for enhanced security This processor series represents a new family of processors designed from the groundup on a ground-breaking new low-power microarchitecture. 1.6 GHz. share. 6 Datasheet . Note: In this document. Intel chipsets shall be referred as GMCH and ICH respectively. watch. and learn. mechanical and thermal specifications for the processor. play. the Intel Atom processor 330 series will be referred to as the processor. This document contains electrical. This processor series enables a new class of simple and affordable internet-centric computers called “antelopes” that is best suited for applications focused on internet usage models—communicate. It is manufactured on industry-leading 45-nm process with Hi-K Metal Gate technology. per core • 533-MHz Source-Synchronous front side bus (FSB) • Threading enabled • On die 512-kB.
unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. L= Low logic level). Upon exposure to “free air” (i. For example. Used to refer to Assisted GTL+ signaling technology on some Intel processors. Advanced Gunning Transceiver Logic. in a tray. Thermal Design Power The processor core power supply Voltage Regulator The processor ground Front Side Bus (FSB) AGTL+ CMOS Storage Conditions Processor Core Intel® 64 Technology TDP VCC VR VSS Datasheet 7 .e. processor landings should not be connected to any supply voltages. have any I/Os biased or receive any clocks. Conversely. the “#” symbol implies that the signal is inverted. D[3:0] = “HLHL” refers to a hex ‘A’. All AC timing and signal integrity specifications are at the pads of the processor core. Refers to a non-operational state. or loose. Complementary metal-Oxide semiconductor. and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level. when RESET# is low. Under these conditions. The processor may be installed in a platform. a nonmaskable interrupt has occurred. Processor core die with integrated L1 and L2 cache. For example. a reset has been requested. when NMI is high. Refers to the interface between the processor and system core logic (also known as the GMCH chipset components). indicating a signal is in the active state when driven to a low level.2 Terminology Term # Definition A “#” symbol after a signal name refers to an active low signal.. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data). Processors may be sealed in packaging or exposed to free air.Introduction 1. 64-bit memory extensions to the IA-32 architecture.
pdf http:// www.htm § 8 Datasheet . Intel® Processor Identification and CPUID Instruction Application Note Voltage Regulator-Down (VRD) 11.0 .com/ design/processor/ applnots/ 241618.Introduction 1.pdf www.com/ design/processor/ designex/ 319979.htm Intel® Atom™ Processors 200 Series Thermal and Mechanical Design Guidelines AP-485.intel. N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide http:// www.intel.intel.htm http:// www.3 References Material and concepts available in the following documents may be beneficial when reading this document: Document Intel® Atom™ Processors 200 Series Specification Update Document Number www.com/ products/processor/ manuals/index.com/ design/processor/ applnots/ 313214.Processor POwer Delivery Design Guidelines Intel® 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference.intel.intel.com/ design/processor/ specupdt/ 319978. A-M Volume 2B: Instruction Set Reference.
Introduction Datasheet 9 .
Low Power Features 2 2. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. Figure 2-1 shows the thread low-power states. Figure 2-1. The monitor address does not need to be setup before using the P_LVLx I/O read interface. A thread may independently enter the C1/AutoHALT and C1/MWAIT low power states. NMI. Package low power states include Normal. or APIC interrupt core state break = (halt break OR Monitor event) 10 Datasheet . The sub-state hints used for each P_LVLx read can be configured in a software programmable MSR. PREQ#. RESET#.1 Low Power Features Clock Control and Low-power States The processor supports low power states at the thread level and the package level. Stop Grant. MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. Table 2-1 provides a mapping of thread low-power states to package low power states. INTR. When both threads are in a common low-power state the central power management logic ensures the entire processor enters the respective package low power state by initiating a P_LVLx I/O read to the chipset. Thread Low-power States C1/ MWAIT Core state break C1/Auto Halt HLT instruction MWAIT(C1) Halt break C0 halt break = A20M# transition. and Stop Grant Snoop. SMI#. The processor implements two software interfaces for requesting low power states. INIT#.
Coordination of Thread Low-power States at the Package Level Thread State C0 C1 1 Package State2 C0 Normal Normal C11 Normal AutoHalt NOTES: 1. The processor thread will transition to the C0 state upon occurrence of SMI#. N-Z. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals.1. While in AutoHALT Powerdown state. INIT#. 2. the processor threads will process bus snoops and snoops from the other thread.1. Datasheet 11 . The processor will enter a snoopable sub-state (not shown in Figure 2-1) to process the snoop and then return to the AutoHALT Powerdown state. Volume 2A: Instruction Set Reference. 2.1.2 Thread C1/AutoHALT Powerdown State C1/AutoHALT is a low-power state entered when a thread executes the HALT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the C0 state. the package state will resolve to the highest power C state.Low Power Features Table 2-1. 2. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals. RESET# will cause the processor to immediately initialize itself. 2. for more information.1.1. Volume 3A/3B: System Programmer's Guide for more information.1.3 Thread C1/MWAIT Powerdown State C1/MWAIT is a low-power state entered when the processor thread executes the MWAIT(C1) instruction. A-M and Volume 2B: Instruction Set Reference.1 Thread Low-power State Descriptions Thread C0 State This is the normal operating state for threads in the processor. or FSB interrupt messages. both threads must be in a common low power state. INTR). AutoHALT or MWAIT/C1. To enter a package state.1. If the threads are not in a common low power state. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state.1 2. LINT[1:0] (NMI.
2.1. where the data and address busses and the strobe signals are operating in GTL mode.3 Front Side Bus The processor has only one signaling mode. C1/AutoHALT. For cases when only one thread is in a low power state. The reason to use GTL is to improve signal integrity. The processor remains in the Normal state when the threads are in the C0. or C1/MWAIT state.1. 2.Low Power Features 2.1 Normal State This is the normal operating state for the processor.2 Note: Package Low-power State Descriptions The following state descriptions assume that both threads are in the a common low power state. please see Section 2.1. § 12 Datasheet .1.1. 2.
Low Power Features Datasheet 13 .
The AGTL+ inputs.10 V (nominal). absolute maximum ratings. All power pins must be connected to VCCP power planes while all VSS pins must be connected to system ground planes. The processor VCCP pins must be supplied the voltage stated in Table 3-7 14 Datasheet . The AGTL+ bus depends on incident wave switching. only AGTL+ is used. The appropriate chipset will also provide on-die termination. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (VTT). Timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. GTLREF_EA) that is used by the receivers to determine if a signal is a logical 0 or a logical 1.1 FSB and GTLREF The processor supports two kinds of signalling protocol: Complementary Metal Oxide Semiconductor (CMOS). For FSB data and address bus. 3. Use of multiple power and ground planes is recommended to reduce I*R drop.2 Power and Ground Pins For clean. is highly recommended when designing a system. signal integrity and platform design methods have become more critical than with previous processor families. The termination voltage level for the processor CMOS and AGTL+ signals is VTT = 1. including trace lengths. 3. Due to speed improvements to data and address bus. including timing diagrams. The chapter also includes DC and AC specifications. including the sideband signals listed in Table 3-5. Analog signal simulation of the FSB.Electrical Specifications 3 Electrical Specifications This chapter contains signal group descriptions. require a reference voltage (GTLREF_MA. GTLREF_* must be generated on the system board. voltage identification and power sequencing. on-chip power distribution. The CMOS sideband signals are listed in Table 3-5. VCCP (power) and VSS (ground) inputs. thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. and Advanced Gunning Transceiver Logic (AGTL+). the processor will have a large number of VTT (FSB AGTL+ reference voltage).
Datasheet 15 . such as electrolytic capacitors. refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. 3. 3. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.0 Processor Power Delivery Design Guidelines.3.3. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 3-7. Failure to do so can result in timing violations or reduced lifetime of the component. Larger bulk storage. For further information and design guidelines. the processor is capable of generating large average current swings between low and full power states. Bulk decoupling for the large current swings when the part is powering on.Electrical Specifications 3. or entering/exiting low-power states.1 VCCP Decoupling VCC regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. supply current during longer lasting changes in current demand by the component. such as coming out of an idle condition. refer to the Voltage Regulator-Down (VRD) 11.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds. they act as a storage well for current when entering an idle condition from a running condition. must be provided by the voltage regulator solution For more details on decoupling recommendations. Similarly.2 FSB AGTL+ Decoupling The processors integrate signal termination on the die.
Table 3-2 specifies the voltage level corresponding to the state of VID[6:0]. to support automatic selection of power supply voltages. For more details about VR design to support the processor power supply requirements.9125 0.0375 1.9500 VID 6 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID 5 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID 4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID 3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID 2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 3-2.7875 0.7750 0.0000 0.8000 0.0500 1.0750 1.0125 1.7250 0.0 Processor Power Delivery Design Guidelines.0625 1.7375 0.7125 0.9250 0.VID[6:0].9000 0.8875 0.1750 1.9375 0.0 Processor Power Delivery Design Guidelines. 16 Datasheet .7500 0.Voltage Regulator-Down (VRD) 11. VRD11 VID should be tied to Vss.9875 0. The processor uses seven voltage identification pins.9750 0. A “1” in this refers to a high-voltage level and a “0” refers to low-voltage level.7625 0.8750 0.0875 1.1500 1.Electrical Specifications 3.1000 1.8125 0. Refer to the Voltage Regulator-Down (VRD) 11.4 VID 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Voltage Identification and Power Sequencing VID 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID 3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID 2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.8625 0.1375 1.7000 The VID specification for the processor is defined by the RS .1125 1. VRD11 has 8 VID pins (VID[7:0]) compared to 7 VID pins for processor.8250 0.2000 1.8500 0. Voltage Identification Definition VCC (V) 0.9625 0.1250 1.1875 1. VRD11 VID[n] should be connected to processor VID[n-1]. The VID pins for processor are CMOS outputs driven by the processor VID circuitry.8375 0.1625 1.0250 1.
VSS. See section Chapter 4. or if the THERMTRIP# signal is asserted. leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted. always connect unused inputs or bidirectional signals to an appropriate signal level. Unused outputs can be left unconnected. Unused active high inputs should be connected through a resistor to ground (VSS). For reliable operation. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum). 3. Connection of these pins to VCC. which halts all processor internal clocks and activity. or to any other signal (including each other) can result in component malfunction or incompatibility with future processors.6 Reserved and Unused Pins All RESERVED (RSVD) pins must remain unconnected.5 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. Datasheet 17 . Even with the activation of THERMTRIP#. 3.2 for a pin listing of the processor and the location of all RSVD pins. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Processor VID Pin to VRD11 VID Pin Mapping Processor VID pin 6 5 4 3 2 1 0 map to VRD11 VID pin 7 6 5 4 3 2 1 0 (tie to VSS) Power source characteristics must be stable whenever the supply to the voltage regulator is stable. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures.Electrical Specifications Table 3-3. the VCCP supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor.
AGTL+ input signals have differential input buffers. HITM#. the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Table 3-5 identifies which signals are common clock. “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. In this document. These signals should be connected to the clock chip and the appropriate chipset on the platform. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. Similarly. Asychronous signals are still present (A20M#.7 FSB Frequency Select Signals (BSEL[2:0]) Only 133 MHz is supported by the processor. which use GTLREF as a reference level.Electrical Specifications 3. etc. and asynchronous. BSEL[2:0] Encoding for BCLK Frequency BSEL L BSEL L BSEL H BCLK Frequency 133 MHz NOTE: All other bus selections reserved. The BSEL[2:0] signals need to be set accordingly to select the frequency of the processor input clock (BCLK[1:0]). One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#. the FSB signals have been combined into groups by buffer type. IGNNE#. HIT#.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. source synchronous. etc. 3.8 FSB Signal Groups To simplify the following discussion.) and can become active at any time during the clock cycle. Table 3-4. The BSEL encoding for BCLK[1:0] is shown in Table 3-4. 18 Datasheet .
DINV# D[47:32]#. DRDY#. DBSY#. BPM[3:0]#. VTT. SMI# FERR#. VCCA.Electrical Specifications Table 3-5. DINV# D[63:48]#. A[16:3]# A[32:17]# D[15:0]#. PRDY#. BNR#. DPWR# ADS#. In processor systems where there is no debug port implemented on the system board. DSTBN0# DSTBP1#. DBI3#. these signals are used to support a debug port interposer. THERMDA. DBI2#. these signals are no connects. In systems with the debug port implemented on the system board. 2. DINV# D[31:16]#. 4. HITM#. FSB Pin Groups Signal Group AGTL+ Common Clock Input AGTL+ Common Clock I/O AGTL+ Source Synchronous I/O Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Synchronous to assoc. Refer to Chapter 4 for signal descriptions and termination requirements. BPM_2[3:0]. DSTBP[3:0]#. DSTBN3# AGTL+ Strobes CMOS Input Open Drain Output Open Drain I/O CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock ADSTB[1:0]#. DSTBN1# DSTBP2#. RS[2:0]#. BR0#. Datasheet 19 . VSS_SENSE. BSEL[2:0] TCK. refer to your Platform Design Guidelines for up to day recommendations. IERR# PROCHOT# VID[6:0]. TEST2/DCLK. THERMDC. INIT#. TDI. 3. DBI1#. TMS. COMP_2[3:0]. GTLREF_EA. RESET#. VCC_SENSE. VCCP. DSTBN[3:0]# IGNNE#. Signals REQ[4:0]#. LINT0/INTR. PROCHOT# signal type is open drain output and CMOS input. DEFER#. TRDY#. TEST1/ACLK. HIT#. VCCQ[1:0]. strobe Signals1 BPRI#. THRMDC_2 NOTES: 1. DBI0#. THERMTRIP#. DINV# Associated Strobe ADSTB0# ADSTB1# DSTBP0#. TDI_M TDO. PREQ#. VSS. TDO_M BCLK[1:0] COMP[3:0]. LINT1/NMI. DSTBN2# DSTBP3#. PWRGOOD. TRST#. On die termination differs from other AGTL+ signals. GTLREF_MA. LOCK#. THRMDA_2.
2 V but the parameter can change (burnin voltage is higher). See Section 3. 3. At conditions exceeding absolute maximum and minimum ratings. 3. At conditions outside functional operation condition limits. neither functionality nor long term reliability can be expected. IERR# and other non.1 Unit °C V V V V Notes1. neither functionality nor long term reliability can be expected. Although the processor contains protective circuitry to resist damage from static electric discharge. The VCC max supported by the process is 1.5 2. Storage within these limits will not affect the long term reliability of the device. but within absolute maximum and minimum ratings.9 CMOS Asynchronous Signals CMOS input signals are shown in Table 3-5. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits.4 6 NOTES: 1. Legacy output FERR#.3. the processor must not receive a clock.1 Max 85 1. 5. 4.1 1. Table 3-6. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. functionality and long-term reliability can be expected. mechanical and thermal specifications must be satisfied. Failure to adhere to this specification can affect the long term reliability of the processor. Storage temperature is applicable to storage conditions only. if a device is subjected to these conditions for any length of time then. Processor Absolute Maximum Ratings Symbol TSTORAGE VCCP VCCA VinAGTL+ VinAsynch_CMOS Parameter Processor Storage Temperature Any Processor Supply Voltage with Respect to VSS PLL power supply AGTL+ Buffer DC Input Voltage with Respect to VSS CMOS Buffer DC Input Voltage with Respect to VSS Min -40 -0.11 for the DC specifications for the CMOS signal groups. For functional operation.575 1. refer to the processor case temperature specifications. 20 Datasheet .1 -0. However.Electrical Specifications 3.1 1.AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. it will either not function or its reliability will be severely degraded. but within the absolute maximum and minimum ratings. but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. This rating applies to the processor and does not include any tray or packaging. signal quality.3 -0. when returned to conditions within the functional operating condition limits. Within functional operation limits. For functional operation. precautions should always be taken to avoid high static voltages or electric fields. In this scenario. all of the CMOS signals are required to be asserted for more than 4 BCLKs for the processor to recognize them. Moreover.3 -0.10 Maximum Ratings Table 3-6 specifies absolute maximum and minimum ratings. and no lands can be connected to a voltage bias. 2. the device may be functional. all processor electrical.
5 1. The DC specifications for these signals are listed in Table 3-9. Refer to the RS . See Chapter 4 for the pin signal definitions and signal pin assignments. Care should be taken to read all notes associated with each parameter. Specified at the nominal VCC. Not 100% tested.425 1.Electrical Specifications 3. 2. Specified by design/ characterization at nominal VCC.10 1. 5 Parameter Min 132.20 1. 7. 2 4. 6. 4. Specified at 90°C TJ. Unless otherwise noted. Table 3-9 through Table 3-11 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature. Individual Datasheet 21 .0 . Table 3-7.05 0. 2 1. and input voltages.6 1.20 1.5 8 A 3 Unit MHz V V V V A 3 8 10 Notes6 ICC Auto-Halt VCC Power Supply Current Slew Rate at Processor Package Pin (Estimated) ICC for VCCA Supply NOTES: 1. Most of the signals on the FSB are in the AGTL+ signal group.Voltage Regulator-Down (VRD) 11. clock frequency.10 Max 133.15 1. Measured at the bulk capacitors on the motherboard. dICC/dt ICCA Core Frequency/Voltage 1. all specifications for the processor are at TJ = 90°C. Based on simulations and averaged over the duration of any change in current.Processor Power Delivery Design Guidelines for design target capability. These specifications will be updated with characterized data from silicon measurements at a later date. 3.7 1.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. Unless specified otherwise. Voltage and Current Specifications for the processor Symbol FSB Frequency VTT VCCP VCC BOOT VCCA ITT ICCDES ICC BCLK Frequency FSB AGTL+ termination voltage with respect to VSS Vcc Core voltage with respect to VSS Default VCC voltage for initial power up PLL Supply voltage ICC for VTT supply after VCC stable ICC for VTT supply at startup ICC for processors recommended design target (estimated) ICC for processors Processor Number 330 IAH.33 1.5 Typ 133.575 1. DC specifications for the CMOS group are listed in Table 3-10. 5. VCCP is determined by processor VID[6:0] pins.6 GHz @ VCC (AVID controlled) 8 4 5 260 A A A/µs mA 1.5 2. all specifications in this table are based on estimates and simulations or empirical data. which is set at manufacturing and can not be altered. Each processor is programmed with a maximum valid voltage identification value (VID).
ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2. 9 2. 8 2. no “Maximum DC test (Current I_DC_MAX)”.55 140 Unit V V V mV mV µA pF Figure Notes1 7. 7.3 0. “current step rise time (I_RISE) of 5A/us” +/.50mV. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. “Steady state” voltage. 22 Datasheet .15 -0.50 mV tolerance Table 3-8. Since processor is soldered down with no loadline and no dynamic VID. 9. 8. 6. “Voltage Regulator Thermal Design Current (VR_TDC) of 3. no “maximum overshoot time duration above VID (OS_TIME)”.Refer to VID Table 3-2 for the specific voltages corresponding to VID[6:0] codes. 7. 3. 7.3 Min Typ Max 1. 5.2 1. Only applies to the differential rising edge (clock rising and clock# falling). Measurement taken from differential waveform. no “maximum overshoot above VID (OS_AMP)”. Cpad includes die capacitance only. This is the Vcc range. inclusive of ripple. no “thermal compensation voltage drift (THERMAL_DRIFT)”. all specifications in this table apply to all processor frequencies.0 0. 10. 9. not the absolute Vcc for the core. maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within VID range. The Vccp tolerance should be +/. VR tolerance and transient (droop and overshoot). 5 6 3 4 NOTES: 1. no “minimum DC test *(Current I_DC_MIN)”. Measurement taken from single-ended waveform.64A. 2. not including Overshoots or Undershoots. 8 7. No package parasitics are included. 4. For Vin between 0 V and VIH. no “peak to peak ripple amplitude (RIPPLE)”. there is no “socket load line slope (SKT_LL)”.45 +5 2.Electrical Specifications 8. no “socket load line tolerance band” but only “Tolerance Band (TOB)” of 50mV. FSB Differential BCLK Specifications Symbol VIH VIL VCROSS ΔVCROSS VSWING ILI Cpad Parameter Input High Voltage Input Low Voltage Crossing Voltage Range of Crossing Points Differential Output Swing Input Leakage Current Pad Capacitance 300 -5 1. Unless otherwise noted.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. Refer to processor I/O buffer models for I/V characteristics.25 50. 4.10 -0. 11. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver.10 0. all specifications in this table apply to all processor frequencies. 7.31*VCCP.Electrical Specifications Table 3-9.58 VTT Max 1. AGTL+/CMOS Signal Group DC Specifications Symbol VTT GTLREF_EA GTLREF_MA RCOMP Parameter I/O Voltage GTL Reference Voltage.4 5 6 Min 1.10 VTT-0.10 GTLREF-0.5 ±100 2.33*VTT. 10. However. 8. input signal drivers must comply with the signal quality specifications.15 Unit V V V Ω Notes1 11 5. middle-agent Compensation Resistor COMP & COMP COMP & COMP RODT VIH VIL VOH RTT RON (GTL mode) ILI Cpad Termination Resistor Input High Voltage Input Low Voltage Output High Voltage Termination Resistance GTL Buffer on Resistance Input Leakage Current Pad Capacitance 1. endagent GTL Reference Voltage.5 25 50 55 VTT 0 VTT 50 8.10 VTT 55 25. 2. measured at 0.63 VTT 0. 12. 9.75 VTT+0. Datasheet 23 . GTLREF should be generated from VTT with a 1% tolerance resistor divider. 5. VIH and VOH may experience excursions above VTT. RTT is connected to VCCP on die. 6.5 Ω V V V Ω Ω µA pF 7 8 10 3. Measured at 0. RCOMP resistance must be provided on the system board with 1% resistors. GTLREF_EA & GTLREF_MA resistor divider needs to be separate.1 GTLREF+0.10 45 24.5 2. 11 NOTES: 1.75 49. 13 9. This is for better FSB margin. 13 5. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 12.8 2. No package parasitics are included. Cpad includes die capacitance only. Vin between 0 and VTT. Unless otherwise noted. On die termination resistance. 12. Specified with on die RTT and RON are turned off. 3.05 Typ 1. The VTT referred to in these specifications is the instantaneous VTT. This is the external resistor on the comp pins.
6. The VTT referred to in these specifications refers to instantaneous VTT. 4.6 0.10 0.1 0.9*VTT -0.95 2. For Vin between 0 V and VOH.1 1. Cpad includes die capacitance only.45 Unit V V mA µA pF 2 4 5 Notes1 3 NOTES: 1. No package parasitics are included.Legacy CMOS Signal Group DC Specifications Symbol VTT VIH VIL VOH VOL IOH IOL ILI Cpad1 Cpad2 Parameter I/O Voltage Input High Voltage Input Low Voltage CMOS Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current Pad Capacitance Pad Capacitance for CMOS Input 1.10 VTT 0.2 Min 1.Electrical Specifications Table 3-10.55 1. Table 3-11. 24 Datasheet . Cpad2 includes die capacitance for all other CMOS input signals. Cpad1 includes die capacitance only for DPRSTP#.9*VTT.2 V.15 VTT+0. all specifications in this table apply to all processor frequencies. Measured when the driver is tri-stated. 3. For Vin between 0V and VTT.1*VTT 4. 7. No package parasitics are included. Unless otherwise noted. PWRGOOD. Measured at 0.3*VTT VTT+0. 2. No package parasitics are included.45 Unit V V V V V mA mA µA pF Notes1 9 2 2.1 0. Measured at 0. 3.1*VTT. 5. DPSLP#.05 0.2 Min VTT-5% 0 16 Typ VTT Max VTT+5% 0. Unless otherwise noted. 2. all specifications in this table apply to all processor frequencies.7*VTT -0.5 1. 3 2 2 5 4 6 7 8 NOTES: 1. 4.9 2.1 4. VOH is determined by value of the external pull-up resistor to VTT.00 VTT 0 Max 1. 5.10 1. Refer to platform design guide for details. Measured at 0.20 50 ±200 2.Open Drain Signal Group DC Specifications Symbol VOH VOL IOL ILO Cpad Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance 1.1 ± 100 2.5 Typ 1.
Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation). For more details on platform design.controlled. as these are integrated into the processor silicon. The AGTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. see the appropriate platform design guides. It is important that the system board impedance is held to the specified tolerance. Termination resistors are not required for most AGTL+ signals.12 AGTL+ FSB Specifications Routing topology recommendations may be found in the appropriate platform design guides. Table 3-9 lists the GTLREF specifications. and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well.Electrical Specifications 3. § Datasheet 25 .
pinout assignments. and signal description. 26 Datasheet . 4.1 Package Mechanical Specifications The processor will be available in 512 kB. 437 pins in FCBGA8 package.Package Mechanical Specifications and Ball Information 4 Package Mechanical Specifications and Ball Information This chapter provides the package specifications.
4.Package Mechanical Specifications and Ball Information 4.1.2 Processor Pinout Assignment Figure 4-3 and Figure 4-4 are graphic representations of the processor pinout assignments.8g.2 Package Loading Specifications Package loading is 10lb max static compressive.3 Processor Mass Specifications Processor mass is 1. 4.1.1 Package Mechanical Drawings Figure 4-2. Datasheet 27 . Table 4-12 lists the pinout by signal name.1. Package Mechanical Drawing 4.
Package Mechanical Specifications and Ball Information Figure 4-3. Pinout Diagram (Top View. Left Side) 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 VSS VSS RSVD VSS D# D# VSS D# D# VSS DINV VSS D# D# VSS COMP D# VSS VSS VSS VSS D# D# DSTBN D# D# D# D# RSVD D# D# D# VSS VSS D# D# RSVD THRMDA D# VSS DINV VSS THRMDC VSS BSEL BSEL VSS BPM_2 COMP_2 VSS D# D# D# GTLREF_EA VSS VSS BPM_2 BPM2 BSEL VSS VSS EXTBGREF RSVD VSS RSVD RSVD VSS VSS D# DINV D# 6 GTLREF_ MA CMREF D# VCCA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D# D# VSS 7 VSS VSS VSS VSS VSS VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VSS VSS D# VCCQ0 VCCQ0 VTT VTT VTT VTT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT RSVD VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VSS VTT VTT VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VSS VTT VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VSS VTT RSVD VSS VCCSE NSE VSSSE NSE VTT VTT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VSS D# D# A # A # A # VSS VTT VTT VCCQ 1 VCCQ 1 VTT VTT VTT VTT VTT VTT VTT VTT VTT VSS VSS DSTB N A B B C C D D E F G E F G DSTBP THRMDC_2 D# VSS D# THRMDA_2 VSS IGNNE# BPM_2 VSS RSVD H H J K L M N P R T U V W Y J K L M N P R T U V W Y DSTBN DSTBP D# D# D# D# D# COMP D# D# D# VSS VSS VSS D# D# VSS D# D# VSS D# D# D24# VSS 3 COMP_2 COMP_2 COMP_2 RSVD VSS DPWR# VSS D# DSTBN VSS 4 RSVD VSS RSVD RSVD RSVD VSS DSTBP D# 5 BCLK BCLK VSS D# D# 11 D# D# VSS 12 D# D# D# D# VSS 10 AA D# D# 8 9 D# D# AA 13 14 1 2 28 Datasheet .
Package Mechanical Specifications and Ball Information Figure 4-4. Pinout Diagram (Top View. Right Side) 15 A B C D E F G H J K L M N P R T U V W Y AA 16 17 18 19 20 21 A VSS A# A# RESET# VSS VID VID BPM# BPM# VSS RSVD TDI_M FORCEPR# VSS LINT1 LINT0 VSS BR1# D# DSTBP VSS 15 A# A# A# VID VSS IERR# VID VSS PREQ# TRST# TDO_M TDO TDI VSS STPCLK# FERR# VSS INIT# DINV D# D# 16 A# A# VSS RSVD VID VSS PROCHOT# THERMTRIP# VSS BPM# TMS TCK VSS RSVD DPSLP# RSVD SMI# PWRGOOD VSS RS# HIT# 17 VSS A# A# VSS VID VSS VID VSS BPM# PRDY# VSS RSVD SLP# VSS DPRSTP# VSS A20M VSS RS# DBSY# VSS 18 RSVD ADSTB# A# A# VSS A# REQ# VSS A# A# VSS A# A# VSS REQ# DRDY# VSS ADS TRDY# BNR# VSS 19 VSS VSS A# A# A# COMP A# A# A# ADSTB# A# A# A# REQ# A# BR0# RS# HITM# LOCK# VSS VSS 20 21 VSS RSVD VSS A# COMP VSS A# REQ# VSS A# VSS REQ# A# VSS DEFER# BPRI# VSS VSS VSS B C D E F G H J K L M N P R T U V W Y AA Datasheet 29 .
Package Mechanical Specifications and Ball Information Table 4-12.Pinout Arranged By Signal Name (Sheet 1 of 4) Signal Name A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A# A20M# RSVD ADS# ADSTB# Ball # M19 H21 L20 M20 K19 J20 L21 C19 F19 E21 A16 D19 C14 C18 C20 E20 D20 B18 C15 B16 P21 B17 C16 A17 B14 B15 A14 H20 N20 R20 J19 N19 G20 U18 U5 V19 K20 Signal Name BCLK BCLK BNR# BPM# BPM# BPM# BPM# BPRI# BR0# BR1# BSEL BSEL BSEL COMP COMP COMP COMP D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# Ball # V11 V12 Y19 K17 J18 H15 J15 U21 T20 V15 J6 H5 G5 T1 T2 F20 F21 Y11 W10 W15 AA13 Y16 W13 AA9 W9 AA5 Y8 W3 U1 Y12 W7 W6 Y7 AA6 Y3 W2 V3 Signal Name D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# D# Ball # T3 AA8 AA14 V2 W4 R3 R2 P1 N1 M2 P2 J3 N3 AA11 G3 H2 N2 L2 M3 J2 H1 J1 C2 G2 W12 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 AA16 B3 Signal Name D# D# D# D# D# DBSY# RSVD DEFER# DINV# DINV# DINV# DINV# DPRSTP# DPWR# DRDY# DSTBN# DSTBN# DSTBN# DSTBN# DSTBP# DSTBP# DSTBP# DSTBP# FERR# FORCEPR# GTLREF_MA HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# RSVD GTLREF_EA BPM_2# Ball # C7 D2 Y10 Y9 Y13 Y18 V5 T21 W16 Y6 L1 C5 R18 U4 T19 Y14 Y4 K2 E2 Y15 Y5 K3 F3 T16 N15 A7 AA17 V20 F16 J4 V16 T15 R15 W20 P17 D6 G6 30 Datasheet .
Package Mechanical Specifications and Ball Information Table 4-12.Pinout Arranged By Signal Name (Sheet 2 of 4) Signal Name ADSTB# BPM_2# BPM_2# TDI_M TDO_M PRDY# PREQ# PROCHOT# PWRGOOD REQ# REQ# REQ# REQ# REQ# RESET# RS# RS# RS# RSVD DPSLP# RSVD RSVD CMREF RSVD RSVD RSVD RSVD RSVD RSVD RSVD VTT VTT VTT VTT SLP# SMI# STPCLK# Ball # B19 K4 K5 M15 L16 K18 J16 G17 V17 N21 J21 G19 P20 R19 D15 W18 Y17 U20 D17 R17 M18 T17 B7 A13 R6 N6 T6 A3 C1 C21 E13 E14 F13 F14 N18 U17 R16 Signal Name D# TDO EXTBGREF THERMTRIP# THRMDA THRMDC TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # U2 M16 M6 H17 E4 E5 L17 W19 K16 A10 A11 A12 B10 B11 B12 C10 C11 C12 D10 D11 D12 E10 E11 E12 F10 F11 F12 G10 G11 G12 H10 H11 H12 J10 J11 J12 K10 Signal Name D# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VTT VCCQ0 VCCQ0 VCCSENSE VID VID VID VID VID VID VID VSS VSS VSS VSS VSS RSVD VSS VSS VSS Ball # C4 L10 L11 L12 M10 M11 M12 N10 N11 N12 P10 P11 P12 R10 R11 R12 D7 V10 A9 B9 C13 F15 D16 E18 G15 G16 E17 G18 A2 A4 A8 A15 A18 A19 A20 B1 B2 Signal Name BPM_2# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS THRMDC_2 VSS VSS VSS VSS VSS VSS THRMDA_2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # H6 B13 B20 B21 C8 C17 D1 D5 D8 D14 D18 D21 E3 E6 E7 E8 E15 E16 E19 F4 F5 F6 F7 F17 F18 G1 G4 G7 G9 G13 G21 H3 H4 H7 H9 H13 H16 Datasheet 31 .
Pinout Arranged By Signal Name (Sheet 3 of 4) Signal Name TCK TDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS COMP_2 VSS VSS VSS VSS RSVD VSS VSS VSS VSS VSS VSS VSS VSS COMP_2 COMP_2 VSS VSS VSS VSS VSS Ball # M17 N16 J5 J7 J9 J13 J17 K1 K6 K7 K9 K13 K15 K21 L3 L4 L5 L6 L7 L9 L13 L15 L18 L19 M1 M5 M7 M9 M13 M21 N4 N5 N7 N9 N13 N17 P3 Signal Name VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # K11 K12 P7 P9 P13 P15 P16 P18 P19 R1 R5 R7 R9 R13 R21 T4 T5 T7 T9 T10 T11 T12 T13 T18 U3 U6 U7 U15 U16 U19 V1 V4 V6 V7 V8 V13 V14 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT Ball # B5 B8 W5 W8 W11 W14 W17 W21 Y1 Y2 Y20 Y21 AA2 AA3 AA4 AA7 AA10 AA12 AA15 AA18 AA19 AA20 D13 C9 D9 E9 F8 F9 G8 G14 H8 H14 J8 J14 K8 K14 L8 Signal Name VSS VSS VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT RSVD RSVD RSVD RSVD Ball # H18 H19 N8 N14 P8 P14 R8 R14 T8 T14 U8 U9 U10 U11 U12 U13 U14 V9 R4 M4 D4 32 Datasheet .Package Mechanical Specifications and Ball Information Table 4-12.
to ensure recognition of this signal following an input/output write instruction. All bus agents observe the ADS# activation to begin parity checking. Address strobes are used to latch A[32:3]# and REQ[4:0]# on their rising and falling edges. internal loop. In sub-phase 2. the current bus owner cannot issue any new transactions. These signals must connect the appropriate pins of both agents on the processor FSB. or deferred reply ID match operations associated with the new transaction. these pins transmit transaction type information. All FSB agents must receive these signals to drive their outputs and latch their inputs.3 Signal Description Table 4-13. In subphase 1 of the address phase. A[32:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. SignalsAssociated Strobe REQ[4:0]#. these pins transmit the address of a transaction.Signal Description (Sheet 1 of 8) Signal Name A[32:3]# Type I/O Description A[32:3]# (Address) defines a 232-byte physical memory address space. address decode. ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[32:3]# and REQ[4:0]# pins. A[16:3]#ADSTB# A[32:17]#ADSTB# BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the FSB frequency. Strobes are associated with signals as shown below. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. A20M# is an asynchronous signal. However. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. protocol checking. it must be valid along with the TRDY# assertion of the corresponding input/ output Write bus transaction. ADSTB[1:0]# I/O BNR# I/O 33 CDI/IBL Document # 379115 .Pinout Arranged By Signal Name (Sheet 4 of 4) Signal Name COMP_2 RSVD VSS Ball # P4 P5 P6 Signal Name VSS VSS VSS Ball # V18 V21 W1 Signal Name VTT VTT VTT Ball # L14 M8 M14 Signal Name Ball # 4. Assertion of A20M# is only supported in real mode. During a bus stall. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.Package Mechanical Specifications and Ball Information Table 4-12. A20M# I If A20M# (Address-20 Mask) is asserted. Address signals are used as straps which are sampled before RESET# is deasserted.
then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. BPM_2# BPRI# Type O I/O O I/O I Description BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. These signals provide a 64bit data path between the FSB agents. The data bus is released after DBSY# is deasserted. BPM[3:0]# should connect the appropriate pins of all FSB agents. BR[1:0]# BSEL[2:0] I/O O COMP[3:0]. Quad-Pumped Signal Groups Data GroupDSTBN#/DSTBP#DINV# D[15:0]#00 D[31:16]#11 D[47:32]#22 D[63:48]#33 Furthermore. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. When the DINV# signal is active. D[63:0]# I/O D[63:0]# (Data) are the data signals. unless such requests are part of an ongoing locked operation.The data driver asserts DRDY# to indicate a valid data transfer.Signal Description (Sheet 2 of 8) Signal Name BPM#. BPM_2# BPM#. the BSEL is fixed to operate at 133-MHz BCLK frequency. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. and must connect the appropriate pins on both agents. For processor. BPM_2#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. BPM_2# BPM#. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. COMP_2[3:0] PWR CDI/IBL Document # 379115 34 . the corresponding data group is inverted and therefore sampled active high. * BPM_2[3:0] refer to core #2. Refer to the platform design guide for more details on implementation. Refer to the platform design guide for more detailed information. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. It must connect the appropriate pins of both FSB agents. The priority agent keeps BPRI# asserted until all of its requests are completed. This signal must connect the appropriate pins on both FSB agents. Each group of 16 data signals corresponds to one DINV# signal. The following table shows the grouping of data signals to data strobes and DINV#. * COMP_2[3:0] refer to core #2. DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use.This includes debug or performance monitoring tools. the DINV# pins determine the polarity of the data signals. BPM#.Package Mechanical Specifications and Ball Information Table 4-13.
DPWR# is a control signal from the chipset used to reduce power on the processor data bus input buffers.Signal Description (Sheet 3 of 8) Signal Name DEFER# Type I Description DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. DSTBN# D[47:32]#DINV#. indicating valid data on the data bus. DPSLP# must be deasserted. DINV[3:0]# Assignment To Data Bus Bus SignalData Bus Signals DINV#D[63:48]# DINV#D[47:32]# DINV#D[31:16]# DINV# D[15:0]# DPSLP# I DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. DRDY# may be deasserted to insert idle clocks. This signal is not used for nettop platform 08 and tied to VTT. DRDY# (Data Ready) is asserted by the data driver on each data transfer. This signal is not used for nettop platform 08 and tied to VTT through a 1k Ohm resistor. DSTBP# D[63:48]#DINV#. DPSLP# is driven by the SCH chipset. This signal is not used for Nettop platform 08 and tied to VTT. This signal must connect the appropriate pins of both FSB agents.Package Mechanical Specifications and Ball Information Table 4-13. In order to return to the Sleep State. DSTBN# D[63:48]#DINV#. DPRSTP# must be deasserted. DPRSTP# is driven by the SCH chipset. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/ Output agent. SignalsAssociated Strobe D[15:0]#DINV#. SignalsAssociated Strobe D[15:0]#DINV#. In order to return to the Deep Sleep State. The bus agent will invert the data bus signals if more than half the bits. DSTBP# DINV[3:0]# I DPRSTP# I DPWR# I DRDY# I/O DSTBN[3:0]# I/O 35 CDI/IBL Document # 379115 . DSTBP# D[31:16]#DINV#. The DINV[3:0]# signals are activated when the data on the data bus is inverted. DSTBN# D[31:16]#DINV#. within the covered group. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. In a multi-common clock data transfer. would change level in the next cycle. DSTBN# DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. DSTBP# D[47:32]#DINV#. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. DPRSTP# when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state.
refer to the platform design guide. an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor. GTLREF_MA PWR GTLREF_EA HIT# HITM# I/O IERR# O 36 Datasheet . This transaction may optionally be converted to an external error signal (e. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. refer to Volume 3 of the Intel® 64 and IA-32 Architectures Software Developer's Manuals and the Intel® Processor Identification and CPUID Instruction Application Note.type floating-point error reporting. GTLREF End Agent. it will remain asserted until STPCLK# is deasserted. which can be continued by reasserting HIT# and HITM# together. For termination requirements. GTLREF_MA should have separate voltage divider resistor network to set the right reference voltage and cannot share the voltage divider resistor network with GTLREF_EA. GTLREF Middle Agent. When FERR#/PBE# is asserted. Refer to the platform design guide for details on GTLREF implementation.. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. When STPCLK# is not asserted.g. indicating a break event. For additional information on the pending break event functionality. FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error.Package Mechanical Specifications and Ball Information Table 4-13.Signal Description (Sheet 4 of 8) Signal Name FERR#/PBE# Type O Description FERR# (Floating-point Error)/PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. IERR# (Internal Error) is asserted by a processor as the result of an internal error. EXTBGREF should be set at 2/3 VTT. For termination requirements. CMREF EXTBGREF PWR PWR PWR CMREF should be set the same as GTLREF_*. or INIT#. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall. and is included for compatibility with systems using MSDOS*. including identification of support of the feature and enable/disable information. refer to the platform design guide. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. When STPCLK# is asserted. GTLREF_EA should have separate voltage divider resistor network to set the right reference voltage and cannot share the voltage divider resistor network with GTLREF_MA. Refer to the platform design guide for details on GTLREF implementation.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. and LINT1 becomes NMI. a maskable interrupt request signal. However. When the APIC is disabled. the LINT0 signal becomes INTR. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Probe Request signal used by debug tools to request debug operation of the processor. LOCK# PRDY# I/O O Probe Ready signal used by debug tools to determine processor debug readiness. Both signals are asynchronous. LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. Because the APIC is enabled by default after Reset. The processor continues to handle snoop requests during INIT# assertion. INIT# I INIT# (Initialization). If INIT# is sampled active on the active to inactive transition of RESET#. However. it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. to ensure recognition of this signal following an Input/Output Write instruction. resets integer registers inside the processor without affecting its internal caches or floating-point registers. PREQ# I Datasheet 37 . processor reverses its FSB data and address signals internally to ease mother board layout for systems where the chipset is on the other side of the mother board.Package Mechanical Specifications and Ball Information Table 4-13. to ensure recognition of this signal following an Input/Output write instruction. operation of these pins as LINT[1:0] is the default configuration. when asserted. the processor generates an exception on a non-control floating-point instruction if a previous floating-point instruction caused an error. INIT# must connect the appropriate pins of both FSB agents. The processor then begins execution at the power-on Reset vector configured during power-on configuration. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. D[63:0] => D[0:63] A[32:3] => A[3:32] DINV[3:0]# is also reversed. a non-maskable interrupt. INIT# is an asynchronous signal. it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. Refer to the platform design guide for more implementation details. If IGNNE# is deasserted. Refer to the platform design guide for more implementation details. IGNNE# is an asynchronous signal. Probe Request signal used by debug tools to request debug operation of the processor.Signal Description (Sheet 5 of 8) Signal Name IGNNE# Type I Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions.
PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature.Package Mechanical Specifications and Ball Information Table 4-13. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction). RESET# I RS[2:0]# I RSVD Reserved/ No Connect 38 Datasheet . It should be driven high throughout boundary scan operation. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. These signals are source synchronous to ADSTB#. assertion of PROCHOT# by the system will activate the TCC. This signal may require voltage translation on the motherboard. from the time that the power supplies are turned on until they come within specification. PWRGOOD I PWRGOOD (Power Good) is a processor input. These pins are RESERVED and must be left unconnected on the board. The PWRGOOD signal must be supplied to the processor. if enabled. but clocks and power must again be stable before a subsequent rising edge of PWRGOOD.Signal Description (Sheet 6 of 8) Signal Name PROCHOT# Type I/O. However. All processor straps must be valid within the specified setup time before RESET# is deasserted. refer to the platform design guide. The TCC will remain active until the system deasserts PROCHOT#. it is recommended that routing channels to these pins on the board be kept open for possible future use. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. and must connect the appropriate pins of both FSB agents. The signal must then transition monotonically to a high state. O (DP) Description As an output. RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. This indicates that the processor Thermal Control Circuit (TCC) has been activated. On observing active RESET#. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current). both FSB agents will deassert their outputs within two clocks. it is used to protect internal circuits against voltage sequencing issues. As an input. if enabled. PWRGOOD can be driven inactive at any time. For a power-on Reset. Refer to the platform design guide for more details. They are asserted by the current bus owner to define the currently active transaction type. without glitches. For termination requirements.
This signal is not used for nettop platform 08 and tied to VTT.Anode * THRMDA_2 refers to core #2. TDI_M I THRMDA. * TDO_M refers to core #2. On accepting a System Management Interrupt. TRDY# must connect the appropriate pins of both FSB agents. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. THRMDA_2 THRMDC. the processor stops providing internal clock signals to all units. SMI# (System Management Interrupt) is asserted asynchronously by system logic. TDO. PWR I Thermal Diode . TDO_M O TDO (Test Data Out) transfers serial test data out of the processor. restarting its internal clock signals to the bus and processor core units. RSVD. Refer to the platform design guide for termination requirements and implementation details.Signal Description (Sheet 7 of 8) Signal Name SLP# Type I Description SLP# (Sleep). the processor exits Sleep state and returns to StopGrant state. * TDI_M refers to core #2. leaving only the Phase-Locked Loop (PLL) still operating. The processor will recognize only assertion of the RESET# signal. The processor will stop all execution when the junction temperature exceeds approximately 125°C. deassertion of SLP#. TDI provides the serial input needed for JTAG specification support. THRMDC_2 TMS PWR TRDY# I Datasheet 39 . During Sleep state. and removal of the BCLK input while in Sleep state. Refer to the platform design guide for termination requirements and implementation details. Processors in this state will not recognize snoops or interrupts. when asserted in Stop-Grant state. For termination requirements. TDI (Test Data In) transfers serial test data into the processor. TDO provides the serial output needed for JTAG specification support. SMI# I STPCLK# TCK I I TDI. causes the processor to enter the Sleep state. THRMTRIP# O The processor protects itself from catastrophic overheating by use of an internal thermal sensor. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). the processor saves the current state and enter System Management Mode (SMM). the processor will exit the Sleep state and transition to the Deep Sleep state. If SLP# is deasserted. This sensor is set well above the normal operating temperature to ensure that there are no false trips. and the processor begins program execution from the SMM handler. Thermal Diode . An SMI Acknowledge transaction is issued. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. If DPSLP# is asserted while in the Sleep state.Cathode * THRMDC_2 refers to core #2.Package Mechanical Specifications and Ball Information Table 4-13. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. refer to the platform design guide.
Refer to the platform design guide for termination recommendations and more details. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC) but these pins are not used in the nettop platform 08 as the VID is fixed at 1. Connect this to VTT. VSS_SENSE O VSS_SENSE is an isolated low impedance connection to processor core VSS. AGTL+ reference voltage VCC_SENSE is an isolated low impedance connection to processor core power (VCCP).Signal Description (Sheet 8 of 8) Signal Name TRST# Type I Description TRST# (Test Reset) resets the Test Access Port (TAP) logic. Refer to the platform design guide for complete implementation details.Package Mechanical Specifications and Ball Information Table 4-13.1V. VCCA PWR VCC VSS VID[6:0] PWR GND O VTT VCC_SENSE PWR O VCCQ0. TRST# must be driven low during power on Reset. VCCQ1 PWR § 40 Datasheet . Processor core power supply Processor core ground node. VCCA provides isolated power for the internal processor core PLLs. It can be used to sense or measure voltage near the silicon with little noise. Refer to the platform design guide for termination requirements and implementation details. It can be used to sense or measure ground near the silicon with little noise.
Package Mechanical Specifications and Ball Information Datasheet 41 .
please refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section Thermal Specifications. long-term system operation. The case temperature is defined at the geometric top center of the processor.1. the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. 5.3). thermal management becomes increasingly crucial when building computer systems. Alternatively. Intel recommends that complete thermal solution designs target the TDP indicated in Table 5-14 instead of the maximum processor power consumption.3). The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more information on designing a component level thermal solution. Maintaining the proper thermal environment is key to reliable.1 Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor based systems. For more details on thermal solution design. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. A typical system level thermal solution may consist of a system fan used to evacuate or pull air through the system. but would likely still use a multi-component heat spreader.2. A complete thermal solution includes both component and system level thermal management features. the system/processor thermal solution should be designed such that the processor remains within minimum and maximum case temperature (Tc) specification at the corresponding thermal design power (TDP) value listed in Table 5-14. In all cases. refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1. 42 Datasheet . the processor may be in a fan-less system. Note that trading of thermal solutions also involves trading performance. For more details on the usage of this feature. Component level thermal solutions include active or passive heatsink attached to the exposed processor die. refer to Section 5. As processor technology changes. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Thermal solutions not designed to provide this level of thermal capability may affect the longterm reliability of the processor and system. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure.
on-die temperature gradients between the location of the thermal diode and the hottest location on the die. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. Not 100% tested.1. 2. a temperature offset value must be read from a processor MSR and applied. See Section Section 5. This is due to inaccuracies in the external thermal sensor. 5.2 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. This offset is different than the diode Toffset value programmed into the processor Model Specific Register (MSR). 3.Power Specifications for the Standard Voltage processor Symbol TDP Symbol PAH Processor Number 330 Core Frequency and Voltage 1. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. When using the thermal diode.Thermal Specifications and Design Considerations Table 5-14.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal “diode”. 4.2 Notes 1.0 Typ — Max 2 Unit W Unit W 2 Tc min (°C) 0 Tc max (°C) 85. VCC is determined by processor VID[6:0].2 for more details. with its collector shorted to ground. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications.1. The TDP is not the maximum theoretical power the processor can generate. The TDP specification should be used to design the processor thermal solution. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit.6 GHz & VCC Parameter Auto Halt Min — Thermal Design Power 8. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die. 3. See Section 5. 4 NOTES: 1. Datasheet 43 .1. Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of the thermal control circuit. and time based variations in the die temperature measurement.
5 NOTES: 1. Calculating the temperature is then accomplished using the equations listed under Table 5-16. 44 Datasheet .Thermal Specifications and Design Considerations Table 5-15 and Table 5-16 provide the diode interface and specifications. Not 100% tested.4 2.24 Ω Unit μA μA Notes 1 1 2. and T = absolute temperature (Kelvin). although are capable of also measuring the series resistance. In most sensing devices. The thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. nQ. 4. The ideality factor. 5. If the designer of the temperature sensing device assumes a perfect diode. 2. Contact your external sensor supplier for their recommendation.3. The series resistance. represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT –1) where IS = saturation current. Most devices measure the diode ideality and assume a series resistance and ideality trim value.001 Typ Max 200 200 1. Characterized across a temperature range of 50–100°C. RT.52 1. provided in the Diode Model Table (Table 5-16) can be used for more accurate readings as needed. k = Boltzmann Constant.997 0.3 2. Transistor model parameters shown in Table 5-16 providing more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits.25 2. 3. VBE = voltage across the transistor base emitter junction (same nodes as VD). Intel does not support or recommend operation of the thermal diode under reverse bias.000. an expected value for the diode ideality is designed-in to the temperature calculation equation.Thermal Diode Parameters using Transistor Model Symbol IFW IE nQ Beta RT Series Resistance Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0. When calculating a temperature based on the thermal diode measurements.Thermal Diode Interface Signal Name THERMDA THERMDC Pin/Ball Number E4 E5 Signal Description Thermal diode anode Thermal diode cathode Table 5-16. a number of parameters must be either measured or assumed.65 6. q = electronic charge. the ideality value (also called ntrim) will be 1.015 0. Table 5-15.79 4. Specified by design characterization.
With a properly designed and characterized thermal solution. the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. Intel recommends TM1 be enabled on the processors. the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation.Thermal Specifications and Design Considerations Given that most diodes are not perfect. If both modes are activated. 5. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. Once the temperature has returned to a non-critical level. Tmeasured is in Kelvin. automatic mode takes precedence.1. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured * (1 . A small amount of hysteresis has been included to prevent rapid Datasheet 45 . This mode is selected by writing values to the MSRs of the processor. it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. modulation ceases and TCC goes inactive. There is only one automatic modes called Intel Thermal Monitor 1 (TM1). The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. and ntrim is the diode ideality assumed by the temperature sensing device. After automatic mode is enabled. In addition.nactual/ntrim) where Terror(nf) is the offset in degrees C. If the processor diode ideality deviates from that of the ntrim.2 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. each calculated temperature will be offset by a fixed amount. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. nactual is the measured ideality of the diode. When TM1 is enabled and a high temperature situation exists.
the processor will be operating out of specification. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1. Regardless of enabling the automatic or on-demand modes. if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists. however in on-demand mode. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. Bus snooping and interrupt latching are also active while the TCC is active. the TCC will be activated immediately independent of the processor temperature. An external signal. PROCHOT# will remain asserted until the processor exits the Stop Grant power state and the processor junction temperature drops below the thermal trip point. Besides the thermal sensor and thermal control circuit. the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. the duty cycle is fixed at 50% on. the system must initiate an orderly shutdown to prevent damage.5% off in 12. however. 46 Datasheet . one performance counter register. in the event of a catastrophic cooling failure. automatic mode does not require any additional hardware. or interrupt handling routines. The duty cycle is factory configured and cannot be modified.5% increments. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. to 87. and one I/O pin (PROCHOT#). automatic mode will take precedence. The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. If the processor enters one of the above power states with PROCHOT# already asserted. PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. software drivers. the Intel Thermal Monitor also includes one ACPI register. three MSR. When using on-demand mode to activate the TCC. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification. In automatic mode.5% off.5% on/12. hence. PROCHOT# will not be asserted when the processor is in the Stop Grant power states. At this point the THERMTRIP# signal will go active.Thermal Specifications and Design Considerations active/inactive transitions of the TCC when the processor temperature is near the trip point. Intel recommends TM1 be enabled on the processors. Also. The TCC may also be activated via on-demand mode. 50% off. On-demand mode may be used at the same time automatic mode is enabled. the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C.5% on/ 87. If Intel Thermal Monitor automatic mode is disabled. TM1 feature is referred to as Adaptive Thermal Monitoring features. the duty cycle can be programmed from 12. All are available to monitor and control the state of the Intel Thermal Monitor feature.
the TM1 hardware thermal control mechanism will activate. The processor can be configured to Datasheet 47 . These thresholds have the capability of generating interrupts via the core's local APIC. The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1) trigger point.Thermal Specifications and Design Considerations 5. the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Thermal Monitor. If TM1 is enabled. Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs.1. The temperature returned by the DTS will always be at or below TJ_max. mechanical and thermal attach. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. Catastrophic temperature conditions are detectable via an Out Of Spec status bit.5 PROCHOT# Signal Pin An external signal.3 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor (DTS) that can be read via an MSR (no I/O interface). It is the responsibility of software to convert the relative temperature to an absolute temperature. The DTS is only valid while the processor is in the normal operating state (the Normal package level low power state). The DTS and TM1 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. If the processor’s TM1 are triggered and the temperature remains high.1. is asserted when the processor die temperature has reached its maximum operating temperature. The processor operation and code execution is not ensured once the activation of the Out of Spec status bit is set. The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications. and software application.4 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. the DTS will output a temperature relative to the maximum supported operating temperature of the processor (TJ_max). This bit is also part of the DTS MSR. PROCHOT# (processor hot). Additionally. 5. then the TCC will be active when PROCHOT# is asserted. Unlike traditional thermal devices. When this bit is set. an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. This feature is intended for graceful shut down before the THERMTRIP# is activated. 5. the processor is operating out of specification and immediate shutdown of the system should occur. When the DTS indicates maximum processor core temperature has been reached.1.
Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details. When PROCHOT# is driven by an external agent. With a properly designed and characterized thermal solution. it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. PROCHOT# will be asserted. PROCHOT# may be used for thermal protection of voltage regulators (VR). By asserting PROCHOT# (pulled-low) and activating the TCC. When the core's thermal sensor trips.Thermal Specifications and Design Considerations generate an interrupt upon the assertion or deassertion of PROCHOT#. then the processor core will have the clocks modulated. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulation Specification for details on implementing the bidirectional PROCHOT# feature. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. § 48 Datasheet . The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. Only a single PROCHOT# pin exists at a package level of the processor. If TM1 is enabled. PROCHOT# signal will be driven by the processor package.It is important to note that Intel recommends TM1 to be enabled. the VR will cool down as a result of reduced processor power consumption. if TM1 is enabled on the core. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.
Thermal Specifications and Design Considerations Datasheet 49 .
§ 50 Datasheet . Contact your Intel representative for more information.Debug Tools Specifications 6 Debug Tools Specifications The ITP-XDP debug port connector is the recommended debug port for platforms using the processor.
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