Guide to cadence IC Design Software (Virtuoso Schematic/Layout, Analog Environment, and Assura DRC/LVS) Department of Electrical

and Computer Engineering Fall 2007
(last revised 10/17/07)

Summary This is a tutorial on how to design, simulate, layout, run DRC & LVS, and generate fabrication files for an Integrated Circuit (IC) using the cadence Virtuoso design platform. This tutorial will walk through an example CMOS inverter design from start to finish in order to explain each of the steps in the design. Cadence runs in on Linux environment. Linux workstations are available in Cobleigh Hall, Rm 620. The following lists the steps that will be covered in this tutorial: Step 1: Launching Cadence Step 2: Creating a Library Step 3: Creating a Schematic and Symbol for the Inverter Step 4: Creating a Simulation Test Bench for the Inverter Step 5: Running a SPICE simulation (DC and Transient) Step 6: Creating a Layout Step 7: Running DRC Step 8: Running LVS Step 9: Generating fabrication files to create masks (not available yet)

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Step 1: Launching Cadence 1) Log into the Linux workstations in Cobleigh 620 using the KDE desktop option. a) If you are enrolled in EE414 (Fall 2007) - your username is: - your password is: NOTE 1: “first initial” followed by “last name” your banner ID without the “-“

Don’t change your password, it will only change on the workstation that you are logged into. You don’t have permission to change your password on the server. Also don’t change your shell, Cadence won’t run in any other shell than the default. The computers in COBH 620 are dual boot. They automatically come up in SuSE Linux. If they are booted into windows, you will need to shutdown and restart to bring up Linux. When Linux boots, it will automatically mount your home directory. Your home directory exists on a server called ece-fileserver. The Linux workstation tries to mount this drive once every minute. If you boot up and then login before this drive has been mounted, you will not see any of your files and not be able to do anything. The solution is to wait a couple of minutes after booting up and allow the drive to automatically mount before logging in. This is only an issue if you have to reboot. If the workstations are already booted into Linux, then you don’t need to worry about it.

NOTE 2:

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Start a terminal window a) On the taskbar at the bottom of the screen, you’ll see an icon of a monitor with a little shell next to it. Click on this to bring up a terminal window. The terminal should be brought up in your home directory. Test to make sure everything is OK by doing a: >> whoami >> pwd (it should return your username) (it should return your home directory /home/username)

b)

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Change into your working directory a) In the terminal window, change to “work” by typing >> cd work NOTE 1: In this directory, you will see a file called “cds.lib”. This is the file that sets up the Cadence licenses and the toolkit we’ll be using. 3

you will create a folder under work called “Cadence_Libraries”. You can return to your home directory no matter where you are by typing: >> cd Now change to your “work” directory by typing: >> cd work b) Start cadence by typing: >> icfb & NOTE 1: the “&” means that the program will run in the background. If you ever want to create another library for a senior design or research project.lck files that exist. Then in Cadence. we will create the actual libraries. the program will still be running in the background and your files will be locked the next type you login.4) Launch Cadence a) You will need to be in your “work” directory in order to start Cadence. We are going to manually create a Directory using the terminal window called “Cadence_Libraries”. “Window-Close”. Cadence organizes all of its files using libraries. In this directory. you would do it in this folder: Make a directory for your library by typing: >> mkdir Cadence_Libraries b) Check that the directory was successfully created by typing: >> ls –al You should see your recently created library 4 . To keep things organized. you need to close the program using the “File-Exit”. etc… If you click on the “X” button of the terminal. It is important that when you are done with cadence. NOTE 2: If you login and run cadence and your files are locked. Step 2: Creating a Library 1) Make a directory to store your Cadence Library (only do this once) a) You will be working with Libraries in cadence. you need to find and delete any *. we will create a library for EE414. You create your libraries in Cadence.

You should see the following Libraries in the “Library” section of the Library Manager. enter the following: Name: Directory: Click “OK” EE414_Library Browse to your “Cadence_Libraries” directory In the Technology File for New Library window that pops up. the Library Manager is the first window that comes up. . The second thing to check is that your home drive was successfully mounted upon login.ami500hxkx .lib file. If it was mounted correctly. you should automatically see a work directory in your home directory. b) Now create a library called “EE414_Library” by using the pull-down menus in the Library Manager window: File – New – Library In the New Library window.2) Create a Library in Cadence a) We are going to create a Library called “EE414_Library”.5um technology file to our library: Select “Attached to an existing techfile Click “OK” In the Attach Design Library to Technology File window: Select “ami500hxkx” from the pull-down box.ami500hxtx These are the libraries for the AMI 0. we want to attach the AMI 0. Click “OK 5 . which contained the cds. something is wrong and you need to exit cadence. This library will hold all of our projects for the semester. If you do NOT see these libraries. First check that the software has come up correctly with the necessary design kits. When you launch Cadence.5um CMOS process we will be using. The first thing to check is that you launched Cadence in your work directory. We will do this in the Cadence Library Manager window.

In the Library Manager window.this brings up the Add Instance window” In this window. etc… We will begin by creating a cell for our inverter called INV that will have a schematic and a symbol. 2) Enter the schematic for the inverter a) Enter an NMOS transistor . spectre simulation info. A cell can contain various views such as schematics. use the pull-down menus to create a new cell: File – New – Cell View In the Create New File window. . You can also use the [i] button. we’ll create another cell called test_INV.lib This will bring up the Virtuoso Schematic Editing window. The test_INV cell will contain a schematic in which we will instantiate our INV cell. select the following: 6 . symbols. Click on the “Instance” icon. Verilog. select: Library Name: Cell Name: View Name: Tool: Library Path file: EE414_Library (this is the library the cell will be part of) (our unique name) (Default) INV Schematic Composer-Schematic verify this is set to: /home/username/work/cds. In order to simulate our INV cell.Step 3: Creating a Schematic and Symbol for the Inverter 1) Create a cell called INV a) When we create an item in Cadence. you’ll see some icons. it is called a Cell. layout.on the left hand side of the schematic window.

We need to add I/O pins to show the inputs and outputs. .clicking on the Property icon on the left . d) Modify the properties for the PMOS transistor . . so just enter 5) .select the cell called “p” .Library: .in the Add Instance window”.bring up its properties dialog by either: .select the view called “symbol” (click on it once) .Browse to the ami500hxtx library .on the left hand side of the schematic window.you will see an NMOS symbol now connected to your mouse in the schematic window. Click once to drop the symbol in the schematic.change the Width to 5u (Note the default units are um.select the view called “symbol” (click on it once) . so just enter 10) .bring up its properties dialog by either: .Click “OK” c) Enter a PMOS transistor .select the cell called “n” .this circuit will ultimately have a symbol that will be instantiated in a higher level design.on the left hand side of the schematic window. Hit the [ESC] button to exit the “add instance” command mode. b) Modify the properties for the NMOS transistor .Click “OK” e) Add I/O pins .change the Width to 10u (Note the default units are um. Click once to drop the symbol in the schematic.Browse to the ami500hxtx library .you will see a PMOS symbol now connected to your mouse in the schematic window.clicking on the Property icon on the left (or hit [q]) . click on the “Instance” icon. select the following: Library: .hitting the [q] button . Hit the [ESC] button to exit the “add instance” command mode. click on the “Pin” icon to add an I/O pin 7 .click on the NMOS symbol .click on the PMOS symbol .

you will start adding a wire. hit the [ESC] button and the dialog will disappear. While you are dragging the pin around. you’ll notice that the Add Pin dialog is still open. f) Re-Position your instances . Click once in the schematic window to add your pin. On the right hand side of the schematic window click on the Wire (narrow) icon.select an instance by clicking on it once. you’ll see a pin attached to it. click once.when in the move command.to end the Add Pin command.you can move the selected by doing either: . .you are now in add wire mode. . Add the 3 remaining pins to your inverter as follows (rotate them as you place them to make them fit properly): Pin Names: Direction: Pin Names: Direction: Pin Names: Direction: OUT output VDD inputOutput VSS inputOutput . g) Add wires . PMOS. . To drop the instance.Now when you drag your mouse into the schematic window. . click the [ESC] button. . You can use this to add the remaining pins.clicking the [m] button .before you wire up your circuit. If you click once. Fill in the following: Pin Names: Direction: IN input . 8 .now you will wire up the circuit.Edit-Move .to end the move command. you want to move around your NMOS.Now that the pin has been placed.when you do this. you can go back into the Add Pin dialog and rotate the pin to your desired orientation by clicking on “Rotate”. the instance will be attached to your mouse. and pins so they are in a good location. an Add Pin dialog will come up..

. Then you can highlight a wire and click [Delete] to remove the wire. you can single-click.leave the schematic window OPEN in order to create a symbol.In the Cellview From Cellview window ensure the following settings: 9 . you can get out of the add wire mode by clicking [ESC]. You can end the add wire mode by clicking once on an instance pin or double clicking on the same location. However.in the schematic window. 3) Create a symbol for the inverter a) You will now create a symbol view for your INV cell . To see the details of the warnings and errors. output. if you want to manually add a corner. do the following: Design – Check and Save . VSS.Cadence will automatically try to create the shortest path between pins.in the Schematic window pull-down. . use the pull-downs to perform: Design – Create Cellview – From Cellview This will automatically create a symbol for your schematic with ports associated with the pins that you’ve added.connect up the inverter input. . If you make a mistake. and body connections. VDD.if you have any warnings or errors. h) Check and Save . look in the Log window. you will get a pop up window telling you how many.

perform: Design – Check and Save In Out VDD VSS 10 . Modify your pins as follows: Left Pins: Right Pins: Top Pins: Bottom Pins: Click “OK” . For now. . leave these as they are.(NOTE: these should default to the correct settings) Library Name: Cell Name: From View Name: To View Name: Tool / Data Type: b) EE414_Library INV schematic symbol Composer-Symbol Position the pins of your symbol .you should now see a Virtuoso Symbol Editing window pop up that has your newly generated symbol.in the Symbol Generation Options dialog. You will see your pin names in addition to various parameters that can be used to pass in information to your lower-level circuit. they will not show up when you instantiate this symbol.Using the pull-down menus. you will tell the tool where to locate your pins. When the parameters are not used.

. and pins around by first selecting. .Close 11 . perform: Design – Check and Save .close the symbol editor by performing: Window – Close . and then clicking [m] to get into the move mode. For this inverter.the default shape for the symbol is a rectangle. To get out of the move mode.You can add a triangle shape using the pull-down menus: Add – Shape – Polygon . click the [ESC] button.you can also rotate items by selecting them and clicking [r]. . properties.close your schematic window by performing Window .clean up any warnings or errors that you have.once you have created an accurate symbol for your circuit. . you should modify the symbol shape to reflect the traditional “triangle with a bubble” so that this circuit is easily recognizable.You can move shapes.You can add a circle using the pull-down menus: Add – Shape – Circle .c) Modify the symbol .You can select and delete the default square shape in the symbol .

In the Add Instance dialog. and a load capacitance. To keep this straight. As such. your library will contain many levels of circuit blocks and test benches. VHDL. Verilog. enter the following: Library: Browse to your EE414_Library While this browse window is open. we will use a prefix of ”test_<cell name>” to easily identify the cells in our library which are test benches. This will contain an instantiation of our INV cell symbol.On the left hand side of the schematic window. 2) Enter the test bench schematic a) Instantiate the inverter (INV) . power supplies. click on the Instance button (NOTE: you can also click the [i] button) .In Library Manager. select: Library: Cell: View: EE414_Library INV symbol 12 EE414_Library test_INV schematic Composer-Schematic . symbol. fill in the following: Library Name: Cell Name: View Name: Tool: Click “OK” . A test bench will only contain a schematic view while an actual circuit that will be fabricated will contain many views such as schematic. It will also contain voltage sources.A new schematic window will pop up. aVerilog.In the Create New File window. layout. use the pull-downs to perform: File – New – Cell View .Step 4: Creating a Simulation Test Bench for the Inverter 1) Create a cell called test_INV a) Now we will create a new cell which will consist of a schematic view. It is ALWAYS a good idea to test each lower-level hierarchical block separately before incorporating it into a higher level design. etc… .

Again.You can set the properties for vdc by selecting it and hitting [q]: . select the analogLib library. Click once to instantiate vdc. . 13 . the vdc instance will attach to your mouse in the schematic window.Browse to the analogLib library. use the instance command to bring up the Library Browser..scroll through the Cells until you find vdc.You can rotate the vdc instance by selecting it and clicking [r].In the Cell column.Set the DC Voltage to 5 . You can click once to instantiate it in your test bench schematic . Click [ESC] to end the add instance mode. scroll down to find gnd. then select the symbol view. . . . .rotate and attach the GND symbol to the VDD supply that you entered earlier. lumped capacitors. .You can move the vdc instance by selecting it and clicking [m] .once you click on symbol. Select the vdc cell. the inverter symbol for INV will be attached to your mouse.In the Library Browser window. etc… There is a library called analogLib that exists in the Library Manager that contains all of these elements.You can also change the instance name to something more descriptive if you wish .once you click on the view symbol. .Click on the symbol view to instantiate it in your test bench schematic. .For a test bench. . we use ideal components for voltage sources.Click “OK” c) Enter a GND node: .Click on the Instance icon on the left hand side of the schematic window: (or you can click [i]).click the [ESC] button to exit the instance mode. b) Enter a Voltage Source for VDD: . .

. position all of the instances in a good location around the INV. value=150fF) (used for Vin in a DC simulation.before wiring up the schematic.e. . Enter the following wire names: VIN.d) Enter the remaining instances of the test bench . VDD Note that you can’t name the GND net as it is already named by connecting it to the gnd instance.cap . don’t put the instances on top of each other) .. You will enter a wire name and then click on the wire in the schematic window to assign the name.this brings up the Add Wire Name dialog. 14 . VOUT. set to: voltage 1: voltage 2: rise time: fall time: pulse width: period: 0 5 1ps 1ps 5ns 10ns . enter the following items from analogLib: . Note that we will be naming nets so leave a lot of room to enter a net and give it a name (i. set to 0v and name the instance Vin_dc) (used for Vin in a transient simulation.on the left hand side of the schematic window. click on the Wire Name icon.use the Wire (narrow) icon on the left hand side of the schematic to enter the wires for your schematic.vdc (used for a load capacitance.we are going to put the DC source for VIN in series with the PULSE source. g) Name the wires .vpulse e) Position the instances in the schematic .using the same process. Put the vdc source below the vpulse source.you can copy an instance by selecting and hitting [c] f) Wire up the instances .

we will be using the Spectre simulator. Instead. we can direct the simulator to store the temporary information to our local disk. Step 5: Running a SPICE Simulation 1) Setup the simulation a) Open the Analog Design Environment . there will be a directory called /tmp. If everybody in our class simulated at once and stored the data on ece-fileserver we would fill its disks up very quickly.h) Check and Save Use the pull-down menus to perform: Design – Check and Save Keep the schematic window open for the next part. We will tell the simulator to put all of our results in a directory called: /tmp/simulation 15 . On the machine you are logged into. This simulator generates a large amount of temporary data that we don’t want to store on ece-fileserver. perform: Tools – Analog Environment b) Choose the Spectre Simulator and the location of simulation files .In the schematic pull-down menus.

uncheck all others Check “Component Parameter” Click on “Select Component” No click on the Vin_dc instance in the schematic: In the Select Comp Param dialog that comes up.Let’s first start with a DC simulation to plot the Voltage Transfer Characteristics (VTC) of the inverter: ..Choose Analysis: Sweep Variable: Check DC.In the Analog Design Environment window. use the pull-downs: Setup – Simulator/Directory/Host Simulator: Project Directory: .Click “OK” e) Setup DC Analysis . use the pull-downs: Analysis .In the Analog Design Environment window.In the Analog Design Environment window.Click “OK” d) Setup Temperature .Click “OK” c) Setup the Model Path . highlight “dc” and click “OK” 16 Celsius 27 ami500hxkx typ for all spectre /tmp/simulation . use the pull-downs: Setup – AMI Set Model Path (defaults should be OK) techLib: process corners: . use the pull-downs: Setup – Temperature (default should be OK) Scale: Degrees: .In the Analog Design Environment window.

click “OK” g) Run the DC Simulation .You can also perform a: File – Save as Image . This will print to the printer in COB 625. use the pull-downs to perform: File – Print .In the Analog Design Environment window.in the plot window. 17 .In the Analog Design Environment window.Save All Leave the Keep Options dialog defaults.a window will pop up with the VTC h) Print or Save the results .Sweep Range: Start = 0 Stop = 5 Automatic Sweep Type: Click “OK” f) Select Outputs to monitor . .this will give you a file that you can insert into your project report. use the pull-downs: Outputs .Click on the “Print” button. click on the Green Stoplight: .

From the pull-down menus: Analyses – Choose . This will disable the simulation but keep all of your setup information for the DC analysis.you can retrieve this state the next time you run cadence by performing: Session – Load State 18 . You also will notice that the DC simulation still ran.i) Run a transient simulation .give a descriptive name such as “test_INV_DC_and_TRAN” . perform: Session – Save State . select “dc”.enter a Stop Time of 20ns (you MUST put the “n” for nano) . This is handy when you are altering the sizes of the inverter and monitoring Vth in addition to the delay. you want to save your simulation environment. you can click on the “choose analysis” button in the analog environment window.Go back into the Analog Environment window: .click the tran radio button . Using the pull-down menus in the analog environment.click the Green Stoplight to run the simulation .a plot will come up showing 2 cycles of your 10ns period input. If you don’t want to run the DC simulation anymore.in addition to saving your schematics. then uncheck the Enabled radio button at the bottom of the window. j) Save your session .

use the Pull-down menu: Options – Display Options .lib This will bring up the Virtuoso Layout Editing window and the layers menu. a) Enter Active/Diffusion Region .1 = 0.Step 6: Creating a Layout for the Inverter 1) Create a layout Cell view for the inverter a) In the Library Manager window.1 =1 = 0.In the X-direction.In the Create New File window. . use the pull-down menus to create a new cell: File – New – Cell View . select: Library Name: Cell Name: View Name: EE414_Library INV layout (this will updated when you choose the tool) (this is the name of the layout editor) (this is the library of your cell) Tool: Library Path file: Virtuoso verify this is set to: /home/username/work/cds. The first is to define the active region for our NMOS transistor. you can modify the grid and snap attributes . 2) Setup your display options a) If you’d like.Set the following: Minor Spacing Major Spacing X Snap Spacing Y Snap Spacing = 0. we need the DIF rectangle to be large enough for the following 19 .1 3) Create the layout for the NMOS transistor NOTE: our process assumes that we are using a p-type substrate. The second is to define where the n+ implants will occur.we use the DIF layer to accomplish two things.

4um minimum) (0.4 x 5.5um fixed) (0.In the Y-direction. 20 .in the Layout window (you may have to click on it to make it active).the source contact window .4um minimum) (0. click on DIF .Create – Rectangle (or use the hotkey [r]) .5um fixed) (0.the source contact-to-poly spacing .6um minimum) (0.(described from left-to-right) .the drain contact-to-active spacing Total (0. You can put your mouse over an edge and it will turn into a dotted line.4um minimum) > 3. start a rectangle by: .the drain contact window .resize if necessary. we make DIF the size of our desired W.in the Layer menu. .the source contact-to-active spacing . .draw a rectangle that is at least 3.the poly gate .the drain contact-to-poly spacing .4um minimum) (0. which in this example is 5um.2um (+ margin) . You can then click [s] to stretch the shape.

.6um in the X-direction.in the Layout window (you may have to click on it to make it active). 21 . We’ll resize it later when we hook up the PMOS. We will make the gate rectangle 0. we can tell the command how many and of what type.we insert contacts using an automatic command in Cadence. .in the Layer menu.5um on each side.put the rectangle directly in the middle of the DIF rectangle c) Enter the Active Contacts . It is a good design practice to put as many contacts as will fit.a window will appear and a contact will snap to your mouse. Since our NMOS is 5um wide. start a rectangle by: . we can put more than 1 contact on each terminal. click on POLY1 .Create – Contact .we use the POLY1 layer to enter the gate. perform: .Create – Rectangle (or click the hotkey [r]) .b) Enter the polysilicon gate .In the file pull-down menus. As we insert the contacts. You’ll need to overlap the POLY1 over the diffusion region by at least 0.

we choose DIFCT in the “contact type” pull-down. we also need to define what type of contact we are inserting.again. This will tell the tool that we need to implant a p+ region beneath the contact to form an Ohmic contact to the p-type substrate.5um x 0.In the file pull-downs. . Since this is an active region contact.in the dialog window. 22 .5um. . Since this is a Body contact for an NMOS. . select 4 rows of contacts.in the dialog window. we need to select PDIFCT.Click in the diffusion regions to place your source and drain contacts. perform: Create – Contact .the minimum active-to-active spacing is 0. set the number of rows to 4.Click in the layout window to add the Body contacts.it is mandatory for the process that the size of the contacts be 0.9um so the body contacts will need to be at least this distance away from the DIF region. Now click back in the layout window and you’ll see 4 contacts attached to your mouse. d) Enter the Body Contacts .. . .

4) Create the layout for the PMOS transistor NOTE: the process for the PMOS is similar to the NMOS. Step 7 in this tutorial will walk you through how to run the DRC check. We will move on to entering the PMOS and then we’ll hook everything up.we create the N-well using a combination of 2 layers (TUB and NFIELD) . a) Enter N-well .NOTE: This is all we can do on the NMOS for now. Remember that we need to create an N-well for the PMOS substrate.5um between the edges of active regions.5um . This makes duplicating shapes very easy. It is a good idea to run DRC right now.create the exact same sized rectangle using NFIELD and place directly on top of the TUB rectangle NOTE: you can copy the TUB rectangle and then perform a [q] to change its layer to NFIELD.enter a rectangle using the TUB that is large enough to accommodate our PMOS and still have at least 1.key spacing’s for the N-well are: .5um .minimum N-well width = 2. 23 .minimum N-well to N+ Active spacing = 1. .

.we now add the body contacts. At this point. There should be room to add 9 contacts to both the Drain and Source e) Add the body contacts .this is accomplished using 3 layers (DIF.first create a DIF region that has the same X-dimensions as your NMOS and a Y-dimension of 10um (Wp=10um) . However. The combination of these three regions tells the tool that we are going to create an Active region that is p+ doped in an N-well. We again choose DIFCT as the type of contact.now you will overlap this DIF region with both an NPLS and an PPLS rectangle. The size should be 0. c) Enter the polysilicon Gate . and PPLS) .3um. 24 . it is a good time to run DRC.6um in the X-dimension and in the Y-dimension it should overlap the DIF rectangle by 0.b) Enter the PMOS Active Region .use POLY1 just as in the NMOS. NPLS.5um d) Add the active contacts .just as in the NMOS. Use the Create-Contact pull-down. We want to make sure the transistors are correct prior to connecting them up. we add the active contacts using the Create – Contact pull-down. The sizes of the NPLS and PPLS shapes must extend beyond the edges of the DIF region by 0. you will choose NDIFCT as the type of contact to indicate an n+ diffusion contact.

This will allow a single from Metal1 to change layers to POLY1 in order to drive the input of in the inverter.in the layout window. b) Create the output node using Metal1 . click on M1. create a rectangle using [r] .5) Connect the nodes of the inverter a) Create the Input node using Polysilicon . select M1PLY as the contact type. the input and output can be accessed on M1.Click on the POLY1 layer and then add a rectangle (or polygon) in the layout to complete the connection .Add a Poly-to-Metal1 using the pull-down menus in the layout window: Create – Contact .also add some metal over the M1PLY contact so that when this INV is instantiated in high-level layout. .In the layer menu. .in the dialog window.Use the M1 layer to connect the drains of the PMOS and NMOS transistors together to form the output of the inverter .Use the POLY1 layer to connect the gates of the PMOS and NMOS in addition to creating a region for a signal to enter the circuit from Metal1. 25 .

the VSS/VDD rails will line up.Use the M1 layer to create the VSS and VDD notes of the inverter. 26 . We will create a horizontal trace below the inverter for VSS. We will create a horizontal trace above the inverter for VDD. We can choose a pitch of 25um for the VSS and VDD rails. Remember that these connections must also pick up the body contacts of the transistors .a good layout practice is to keep a consistent pattern of the VSS and VDD traces so that when you interface with other circuits.c) Create the VSS and VDD rates using Metal 1 .

If they are on poly. output. Repeat for all pins (VDD. a) Adding Pins . we need to add the net names of our circuit in the schematic. set the following: Terminal Names = I/O Type = Pin Type = Type in the EXACT name of the pin that you used in the schematic Use the EXACT type that you used in the schematic (input.OUT).6) Add Pins and Labels to the Labels and Pins to the Device In order to be able to run the Layout vs. you should select the poly pin type. Place this pin within the metal of your layout in the appropriate spot.Create – Pin .in the create pin dialog.IN. This is a manual process and requires to type in the net names EXACTLY as you defined them in your schematic. use the pull-down menus to perform: . This is a two step process that involves first adding a Pin and then adding a Label to a given Metal or Poly shape in your layout.in the layout window. Click in the layout window to drop your pin. this assumes that all of your inputs and outputs of your layout are on Metal 1.VSS. inputOutput) M1PIN (Metal 1 Pin. Click “OK . 27 .you will see the pin attached to your mouse in the layout editor window. Schematic (LVS) check.

now we need to change the layer of the Label we just added. 28 . select the Label you just put in .b) Adding Labels .in the layout window. Meta l 1) . use the pull-down menus to perform: Create – Label . set the following: Label = Height = Type in the EXACT name of the pin that you just created this is the size of the font that the label will have. If you click in the layout window. you’ll see the text attached to your mouse.in the dialog box.in the layout window. but not so large it will clutter the layout. Remember that this layout will be used in higher-level blocks . We need to put the label on the same layer as our Pin Type and the layer in our layout that is our node we are naming (in this case.bring up the properties of the label and change the layer to M1. Make this size something readable. “OK” the properties dialog.

perform: . perform . . it will take a few moments to complete. click “OK” to overwrite: . not that you passed DRC.Step 7: Running Design Rule Check (DRC) DRC will check your layout against the layout design rules for the process. a window will appear saying the DRC has successfully ran. use the pull-down menus: .in the error layer window.in the Virtuoso Layout Editor window.if a popup comes up saying that the DRC data already exists. Click “Yes” to view the errors. you need to first select the technology file you are going to check against.Assura – Stop Run 29 .File – Close ELW .in the layout window. This is just telling you that the DRC ran. You do not need to wait until your design is complete to run DRC.in the popup window.a small window will appear that says DRC is running.click “OK” . . You can run it periodically to make sure that each step meets the design rules: 1) Run DRC .when complete. View Rules Files: .errors will be highlighted in the layout window ami500hxkx 2) End DRC .Assura – Run DRC .

It compares the two to make sure that each net is correct and the number of transistors you intended are present. it will take a few moments to complete. ami500hxkx 30 .Assura – Run VLS . Also if your label is not on the correct layer. 1) Run LVS . This includes the sizes of your transistors. Click “Yes” to view the errors. it will not pass LVS. you won’t be able to run LVS.in the Virtuoso Layout Editor window. If you don’t add the Pin and Label. use the pull-down menus: .a report window will be given that shows the results of LVS. This is just telling you that the LVS ran. click “OK” to overwrite: .when complete. . .a small window will appear that says LVS is running. You can scroll through the report to see what errors and warning (if any) occurred.if a popup comes up saying that the LVS data already exists. a window will appear saying the LVS has successfully ran. not that you passed LVS. In order for the nets to be identified by name in the layout. you need to first select the technology file you are going to check against (you only need to do this once) View Rules Files: .in the popup window.click “OK” . LVS works by creating a netlist of your schematic and then one of your layout. you will need to have added a Pin and a Label to each node. LVS should be successfully run on each block prior to including it in a higher level schematic.Step 8: Running Layout versus Schematic (LVS) LVS will check your layout against your schematic to verify that the gates you’ve created are what you intended.

2) View LVS Results .in the LVS Debug window. 3) End LVS .if you has errors. The top one will be your design. . You can view both of these netlist to see what information LVS is or isn’t seeing in your design.this netlist gives the SPICE deck of what it found in your layout.using the pull-downs.in the LVS Debug window.File – Close 31 . including the node names and the sizes.Layout VNL Netlist . . highlight the results in the Cell List. perform View . you will also be able to view the Schematic VNL Netlist. perform . You should see your n and p devices.

Appendix A: Cadence Hot Keys Schematic Entry (and other windows where applicable): c copy e descend (read only) E descend (edit mode) ^e ascend up one level f zoom to fit design to window i add instance l label wire m move p add pin q edit parameters r rotate u undo U redo w add wire z zoom to box using left-mouse clicks [] zoom in and out arrow keys move around window F3 Command options left-mouse select/click middle-mouse over object brings up typical properties right-mouse repeat last operation Layout Entry (and other windows where applicable): c m r R Cntl+p l L z Z f [TAB] cntl+f shift+f s copy move add rectangle add polygon add a pin label a wire label a wire zoom in to area zoom out 2x fit in window pan toward mout convert instantiated instance to block view convert instantiated instance to layer view stretch the side of a rectangle if mouse is over it 32 .

including hidden files : NOTE: files that start with “. >> pwd >> ls >> ls –al >> mkdir <name> >> rm <name> >> mv <name> <path> >> mv –r <name> <path> >> cp <name> <path> >> cp –r <name> <path> >> more >> whoami >> hostname >> man <topic> 33 . i. >> cd <directory name> : this takes you to your working directory : a “~” is a shortcut for your home directory : change into a directory : you can type the first few letters of the directory name : and then click [TAB] to have the rest of the name : automatically filled in for you : go UP one directory : check your present working directory. what directory : you’re in : get a list of the files and directories in your current directory : get a list of all files and directories.. : make a directory : remove a file : move a file to <path> : move a directory and all of its subfolders and files to <path> : copy a file to <path> : copy a directory and all of its subfolders and files to <path> : shows you the contents of a file : tells you the username you are logged in as : tells you the computer that you are logged into : displays the manual (or help file) for a given command >> cd .Appendix B: UNIX / LINUX Commands Useful commands: >> cd >> cd ~/.e. are hidden and can only : be seen with ls –al.”..

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