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Advances in high-speed DACs, ADCs, and DSP for optical coherent


Article  in  Journal of Lightwave Technology · February 2014

DOI: 10.1109/JLT.2013.2284134

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Charles Laperle Maurice O'Sullivan

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Advances in High-Speed DACs, ADCs, and DSP

for Optical Coherent Transceivers
Charles Laperle, Member, IEEE, and Maurice O’Sullivan

(Invited Tutorial)

Abstract—We examine analog-to-digital and digital-to-analog and FEC has evolved from a hard decision to a soft decision
converters (ADCs and DACs), as well as digital signal processing implementation to maintain transceiver reach as symbol rate
(DSP) functions for optical coherent modems. increased. Next generation transceivers will enable bit rates from
Index Terms—Analog–digital conversion, digital–analog conver- 100 Gb/s to 400 Gb/s and 1 Tb/s.
sion, digital signal processing, optical coherent transceivers, optical The remainder of this paper is organized as follows. The
fiber communication. architecture of optical coherent transceivers is described in
Section II. Section III presents digital-to-analog converters.
Analog-to-digital converters are discussed in Section IV. Section
V presents an overview of digital signal processing functions
LOBAL IP traffic is predicted to increase by 23% year
G over year between 2012 and 2017 [1]. This growing de-
mand, together with a minimum transmission cost imperative,
used in coherent transceivers. This includes functions which
can be performed either at the transmitter or receiver as well as
functions which are specific to each. Forward error correction
have spurred the development of optical transmission technolo- is also discussed in Section V. Examples of transmitter and re-
gies designed to make most efficient use of available spectrum. ceiver ASICs are presented in Section VI. Finally, Section VII
Electric field modulation and coherent detection are leading presents flexible transceivers.
most product development efforts. They rely heavily on digital
signal processing (DSP) and require conversion between ana- II. COHERENT TRANSCEIVERS
log and digital domains. Cost optimization drives designs to the
largest practical symbol rate as determined by electro-optic and Fig. 1 shows a generic block diagram for a single carrier
CMOS technologies. With this perspective, we review enabling flexible coherent optical transceiver.
data conversion and DSP implementations.
High-speed digital-to-analog converters (DACs) and DSP A. Transmitter Path
were introduced into optical transmission in 2005 [2] with The transmitter path is shown at the top of Fig. 1. Data ar-
the commercialization of a 10 Gb/s intensity-modulated direct- rive from the client/switch side through the data interface are
detection (IM-DD) transceiver capable of electronic pre- FEC encoded, and then, encoded for modulation. Two complex
compensation for chromatic dispersion. There followed from signals are generated, one for each of X- and Y -polarizations.
this a 40 Gb/s coherent transceiver with analog-to-digital con- These signals are digitally processed (mainly digital filtering)
verters (ADCs) and DSP in its receiver section [3]. Present day before serving as instruction to four DACs. The analog tribu-
multi-rate coherent 100 Gb/s dense wavelength division mul- taries at the output of the DACs are linearly amplified to drive
tiplexing (DWDM) transceivers have transmit DSP and DACs the modulation of a continuous wave (cw) tunable laser. The
as well as receiver ADCs and DSP. These can transmit up to transmitter’s output is connected to the line side. Note that a
200 Gb/s on a single carrier. Over this time span, supporting single tunable laser can be shared between transmitter and (to be
ASIC technology has migrated from 130-nm CMOS-BiCMOS discussed) receiver sections or two separate lasers can be used.
to 28-nm CMOS and accommodated a 20-fold increase in
throughput as well as gate count.
B. Receiver Path
Forward error correction (FEC) is also essential to practical
implementation of such transceivers. Over the same time span The receive path is presented at the bottom of Fig. 1. The
FEC overhead has grown by a factor of approximately four received, line side optical signal is converted to four baseband
electrical tributaries by means of an integrated optical hybrid
front-end with balanced detectors. A tunable laser-local oscilla-
tor and polarization beam splitter serve as local phase and po-
Manuscript received June 25, 2013; revised September 10, 2013; accepted larization references, respectively. The four analog signals are
September 22, 2013. Date of publication October 1, 2013; date of current ver-
sion January 10, 2014. then converted to digital domain by four ADCs. Equalization,
The authors are with the Ciena Canada-Ottawa, Ottawa, ON K2H 8E9, clock, carrier, and polarization recovery are performed before
Canada (e-mail:; modulation is decoded. Finally, recovered information is sent
Color versions of one or more of the figures in this paper are available online
at through the data interface to the client/switch side after FEC
Digital Object Identifier 10.1109/JLT.2013.2284134 decoding.
0733-8724 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See standards/publications/rights/index.html for more information.

Fig. 1. Generic block diagram of optical coherent transceiver.

with –40 ns/nm of pre-dispersion (one polarization is shown).

In operation, the transmitter implements a field closest to the
desired field at each instant.
In practice, the E/O transduction may not be linear and ad-
dressable field locations are, consequently, not regularly spaced
as in Fig. 2. In such cases, pre-compensation for a memory-less
nonlinearity might be used. This can take the form of a lookup
table which conditions the DAC input.
High-speed DAC, and ADC, design attends: bit resolution,
sample rate, signal-to-noise-plus-distortion ratio (SNDR), clock
speed, jitter, and power dissipation. As consequence of bit res-
olution at high speed, it is necessary to co-integrate converters
with the DSP. For example, four 6-bit 40 GSa/s converters would
require an overall transfer rate of 960 Gb/s between DACs and
Fig. 2. (a) Flexible output field using DAC technology (32 × 32 addressable
DSP. This requirement informs the choice of technology, such
levels). (b) Example of 200 Gb/s payload 16-QAM field values pre-compensated as CMOS or BiCMOS, as well as designs for low power dissi-
with –40 ns/nm of pre-dispersion (one polarization shown). pation and small footprint.


Digital-to-analog converters at the transmitter allow DSP for High-speed DAC cores are usually based on a current-
equalization and the capability of a wealth of software definable steering architecture. Examples include [4]: i) thermometer [5],
modulation formats from a single transceiver. In combination ii) R-2R ladder network [6], iii) binary weighted [6], and iv)
with electro-optics, near-arbitrary 4-D (magnitude and phase on segmented [7]. These are shown in the schematics of Fig. 3. In
each of two polarizations) optical fields can be constructed at the thermometer architecture, 2N – 1 switchable identical cur-
the transmitter output. Fig. 2(a) shows a configuration to gen- rent sources are used, where N is the converter’s number of bits
erate such fields using 5-bit DACs (25 = 32 levels) for a linear [see Fig. 3(a)]. Only one current source is switched by means of
electro-optics (E/O) transduction. Each dot of the transmitter decoding logic for any single least significant bit (LSB) change
complex output field is addressable. Fig. 2(b) shows an example in the digital input. The circuit is comparatively large but has
of a 200 Gb/s payload 16-QAM field values pre-compensated guaranteed monotonicity.

Fig. 3. High-speed DAC architectures: (a) thermometer, (b) R-2R ladder network, (c) binary weighted, and (d) segmented.

The R-2R resistor ladder network uses resistors of only two TABLE I
different values and their ratio is 2:1 [see Fig. 3(b)]. An N -bit
DAC requires 2N resistors. In this architecture, all stages have
identical devices and the resistors need to be matched. This
architecture dissipates the most power (mainly in the internal
resistors). The weighted binary currents architecture of Fig. 3(c)
executes an N bit DAC with N current sources weighted in
power of two (1:2:4:. . .:2N −1 ). It dissipates less power than the
R-2R ladder network and consumes less area. No decoding logic
is required for either R-2R ladder network or binary weighted
Timing is always critical in high-speed circuits. Among other
things mistiming can lead to transients. This is particularly true
in the binary weighted architecture where large transients can
occur at major code transitions (for example, when input code
is changing from 011111 to 100000 for a 6-bit DAC).
Segmentation, wherein the DAC is divided into two sub-
ity of the code transitions of the converter. INL is the maximum
DACs, one for the most significant bits (MSBs) and one for
difference between converted input and its ideal value. DNL and
the least significant bits (LSBs), allows higher-resolution DAC
INL affect a converter’s quantization performance and are con-
implementations. By this method, transients are reduced signifi-
sidered signal frequency independent. In the absence of noise,
cantly at the cost of additional logic. An example of a segmented
a converter’s near static ENOB is less than its resolution by the
architecture is shown in Fig. 3(d). Thus, segmentation provides
effects of DNL and INL which persist at all operating frequen-
a means of trading circuit complexity for DAC performance
cies. In practice, this effect on the ENOB of a 6-bit resolution
[8]. Table I summarizes the benefits and drawbacks of DAC
high-speed converter can be kept less than half a bit.
Dynamic performance measurements are based on fast-
Fourier transform (FFT) or spectral analysis. The spectral analy-
B. DAC Performance Characterization
sis of DACs is as follows. The DAC memory is loaded with a full
Static converter linearity is characterized by two parameters: scale digital representation of a sinusoidal waveform at a given
differential nonlinearity (DNL) and integral nonlinearity (INL). frequency below Nyquist (half the sampling frequency, fs /2, of
DNL is the deviation of the difference between any two adjacent the DAC). The DAC’s output is measured either with a spectrum
codes and an ideal one LSB step. DNL is a measure of the linear- analyzer or a sampling oscilloscope (see Fig. 4). In case of an

Fig. 4. Test setup for measuring a DAC’s dynamic performance. Differential

configuration is shown.

Fig. 5. Example of spectrum measured at the output of a 40 GSa/s high-speed

oscilloscope the time-domain waveform is processed by FFT to DAC generating a sinusoidal waveform at approximately 3 GHz.
obtain the spectrum. A separate spectrum is parameterized at
each frequency below Nyquist. Single-ended or differential (as
shown in Fig. 4) measurements can be performed.
The spectra are converted to measures of quality which are
relevant to both DACs and ADCs [8]: total harmonic distortion
(THD), total harmonic distortion plus noise (THD+N), spuri-
ous free dynamic range (SFDR), signal-to-noise-plus-distortion
ratio (SNDR), signal-to-noise ratio (SNR), and effective number
of bits (ENOB). Note that signal-to-noise and distortion ratio
(SINAD or SINADR), also used in the literature, and SNDR all
have the same meaning.
THD is the ratio of the root-mean-square (rms) signal energy
to the rms value of the sum of the harmonics. THD+N is the
ratio of the rms value of the fundamental signal to the mean rms
value of its harmonics plus all noise components (excluding dc).
SFDR is the ratio of the rms value of the signal to the rms value
of the worst spurious signal regardless of where it falls in the Fig. 6. ENOB measurement of 6-bit 65-nm CMOS DAC running at 40 GSa/s.
frequency spectrum.
SNDR is the ratio of the rms value of a single frequency the converter’s number of bits [9], [10]:
tone to the rms value of all other spectral components, including
SNDR(dB) − 1.76 dB
harmonics, but excluding dc. SNDR can also be written in terms ENOB = . (2)
of a power ratio and expressed in decibel as follows: 6.02
Fig. 5 shows an example of a spectrum measured at the output
  of a 65-nm CMOS 40 GSa/s 6-bit DAC with a tone frequency set
SNDR(dB) = 10 × log 10  (1) to approximately 3 GHz. From this spectrum, SNDR, ENOB,
PHarm +Noise
and SFDR can be calculated. Fig. 6 shows ENOB versus fre-
quency for the same DAC. We notice that ENOB is a function
including all components which make up noise and distortion.
of frequency. Reduction in ENOB at high frequencies is mainly
The SNR of an ideal converter is defined by the number of
due to clock jitter. ENOB measurement results for single-ended
bits N which sets the quantization noise floor of the device.
and differential outputs are included on the plot. Even harmon-
In practical converters, other distortions will add to this noise
ics are cancelled in differential mode thus improving SNDR
floor resulting in a lower SNR (called SNDR as described previ-
and ENOB. High-speed DACs are usually implemented with
ously), which leads to an effective number of bits (ENOB) less
differential outputs.
than N bits. ENOB takes many converter errors (such as integral
nonlinearity, differential nonlinearity, total harmonic distortion,
and noise) and conveniently reports them as one specification, C. High-Speed DAC Examples
providing an overall picture of a converter’s dynamic perfor- Fig. 7 shows two examples of high-speed 6-bit DACs. The
mance. SNDR translates to ENOB using the theoretical SNR of first, (a), is realized in 130-nm SiGe BiCMOS technology and
an ideal converter, SNR(dB) = 6.02 N + 1.76 dB, where N is has a sample rate of 22 GSa/s [11]. The second, (b), is in 90-nm

Fig. 7. Micrographs of 6-bit high-speed DACs. (a) fs = 22 GSa/s in 130-nm BiCMOS technology [11]. (b) fs = 56 GSa/s in 65-nm CMOS technology [12].
(c) ENOB and (d) SFDR versus frequency of 56 GSa/s DAC.


CMOS technology and achieves a sample rate of 56 GSa/s [12].

Power dissipation is 1.2 and 0.75 watts, respectively. Table II
lists state-of-the-art high-speed DACs with sample rates of
20 GSa/s or more. DACs are listed in order of resolution and
sample rate.

D. Extending DAC Sample Rate

The lowest cost of transmission is usually achieved when
each electro-optic operates at maximum practical capacity. This
compels a maximum DAC sample rate. At a given technology
node, DACs may be combined to augment their sample rate and
bandwidth by integer multiples. Fig. 8 shows an architecture
which doubles a DAC effective sample rate. The operation of Fig. 8. Architecture for doubling DAC sample rate. fs = sample rate of
this configuration can be explained as follows. Assume the over- combined DAC outputs. Single DAC input clock frequency is half its sample
all DAC sample rate to be fs with individual DACs sample rate rate.
being half this rate or fs /2. A first DAC generates half the desired
final spectrum (from 0 to fs /4). A second DAC also generates a
and incurs some degradation to ENOB. This architecture can be
spectrum occupying the same bandwidth. This spectrum is up-
extended beyond a multiplication factor of two shown here.
converted with a mixer from baseband to fs /4 (now occupying
the bandwidth from fs /4 to fs /2). The combined spectrum from
the two outputs occupies 0 to fs /2 for an effective sample rate IV. ANALOG-TO-DIGITAL CONVERTERS
of fs . The data instructions to the DACs are pre-equalized to
obtain the desired time-domain signal at the combined output A. ADC Topologies
(represented by the DSP block in the diagram). Any neces- Topologies for high-speed ADC cores include [4]: i) succes-
sary anti-aliasing takes place at the filters in the diagram. This sive approximation register (SAR), ii) flash, iii) pipeline, iii) se-
scheme is more complex, requires equalization and calibration, rial/ripple, iv), folding/interplolating, and iv) time-interleaved.

Fig. 9. High-speed ADC architectures: (a) SAR, (b) flash, (c) pipeline, (d) serial/ripple, (e) folding/interpolating, and (f) time-interleaved.

Fig. 9 shows conceptual implementations of high-speed ADC flash topology. It is a simple architecture since the number of
architectures. amplifiers and flip–flops is equal to the resolution. Propagation
A successive approximation register (SAR) ADC implements delay through each stage is critical.
a binary search algorithm. In a SAR ADC, the bits are decided The folding ADC is similar to the flash ADC but reuses the
by a single high-speed, high accuracy comparator bit by bit, comparators multiple times which reduces the number of com-
from the MSB down to the LSB [see Fig. 9(a)]. The SAR ADC pators from 2N –1 to 2N /M , where M is the M -times folding
compares the analog input with a DAC, whose output is updated circuit (typically M = 2) [see Fig. 9(e)]. Interpolation between
by previously decided bits and successively approximates the preamp outputs also reduces number of preamps, which reduces
analog input. An N -bit conversion takes N steps. This serial area and power dissipation.
nature of a SAR ADC limits its operating speed. The time-interleaved ADC is an architecture that cycles
A flash or parallel ADC is comprised of a large bank of through a set of N sub-ADCs, such that the aggregate through-
comparators, each consisting of wideband, low-gain preamp(s) put is N times the sample rate of the individual sub-ADCs [see
followed by a latch [see Fig. 9(b)]. As a result, a flash ADC is a Fig. 9(f)]. The sub-ADCs used in time-interleaved architectures
fast architecture. It is mainly used in low resolution ADCs since are usually SAR ADCs. The SAR architecture is usually slow
the number of comparators is proportional to 2N –1 and can be but it is simple and provides a binary output. The number of
large. For example, a 6-bit flash ADC will require 26 –1 = 63 required sub-ADCs is the ratio of the total sample rate to the
comparators. They also require conversion circuitry from out- sub-ADC sample rate and can be of order 10 or more.
put thermometer code to binary values. It has a higher power Time interleaving allows lower speed CMOS switched capac-
consumption and form factor than the SAR architecture. itor circuits in the implementation of the ADC function above
A pipelined ADC employs a parallel structure in which each 10 GHz sample rate [23]. The input bandwidth is determined by
stage works on one to a few bits (of successive samples) con- the first set of track-and-hold (T/H) circuits. Since the clocks of
currently [see Fig. 9(c)]. This inherent parallelism increases elemental ADCs are offset by a fraction of their sampling rate,
throughput, but at a trade-off of power consumption and la- clock generation and distribution is a challenging component of
tency. A pipelined ADC generally requires significantly more the interleaved ADC design. Calibration circuits are required to
area than an equivalent SAR ADC. In a pipeline, however, to a correct for offset, gain mismatch and timing skew between the
first order the complexity only increases linearly, not exponen- sub-ADCs. For example, in [23], 16 sub-ADCs are used. ADC
tially, with the resolution. A pipelined device usually has much architectures are compared in Table III.
lower power consumption than a flash architecture.
A serial or ripple ADC architecture is shown in Fig. 9(d).
The track-and-hold (T/H) circuit holds the input signal constant B. ADC Specifications and Measurements
during the conversion cycle. There are N stages, each of which ADCs have specifications similar to DACs [9] and the test
have a bit output and a residue output. The residue output of method used to characterize ADCs is also based on spectral
one stage is the input to the next. The last bit is detected with a analysis. The test setup to measure ADCs is shown in Fig. 10. A
single comparator. This architecture is slightly slower than the signal generator is set to the desired frequency. For ADCs with


High ADC sample rates require tight control of clock jitter.
Aperture jitter, the inability of ADCs to sample at precisely
defined times, limits ADC sample rate and ENOB. Fig. 12 show
a plot of ENOB as a function of ADC input frequency. It was
originally initiated by Walden [36] and has since been updated
by various people. On the plot, blue dots refer to electronic
ADCs performance compiled by Murmann [37]. Red stars refer
to photonic ADCs compiled by Khilo [38]. The dashed lines
represent the loci of constant values of aperture jitter. SNDR in
decibel is related to aperture jitter as follows [39]:
SNDR(dB) = −20 × log 10 (2πf tj ) (3)
where f is the input analog frequency and tj is the rms aperture
jitter of the ADC. Eq. (3) assumes an infinite resolution ADC
where aperture jitter is the only factor in determining SNDR.
Theoretical ENOB for fixed aperture jitter is calculated using
Eq. (3). The scatter plot in Fig. 12 shows that electronic ADCs
are limited by aperture jitter. In order to move beyond this
limit other architectures such as photonic ADCs may have to be
Fig. 10. Test setup for measuring an ADC’s dynamic performance. Differen-
tial configuration is shown.
considered [38].
In standard operation, the receiver locks the sampling instant
to the data clock phase. Untracked jitter is that part of the data
clock phase not tracked by the receiver clock recovery. Fig. 13
shows ENOB is influenced by resolution and untracked jitter.
Note the effects of INL/DNL are included as a half bit off-
set for both 6- and 8-bit designs. These results are calculated
as follows. A zero mean, normally distributed, untracked jitter
with jitter standard deviation σt contributes a noise-to-signal
ratio (NSR) of NSR = 4 · π 2 · (σt · v)2 to a converted sine tone
of frequency v. This frequency dependent noise-to-signal ratio
adds to the quantization noise-to-signal ratio to affect the fre-
quency dependence of ENOB as shown in Fig. 13. Untracked
jitter will produce larger ENOB variation in higher resolution
Fig. 11. (a) Example of 40 GSa/s 6-bit ADC in 65-nm CMOS technology [25].
(b) Measured ENOB versus frequency. Fig. 14 presents the OSNR penalty due to ADC, or DAC,
noise for different modulation formats (cardinality). The as-
sumptions used in generating that plot are: i) a 25 dB SNR
a differential input the signal generator output is connected to implementation noise with 0 dB eye closure is used, ii) the sym-
a 180-degree hybrid to generate a differential signal as shown bol rate is 35 Gsymbol/s, iii) the error rate is 3%, iv) optimum
in Fig. 10. The amplitude is set to 95% full scale so that the power is launched into fiber in presence of optical nonlinear,
ADC input is not saturated. Once the signal is digitized, data are clipping, and quantization noises, and v) untracked clock jitter
transferred to the computer for calculating the frequency domain is less than 2% unit interval (U.I.) rms. The ENOB referenced
spectrum from which dynamic parameters are calculated (see at 1 GHz on the plot refers to the near static resolution of the
Section III-B). This process is repeated for each frequency of converter. It is the resolution minus approximately half a bit to
interest up to Nyquist frequency. ADCs characterization usually account for INL/DNL. For a given OSNR penalty, higher cardi-
follows the IEEE Standard 1241-2000 test methodology [24]. nality requires higher ADC/ADC resolution. For example, from
Fig. 14, six ENOB can provide less than 0.1 dB OSNR penalty
C. High-Speed ADC Examples up to 16-QAM.
Fig. 11 shows an example of a 6-bit 40 GSa/s ADC realized
in 65-nm CMOS technology [25]. Power dissipation is 1.5 W. E. Extending ADC Sample Rate
Reduction in ENOB at high frequencies is primarily due to As it is with DACs, it is possible to combine several ADCs to
clock jitter, uncompensated timing skew, and track-and-hold multiply the effective sample rate and addressable bandwidth.
(T/H) non-linearity. Table IV lists state-of-the-art high-speed The diagram in Fig. 15 includes two ADCs which doubles the
ADCs with sample rates of 20 GSa/s or more. ADCs are listed sample rate. The spectrum of the input signal from 0 to fs /2
in order of resolution and sample rate. is split into two halves through filtering. The first part of the


Fig. 14. OSNR penalty due to ADC or DAC noise.

Fig. 12. “Walden plot” showing ADC ENOB as a function of analog in-
put frequency. Blue dots refer to electronic ADCs performance compiled by
Murmann [37]. Red stars refer to photonic ADCs compiled by Khilo [38]. The
dashed lines represent the loci of constant values of aperture jitter.

Fig. 15. Architecture for doubling ADC sampling rate. fs = sampling rate of
combined ADC inputs.

input signal. A similar scheme is used in high-end real-time

sampling oscilloscopes [40].

Fig. 13. Frequency dependence of ENOB versus untracked jitter. V. DIGITAL SIGNAL PROCESSING

spectrum from 0 to fs /4 is digitized by a first ADC. The second A. Transmitter and Receiver Functions
half is downconverted to baseband through a mixer and digitized Transmit DSP functions can include: i) mapping of data
by a second ADC. These two digitized signals are recombined onto phase, amplitude, and polarization, ii) transmitter synchro-
in the DSP section to produce a digital version of the analog nization and timing, iii) dispersion pre-compensation, iv) pulse

Fig. 17. Time- and frequency-domain relative equalizer (EQ) complexity ver-
sus number of taps.

pulse response is given by

2πc 2
h(t) = exp j t (4)
DLλ2 DLλ2

where c is the speed of light, λ is the wavelength of the laser

source in nanometers, L is the length of the fiber in km, and
D is the dispersion parameter of the fiber in ps/(nm–km). In
the time-domain linear finite-impulse response (FIR) filters are
used for dispersion compensation. Filter length grows linearly
with the maximum dispersion compensated. For symbol rate R,
Fig. 16. Time-domain (a) and frequency-domain (b) equalizers. CFFT: com-
plex FFT; ICFFT inverse complex FFT. the number of T /2 taps, N , at wavelength λ, is of order:

N ≈ 2 · L · D · R2 · . (5)
shaping, v) RF drivers and electro-optics (E/O) equalization as c
well as nonlinearity compensation, and vi) pre-compensation of Dispersion equalizers typically have a large number of taps
intra-channel propagation nonlinearities (e.g., self-phase mod- and slow update rate (consistent with slow changes in link
ulation or SPM). Coherent receiver DSP functions include: dispersion). For example, a 115 Gb/s DP-QPSK transmitter
i) channel equalization and dispersion compensation, ii) carrier, equalizer uses approximately 320 T/2 taps to compensate for
clock, and polarization recovery, and framing, iii) receiver syn- 1500 km of G.652 fiber with update rates of order seconds. The
chronization and timing, and iv) data detection and de-mapping. same equalizers serve to compensate receiver and/or transmit-
Some of the transmitter and receiver functions use the same ter responses and delays. The long timescale of link dispersion
procedure, for example, equalization. Other functions are spe- change, in comparison with roundtrip propagation delays (less
cific to each. than 12 ms) makes dispersion compensation and tracking as ef-
fective (in terms of linear performance) whether implemented at
the transmitter or the receiver. In case of the former, a transmitter
B. Equalization DAC is required. It has been shown [43], [44] that single chan-
Equalization can be performed either in the time [41] or fre- nel performance improves in the presence of Kerr nonlinearity
quency domain [42]. Fig. 16(a) and (b) shows typical architec- when dispersion compensation is shared between the receiver
tures for time- and frequency-domain equalizers, respectively. and transmitter.
Given a filter length of N taps operating on N samples, complex-
ity is proportional to N 2 in the time domain and N × log2(N )
C. Transmitter Pulse Shaping
in the frequency domain (see Fig. 17). Complexity determines
power dissipation at a given process node. Pulse shapes can be designed for high spectral efficiency.
Chromatic dispersion is compensated through equalization. To this end, a pulse shape is chosen to reduce spectral occu-
Chromatic dispersion is a linear operation on the electrical field. pancy and minimize inter-symbol interference (ISI). A well-
It can be equalized using linear filtering. To this end, fiber im- known family of pulse shapes with the requisite properties is a

Fig. 18. Raised-cosine filter response for various roll-off (α) factors.

Fig. 20. (a) Untracked jitter is modeled as Gaussian distributed. (b) SNR as a
function of pulse shaping and untracked jitter.

Fig. 19. Spectral occupancy control using spectral shaping. (a) No extra spec-
tral shaping used. (b) Spectral shaping using raised-cosine filtering (α = 0.14).

raised-cosine filter given by

1 for |f | ≤ 2W0 − W

⎨  2
π |f | + W − 2W0
H(f ) = cos

for 2W0 − W < |f | ≤ W

⎪ 4 W − W0
⎩ Fig. 21. SNR penalty as a function of subcarrier separation for standard (non-
0 for |f | > W spectrally shaped) and spectrally shaped subcarriers.
where W = total bandwidth, W0 = 1/2 T, and W − W0 = in [45], Nyquist pulses were designed to improve nonlinearity
excess bandwidth. 2W is the spectral occupancy and 2W0 is tolerance and reach for DP-QPSK and DP-16QAM systems. The
the symbol rate. The roll-off factor α equals (W − W0 )/W0 . transmitter DAC is a powerful tool for practical implementation
It controls excess bandwidth for a given symbol rate. Fig. 18 of this function.
shows the raised-cosine response for several roll-off factors. In Pulse shaping maintains eye opening as shown in Fig. 19. It
practice, the overall raised-cosine response of the channel is can be seen that the timing window decreases for small roll-off
shared as root-raised-cosine filters at Tx and Rx. This matched factor values. Fig. 20 shows how pulse shaping and untracked jit-
filter arrangement gives maximum channel SNR. ter affect SNR. Untracked jitter instances are modeled as Gaus-
Fig. 19 is an example pulse shaping to control spectral oc- sian distributed. Higher spectral efficiency obtained using pulse
cupancy. In Fig. 19(a), the spectrum is largely controlled by shaping demands lower untracked jitter.
analog hardware responses (e.g., RF drivers and E/O modulator Fig. 21 compares measured crosstalk penalty (dB SNR) ver-
frequency responses). On the other hand, filtering in the digital sus normalized channel separation (separation divided by sym-
domain allows precise control on the desired spectral shape. bol rate) for two implementations. One of these has a raised-
Other types of pulse shaping can be designed. For example, cosine α = 0.14 channel shape obtained using a DAC and linear

Fig. 22. 1 Tb/s (a) and 2 Tb/s (b) superchannels. Each subcarrier is carrying Fig. 24. Block diagram of polarization recovery circuit.
a payload of 200 Gb/s using DP-16QAM modulation format. Optical spectrum
analyzer (OSA) resolution bandwidth (rbw): (a) 0.031 nm and (b) 3 pm.

Fig. 25. Cycle slip occurrence.

Fig. 23. Frequency offset compensation and carrier recovery.
tion channel which can be of order 10 Poincaré kilo-radians per
modulator driver. The other has a more standard channel shape second. To meet this requirement, it is useful to keep the filters
obtained using a limiting modulator driver. It can be seen that length short. At the same time, the filters must be long enough
the raised-cosine shape allows a normalized channel separation to contend with the maximum polarization delay expected from
which is approximately 60% lower than the more standard shape the channel. This maximum delay is roughly three times the
for an SNR penalty of less than 0.5 dB. maximum mean differential group delay (DGD) of any link on
Pulse/spectral shaping is a key capability for flexible grid or which the transceiver is deployed.
gridless networks, and for spectral aggregates such as “super-
channels.” Fig. 22 shows examples of 1 and 2 Tb/s aggregates F. Cycle Slips
composed of present day commercial technology. These have Coherent systems require accurate phase reference. Carrier
200 and 400 GHz spectral occupancy, respectively, achieving a phase reference must be tracked at high speed. Cycle slips oc-
spectral efficiency of 5 b/s/Hz. Each subcarrier carries a payload cur when there is too much phase noise (rotational noise) in
of 200 Gb/s using DP-16QAM modulation format. Many super- the received signal (see Fig. 25). For example, cycle slips can
channel trials have been realized (see, for example, [46]). Pulse occur when phase tracking error reaches π/4 for QPSK or π/2
shaping applied in the digital domain outperforms pulse shaping for BPSK modulation formats. Several factors can contribute
techniques using state-of-the-art electrical or optical filters [47]. to the probability of cycle slip occurrence: laser phase noise,
optical amplifier noise, and non-linear effects from neighboring
D. Receiver Frequency Offset Compensation channels on dispersion compensated links.
and Carrier Recovery Cycle slips occur with some probability, driven by noise,
when untracked phase wander causes a reference error which
Fig. 23 shows the processing steps for frequency offset com-
interchanges decision boundaries. The new, errored, reference
pensation and carrier recovery. The frequency offset is first es-
phase is stable. This phase error is undetected by carrier recov-
timated, and then, it is removed. What remains is phase random
ery. The resulting high symbol error rate persists until the cycle
walk that is tracked by the carrier recovery circuit.
slip is corrected. To keep cycle slip probability below 10−19
per symbol, which represents approximately 1 cycle slip per
E. Polarization Recovery 10 year lifetime at 28 Gsymbol/s, and in the limit when linewidth
Polarization is recovered with four independent pro- is the dominant contribution to phase noise, corresponds to the
grammable filters arranged in a multiple input multiple output following condition for QPSK modulation format [48]:
(MIMO) configuration as in Fig. 24. These filters converge by
LW × T < 10−6 . (7)
method of minimum least square error to approximately contain
the inverse of the polarization channel. This solution compen- Where LW is the laser linewidth and T is the symbol period.
sates for PMD and also redresses the effects of PDL at the cost of Cycle slips can be managed by design. For example, pilot
some noise enhancement. The convergence speed of the MIMO symbols with known data information can be inserted periodi-
must be compatible with the speed of change of the polariza- cally within the data transmission as shown in Fig. 26(a) [49],

Fig. 27. Corrected BER versus Q2 for different FEC encoding. Net effective
coding gain (NECG) relative to uncoded system is indicated on plot.
Fig. 26. Cycle slip mitigation. (a) Using pilot symbols insertion. (b) Using
differential encoding/decoding.

[50]. This would allow a phase correction since the recovered

carrier phase could be compared with the phase derived from
that of known pilot symbols. Pilot symbols constitute overhead
and require an increase in symbol rate at a given capacity.
Alternately, differential encoding/decoding might be used
[see Fig. 26(b)] whereby information is encoded in phase tran-
sitions, rather than absolute phase. The differential decode can
be applied before or after data detection. In the latter case, the
error rate doubles since each symbol interval is a party to two
phase transitions. In the former case, the receiver noise dou-
bles because data are obtained from the comparison of a noisy
signal with a delayed noisy signal rather than the comparison
of a noisy signal with a quiet local oscillator. In either case, a
Fig. 28. Shannon limit of net effective coding gain (NECG) versus FEC
cycle slip only affects two symbols. Thus, differential modula- overhead.
tion provides increased tolerance to cycle slips at the expense
of reach. Cycle slips can also be mitigated by using advanced
carrier recovery and/or advanced FEC algorithms. decision (SD) decoder. Hard decision FEC (hard-FEC) requires
less information to be transferred between the detector and the
FEC engine thereby allowing separately integrated receiver and
G. Forward Error Correction FEC ASICs. Soft decision FEC (soft-FEC) entails more infor-
Forward error correction (FEC), by which transmitted data mation such that the FEC engine is usually co-integrated with
are pre-coded to allow identification of errors on detection after the receive DSP.
decoding, is essential to high capacity transmission [51]. Fig. 27 The first commercial coherent 40 Gb/s and 100 Gb/s
shows output BER versus Q2 for different FEC codes. For each transceivers used integrated receive DSP and hard decision FEC
example, the net effective coding gain (NECG) in dBQ2 eval- to achieve a coding gain greater than 9 dB with 7% overhead.
uated at a corrected error rate of 10−15 is displayed. Coding More recently, soft decision FEC co-integrated with receiver
gain is a rough measure of reach improvement provided by the DSP has been commercialized.
FEC. Among other things, coding gain is related to the ratio of Fig. 29 displays the relation between system reach relative
transmitted error correction bits to information bits. This ratio is to DP-QPSK at BER = 0.02 (red square), modulation cardinal-
also known as overhead. All other things being roughly equal, ity, and the uncoded BER for uncorrectable errors below 10−15
the greater the overhead the higher the coding gain. Coding probability of occurrence. The latter metric is often used as a
gain also depends on the amount of detected signal informa- proxy for coding gain. For this graph, implementation noise is
tion which is used in the correction of errors. It is shown in set to 15 dB and links are comprised of 100 km spans of G.652
Fig. 28 that, for a given overhead, a FEC that relies on detected fiber at insertion loss of 21 dB/span with per span lumped am-
symbols, a so called hard decision (HD) decoder, has a coding plification at 5 dB noise figure. Relative reach is evaluated for
gain which, at its limit, is approximately 1.1 –1.6 dB lower than a full fill C-band system. Lines of constant uncoded BER inter-
a FEC which relies on symbol probabilities, or so called soft sect with modulation cardinality lines at the maximum relative

Fig. 31. Micrographs of transmitter ASICs including DSP and 6-bit DACs.
(a) 130-nm BiCMOS ASIC with two 23 GSa/s DACs for transmitter chromatic
dispersion compensation in 10 Gbs IM-DD transceiver. (b) 65-nm ASIC with
four 40 GSa/s DACs used in 100 Gb/s coherent transceiver.

Fig. 29. FEC performance and reach at maximum capacity for different mod-
ulation formats. Isolines represent constant BER values. Reference reach (red
open square) is set for DP-QPSK modulation format at BER = 0.02.

Fig. 32. Micrographs of receiver ASICs including DSP and four 6-bit ADCs
all in CMOS technology used in coherent transceivers. (a) 90-nm used in 40 Gb/s
transceiver [3]. (b) 65-nm used in 100 Gb/s dual-carrier transceiver. (c) 32-nm
used in multi-rate transceiver.

Several ASICs incorporating DSP and DACs or ADCs have
been realized.

A. Transmitter
Fig. 31 shows two transmitter monolithic ASICs comprising
6-bit DACs plus DSP used in commercial products. Fig. 31(a)
Fig. 30. Spectral efficiency versus reach for dual-polarization systems with is a 130-nm BiCMOS ASIC circa 2005 with two 23 GSa/s
different modulation formats. DACs used for transmitter dispersion compensation in a 10 Gb/s
IM-DD transceiver. Fig. 31(b) presents a 65-nm CMOS ASIC
circa 2012 with four 40 GSa/s DACs used in a 100 Gb/s coherent
reach supported provided ideal execution and zero excess
margin at the nonlinear Shannon limit. It can be seen that max-
imum relative reach increases for increasing FEC-supported B. Receiver
uncoded BER and decreasing cardinality. Fig. 32 shows examples of receiver monolithic ASICs in-
Fig. 30 shows spectral efficiency on two polarizations versus cluding four 6-bit ADCs and associated DSP. Fig. 32(a) shows
reach for square QAM modulation formats of different cardi- a receiver ASIC in 90-nm CMOS technology used in 40 Gb/s
nalities. Of these, the solid lines depict performance obtainable coherent transceivers [3]. Fig. 32(b) presents a 90-nm CMOS
with soft decision FEC and the dashed lines, obtainable with ASIC used in 100 Gb/s dual-carrier transceivers. Fig. 32(c)
hard decision FEC. Also drawn is the limiting performance ob- shows a receiver ASIC realized in 32-nm CMOS process which
tainable with Gaussian modulation. Estimates assume the same allows multi-rates up to 200 Gb/s.
line parameters and implementation noise as used in Fig. 29. At Other receiver ASICs have been realized. In [52], four
a given reach, spectral efficiencies offered by commercial sys- 8-bit 56 GSa/s ADCs are integrated with DSP in 65-nm CMOS
tems are 50%–70% of the values depicted in Fig. 29. It can be technology. In [53], a 50-Gb/s coherent transceiver ASIC in
seen that the cardinalities of practical systems are not likely to 40-nm CMOS technology includes transmit, receive, framer,
much exceed that of 64-QAM and, from Fig. 14, that the high- host interface, and analog front-end functionality in a single
est DAC or ADC resolution required amounts to approximately chip. The four ADC channels consist of eight interleaved 6-bit
7 bits. flash ADCs. This ASIC can compensate up 55 000 ps/nm of

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ACKNOWLEDGMENT measurement/waveform-generators-run-50-gsampless
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1192, Sep./Oct. 2010. He was with the Optical Research and Development Group, Nortel, Ottawa, as
[42] R. Kudo, T. Kobayashi, K. Ishihara, Y. Takatori, A. Sano, and an electro-optic hardware designer from 2001 to 2010. He has been with Ciena,
Y. Miyamoto, “Coherent optical single carrier transmission using overlap Ottawa in a similar role since 2010. His current activities are the development of
frequency domain equalization for long-haul optical systems,” J. Lightw. electro-optic engines and optical coherent modems for next-generation optical
Technol., vol. 27, no. 16, pp. 3721–3728, Aug. 2009. communication systems and system performance evaluation.
[43] A. Mecozzi, C. B. Clausen, and M. Shtaif, “Analysis of intrachannel Dr. Laperle was a Technical Committee Member of OFC/NFOEC from 2010
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communications,” Opt. Exp., vol. 20, no. 8, pp. 8397–8416, Apr. 2012.
[46] BT and Ciena Light World’s First 800G Super-Channel. (May 2013). [On- Maurice O’Sullivan received the Ph.D. degree in physics from the University
line]. Available: of Toronto, Toronto, Canada. He has developed innovative optical transmission
BT-and-Ciena-Light-Worlds-First-800G-Super-Channel.html products for many years.

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