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• Fan-out, Noise Margin, Propagation Delay

– TTL Logic Family

– Supply current spikes and ground bounce

– TTL Logic Family Evolution

– ECL

– CMOS Logic Families and Evolution

– Logic Family Overview

Logic Families/Level of Integration

Level of integration ever

– SSI <12 gates/chip increasing, because of

– MSI 12..99 gates/chip •cost

•speed

– LSI ..1000 gates/chip •size

•power

– VLSI …10k gates/chip •reliability

Limits of integration:

– GSI …1Meg gates/chip •packaging

•power dissipation

•inductive and capacitive

components

Note: Ratio gate count/transistor count •flexibility

is roughly 1/10 •critical quantity

Logic Families/Level of Integration

– Remember: Gordon Moore, 1975. Predictions:

• Mosfet device dimensions scale down by a factor of 2 every 3 years

• #transistors/chip double every 1-2 years.

29/09/2005 EE6471 (KR) 123

Logic Families/Static VI Parameters

Vcc Vcc Vcc

Parameter Comment

Voh(min) High-Level Output Voltage. The minimum voltage level at a logic

circuit output in the logical 1 state under defined load conditions.

Vol(max) Low-Level Output Voltage. The maximum voltage level at a logic

circuit output in the logical 0 state under defined load conditions.

Logic Families/Static VI Parameters

Vcc Vcc Vcc

Parameter Comment

Vih(min) High-Level Input Voltage. The minimum voltage level required for

a logical 1 at an input. Any voltage below this level may not be

recognized as a logical 1 by the logic circuit.

Vil(max) Low-Level Input Voltage. The maximum voltage level required for

a logical 0 at an input. Any voltage above this level may not be

recognized as a logical 0 by the logic circuit.

Logic Families/Static VI Parameters

Vcc Vcc Vcc

Parameter Comment

Ioh High-Level Output Current. Current flowing into an output in the

logical 1 state under specified load conditions.

Iol Low-Level Output Current. Current flowing into an output in the

logical 0 state under specified load conditions.

Logic Families/Static VI Parameters

Vcc Vcc Vcc

Parameter Comment

Iih High-Level Input Current. Current flowing into an input when a

specified high-level voltage is applied to that input.

Iil Low-Level Input Current. Current flowing into an input when a

specified low-level voltage is applied to that input.

Logic Families/Fan-Out

logic inputs that an output can drive

reliably.

Beware:

Modern mixed-technology digital systems often employ logic from different logic families. In

this case Fan-out is meaningless, unless the operating condition is specified exactly.

Unless otherwise specified, fan-out is always assumed to refer to load devices of the same

family as the driving output.

Logic Families/Noise (Voltage) Margin

Vcc Vcc

High state noise margin :

Vnh = Voh(min) − Vih(min)

Vnl = Vil(max) − Vol(max)

Logic 1 Logic 1

Noise margin :

Voh(min)

Vnh Vn = min(Vnh,Vnl)

Vih(min)

Abnormal Indetermined

Operation Range Noise margin required for reliable operation

Vnl

Vil(max) of digital systems in the presence of noise,

Vol(max)

crosscoupling, and ground-bounce.

Logic 0 Logic 0

Sometimes quoted: Percentage noise

margin… bears little practical value.

Logic Families/Propagation Delay

vi

50%

Input

t

vo

vi vo

50%

Output

t

tphl tplh

Parameter Comment

tphl Input-to-output propagation delay time for output going from high

to low.

tplh Input-to-output propagation delay time for output going from low

to high.

(e.g. for 74HC00: 25ns*100µW=2.5pJ) tpavg ⋅ Pdissavg

Logic Families/TTL Logic

Inputs

A

B

Output

Standard TTL Logic:

•Bipolar Transistor-Transistor Logic

•Introduced in 1964 (Texas Instruments)

A B Y •Tremendous influence on the characteristics

0 0 1 Vcc of all logic devices today

0 1 1 5V

1 0 1 •Standard TTL shaped digital technology

1 1 0 R1 R2 R4 •Standard TTL Logic (e.g. 7400) practically

4k 1.6k 130

obsolete (i.e. replaced by more advanced

Q3

logic families, e.g. 74ALS00)

•A large variety of logic functions available

Inputs Q1 D1 •Single- or multi-emitter input transistor Q1

A Q2 Output (up to eight emitters)

B

Q4

•Totem-pole output arrangement (Q3, Q4)

R3

1k

Logic Families/TTL Logic/Static Analysis

Vcc Vcc Low State Analysis:

5V 5V

•Inputs high (connected to Vcc)

•Q1: Inverse-active mode

R1 R2 R4

4k 1.6k 130

•Input currents very low (base current of Q2)

•Q2 conducting (saturated)

•Q4 conducting

Q3

•Q3 and D1 off (approx 0.8V at B of Q3)

OFF

•Power dissipation in R1, Q1, R2, Q2, R3, Q4

OFF Q1 D1 •On-state resistance of Q4 is roughly 1..25Ω

Q2 •Non-ideal pull-down: Vcesat (Q4)

ON •Load will supply output low state current

Q4

R3 ON

1k

Q4 is referred to as current-sinking transistor or pull-

down transistor

Inputs interpreted as “high” when unconnected

(floating).

DON’T LEAVE INPUTS UNCONNECTED !

Floating inputs are susceptible to noise…

Logic Families/TTL Logic/Static Analysis

Vcc

5V High State Analysis:

•One or both inputs low (connected to GND)

R1 R2 R4 •Substantial input current (emitter current Q1)

4k 1.6k 130

controlled by R1

•Q1 on (saturated)

Q3 •Q2 off

ON •Q4 off

ON Q1 D1 •Q3 and D1 on

•Q3 acts as an “active pull-up”

Q2

OFF •Non-ideal pull-up: Vbe (Q3) and Vfw (D1)

Q4 •Output high current through R4, Q3, D1

R3 OFF •Power dissipation in R1, Q1, R2, R4, Q3, D1

1k •Vcc will supply output high state current

pull-up transistor

Logic Families/TTL Logic/Cascading TTL

5V 5V 5V

R1 R2 R4 R1 R2 R4 R1 R2 R4

4k 1.6k 130 4k 1.6k 130 4k 1.6k 130

Q3 Iih Q3 Q3

Iil

Q1 D1 Q1 D1 Q1 D1

Q2 high

Q2 low

Q2

Q4 Q4 Q4

R3 R3 R3

1k 1k 1k

Logic Families/Supply Current Spikes

Vcc

5V Output Low-to-High Transient:

R1 R2 R4

•Initially: Q3 off, Q4 on (saturated)

4k 1.6k 130 •Q4 turned off, Q3 turned on

•Change of state of Q4 takes longer than Q3

Q3 •During a short interval both Q3 and Q4 are

conducting (cross-conduction, “shot-through”).

Q1 D1 i_transient

•Supply sees a relatively large current surge.

Q2 •Additional current surge due to load

Q4 capacitance (e.g. input capacitance of following

R3 gate)

1k Cload

vo

to HIGH, a current spike is drawn from the supply.

t Essential: POWER SUPPLY DECOUPLING!

icc iccl

icch Current spikes can cause noise problems (inductive cross-

t coupling). Identify loops and minimise loop areas!

Logic Families/Ground Bounce

Vcc

5V Output High-to-Low Transient:

R1 R2 R4

•Initially: Q3 on, Q4 off

4k 1.6k 130 •Negligible Q3/Q4 cross-conduction

•Fast discharge of load capacitance through Q4

Q3

•Discharge current spike through IC ground pin.

Q1 D1 i_transient

Q2

Q4

vi R3

1k Cload

coupling). Identify loops and minimise loop areas!

Logic Families/Ground Bounce

Vcc

5V

Discharge current path

R1 R2 R4 •positive electrode of load capacitance

4k 1.6k 130

•Q4

Q3 •bond wire

•IC pin

Q1 D1 •tracks on PCB

Q2 •ground plane on PCB

Q4 •negative electrode of load capacitance

R3

1k Cload •sections of the discharge current path are

vi_eff

i_transient shared with the input voltage loop

internal IC GND

vi

L_shared Transient currents through shared inductance (bond wire,

(package, tracks) vl_s tracking) is the cause for “ground bounce”.

Ground Bounce = Voltage Difference between internal and

external ground

external IC GND L_unshared

diL _ shared

vl _ s = L _ shared ⋅ vi _ eff = vi − vl _ s

dt

29/09/2005 EE6471 (KR) 137

Logic Families/Ground Bounce

Digital logic gates are differential amplifiers!

They look at input voltages with respect to their

internal ground.

Transient voltages across inductances between

internal and external ground distort the input

voltage and results in undesired feedback

(positive or negative).

Typically ground bounce does not significantly

impair the transmitted signal, but it interferes in

a major way with signal reception.

•Minimise di/dt by proper choice of gate family

•Minimise shared inductance (star point GND

connection)

•Use ICs with separate driver and logic ground pins

•Identify current loops and minimise loop areas

Logic Families/Ground Bounce 8.46

10

Vcc

5

v1 j

v2 R V

v2 j

0

V

v1eff i2 j

v1 i2 10 ⋅m ⋅A

vls Ls

C − 8.46 10

0 10 20 30 40 50 60 70 80 90 100

0 t( j) 99.994

n ⋅s

10

8.46

Example Parameter: 5

v1effj

•Vcc=5V V

•Tr=10ns vls j

0

V

•Tpd=15ns

ils j

•Ls=40nH 10 ⋅m ⋅A

•C=100pF 5

dils

•R=10Ω vls = Ls ⋅

dt − 10 10

0 10 20 30 40 50 60 70 80 90 100

0 t( j) 99.994

n ⋅s

29/09/2005 EE6471 (KR) 139

Logic Families/TTL/Logic Evolution

BJT (Bipolar Junction Transistor) storage time

reduction by using a BC Schottky diode.

Schottky diode has a Vfw=0.25V. When BC

junction becomes forward biased Schottky diode

will bypass base current.

Vcc V cc

R1 R2 R4 R1 R2 R4

4k 1.6k 130 4k 1.6k 130

Q3 Q3

Q1 D1 Q1 D1

A Q2 Y A Q2 Y

B B

Q4 Q4

R3 R3

1k 1k

Logic Families/TTL/Logic Evolution

74 Series

Bipolar. Saturated BJTs. Practically

obsolete. Don't use in new designs!

Bipolar. Deep saturation prevented by Innovations in IC design and

BC Schottky Diode. Reduced storage- fabrication. Improvement in speed and

time delay. Practically obsolete. power dissipation. Relatively popular.

Fastest TTL available.

Bipolar. Lower-power slower-speed Innovations in IC design and Innovations in IC design and

version of the 74S Series. fabrication. Improvement in speed and fabrication. Popular.

power dissipation. Popular.

Logic Families/ECL

Vss TTL

•BJTs operating in saturated mode

•Limited switching speed (storage time)

A

ECL (Emitter-Coupled Logic)

•BJTs operating in unsaturated mode (i.e.

emitter-follower mode)

•Principle: Current switching (ECL is also

Vee

-5.2V

sometimes called Current-Mode-Logic CML)

•fastest logic family available •negative supply (awkward)

•high static power dissipation

•limited choice of manufacturers and devices

•low noise margin

Logic Families/ECL

•Logic 0: -1.7V

•Logic 1: -0.8V

Vss Vss

R1 R2

300 300

Q1 Q2

-1.3V •Very low output impedance

A Y1

(typically 7Ω)

R3 R3

1k 1.5k •Large fan-out

Vee Vee •Fast charge/discharge of load

-5.2V -5.2V capacitances

Logic Families/ECL

•ECL BJTs never saturate. Typical

propagation delays 1ns and below

Vss Vss

•ECL noise margins are very low

(150mV typ)

R1 R2

300 300 •Fan-out is high (25)

•Power dissipation remains

Vbb Q1 Q2 A B relatively constant regardless of

-1.3V

Y1 logic state

R3 R3

1k 1.5k •No current spikes during switching

Vee Vee transistions

-5.2V -5.2V

•Negative supply voltages and logic

levels makes it awkward to

interface ECL to TTL/CMOS.

Logic Families/CMOS

MOS Logic:

MOS: Metal-Oxide-Semiconductor (Metal-

Oxide-Silicon

MOS Logic Categories:

•NMOS (obsolete)

•PMOS (obsolete)

•CMOS: complementary MOS

Advantages of MOS

•inexpensive and simple to fabricate

•high speed

•low static power consumption

•scaling of mosfets: higher integration possible

•rail-to-rail outputs

First CMOS logic family CD4000 introduced in

1968.

Disadvantages of MOS

Because of their advantages CMOS devices •susceptibility to electro-static damage, ESD

have become dominant in the IC market •susceptibility to latch-up

Logic Families/CMOS

CMOS Gate Characteristics:

•No resistive elements (resistors elements

require large chip areas in bipolar ICs)

A Y

•Extremely low static power consumption

(Roff > 1010Ω)

B •Extremely low static input currents

•Cross-conduction and charge/discharge of

internal capacitances lead to dynamic power

dissipation

•Output Y swings rail-to-rail (low Ron)

•Supply voltage can be reduced to 1V and

below

Unused CMOS inputs must be tied to a fixed voltage level (or to another input).

Logic Families/CMOS/Logic Evolution

4000 Series CMOS Logic Trend:

CMOS. Wide supply voltage range.

High noise margin. Low speed. Weak

Reduction of dynamic losses (cross-conduction,

output drive. Practically obsolete. capacitive charge/discharge cycles) by decreasing

supply voltages

(12V→5V → 3.3V → 2.5V → 1.8V → 1.5V…).

74C Series

CMOS. Pin-compatible with TTL

devices. Low speed. Obsolete.

Replaced by HC/HCT family.

Reduction of IC power dissipation is the key to:

•lower cost (packaging)

•higher integration

74HC/HCT Series •improved reliability

CMOS. Drastic increase in speed.

Higher output drive capability. HCT

input voltage levels compatible with

TTL.

CMOS. Functionally compatible, but CMOS. Improved speed, lower power, CMOS/Bipolar. Combine the best CMOS. Reduced supply voltage.

not pin-compatible to TTL. Improved lower drive capability. features of CMOS and bipolar. Low LVC: 5V/3.3V translation

noise immunity and speed. ACT inputs power high speed. Bus interfacing ALVC: Fast 3.3V only

are TTL compatible. applications (74BCT, 74ABT) AVC: Optimised for 2.5V, down to 1.2V

Logic Families/Overview

Logic Prop. Rise/Fall Vihmin Vilmax Vohmin Volmax Noise

Family Delay Time Margin

74 22ns 2.0V 0.8V 2.4V 0.4V 0.4V

74LS 15ns 2.0V 0.8V 2.7V 0.5V 0.3V

74F 5ns 2.3ns 2.0V 0.8V 2.7V 0.5V 0.3V

74AS 4.5ns 1.5ns 2.0V 0.8V 2.7V 0.5V 0.3V

74ALS 11ns 2.3ns 2.0V 0.8V 2.5V 0.5V 0.3V

ECL 1.45ns 0.35ns -1.165V -1.475V -1.025V -1.610V 0.135V

4000 250ns 90ns 3.5V 1.5V 4.95V 0.05V 1.45V

74C 90ns 3.5V 1.5V 4.5V 0.5V 1V

74HC 18ns 3.6ns 3.5V 1.0V 4.9V 0.1V 0.9V

74HCT 23ns 3.9ns 2.0V 0.8V 4.9V 0.1V 0.7V

74AC 9ns 1.5ns 3.5V 1.5V 4.9V 0.1V 1.4V

74ACT 9ns 1.5ns 2.0V 0.8V 4.9V 0.1V 0.7V

74AHC 3.7ns 3.85V 1.65V 4.4V 0.44V 0.55V

(Typical values for rough comparison only. Refer to datasheet. Values valid for Vcc=5V)

Care is needed when driving inputs of one logic family by outputs of a different family !

Watch voltage levels and fan-out !

Logic Families/Overview

View of a Logic

IC manufacturer

(Fairchild)…

Biased?

http://www.fairchildsemi.com/collateral/lsg2000.pdf

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