0 views

Uploaded by Gayathri cn

MJNHBN

- Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating
- MSM6544
- Lecture17-Domino+Registers
- 10 Tips for Successful Scan Design Part One
- April May 2011
- Clock Dividers 1.5, 2.5, 3 and 5
- Ch7 Sequential
- Static Timing Analysis Facts PDF
- ch03art
- An Efficient D-Flip Flop Using Current Mode Signalling Scheme
- Static Timing Analysis
- 10.1.1.137.3981
- 2S100.pdf
- ATPG Methodology Flow
- Sample Research Paper
- EC_Gate Morning 16 feb_update.pdf
- List Active Parts, TAMU ECE equipment room
- 144551742010
- L34.pdf
- Encryption

You are on page 1of 10

Chapter 3

KEY GENERATION USING ESPRESSO ALGORITHM

3.1. Introduction

specifications get updated to meet the evolving technological requirements, set by

society and other technological advances. In the upcoming 5th generation 5G

networks, one of the major focuses is on the Internet of Things (IOT). With the

growth of IOT, more devices will be connected at once, sending more data than ever

before. Because of this, it expected to see data rates increase by a factor of 1000.

Another aspect of IOT is that the type of devices that are connected will vary more

and bring with them new requirements and limiting factors such as internal, limited

power sources, limited resources in terms of size and more [1].

As the development of these technologies progresses, we will therefore not

only see increased demands on data rates but also power efficiency while still

requiring data to be sent securely. This makes it highly relevant to develop safe

encryption technologies that are fast enough to handle the increased data rates while

also being small and energy efficient. Currently, one of the most widely used

encryption algorithm for wireless communication is the industry standard, Advanced

Encryption Standard (AES). As AES might not meet the evolving requirements of the

new 5G networks, it is crucial to compare it to other ciphers in order to find out if

better alternatives exist. Many attempts have been made to find more effective

ciphers. These attempts often focus on only optimizing either size or speed, resulting

in failure to meet the mentioned requirements for different 5G applications. A stream

cipher called Espresso has been proposed as an alternative to today’s encryption

methods, trying to optimize for several of the required parameters

With the increasing demands on data rates, reliability and size, today’s

encryption algorithms may not be good enough to keep up with the upcoming 5G

Department of ECE, Dr. AIT, Bengaluru-560056 Page 14

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

networks. Even if they are, the requirements for energy efficiency will also be

increasing as they might need to be implemented in mobile devices with limited,

internal power sources. The new stream cipher Espresso has been proposed to solve

many of these issues, however not much work has been done to see if Espresso can

deliver. More in depth testing needs to be carried out in order to determine its

viability as a new standard. For Espresso to be considered as a new standard, it is

relevant to make fair comparisons against the Industry standard AES. This has been

done to some extent, but need to be evaluated further [1].

This section describes the stream cipher using Espresso algorithm.

The two main building blocks of Espresso are a 256-bit NLFSR G in the

Galois configuration and a 20-variable nonlinear output function. To avoid confusion

between the feedback functions of G and the feedback functions of the transformed

NLFSR F introduced later, we denote a feedback function of the stage i of G by g,,

for all i € {0, 1, . . . , 255}. The feedback functions of the NLFSR G are specified as

follows:

g255(x) = x0 ⊕ x41x70

g251(x) = x252 ⊕ x42x83 ⊕ x8

g247(x) = x248 ⊕ x44x102 ⊕ x40

g243(x) = x244 ⊕ x43x118 ⊕ x103

g239(x) = x240 ⊕ x46x141 ⊕ x117

g235(x) = x236 ⊕ x67x90x110x137

g231(x) = x232 ⊕ x50x159 ⊕ x189

g217(x) = x218 ⊕ x3x32

g213(x) = x214 ⊕ x4x45

g209(x) = x210 ⊕ x6x64

g205(x) = x206 ⊕ x5x80

g201(x) = x202 ⊕ x8x103

g197(x) = x198 ⊕ x29x52x72x99

Department of ECE, Dr. AIT, Bengaluru-560056 Page 15

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

All remaining feedback functions of G are of type gi(x) = x i+1. The output function

z(x) is specified as follows:

z(x) = x80 ⊕ x99 ⊕ x137 ⊕ x227 ⊕ x222 ⊕ x187 ⊕ x243x217 ⊕ x247x231 ⊕ x213x235 ⊕

x255x251 ⊕ x181x239 ⊕ x174x44 ⊕ x164x29 ⊕ x255x247x243x213x181x174

In order to reduce the propagation delay of the circuit implementing the output

function z(x), we can pipeline it as follows:

z2(x) = x222 ⊕x187 ⊕ x243x217

z3(x) = x247x231 ⊕ x213x235

z4(x) = x255x251 ⊕ x181x239

z5(x) = x174x44 ⊕x164x29

z6(x) = x255 x247 x243x213x181x174

z7(x) = z1(x) ⊕ z2(x) ⊕ z3(x) ⊕z4(x)

z8(x) = z5(x) ⊕ z6(x)

z(x) = z7(x) ⊕ z8(x)

Figure 3.1. As a consequence of the pipelining, the output of the stream cipher is

delayed by two clock cycles, increasing the latency. In addition, the pipelining

increases the area by 8 flip-flops. However, it allows us to increase the throughput by

1.7 times [1].

In order to further reduce the propagation delay of the presented design, we

apply De Morgan rule to re-express the feedback functions g235 and g197 of the

NLFSR G as follows:

g197(x) = x198 ⊕ x29x52x72x99 = x198 ⊕ ((x29x52)′ + (x72x99)′)′

where x′ denotes the Boolean complement of x (defined as x′ = x ⊕ 1), and”+”

denotes the Boolean OR.

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

256 255 . . . . . . . . . . . . 4 3 2 1

The cipher Espresso is initialized as follows. Let ki denote the bits of the key

k, 0 ≤ i ≤ 127, and IVi denote the bits of the initialization value IV, 0 ≤ i ≤ 95. The key

and IV bits are loaded into the shift register as follows:

xi = ki , 0 ≤ i ≤ 127

xi = IVi−128 , 128 ≤ i ≤ 223

xi = 1 , 224 ≤ i ≤ 254

xi = 0 , i = 255

The initialization phase consists of clocking the cipher 256 times; XORing the

produced output bit with the stages x255 and x217. Thus, in this phase the feedback

functions g255(x) and g217(x) of the NLFSR G are given by

Department of ECE, Dr. AIT, Bengaluru-560056 Page 17

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

After initialization, the cipher is clocked for three more cycles and then the

key stream is produced.

the number of random numbers generated before the sequence begins to repeat itself.

A good PRNG should have a very long period. The periodicity of the sequence is

given by 2m – 1, where m is the number of stages of Linear Feedback Sift Register.

Periodicity of binary pseudorandom sequence generated using Espresso algorithm is

equal to 2256 – 1.

algorithm corresponding to 256 bit key is implemented on Xilinx Spartan 2

5V1X0FF324-3 FPGA, ISE simulator using Verilog coding. Design summary is

discussed in the following sections.

5V1X0FF324-3 FPGA

Hardware implementation of generation of binary sequence using Espresso

algorithm corresponding to 256 bit key is implemented on Xilinx Spartan 2

5V1X0FF324-3 FPGA, ISE simulator using Verilog coding.

The RTL Top Level Output File Name, Output Format and Optimization Goal

of the generated sequence are as shown in Table 3.1.

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

launches. The design statistics account for terms such as:

The maximum combinational path delay

The maximum net delay

Table 3.2 shows the Design Statics of the generated sequence using espresso

algorithm. It gives the count of cell usage for the corresponding components.

Components Quantity

# Input Outputs 3

Cell Usage :

# BELS 8

# Clock Buffers 1

Clocks(BUFGP)

# Input Output Buffers 2

# Input Buffer 1

# Output Buffer 1

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

gives Logic cells: 43611, Slices: 6822, Flip-flops:57456. “Logic cells” are not a real

FPGA resource. It is a marketing number; something like “system gates” is used to

describe the device capacity in older FPGA families. Slices are real blocks in FPGA,

but they can be partially use4d in some cases or fully used in other cases. Slice

registers is the number of flip-flops that are implemented in slices.LUT is the number

of lookup tables in the slice. Table 3.3 shows the Device utilization summary of the

generated sequence.

Selected Device 5v1x30ff324-3

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

information, timing summary and timing detail of the generated binary sequence as

shown in Table 3.4. Table 3.5 shows the timing report of gate delay and net delay of

data path out_213 to out_0. Table 3.6 gives the timing summary of the

implementation of binary key generation. Table 3.7 gives the timing report of gate

delay and net delay of data path out_1 ren to out_1. It is observed that the maximum

frequency of operation is 472.255 MHz and device utilization is 257 out of 19200

slices which is approximately 1%.

NOTE: These timing numbers are only a synthesis estimate. For accurate timing

information refer to the trace report generated after place- and- route

Clock Information:

clk BUFGP

rst IBUF

Timing Summary:

Speed Grade -3

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

clock

Maximum output required time after 2.498ns

clock

Maximum combinational path delay No path found

Timing Detail:

‘clk’

Clock period 2.117ns(frequency: 472.255MHz)

ports

Delay: 2.117ns (Levels of Logic = 3)

Source Out_213

Destination Out_0

Table 3.5: Timing Report of Gate Delay and Net Delay of Data Path Out_213 to

Out_0

Data Path Out_213 to out_0

Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18

in Image Encryption and Decryption

FDC D -0.024

(27.7% logic, 72.3% route)

Timing constraint Default OFFSET AFTER for clock ‘clk’

Table 3.7: Timing Report of Gate Delay and Net Delay of Data Path Out_1 ren to

Out_1

OBUF 1.939

(91.5% logic, 8.5% route)

CPU 35.11/35.42 | Elapsed 35.00/ 35.00s

- Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock GatingUploaded byIJSTE
- MSM6544Uploaded byShuvamay Guha
- Lecture17-Domino+RegistersUploaded bySurya Kannan
- 10 Tips for Successful Scan Design Part OneUploaded bybesha1987
- April May 2011Uploaded bymichaelmahesh
- Clock Dividers 1.5, 2.5, 3 and 5Uploaded byShibin Bose Kavara
- Ch7 SequentialUploaded byrizky
- Static Timing Analysis Facts PDFUploaded byLalit Gohate
- ch03artUploaded byMohammed TajuddiNadiya Shaik
- An Efficient D-Flip Flop Using Current Mode Signalling SchemeUploaded byIJSTE
- Static Timing AnalysisUploaded byrajivsharma1610
- 10.1.1.137.3981Uploaded byShrinivas Saptalakar
- 2S100.pdfUploaded byaranjessyzat4134
- ATPG Methodology FlowUploaded byAdhi Suruli
- Sample Research PaperUploaded bysaad321
- EC_Gate Morning 16 feb_update.pdfUploaded byMohitRajput
- List Active Parts, TAMU ECE equipment roomUploaded byWilliam Huang
- 144551742010Uploaded byAlishaKor
- L34.pdfUploaded bysomesh
- EncryptionUploaded bySyeda Ashifa Ashrafi Papia
- bes - security technical overviewUploaded byAshish Daga
- MeseconMicroUploaded bytest6347843
- Lecture NotesUploaded byLello Flo
- asm_ch2_dlUploaded byfoxberry1970
- Digital Fan Regulator mini projectUploaded byManoj Gurrala
- 2-Bit Magnitude ComparatorUploaded byShylesh Prabhu
- www.madeUploaded byShubham Vats
- CdrUploaded byAnupjyoti Deka
- 10.1.1.429.569.pdfUploaded bypraveen
- Digital Principal&System Design 2 Mark_newUploaded byaslprassath

- CBSE XII Chemistry Project Variation of Conductance With .Temperature in Electrolytes.pdfUploaded byGayathri cn
- kjhgfUploaded byGayathri cn
- KJHB MKMKMKM M.docxUploaded byGayathri cn
- CBSE-XII-Chemistry-Project-Variation-of-Conductance-with-.Temperature-in-Electrolytes.pdf.docxUploaded byGayathri cn
- Experimental Skills AssignmentUploaded byGayathri cn

- SIRPNET 2Uploaded byElsa Cristina David
- 39601372 Substitution TechniquesUploaded byChetan Chauhan
- Configuración Juniper Para Cliente ZoomUploaded byJoan Viloria
- Operating System Security_Paul Hopkins, CGIUploaded bySidharth Malhotra
- cn_lab_manuel (1)Uploaded byYamuna Devi
- Lesson09 for StudentsUploaded byNiranjan Nadkarni
- gb.psUploaded by'Pulkit Sharma
- Slides1016.pdfUploaded byMohd HelmiHazim
- cheat2Uploaded bygines
- beierleUploaded byRajesh Lingampally
- Programa PartnersUploaded byRealsec Sistemas de cifrado y firma digital
- 464 Bitcoin and Beyond-TschorschUploaded byricardo
- Highly Area efficient AES encryption design with a new approachUploaded byijsret
- CryptographyUploaded byIffat Khan
- Analytical Comparison of Symmetric Encryption in CloudUploaded byAQ Khn
- COMPUTER SECURITY PPTUploaded byanuj kumar
- How to - Establish VPN Tunnel Between Cyberoam and Cisco Router PIXUploaded byNurain Akram
- MC1701 Computer NetworksUploaded bynellaidenison3548
- Brocade MLXe and Brocade NetIron CER Series Ethernet RoutersUploaded bybrenohenrique
- Netwrk Security.less PlanUploaded byPriyaLal
- Secure File Saving SystemUploaded byvaddeseetharamaiah
- 8 Configuring LDAP[2]Uploaded byDexter Lab
- A3 ALGORITHM.pptxUploaded byChetan Sri Krishna
- Smart Card BasicsUploaded bymesminthomas
- Infiltrate the Vault - Security Analysis and Decryption of Lion Full Disk Encryption 374Uploaded bydoppiamunnezza
- An Illustrated Guide to IPsecUploaded byjoenmusik
- Security+ Study Guide Better Version (1)Uploaded byal
- IRJET-Improvement in the Performance and Security of Advanced Encryption Standard Using AES Algorithm and Comparison with BlowfishUploaded byIRJET Journal
- CS507 Quiz # 4 Solved by UsmanUploaded byPower Girls
- 5 Cryptography Part1Uploaded byRuppee Edward