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AIM: Design and simulation of SR flip flop, JK flip flop, D flip flop, T flip flop using verilog.

TOOL USED: Xilinx ISE 14.7

THEORY:

1) SR Flip Flop: An SR Flip Flop is an arrangement of logic gates that maintains a stable output

even after the inputs are turned off. This simple flip flop circuit has a set input (S) and a reset

input (R). The set input causes the output of 0 (top output) and 1 (bottom output).

S R Q State

0 0 Previous No change

state

0 1 0 Reset

1 0 1 Set

1 1 ? Forbidden

Fig 8.1.circuit diagram of SR flip flop

2) JK Flip Flop: The J-K flip-flop is the most versatile of the basic flip-flops. It has two inputs,

traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the

next clock edge.

Table 8.2.truth table of JK flip flop

J K Q State

0 0 Q No

change

0 1 1 Reset

1 0 0 Set

1 1 Toggle

3) D Flip Flop: The D flip-flop is widely used. It is also known as a "data" or "delay" flip-flop.

The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as

the rising edge of the clock). That captured value becomes the Q output.

4) T Flip Flop: The T or "toggle" flip-flop changes its output on each clock edge, giving an

output which is half the frequency of the signal to the T input. It is useful for constructing binary

counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-

flop by tying both of its inputs high.

Table 8.4.truth table of T flip flop

VERILOG CODE:

D flipflop:

module D(

input d,

input clk,

input rst,

output reg q

);

always@(posedge clk)

begin

q = d;

end

endmodule

T flipflop:

module TT(

input t,

input clk,

output reg q,

output reg qba

);

initial begin q=0; qbar=1; end

always@(posedge clk)

begin

q = t^q;

qbar = ~q;

end

endmodule

SR flip flop

module SR(

input s,

input r,

input clk,

output reg q,

output reg qbar

);

initial begin

q=0; qbar=1;

end

always@(posedge clk)

begin

q=s|q&(~r);

qbar = ~q;

end

endmodule

JK Flip flop :

`

module JK(

input j,

input k,

input clk,

output reg q,

output reg qbar

);

initial begin

q=0; qbar=1;

end

always@(posedge clk)

begin

q=(j&(~q))|((~k)&q);

qbar = ~q;

end

endmodule

TEST BENCHES:

D Flip flop:

initial begin

clk=0;

forever #50 clk=~clk;

end

initial begin

d=0;#100; d=1;#100; d=0;#100;

d=1;#100; d=0;#100;

end

T Flip flop:

initial begin

clk = 0;

forever #30 clk = ~clk;

end

initial begin

t=0;#100; t=1;#100; t=0;#100;

t=1;#100; t=0;#100; t=1;#100;

end

SR Flip flop:

initial begin

clk = 0;

forever #50 clk = ~clk;

end

initial begin

s=0;r=0;#100; s=0;r=1;#100; s=1;r=0;#100;

s=1;r=1;#100; s=0;r=0;#100; s=0;r=1;#100;

s=1;r=0;#100; s=1;r=1;#100;

end

JK Flip Flop:

initial begin

clk = 0;

forever #50 clk = ~clk;

end

initial begin

j=0;k=0;#100; j=0;k=1;#100; j=1;k=0;#100;

j=1;k=1;#100; j=0;k=0;#100; j=0;k=1;#100;

j=1;k=0;#100; j=1;k=1;#100;

end

RTL SCHEMATIC:

D Flip Flop:

T Flip Flop:

SR Flip Flop:

JK Flip Flop:

OUTPUT WAVEFORMS:

D Flip Flop:

T Flip Flop:

Fig 8.10.Output Waveform of T flip flop

SR Flip Flop:

JK Flip Flop:

RESULT: Different flip flops have been designed and simulated using Verilog HDL and

output waveforms along with RTL schematic have been verified.

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