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With Improved Efficiency and Reduced Output

Ripple Current

Jae-Won Yang and Hyun-Lark Do

flyback dc–dc converter with improved efficiency and re-

duced output ripple current. Zero-voltage-switching (ZVS)

technique and a dual-flyback module for reducing the num-

ber of snubber current paths are adopted to improve effi-

ciency. For the ZVS technique, a self-driven synchronous

rectifier (SR) is used instead of an output diode. By turning

the self-driven SR off after a short delay, a main switch is

turned on under the ZVS condition. For reducing the num-

ber of snubber current paths, a dual-flyback module and a

snubber diode are used. When the main switch is turned

off, leakage inductance energy is absorbed by a snubber

diode into an input source and a primary dc-bus capacitor. Fig. 1. Conventional flyback dc–dc converter: (a) with an RCD snubber

and (b) with an LCD snubber.

Then, this energy is reprocessed by the dual-flyback dc-dc

module to secondary side. Hence, there is only one snubber

current path. In addition, the proposed converter features a

these problems, two-switch pulse-width-modulated (PWM) fly-

reduced output ripple current because of the continuous

current. Consequently, the proposed converter can achieve back converters are introduced [4], [5]. By using two clamping

high efficiency and reduced output ripple current. To ver- diodes, switch voltage is clamped to input voltage and leakage

ify the performance of the proposed converter, operating inductance energy is recycled to input source. In addition, to

principles, steady-state analyses, and experimental results achieve zero-voltage-switching (ZVS) turn-on of the switch, an

from a 340 to 24-V, 100-W prototype are presented.

additional lossless snubber circuit is adopted. Another solution

Index Terms—Continuous conduction mode, flyback for recycling the leakage inductance energy is using an active

converter, soft switching, synchronous rectifier (SR), zero- snubber circuit [6], [7]. In [6], a half-bridge flyback converter is

voltage switching (ZVS). presented for satisfying both switch voltage clamping and ZVS

I. INTRODUCTION operation. In [7], an adaptive snubber circuit is introduced to

extend the parasitic output capacitance of the switch, and the

OR the advantages of galvanic isolation, design simplic-

F ity, and a simple control technique, a flyback converter

is the most popular topology for dc–dc and ac–dc converters

converter is operated in the critical conduction mode (CRM) for

near-ZVS operation. The operation in CRM minimizes the turn-

on switching loss of the switch because the MOSFET turn-on oc-

[1]–[7]. However, there are some drawbacks such as voltage curs exactly in the valley of the drain–source voltage oscillation

spike ringing on a switch at turn-off state (because of the res- between a transformer inductor and a parasitic output capacitor

onance between the transformer leakage inductance and the of the switch [8]–[10]. Nevertheless, there is a small switching

parasitic output capacitance of the switch) and hard switch- loss in the switch since it is not a full-ZVS operation. There-

ing loss at turn-on state. Eventually, the switch voltage stress fore, various soft-switching techniques are introduced for high

becomes as high as the sum of the input voltage, the reflected efficiency [11]–[18]. In addition, a synchronous rectifier (SR)

output voltage, and the voltage spike on the switch. To overcome is also introduced instead of a diode for reducing the conduc-

tion loss [19]–[23]. Normally, there are three different kinds of

Manuscript received April 7, 2016; revised July 3, 2016, September SR driving strategies—voltage-driving strategy, current-driving

18, 2016, and October 20, 2016; accepted November 29, 2016. Date of

publication January 16, 2017; date of current version April 10, 2017. strategy [19], [20], and MOSFET drain–source voltage detec-

J.-W. Yang is with the 8th Research and Development Institute, tion [21]–[23]. By replacing a diode with an SR, efficiency is

Agency for Defense Development, Taean 357-900, South Korea (e-mail: improved because turn-on voltage drop across the SR is much

fship01@nate.com).

H.-L. Do is with the Department of Electronic and Information Engi- lower than diode forward voltage drop.

neering, Seoul National University of Science and Technology, Seoul Fig. 1(a) shows the conventional flyback dc–dc converter with

139-743, South Korea (e-mail: hldo@snut.ac.kr). a resistor–capacitor–diode (RCD) snubber. The leakage induc-

Color versions of one or more of the figures in this paper are available

online at http://ieeexplore.ieee.org. tance energy is absorbed by the snubber capacitor and dissi-

Digital Object Identifier 10.1109/TIE.2017.2652404 pated in the snubber resistor. Fig. 1(b) shows the flyback dc–dc

0278-0046 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

3588 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 5, MAY 2017

leakage inductance energy is absorbed by the snubber capacitor Fig. 3. Equivalent circuit of the proposed converter.

and the energy stored in the snubber capacitor is transferred to

an auxiliary inductor. This energy is then restored in an input

source. Since there are three conduction paths (the snubber ca- according to the inductor volt–second balance law, Vdc1 is equal

pacitor, auxiliary inductor, and input source), the reprocessed to Vin and Vdc2 is equal to Vo . To analyze the proposed converter

energy is reduced owing to the conduction loss in an LCD snub- at a steady state, several assumptions are made for a switching

ber. However, for the proposed converter shown in Fig. 2, the period of TS . All switching devices are ideal components except

leakage inductance energy is directly stored in an input source for CSm and CSr . The capacitances of C1 , C2 , and Co are large

and a dc-bus capacitor. Then, this energy is reprocessed by a enough to consider the voltages Vdc1 , Vdc2 , and Vo as constants.

dual-flyback dc–dc module. Since there is only one conduction The theoretical waveforms over a switching period are shown in

path, the conduction loss in the reprocessed leakage inductance Fig. 4. The operating stages are divided into six stages as shown

energy is minimized. When transferring the input power on pri- in Fig. 5.

mary side to secondary side, the input power energy is equally Before t0 , Sr is turned ON and its current direction is changed

divided between two coupled inductors and transferred to the from negative to positive. When the switch current is positive,

load because both the coupled inductors are designed to be equal. the absolute value of is2 is larger than that of is1 . This differ-

Hence, the RMS loss in each coupled inductor is reduced. In ential current discharges CSm and charges CSr at stage 1. On

addition, by turning the self-driven SR OFF after a short delay, the primary side, there is a continuous current Ipri for Vdc1 to

a main switch is turned ON under the ZVS condition as a result become equal to Vin because Vdc1 is slightly lower than Vin .

of the differential current via the two coupled inductors. The On the secondary side also, there is a continuous current Isec

output ripple current is also lower than that of the conventional for Vdc2 to become equal to Vo because Vdc2 is slightly higher

flyback dc–dc converter, because of the continuous current in than Vo .

the secondary side. The theoretical analysis and an experimen- Stage 1 [t0 , t1 ]: When Sr is turned OFF, CSm starts dis-

tal prototype of the proposed converter are presented to verify charging and CSr begins charging. Since CSm and CSr are very

the ZVS operation, efficiency improvement, and reduced output small, the transition time is very short. Hence, iL m 1 and iL m 2

ripple current. are regarded as constant values— IL m 1(m in) and -IL m 2(m in) ,

respectively.

Stage 2 [t1 , t2 ]: At t1 , CSm is fully discharged and DSm

II. ANALYSIS OF THE PROPOSED CONVERTER

starts conducting because the absolute value of iL k 2 is larger

Fig. 3 shows the equivalent circuit of the proposed converter. than that of iL k 1 . After a short delay called a dead time, the gate

There are three switching devices—a main switch Sm , an SR Sr , signal is applied to Sm under the ZVS condition. Therefore,

and a snubber diode Dsn . DSm and DSr are the intrinsic body there is no switching loss on Sm . At this stage, the slopes of

diodes of Sm and Sr , respectively. CSm and CSr denote the par- iL m 1 , iL k 1 , iL m 2 , and iL k 2 are all equal to Vin /(Lm 1 + Lk 1 )

asitic output capacitances of Sm and Sr , respectively. C1 and

C2 are the dc-bus capacitors on the primary side and secondary Vin

iL m 1 (t) = IL m 1(m in) + (t − t1 ) (1)

side, respectively. Since input power should be equally divided Lm 1 + Lk 1

into two coupled inductors and transferred to load, the coupled Vin

inductors should be identical, i.e., T1 = T2 . Each coupled in- iL m 2 (t) = −IL m 2(m in) + (t − t1 ). (2)

Lm 1 + Lk 1

ductor is modeled as a magnetizing inductor Lm 1 (= Lm 2 ), a

leakage inductor Lk 1 (= Lk 2 ), and an ideal transformer with At the secondary side, Isec flows through two secondary wind-

a turn ratio of n : 1 (n = N1p /N1s = N2p /N2s ). Because ings of the coupled inductors. The currents is1 and is2 are con-

the average inductor voltage should be zero at a steady state, stants (Isec and -Isec , respectively).

YANG AND DO: SOFT-SWITCHING DUAL-FLYBACK DC–DC CONVERTER WITH IMPROVED EFFICIENCY AND REDUCED OUTPUT RIPPLE CURRENT 3589

Vin

iL k 2 (t) = −Ipri + (t − t2 ). (4)

Lm 1 + Lk 1

iL m 1 and iL m 2 increase linearly from Ipri + Isec /n and -

(Ipri + Isec /n)

Isec Vin

iL m 1 (t) = Ipri + + (t − t2 ) (5)

n Lm 1 + Lk 1

Isec Vin

iL m 2 (t) = −Ipri − + (t − t2 ). (6)

n Lm 1 + Lk 1

At the middle of this stage, iL k 2 changes its direction from

negative to positive since the absolute value of iL m 2 is smaller

than ip2 (= −is2 /n = Isec /n).

Stage 4 [t3 , t4 ]: At t3 , Sm is turned OFF. CSm starts charging

and CDsn and CSr begin to discharge. At this stage, the capacitor

CDsn (which is the parasitic capacitor of the snubber diode Dsn )

is considered because the leakage current flows through Dsn .

However, since CSm , CDsn , and CSr are very small, the transi-

tion time is very short. Hence, iL m 1 and iL m 2 can be regarded

as constant values— IL m 1(m ax) and -IL m 2(m ax) , respectively.

Stage 5 [t4 , t5 ]: When vSm reaches 2Vin , Dsn and DSr start

conducting. The leakage inductance energy of Lk 1 is stored into

C1 . For Lk 2 , the leakage inductance energy is stored into the

input source. This time interval is closely related to the voltage

vL k 1 (= vL k 2 ). iL k 1 and iL k 2 are expressed as follows:

1

iL k 1 (t) = IL k 1(m ax) − (Vin − nVo ) (t − t4 ) (7)

Lk 1

1

iL k 2 (t) = IL k 2(m ax) − (Vin − nVo ) (t − t4 ). (8)

Lk 2

Stage 6 [t5 , t6 ]: When iDsn is zero and Dsn is turned OFF,

this stage begins. On the primary side, only Ipri flows through

Lk 1 , C1 , and Lk 2 . After a short delay called a dead time, the

gate signal is applied to Sr under the ZVS condition. The current

iSr increases linearly with a slope of 2n2 Vo /Lm 1 . At the end

of this stage, iSr changes its direction from negative to positive.

By turning the SR OFF after a short delay, the absolute value of

is2 becomes larger than that of is1 . This differential current is

essential for the ZVS operation of Sm .

The self-driven SR driver used in this paper is referenced from

[22]. Fig. 6 shows the self-driven SR driver. Cceo is the parasitic

output capacitor of Qa . In order to detect the polarity of the SR

voltage vSr , Da is employed. To obtain high and low signals

according to the polarity of vSr , a NPN transistor Qa and two

Fig. 4. Theoretical waveforms of the proposed converter. resistors, Rb and Rc , are used. Rb limits the base current iRb

of Qa . Rc is inserted to limit the collector current iRc , and to

generate high-level signal for the MOSFET driver with a dead

Stage 3 [t2 , t3 ]: When the main switch current iSm becomes

time. For the proper ZVS operation of Sr , the dead-time should

positive, this stage begins. Similar to stage 2, the slopes of

be considered and it is related to the time constant of the RC

iL m 1 , iL k 1 , iL m 2 , and iL k 2 are all equal to Vin /(Lm 1 + Lk 1 ).

circuit, Vcc , Rc , and Cceo . To compensate for the difference

At t2 , iL k 1 (t2 ) and iL k 2 (t2 ) are equal to Ipri and -Ipri ,

between the forward voltage drop VF (D a) and the base–emitter

respectively,

saturation voltage Vb e(sat) , Ra is added. Several assumptions are

Vin made in the analysis at a steady state. Da is an ideal component,

iL k 1 (t) = Ipri + (t − t2 ) (3) except for the forward voltage drop VF (D a) . Qa acts as a switch,

Lm 1 + Lk 1

3590 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 5, MAY 2017

is not considered. The SR is an ideal component, except for

the drain–source on-resistance RDS(on) and the forward voltage

drop VF (D sr ) . The theoretical waveforms and operating stages

of the self-driven SR driver are shown in Figs. 7 and 8.

Before t0 , Sr is turned ON and Da conducts. The base–emitter

voltage vb e is lower than its saturation voltage vb e(sat) .

Stage A [t0 , ta ]: When vb e reaches vb e(sat) , Qa becomes

saturated and this stage begins. The collector–emitter voltage

vce is clamped to its saturation voltage vce(sat) , and Sr is

turned OFF.

Stage B [ta , tb ]: At ta , Sm is turned OFF. DSr and Da start

conducting. vSr and vDa are clamped to the forward voltage

drops, -VF (D sr ) and -VF (D a) , respectively. Since vSr and vDa

are constant, vb e and vRa are also constant given as follows:

Fig. 7. Theoretical waveforms of the proposed SR driver.

vb e(m in) = VF (D a) + VR a(m ax) − VF (D sr ) (9)

RC circuit as follows:

Ra (Vcc − Vb e(m in) )

VR a(m ax) = . (10) −t

Rb vce (t) = Vcc 1 − e R c C c e o . (11)

Because vb e is lower than Vb e(sat) , Qa enters a breakdown Stage C [tb , tc ]: When vce is higher than VIH , which is

region. vce increases nonlinearly with the time constant of an the logic 1 input voltage of the MOSFET driver, the gate signal

YANG AND DO: SOFT-SWITCHING DUAL-FLYBACK DC–DC CONVERTER WITH IMPROVED EFFICIENCY AND REDUCED OUTPUT RIPPLE CURRENT 3591

circuit of RDS(on) and DSr . The voltage vb e is expressed as given

by Tdead−tim e < TZVS Sm (19)

vb e (t) = VF (D a) + Ra iRb (t) + RDS(on) iSr (t) (12) Tdead−tim e < TZVS Sr (20)

Vcc − vb e (t) where Tdead−tim e is the dead time of both Sm and Sr for proper

iRb (t) = (13)

Rb ZVS operation. TZVS S m and TZVS S r are the time intervals

2n2 Vo when each switch is reverse biased and the current flows through

iSr (t) = −IS r (m in) + (t − tb ). (14) its intrinsic body diode.

Lm 1

Since TZVS S r is sufficiently longer than Tdead−tim e , the

Stage D [tc , td ]: At tc , iSr changes its direction from neg- ZVS operation of Sr is always satisfactory. When consider-

ative to positive. Since vb e is still lower than Vb e(sat) , Sr is ing Tdead−tim e and TZVS S m , the time interval between t0 and

turned ON t1 can be omitted because this time interval is very short. From

iL m 1 in Fig. 4, the following equation is obtained:

2n2 Vo

vb e (t) = VF (D a) + Ra iRb (t) + RDS(on) (t − tc ).

Lm 1 Isec Vin

(15) Ipri + − IL m 1(m in) = TZVS Sm

n Lm 1 + Lk 1

To compensate for the difference between VF (D a) and

Vb e(sat) , Ra is added in series with Da . By adjusting Ra , the nVo

= Δtcd . (21)

turn-on time of Sr can be easily controlled. At the end of this Lm 1

stage, vb e reaches vb e(sat) , and then, Sr is turned OFF. vb e(sat)

From (19) and (21), the ZVS condition of Sm can be

is obtained by

rewritten

2n2 Vo

vb e(sat) = VF (D a) + Ra iRb (td ) + RDS(on) Δtcd (16) nVo (Lm 1 + Lk 1 )

Lm 1 Tdead−tim e < Δtcd . (22)

Vin Lm 1

Vcc − vb e(sat)

iRb (td ) = (17)

Rb V. DESIGN PROCEDURE

where Δtcd is the time interval between tc and td . In order to verify the theoretical analysis, the following design

From (16) and (17), Δtcd can be expressed as specifications are determined. Vin = 340 V, Vo = 24 V, Po =

100 W, and minimum switching frequency fSW (m in) = 45 kHz.

Ra + Rb Ra For a simple circuit analysis, the leakage inductances and the

Δtcd = Vb e(sat) − VF (D a) − Vcc

Rb Rb transition times in both stages 1 and 4 are not considered.

Lm 1

× . (18)

2n2 Vo RDS(on) A. Duty Cycle

Hence, it is possible to control the time interval Δtcd (related From iL m 1 , the following equation is obtained:

to the ZVS operation of Sm ) by adjusting the resistance of Ra .

Vin nVo

IL m 1(m ax) − IL m 1(m in) = Ton = Toﬀ . (23)

Lm 1 Lm 1

IV. ZVS CONDITION OF THE MAIN SWITCH

In order to achieve ZVS operations for Sm and Sr , the gate From (23), the duty cycle D is expressed as

signal should be applied to each switch before the current flow-

ing through the intrinsic body diode becomes zero. The follow- nVo

D= . (24)

ing equations are satisfactory conditions for the ZVS operations Vin + nVo

3592 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 5, MAY 2017

B. Continuous Current

By assuming the leakage inductance to be zero, the average

input and output currents in a switching period are given by

Vin

Iin(avg) = Ipri + D 2 TS (25)

2Lm 1

n2 Vo

Iout(avg) = Isec + (1 − D)2 TS . (26) Fig. 10. Structure of the coupled inductor.

2Lm 1

Since the snubber current is not considered, the input current If n = 12 is selected, D = 0.45 is obtained. By substituting

is the sum of the continuous current for charging C1 and the Vin = 340 V, D = 0.45, TS = 22 μs, and Iin(avg) = 0.294 A

charging current flowing through Lm 1 . Because the magnetizing in (28), Lm 1 = 5.1 mH is calculated. Since the leakage induc-

inductances of both the coupled inductors are designed to be tance is not considered in the design procedure, the experimen-

equal, one half of the input power is transferred to the secondary tal value of Lm 1 (= Lm 2 ) would be different. The reason is that

side by Lm 1 and the other half is transferred by Lm 2 . Therefore, some of the magnetizing inductance energy is not transferred

Ipri is half of the input current, Ipri = 0.5 Iin(avg) . to the secondary side. This energy is moved to the input source

Similarly, the output current is the sum of the continuous and the primary dc-bus capacitor by each leakage inductor.

current for discharging C2 and the discharging current flowing

through Lm 2 . Since one half of the output power is transferred D. Determination of Switching Frequency

from the primary side by Lm 1 and the other half is transferred by

Lm 2 , Isec is also half of the output current, Isec = 0.5 Iout(avg) . The input current can be expressed as an average current of

iSm as follows:

C. Design of Coupled Inductors Vin

Iin = iS m (avg) = D 2 TS . (29)

Lm 1 + Lk 1

The determination of the turn ratio n is important for trans-

ferring the input power to the load. When the main switch is By substituting TS = 1/fsw and Vin Iin = Pin = Pout into

turned OFF and the primary voltage of the coupled inductor nVo (29), the switching frequency fsw can be written as follows:

is lower than Vin , the magnetizing inductance energy is trans- 2

ferred to the secondary side. However, if the primary voltage is Vin 2 nVo

fsw = . (30)

higher than the input voltage, the coupled inductor acts only as Po (Lm 1 + Lk 1 ) Vin + nVo

an inductor, and not as a transformer. Therefore, the maximum

turn ratio n is determined by VI. EXPERIMENTAL RESULTS

Vin From the design procedure, the design parameters of the ex-

n< . (27) perimental prototype are obtained as follows: Lm 1 = Lm 2 =

Vo

3.7 mH, n = 12, C1 = 200 μF, C2 = 6.6 mF, and Co =

By substituting Ipri = 0.5Iin(avg) in (25), Lm 1 can be 6.6 mF. Fig. 9 shows the experimental prototype circuit. Fig. 10

obtained by shows the structure of the coupled inductor.

Fig. 11 shows the experimental waveforms of vSW , iL k 1 ,

Vin D2 TS and is1 (= iout ) at Po = 100 W. Since half of the input power

Lm 1 = . (28)

Iin(avg) is transferred to C1 , the leakage inductor current is floating

YANG AND DO: SOFT-SWITCHING DUAL-FLYBACK DC–DC CONVERTER WITH IMPROVED EFFICIENCY AND REDUCED OUTPUT RIPPLE CURRENT 3593

converters.

Fig. 11. Experimental waveforms of v S m , iL k 1 , is 1 ( = io u t ) at

P o = 100 W.

cessed by a dual-flyback dc–dc module. The maximum effi-

ciency of the proposed converter ηm ax = 94.18% is measured

at Po = 90 W. However, at a light load, the proposed converter

features lower efficiency than the conventional flyback converter

with the LCD snubber. This is because the reverse current for

achieving ZVS operation increases the conduction losses on

both the switches and the coupled inductors. Fig. 14 shows the

measured switching frequency according to the output power. At

the full-load condition, a switching frequency (fsw ) of 42.3 kHz

has been measured.

VII. CONCLUSION

Fig. 12. ZVS operations of S m and S r at 100 W: (a) v S m , v g s S m , iS m , In this paper, a soft-switching dual-flyback dc–dc converter

(b) v S r , v g s S r , iS r .

was proposed. By replacing the output diode with an SR, the

conduction loss was minimized. The ZVS operation of the main

because of the continuous current. Similarly, the output current switch was achieved by turning the self-driven SR OFF, after

is also floating since half of the output power is stored in C2 and a short delay. In addition, the reprocessed transformer leakage

is transferred to the output capacitor by the continuous current. inductance energy was maximized because there was only one

Fig. 12(a) and (b) shows the ZVS operations of Sm and Sr snubber current path. Moreover, its output ripple current was

at 100 W, respectively. Before the gate signal is applied to each reduced owing to the continuous current. Consequently, the pro-

switch, the switch voltage is zero. posed converter satisfied both the high efficiency and reduced

Fig. 13 shows the measured efficiencies of the proposed con- output ripple current conditions.

verter and the conventional flyback converters with RCD and

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[8] T. Yan, J. Xu, F. Zhang, J. Sha, and Z. Dong, “Variable-on- 10.1109/TCSI.2014.2309837.

time- controlled critical-conduction-mode flyback PFC converter,” IEEE [23] J. Park, Y.-S. Roh, Y.-J. Moon, and C. Yoo, “A CCM/DCM dual-mode syn-

Trans. Ind. Electron., vol. 61, no. 11, pp. 6091–6099, Nov. 2014, chronous rectification controller for a high-efficiency flyback converter,”

doi: 10.1109/TIE.2014.2311401. IEEE Trans. Power Electron., vol. 29, no. 2, pp. 768–774, Feb. 2014, doi:

[9] X. Xie, C. Zhao, L. Zheng, and S. Liu, “An improved buck PFC converter 10.1109/TPEL.2013.2256371.

with high power factor,” IEEE Trans. Power Electron., vol. 28, no. 5,

pp. 2277–2284, May 2013, doi: 10.1109/TPEL.2012.2214060.

[10] X. Wu, J. Yang, J. Zhang, and Z. Qian, “Variable on-time (VOT)-controlled

critical conduction mode buck PFC converter for high-input AC/DC HB- Jae-Won Yang received the B.S. and M.S. de-

LED lighting applications,” IEEE Trans. Power Electron., vol. 27, no. 11, grees in electronic and information engineering

pp. 4530–4539, Nov. 2012, doi: 10.1109/TPEL.2011.2169812. from Seoul National University of Science and

[11] C.-H. Chang, C.-A. Cheng, E.-C. Chang, H.-L. Cheng, and B.-E. Yang, Technology, Seoul, South Korea, in 2011 and

“An integrated high-power-factor converter with ZVS transition,” IEEE 2014, respectively.

Trans. Power Electron., vol. 31, no. 3, pp. 2362–2371, Mar. 2016, doi: Since 2014, he has been a Researcher with

10.1109/TPEL.2015.2439963. the 8th Research and Development Institute,

[12] X. Huang, F. C. Lee, Q. Li, and W. Du, “High-frequency high-efficiency Agency for Defense Development, Taean, South

GaN-based interleaved CRM bidirectional buck/boost converter with in- Korea. His research interests include power fac-

verse coupled inductor,” IEEE Trans. Power Electron., vol. 31, no. 6, tor correction, dc–dc power converters, renew-

pp. 4343–4352, Jun. 2016, doi: 10.1109/TPEL.2015.2476482. able energy conversion, and LED lighting.

[13] Y. Shi and X. Yang, “Soft switching PWM cascaded three-level combined

DC-DC converters with reduced filter size and wide ZVS load range,”

IEEE Trans. Power Electron., vol. 30, no. 12, pp. 6604–6616, Dec. 2015,

doi: 10.1109/TPEL.2015.2391285.

[14] S. Sathyan, H. M. Suryawanshi, M. S. Ballal, and A. B. Shitole, “Soft- Hyun-Lark Do received the B.S. degree from

switching DC-DC converter for distributed energy sources with high Hanyang University, Seoul, South Korea, in

step-up voltage capability,” IEEE Trans. Ind. Electron., vol. 62, no. 11, 1999, and the M.S. and Ph.D. degrees in elec-

pp. 7039–7050, Nov. 2015, doi: 10.1109/TIE.2015.2448515. tronic and electrical engineering from Pohang

[15] L. Chen, C. Hu, Q. Zhang, K. Zhang, and I. Batarseh, “Modeling and triple- University of Science and Technology, Pohang,

loop control of ZVS grid-connected DC/AC converters for three-phase South Korea, in 2002 and 2005, respectively.

balanced microinverter application,” IEEE Trans. Power Electron., vol. 30, From 2005 to 2008, he was a Senior Re-

no. 4, pp. 2010–2023, Apr. 2015, doi: 10.1109/TPEL.2014.2329278. search Engineer with the PDP Research Labo-

[16] O. Husev, L. Liivik, F. Blaabjerg, A. Chub, D. Vinnikov, and I. Roasto, ratory, LG Electronics Inc., Gumi, South Korea.

“Galvanically isolated Quasi-Z-Source DC-DC converter with a novel Since 2008, he has been with the Department

ZVS and ZCS technique,” IEEE Trans. Ind. Electron., vol. 62, no. 12, of Electronic and Information Engineering, Seoul

pp. 7547–7556, Dec. 2015, doi: 10.1109/TIE.2015.2455522. National University of Science and Technology, Seoul, where he is cur-

[17] M. R. Mohammadi and H. Farzanehfard, “Analysis of diode reverse re- rently a Professor. His research interests include the modeling, design,

covery effect on the improvement of soft-switching range in zero-voltage- and control of power converters, soft-switching power converters, reso-

transition bidirectional converters,” IEEE Trans. Ind. Electron., vol. 62, nant converters, power factor correction circuits, and driving circuits for

no. 3, pp. 1471–1479, Mar. 2015, doi: 10.1109/TIE.2014.2363425. plasma display panels.

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