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the complete details about a Microprocessor. Fig. shows the Block diagram of a Microprocessor.
8085 Bus Structure:
• • • • • • • • • •
The address bus is a group of 16 lines generally identified as A0 to A15. The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral devices. The MPU uses the address bus to perform the first function: identifying a peripheral or a memory location. The data bus is a group of eight lines used for data flow. These lines are bi-directional - data flow in both directions between the MPU and memory and peripheral devices. The MPU uses the data bus to perform the second function: transferring binary information. The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 = 256 numbers). The largest number that can appear on the data bus is 11111111. The control bus carries synchronization signals and providing timing signals. The MPU generates specific control signals for every operation it performs. These signals are used to identify a device type with which the MPU wants to communicate.
Registers of 8085: • The 8085 have six general-purpose registers to store 8-bit data during program execution. • These registers are identified as B, C, D, E, H, and L. • They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit operations.
Accumulator (A): • The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). • This register is used to store 8-bit data and to perform arithmetic and logical operations. • The result of an operation is stored in the accumulator. Flags: • The ALU includes five flip-flops that are set or reset according to the result of an operation. • The microprocessor uses the flags for testing the data conditions. • They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are Sign, Zero, and Carry. The bit position for the flags in flag register is,
1.Sign Flag (S): After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is the magnitude of number. If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as positive number. 2.Zero Flag (z): If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is reset.
3.Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and logical operation, this flag is set. Otherwise it is reset. 4.Parity Flag (P): If the result of arithmetic and logical operation contains even number of 1's then this flag will be set and if it is odd number of 1's it will be reset. 5.Carry Flag (CY): If any arithmetic and logical operation result any carry then carry flag is set otherwise it is reset. Arithmetic and Logic Unit (ALU): • It is used to perform the arithmetic operations like addition, subtraction, multiplication, division, increment and decrement and logical operations like AND, OR and EX-OR. • It receives the data from accumulator and registers. • According to the result it set or reset the flags. Program Counter (PC): • This 16-bit register sequencing the execution of instructions. • It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. • The function of the program counter is to point to the memory address of the next instruction to be executed. • When an opcode is being fetched, the program counter is incremented by one to point to the next memory location. Stack Pointer (Sp): • The stack pointer is also a 16-bit register used as a memory pointer. • It points to a memory location in R/W memory, called the stack. • The beginning of the stack is defined by loading a 16-bit address in the stack pointer (register). • Temporary Register: It is used to hold the data during the arithmetic and logical operations. • Instruction Register: When an instruction is fetched from the memory, it is loaded in the instruction register. • Instruction Decoder: It gets the instruction from the instruction register and decodes the instruction. It identifies the instruction to be performed.
Serial I/O Control: It has two control signals named SID and SOD for serial data transmission. Timing and Control unit: • It has three control signals ALE, RD (Active low) and WR (Active low) and three status signals IO/M(Active low), S0 and S1. • ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation. • RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively. • IO/M(Active low) is used to indicate whether the operation is belongs to the memory or peripherals.
Interrupt Control Unit:It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal. PIN DIAGRAM AND PIN DESCRIPTION OF 8085 :• • • • • • 1. 2. 3. 4. 5. 6. The microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution. In large computers, a CPU implemented on one or more circuit boards performs these computing functions. The microprocessor is in many ways similar to the CPU, but includes the logic circuitry, including the control unit, on one chip. The microprocessor can be divided into three segments for the sake clarity, arithmetic/logic unit (ALU), register array, and control unit. 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows Power supply and clock signals Address bus Data bus Control and status signals Interrupts and externally initiated signals Serial I/O ports
1. Power supply and Clock frequency signals: • Vcc + 5 volt power supply • Vss Ground • X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator. • The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally. • CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor.
2.A7.Pin Diagram of 8085 & Fig(b) . .A15 (output. Address Bus: • A8 . The CPU may read or write out data through these lines.AD7 (input/output. 3. 3-state) • It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address.logical schematic of Pin diagram. • During the opcode fetch operation. Fig (a) . the lines deliver the lower order address A0 . 3-state) • These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. • In the subsequent IO / memory. in the first clock cycle. read / write clock cycle the lines are used as data bus. Multiplexed Address / Data Bus: • AD0 .
• On receipt of an interrupt. • This indicates that the data on the data bus is to be written into the selected memory location or I/O device. active low) . Status Signals: • It is used to know the type of current operation of the microprocessor. • This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device. • RD (output 3-state. • IO/M (output) . active low) . 6. • It goes high to indicate an I/O operation. • This signal helps to capture the lower order address presented on the multiplexed address / data bus. • This status signal indicates that the read / write operation relates to whether the memory or I/O device. • It goes low for memory operations.4. .Read memory or IO device. • WR (output 3-state. 5. • There are five hardware interrupts called.Select memory or an IO device.Write memory or IO device.Address Latch Enable. the microprocessor acknowledges the interrupt by the active low INTA (Interrupt Acknowledge) signal. Interrupts and Externally initiated operations: • They are the signals initiated by an external device to request the microprocessor to do a particular task or work. Control and Status signals: • ALE (output) .
However. active low) • This signal is used to reset the microprocessor. otherwise Q is 0). .Reset In (input. Q is 1. • The program counter inside the microprocessor is set to zero. Reset Out (Output) • It indicates CPU is being reset. when E is low the gate is disabled and the output Q enters into a high impedance state. • The buses are tri-stated. When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0. Fig (a) . Direct Memory Access (DMA): Tri state devices: • • 3 output states are high & low states and additionally a high impedance state. 7.Pin Diagram of 8085 & Fig(b) .logical schematic of Pin diagram. • Used to reset all the connected devices when the microprocessor is reset.
• • • • • • For both high and low states. Single Bit Serial I/O ports: • SID (input) . it does not draw any current from the OR gate's input. the output Q draws a current from the input of the OR gate. Before completing the present job such a slow peripheral may not be able to handle further data or control signal from CPU. When 2 or more devices are connected to a common bus. though it is physically connected.Serial output data line These signals are used for serial communication. the tristate gates are used to disconnect all devices except the one that is communicating at a given instant. to prevent the devices from interfering with each other. high impedance means it is electrically isolated from the OR gate's input. The microprocessor enters into WAIT state while the READY pin is disabled.Serial input data line • SOD (output) . Therefore. Q enters a high impedance state. the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. HOLD signal is generated by the DMA controller circuit. The CPU controls the data transfer operation between memory and I/O device. . After the HLDA signal the DMA controller starts the direct transfer of data. When E is low. On receipt of this signal. The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly. 8. READY (input) • • • • Memory and I/O devices will have slower response compared to microprocessors. The processor sets the READY signal after completing the present job to access the data.
• Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).MEMORY INTERFACING WITH 8085 The memory is made up of semiconductor material used to store the programs and data. Three types of memory is. read control (output enable) and write control (write enable). • The control signals needed for static RAM are chip select (chip enable). The control signals needed for read operation in EPROM are chip select (chip enable) and read control (output enable). . m data pins (or output pins). • Process memory • Primary or main memory • Secondary memory TYPICAL EPROM AND STATIC RAM: • A typical semiconductor memory IC will have n address pins.
Table .Block diagram and Truth table of 2-4 decoder . No of IC's used for decoder is. • 2-4 decoder (74LS139) • 3-8 decoder (74LS138) Fig .Number of Address Pins and Data Pins in Memory ICs DECODER: It is used to select the memory chip of processor during the execution of a program.
e. The range of address for EPROM is 0000H to FFFFH. • • • • • • • The memory capacity is 64 Kbytes. Interface the EPROM with 8085 processor. the active low RD pin is connected to active low output enable pin of EPROM. The chip select (CS) pin of EPROM is permanently tied to logic low (i.Block diagram and Truth table of 3-8 decoder EXAMPLE-1 Consider a system in which the full memory space 64kb is utilized for EPROM memory. n = 16.e 2^n = 64 x 1000 bytes where n = address lines.. . Since the processor is connected to EPROM.Fig . In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory. So. tied to ground). i.
The 32kb memory requires 15 address lines and so the address lines A0 . . it select RAM and If A15 is 0. so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively. The memory used is both Ram and EPROM. Interface the EPROM and RAM with 8085 processor. 32kb RAM capacity is implemented using single IC 62256. Inverter is used for selecting the memory. it select EPROM. • • • • • • • Implement 32kb memory capacity of EPROM using single IC 27256. The unused address line A15 is used as to chip select. The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH to FFFFH.EXAMPLE-2 Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM. If A15 is 1.A14 of the processor are connected to 15 address pins of both EPROM and RAM.
• The address line A15 is used as enable for decoder.A12 of the processor are connected to 13 address pins of all the memory. • The address lines and A13 .A14 can be decoded using a 2-to-4 decoder to generate four chip select signals. • The simplified schematic memory organization is shown. • The total memory capacity is 32Kb. • These four chip select signals can be used to select one of the four memory IC at any one time. Fig . let two number of 8kb n memory be EPROM and the remaining two numbers be RAM.Interfacing 32Kb EPROM and 32Kb RAM with 8085 EXAMPLE-3 Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.Fig . So.Interfacing 16Kb EPROM and 16Kb RAM with 8085 . • Each 8kb memory requires 13 address lines and so the address lines A0.
So. • The address lines A13. • The total memory capacity is 64Kb. So the address line A0 . EXAMPLE-4 Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory.A12 of the processor are connected to 13address pins of all the memory lCs. . let 4 numbers of 8Kb EPROM and 4 numbers of 8Kb RAM.• The address allotted to each memory IC is shown in following table. These eight chip select signals can be used to select one of the eight memories at any one time. • The memory interfacing is shown in following figure. • Each 8kb memory requires 13 address lines. Interface the EPROM and RAM with 8085 processor. A14 and A]5 are decoded using a 3-to-8 coder to generate eight chip select signals.
8Kb RAM with 8085 Is. 8Kb RAM with 8085 • The address allocation for Interfacing 4 no. . 8Kb EPROM and 4 no. 8Kb EPROM and 4 no.Fig .Interfacing 4 no.
I/O INTERFACING WITH 8085 I/O STRUCTURE OF A TYPICAL MICROCOMPUTER: There are three major types of data transfer between the microcomputer and art I/O device. the I/O device will interrupt the processor. the data transfer between memory and I/O can be performed by bypassing the microprocessor. For data transfer from input device to processor the following operations are performed. They are. • The input device will load the data to the port. • The processor will load the data to the port. • After the data have been read by the output device the processor can load the next data to the port. • 8212 • The 8212 is a 24 pin IC. • The processor will read the data from the port. it sends message to the processor to read the data. 8255. 2. For data transfer from processor to output device the following operations are performed. • Interrupt driven I/O : In interrupt driven I/O. 8355 and 8755. INTERFACING I/O AND PERIPHERAL DEVICES: 1. • Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O port and controlled by software. • After a data have been read by the processor the input device will load the next data into the port. • It consists of eight number of D-type latches. • The various INTEL 110 port devices are 8212. • The port will send a message to the output device to read the data. • Direct memory access (DMA) : In DMA. • When the port receives a data. and initiate data transfer. • It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8 • The 8212 can be used as an input or output device . 8155/8156. • The output device will read the data from the port.
8255: • • • • • • It has 3 numbers of 8-bit parallel I/O ports (port A. It requires four internal addresses . Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port. When ports A and B are in mode-0. Port-B can be programmed in mode-1 and mode-2 as 1/Oport. It has two selecting device DS1 (low) and DS2. B and C). One logic low chip select (CS) pin.• If. the port-C can be used as I/O port.
. • Standard I/O mapped I/O device or peripheral mapped I/O device.There are two types for interfacing I/O devices: • Memory mapped I/O device.
• The I/O devices in the system should be mapped by standard I/O mapping. Draw the Interface diagram. 8251 . (8255 .Example 1: A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255. The input to this decoder is A11. Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC's. A14 and A15 are used as input to decoder 74LS138 (3to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of 8085. Hence the address lines A0 . The unused address lines A13. The chip-select signals for these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). There are five peripheral IC's to be interfaced to the system.A12 are used for selecting the memory locations. The RAM is mapped at the end of memory space from C000 to FFFFH. Allocate addresses to all the devices. so that this decoder is enabled for memory read/write operation. The peripheral IC should be I/O mapped. The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.Timer). • • • • • • • • • . so that this decoder is enabled for I/O read/write operation. The 4-outputs of the decoder are used to select memory lCs and the remaining 4 are kept for future expansion. The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085. For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM. The 8kb memories require 13 address lines.Programmable peripheral interface. one number of 8279. one number of 8251 and one number of 8254.USART and 8254 . A12 and A13 The address lines A13. 8279-Keyboard/display controller. The other enable pins of decoder are tied to appropriate logic levels permanently. For 16kb EPROM. we can provide 2 numbers of 2764(8k x 8) EPROM. A14 and A15 are logically ORed and applied to low enable of I/O decoder.
Fig .Memory and I/O Port Interfacing with 8085 .
• The 16 bit address for the memory and 8255 devices are. .
Example 2: A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255. • The I/O devices in the system should be mapped by standard I/O mapping.A12 are used for selecting the memory locations. Hence the address lines A0 . A14 and A15 are used as input to decoder 74LS138 (3to-8-deeoder) of memory IC. The 4-outputs of the decoder are used to select memory lCs and the remaining 4 are kept for future expansion. There are five peripheral IC's to be interfaced to the system. The peripheral IC should be I/O mapped. so that this decoder is enabled for memory read/write operation. • • • • For 16kb EPROM. The RAM is mapped at the end of memory space from C000 to FFFFH. Allocate addresses to all the devices. The input to this decoder is A11.Programmable peripheral interface. so that this decoder is enabled for I/O read/write operation. The unused address lines A13. A14 and A15 are logically ORed and applied to low enable of I/O decoder. we can provide 2 numbers of 2764(8k x 8) EPROM.USART and 8254 . 8279-Keyboard/display controller. . one number of 8279. The 8kb memories require 13 address lines. • • • The EPROM is mapped in the beginning of memory space from 0000H to 3FFF. 8251 . Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC's. The other enable pins of decoder are tied to appropriate logic levels permanently. A12 and A13 • • The address lines A13. (8255 . The logic low enables of this decoder are tied to IO/ M(low) of 8085. Draw the Interface diagram.Timer). The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085. one number of 8251 and one number of 8254. The chip-select signals for these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
Memory and I/O Port Interfacing with 8085 .Fig .
• The 16 bit address for the memory and IO devices are. .
The peripheral IC should be I/O mapped. Hence the address lines A0 . • The 8kb memory requires 13 address lines.Example 3: A system requires 8kb EPROM and 8kb RAM. • Eight bit addresses are allotted to ports of 8l55 and sixteen bit addresses are allotted to RAM memory locations of 8155. Allocate addresses to all the devices.Memory and I/O Port Interfacing with 8085 • The 16 bit address for the memory and IO devices are. 74LS138 is used for generating chip select signals by decoding the address lines A13. Both the memory IC has time compatibility with 8085 processor. Fig . Draw the Interface diagram. • The RAM locations of 8155 are selected by address lines A0 to A7. Also the system has 2 numbers of 8155. . A14 and A15.A12 are used to select memory locations. • 3-to-8 decoder. • The IC 2764 (8k x 8) is selected for EPROM memory and IC 6264 (8k x 8) is selected for RAM memory.
5. Instruction Cycle: The time required to execute an instruction is called instruction cycle. Opcode fetch cycle (4T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T) • Each instruction of the 8085 processor consists of one to five machine cycles. The execution time is represented in T-states.. Machine Cycle: The time required to access the memory or input/output devices is called machine cycle. T-State: • The machine cycle and instruction cycle takes multiple clock periods. • • • . They are 1. • A portion of an operation carried out in one system clock period is called as T-state. The T-state starts at the falling edge of a clock. It represents the execution time taken by each instruction in a graphical format. One T-state is equal to the time period of the internal clock signal of the processor. 2. i. MACHINE CYCLES OF 8085: The 8085 microprocessor has 5 (seven) basic machine cycles. The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states. 3.TIMING DIAGRAM Timing Diagram is a graphical representation. 4. when the 8085 processor executes an instruction. it will execute some of the machine cycles in a specific order.e.
So. the first. The time taken by the processor to execute the opcode fetch cycle is 4T. the processor executes the opcode fetch machine cycle to fetch the opcode from memory. The opcodes are stored in memory. In this time. every instruction starts with opcode fetch machine cycle. Hence.Opcode fetch machine cycle of 8085 : • • • • • Each instruction of the processor has one byte opcode.Timing Diagram for Opcode Fetch Machine Cycle . 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor. Fig .
Timing Diagram for Memory Read Machine Cycle Memory Write Machine Cycle of 8085: • The memory write machine cycle is executed by the processor to write a data byte in a memory location. The processor takes 3T states to execute this cycle. • The processor takes. 3T states to execute this machine cycle. Fig . .Memory Read Machine Cycle of 8085: • • • The memory read machine cycle is executed by the processor to read a data byte from memory. The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.
Fig . • The IN instruction uses this machine cycle during the execution.Timing Diagram for I/O Read Machine Cycle . which is I/O. • The processor takes 3T states to execute this machine cycle. Fig .Timing Diagram for Memory Write Machine Cycle I/O Read Cycle of 8085: • The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral. mapped in the system.
Timing Diagram for I/O Write Machine Cycle TIMING DIAGRAM OF 8085 INSTRUCTIONS • • • The 8085 instructions consist of one to five machine cycles.I/O Write Cycle of 8085: • • The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral. . Fig . 3T states to execute this machine cycle. The processor takes. mapped in the system. The timing diagram of an instruction ate obtained by drawing the timing diagrams of the machine cycles of that instruction. which is I/O. Actually the execution of an instruction is the execution of the machine cycles of that instruction in the predefined order. one by one in the order of execution.
. So. It is fetched from the memory 41FFH(see fig). • The opcode of the STA instruction is said to be 32H. • STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A).OF machine cycle • Then the lower order memory address is read(6A). C7H from accumulator is now stored in 526A. .Timing diagram for STA 526AH. .Memory Write Machine Cycle • Assume the memory address for the instruction and let the content of accumulator is C7H. ..Memory Read Machine Cycle • Read the higher order memory address (52).Memory Read Machine Cycle • The combination of both the addresses are considered and the content from accumulator is written in 526A.
Read the content of port C0H and send it to the accumulator. Read the port address C0H from 4126H. . Let the content of port is 5EH. • • • • Fetching the Opcode DBH from the memory 4125H.Timing diagram for IN C0H.
(MR cycle -To read Memory address and data) Let the content of that memory is 12H. (MW machine cycle) .Timing diagram for INR M : • • • • Fetching the Opcode 34H from the memory 4105H. (OF cycle) Let the memory address (M) be 4250H. Increment the memory content from 12H to 13H.
• • Fetching the Opcode 06H from the memory 2000H. (memory read) . 43H. (OF machine cycle) Read (move) the data 43H from memory 2001H.Timing diagram for MVI B.
Hence the data transfer is copying operation.B (2) MVI C. Ex: (1) Mov A. increment or decrement operations. DATA TRANSFER INSTRUCTIONS: It includes the instructions that move (copies) data between registers or between memory locations and registers. Ex: (1) CALL (2) JMP 4100 5.8085 INSTRUCTION SET CLASSIFICATION The 8085 instruction set can be classified into the following five functional headings. subtraction. Ex: (1) NOP (2) END . OR. In all data transfer operations the content of source register is not altered. 1. LOGICAL INSTRUCTIONS: The instructions which performs the logical operations like AND.05H 3.OR. MACHINE CONTROL INSTRUCTIONS: It includes the instructions related to interrupts and the instruction used to stop the program execution. EXCLUSIVE. The flag conditions are altered after execution of an instruction in this group. BRANCHING INSTRUCTIONS: The instructions that are used to transfer the program control from one memory location to another memory location are grouped under this heading. compare and rotate instructions are grouped under this heading. Ex: (1) ADD A. which performs the addition. 01H 4.B (2) SUI B. The flag conditions are altered after execution of an instruction in this group.45H 2. Ex: (1) ORA A (2) ANI B. complement. ARITHMETIC INSTRUCTIONS: Includes the instructions.
Register Addressing: In register addressing mode. Implied Addressing: In implied addressing mode. Direct Addressing: In direct addressing mode. B . Register Indirect Addressing: In register indirect addressing mode. the program instructions and data can be stored in different memory. ADD C. the instruction itself specifies the data to be operated. Here the data will be in memory and the address will be in the register pair. Direct Addressing 3. LXI SP. Immediate Addressing 2.Complement the content of accumulator. Immediate Addressing: In immediate addressing mode. The data will be a part of the program instruction. MOV A. 2. Implied Addressing 1. EX. CMA . SPHL. The 8085 has the following 5 different types of addressing. SHLD 3000H 3.Move the data 3EH given in the instruction to B register. The method of specifying the data to be operated by the instruction is called Addressing. 4. MOV A. 1. M . LDAX B. EX. Register Addressing 4. EX. the address of the data is specified in the instruction.Move the content of B register to A register. EX. 5. EX. In this addressing mode. 3EH . MVI B. The data will be in memory.Load the data available in memory location 1050H in to accumulator. the instruction specifies the name of the register in which the address of the data is available. RAL .The memory data addressed by H L pair is moved to A register. the data is specified in the instruction itself. the instruction specifies the name of the register in which the data is available.ADDRESSING MODES OF 8085 • • • Every instruction of a program has to operate on a data. 2700H. Register Indirect Addressing 5. LDA 1050H .
from higher addresses to lower) and then the register pair is loaded onto the stack. When you pop. in reverse order! Don't forget .The STACK The stack is one of the most important things you must know when programming. Think of the stack as a deck of cards. If you want. You can't push an immediate value. and then SP increases by 2. which you perhaps don't know). Also. The 8085 uses a 16 bit register to know where the stack top is located. That's called LIFO. When you put a card on the deck. You have to call a subroutine that you know will destroy HL (with destroy I mean that HL will be changed to another value. when is this useful? It's almost always used when you call subroutines. When you remove the cards. you remove them backwards. Perhaps it's worth noting that when you push something. DE. it's often better to use the pushes and pops inside the subroutine. the PC is loaded with the word popped from the top of the stack (TOS). the stack counter will decrease with 2 (the stack "grows" down. N. Of course. if you push DE. push and pop “pushes” bytes on the stack and then takes them off. Then you put another card. you'll have to load a register pair with the value and then push it. Last In First Out. you should try first to change register (try to store the . you can push HL before calling and directly after the calling pop it back. In those cases. When you pop PSW. For example. So. Therefore. the last card first and so on. you can pop it back as HL (you don't have to pop it back to the same register where you got it from). The stack works the same way. if you don't want that to happen. If you want to only push one 8 bit register. The stack is also updated when you CALL and RETurn from subroutines. HL and PSW (Register A and Flags). they won't be erased or something. you still have to push it's "friend". you put (push) words (addresses or register pairs) on the stack and then remove (pop) them backwards. When you push something. the register pair is first lifted of the stack. All registers you know will be changed are often pushed in the beginning of a subroutine and then popped at the end.last in first out. Instead of first saving HL in a memory location and then loading it back after the subroutine. You can push (and pop) all register pairs: BC. remember that all flags may be changed. you have an often used value stored in HL. and that register is called the SP (Stack Pointer). The PC (program counter which points at the next instruction to be executed) is pushed to the stack and the calling address is loaded into PC. the contents of the registers will still be the same. There are instructions that allow you to modify it’s contents but you should NOT change the contents of that register if you don't know what you're doing! PUSH & POP : As you may have guessed. When returning. then another. it will be the top card. be aware that if you want to store away D with pushing and popping. remember that E will also be changed back to what it was before.B: Push and Pop only operate on words (2 bytes ie: 16 bits).
which is often very useful. it’s also a way to jump to the location stored in HL. Push and pop doesn't change any flags. so you can use them between a compare and jump instructions. to do the same thing.information in E in another register if you can) or else you have to store it in a temporary variable. . Before executing a program. the next RET instruction will cause a jump to HL. which can be anywhere in the ROM/RAM and the ccomputer will crash. depending on a condition. if you push HL and then forget to pop it back. you should keep track of your pushes and pops. Note however. since they are responsible for 99% of all computer crashes! For example. but then you should really use the JMP instruction.
5 * 8 = 40 = 28H • Vector address for interrupt RST 5 is 0028H The Table shows the vector addresses of all interrupts. The 8085 has five hardware interrupts (1) TRAP (2) RST 7. Types of Interrupts: It supports two types of interrupts. to request the processor to perform a particular task or work. These instructions are inserted at desired locations in a program. • The 8085 has eight software interrupts from RST 0 to RST 7. If the interrupt is accepted then the processor executes an interrupt service routine. • Hardware Interrupts: • • • An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor. • Software • Hardware Software interrupts: • The software interrupts are program instructions. • It returned to main program by RET instruction. • Interrupt number * 8 = vector address • For RST 5. • The processor will check the interrupts always at the 2nd T-state of last machine cycle. • The vectored address of particular interrupt is stored in program counter.5 (5) INTR . • Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor. • If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral. The vector address for these interrupts can be calculated as follows.INTERRUPT Interrupt is signals send by an external device to the processor.5 (4) RST 5.5 (3) RST 6. • The processor executes an interrupt service routine (ISR) addressed in program counter.
ie. Input goes to high and stay high until it recognized. • • • . Input goes to high and no need to maintain high state until it recognized. • TRAP interrupt is edge and level triggered. RST 6.After reorganization of interrupt.5: The RST 7. is HOLD signal.DI. • Maskable interrupt.5 interrupt is a maskable interrupt. • TRAP bas the highest priority and vectored interrupt..System or processor reset.After reorganization of interrupt.DI. which overrides the TRAP. 3.5 and 5. It is disabled by. It is disabled by.DI instruction 2. It is edge sensitive. If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized). INTR: • INTR is a maskable interrupt. it executes a ISR and send the data from main memory to backup memory. • In sudden power failure. 1. • There are two ways to clear TRAP interrupt. (i. 1.5: • The RST 6. • The RST 6. ie. • Enabled by EI instruction.5 has the third priority whereas RST 5. . SIM instruction 2. It is unaffected by any mask or interrupt enable. SIM instruction 2.5 has the fourth priority. • Maskable interrupt.After reorganization of interrupt.TRAP: • This interrupt is a non-maskable interrupt. • The signal.By giving a high TRAP ACKNOWLEDGE (Internal signal) RST 7. 3.System or processor reset.5 both are level triggered.5 and RST 5.System or processor reset. This means hat the TRAP must go high and remain high until it is acknowledged. It is disabled by. • Enabled by EI instruction.By resetting microprocessor (External signal) 2. It has the second highest priority. 1. 1. 3.e.
In response to the acknowledge signal. 4. If INTR signal is high.5 using SIM instruction. external logic places an instruction OPCODE on the data bus. The 8085 checks the status of INTR signal during execution of each instruction.5 and RST 5. The status of these interrupts can be read by executing RIM instruction. After receiving INTA (active low) signal. the 8085 save the address of next instruction on stack and execute received instruction. additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor. .• • • • • Enabled by EI instruction. 2. RST 6.5. Input goes to high and it is necessary to maintain high state until it recognized. SIM and RIM for interrupts: SIM: • • • • The 8085 provide additional masking facility for RST 7. Non.5 and RST 5. The format of the 8-bit data is shown below. It is a level sensitive interrupts. ie.vectored interrupt. if the interrupt is enabled. then 8085 complete its current instruction and sends active low interrupt acknowledge signal. it has to supply the address of ISR. On receiving the instruction.5 interrupts can be performed by moving an 8-bit data to accumulator and then executing SIM instruction.5. The masking or unmasking of RST 7. The following sequence of events occurs when INTR signal goes high. 1. In the case of multibyte instruction. RST 6. It has lowest priority. 3.
which can be interpreted as shown in fig.RIM : • • The status of pending interrupts can be read from accumulator after executing RIM instruction. . When RIM instruction is executed an 8-bit data is loaded in accumulator.
INTEL 8255 : . PIN DESCRIPTION .INTEL 8255 Pins. Signals and internal block diagram of 8255: • It has 40 pins and requires a single +5V supply.PROGRAMMABLE PERIPHERAL INTERFACE .
DAC. . LCD. keyboard.Block diagram of 8255: • The internal block diagram of 8255 is shown in fig: • The INTEL 8255 is a device used to parallel data transfer between processor and slow peripheral devices like ADC. etc. 7-segment display.
the microprocessor writes into a selected I/O port or the control register. When this signal goes low. • Interfacing of 8255 with 8085 processor: • A simple schematic for interfacing the 8255 with 8085 processor is shown in fig. . Port-B and Port-C. Port-C (8-pins) has different assignments depending on the mode of port-A and port-B. mode-1 and mode-2 as input or output port. When this signal is low. As 8-bit parallel port in mode-0 for input or output. They are. If port-A is programmed in mode. It clears the control register and set all ports in the input mode. The read/write control logic requires six control signals.• • • • • • • • • The 8255 has three ports: Port-A. A0 and A1: These are device select signals. The individual pins of port-C can be set or reset for various control applications. If port-A and B are programmed in mode-0. WR (low): This control signal enables the write operation. Port-B can be programmed to work either in mode-0 or mode-1 as input or output port. RESET: This is an active high signal. As two numbers of 4-bit parallel ports in mode-0 for input or output. 1. RD (low): This control signal enables the read operation. CS (low).1/mode-2 and port-B is programmed in mode-1 then some of the pins of port-C are used for handshake signals and the remaining pins can be used as input/ output lines or individually set/reset for control applications. 4. 3. the microprocessor reads data from a selected I/O port of the 8255A. Port-A can be programmed to work in any one of the three operating modes mode-0. 2. then the port-C can perform any one of the following functions. These signals are given below.
.1 is used to select 8255. Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices. The I/O addresses allotted to the internal devices of 8255 are listed in table. In the schematic shown in above is I/O mapped in the system. The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data transfer. A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this. The address line A7 and the control signal IO/M (low) are used as enable for the decoder. The address lines A4. the chip select IOCS.• • • • • • • The 8255 can be either memory mapped or I/O mapped in the system. The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to A1 of 8255 to provide the internal addresses.
• Each channel can be independently perform read transfer. • The 8257 has four channels and so it can be used to provide DMA to four I/O devices • Each channel can be independently programmable to transfer up to 64kb of data by DMA. The features of 8257 is.PROGRAMMABLE DMA CONTROLLER . So it performs a high-speed data transfer between memory and I/O device. .INTEL 8257 It is a device to transfer the data directly between IO device and memory without through the CPU. write transfer and verify transfer. • It is a 40 pin IC and the pin diagram is.
. The functional block diagram of 8257 is shown in fig.Functional Block Diagram of 8257 :• The functional blocks of 8257 are data bus buffer. control logic. priority resolver and four numbers of DMA channels. read/write logic.
The format of count register is. • Address register is used to store the starting address of memory location for DMA data transfer.OPERATING MODES OF INTEL 8257 :• Each channel of 8257 Block diagram has two programmable 16-bit registers named as address register and count register. • The count register is used to count the number of byte or word transferred by DMA. • The address in the address register is automatically incremented after every read/write/verify transfer. .
If the bit B5 is set to one. 2. B1. When this mode is activated the number of channels available for DMA reduces from four to three. When bit B7 is set to one. If the bit B6 is set to one then the DMA operation is stopped at the terminal count. 5. The bit B7 is used to select the auto load feature for DMA channel-2. • The use of mode set register is. In rotating priority after servicing a channel its priority is made as lowest. • • • • • • The bits B0. 2. B2. 4. then the timing of low write signals (MEMW and IOW) will be extended. In fixed priority the channel-0 has highest priority and channel-2 has lowest priority. 1. 1. then the content of channel-3 count and address registers are loaded in channel-2 count and address registers respectively whenever the channel-2 reaches terminal count. In read transfer the data is transferred from memory to I/O device.• • • • • 14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA transfer (Read/Write/Veri1 transfer). and B3 of mode set register are used to enable/disable channel -0. . The format of mode set register is. Fixed/rotating priority 3. 2 and 3 respectively. 1. Enable/disable a channel. Stop DMA on terminal count. then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.Extended/normal write time. Verification operations generate the DMA addresses without generating the DMA memory and I/O control signals. Auto reloading of channel-2. In write transfer the data is transferred from I/O device to memory. A one in these bit position will enable a particular channel and a zero will disable it. If the bit B4 is set to one. The 8257 has two eight bit registers called mode set register and status register.
B2. • • • • The bit B0.2 and 3 respectively. 1. and B3 of status register indicates the terminal count status of channel-0.• The format of status register of 8257 is shown in fig. These status bits are cleared after a read operation by microprocessor. The bit B4 of status register is called update flag and a one in this bit position indicates that the channel-2 register has been reloaded from channel-3 registers in the auto load mode of operation. B1. The internal addresses of the registers of 8257 are listed in table. A one in these bit positions indicates that the particular channel has reached terminal count. .
the AEN signal is also used to disable the buffers and latches used for address. A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257. These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15 during the DMA mode. In the schematic shown in figure is I/O mapped in the system. Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode. data and control signals of the processor. During DMA mode. in order to receive the acknowledge signal from the processor once the HOLD request is accepted. Therefore the RD (low). • • • • The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation. The 8257 can be either memory mapped or I/O mapped in the system. • • The 8257 provide separate read and write control signals for memory and I/O devices during DMA. . The HLDA output of 8085 is connected to HLDA input of 8257. The address line A7 and the control signal IO/M (low) are used as enable for decoder. The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD request to the processor. The 8257 also supply two control signals ADSTB and AEN to latch the address supplied by it during DMA mode on external latches. The RESET OUT of 8085 processor is connected to RESET of 8257.INTERFACING OF DMA 8257 WITH 8085 :• • • • • • • • • • A simple schematic for interfacing the 8257 with 8085 processor is shown. The address lines A4. Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices. The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with processor during programming mode. WR (low) and IO/M (low) of the 8085 processor are decoded by a suitable logic circuit to generate separate read and write control signals f memory and I/O devices.
The I/O addresses of the internal registers of 8257 are listed in table: .
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