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Ne ee So Via Vis Wi = ‘\ ae AN rd ey + NK ye a > a yy iG r 4 > @ ne ee re ae (wer s “ ey. Ge a ft ee i: FE ee ADVANCED MICROPROCESSORS AND PERIPHERALS AK RAY | KM BHURCHANDI Information contained in this work has been obtained by Tata McGraw-Hill, from sources believed to be reliable. However, neither Tata McGraw-Hill nor its authors guarantee the accuracy or completeness of any information published herein, and neither Tata McGraw-Hill nor its authors shall be responsible for any errors, ‘omissions, or damages arising out of use of this information. This work is published with the understanding that Tata McGraw-Hill and its authors are supplying information but are not attempting to render engineering or other professional services, If such services are required, the assistance of an appropriate professional should be sought. Copyright © 2006, 2000 by Tata McGraw-Hill Publishing Company Limited. Tata McGraw-Hill Eleventh reprint 2009 ROXLCDDXRQLOD No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior written permission of the publishers, ‘The program listings (if any) may be entered, stored and executed in a computer system, but they may not be reproduced for publication. ‘This edition can be exported from India only by the publishers, ‘Tala McGraw-Hill Publishing Company Limited. ISBN-13; 978-0-07-014062-2 USBN-10: 0-67-014062-6 Published by Tata McGraw-Hill Publishing Company Limited, 7 West Patel Nagar, New Delhi 110 008, typeset at Script Makers, 19, Al-B, DDA Market, Pashchim Vihar, New Delhi 110 063 and printed at Pashupati Printers Pvt. Ltd., Delhi 110 095 Contents Preface to the Second Edition. xiii Preface to the First Edition xv Acknowledgements xix 1. The Processors: 8086/8088— Architectures, Pin Dia; and Timing Diagrams ! 1.1 Register Organisation of 8086_2 L2_Architecture _3 1.3 __ Signal Descriptions of 8086 _& 1.4 Physical Memory Organisation _/4 L5__General Bus Operation 16 L6 WO Addressing Capability 7 1.7 _ Special Processor Activities /& 1.8 Minimum Mode 8086 System and Timings 2! 1.9 Maximum Mode 8086 System and Timings 25 L10 The Processor 8088 28 Summary 36 Exercises 36 2. 8086/8088 | s a bier Directi 38 2.1 Machine Language Instruction Formats 38 ‘Addressing Modes of 3086 4 2.3 Instruction Set of 8086/8088 _46 2.4 Assembler Directives and Operators _74 ‘Summary 82 Exercises 83 3._ The Art of Assembly Language Programming 3.1_A Few Machine Level Programs 85 3.2__Machine Coding the Programs 91 3.3 Programming with un Assembler_95 3.4 Assembly Language Example Programs 103 Summary _129 Exercises 129