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PD - 96901C

IRFB3307
IRFS3307
IRFSL3307
Applications
HEXFET® Power MOSFET
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply D
VDSS 75V
5.0m:
l High Speed Power Switching
l Hard Switched and High Frequency Circuits RDS(on) typ.
Benefits G max. 6.3m:
l Improved Gate, Avalanche and Dynamic dV/dt
S
ID 130A
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability

GDS GDS GDS


TO-220AB D2Pak TO-262
IRFB3307 IRFS3307 IRFSL3307

Absolute Maximum Ratings


Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 130 c A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 91 c
IDM Pulsed Drain Currentd 510
PD @TC = 25°C Maximum Power Dissipation 250 W
Linear Derating Factor 1.6 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery f 11 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw x x
10lb in (1.1N m)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 270 mJ
IAR Avalanche Currentc See Fig. 14, 15, 16a, 16b A
EAR Repetitive Avalanche Energy g mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Casek ––– 0.61
RθCS Case-to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220 k ––– 62
RθJA Junction-to-Ambient (PCB Mount) , D2Pak jk ––– 40

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IRFB3307/IRFS3307/IRFSL3307

Static @ TJ = 25°C (unless otherwise specified)


Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.069 ––– V/°C Reference to 25°C, ID = 1mA d
RDS(on) Static Drain-to-Source On-Resistance ––– 5.0 6.3 mΩ VGS = 10V, ID = 75A g
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 150µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 75V, VGS = 0V
––– ––– 250 VDS = 75V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
RG Gate Input Resistance ––– 1.5 ––– Ω f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 98 ––– ––– S VDS = 50V, ID = 75A
Qg Total Gate Charge ––– 120 180 nC ID = 75A
Qgs Gate-to-Source Charge ––– 35 ––– VDS = 60V
Qgd Gate-to-Drain ("Miller") Charge ––– 46 ––– VGS = 10V g
td(on) Turn-On Delay Time ––– 26 ––– ns VDD = 48V
tr Rise Time ––– 120 ––– ID = 75A
td(off) Turn-Off Delay Time ––– 51 ––– RG = 3.9Ω
tf Fall Time ––– 63 ––– VGS = 10V g
Ciss Input Capacitance ––– 5150 ––– pF VGS = 0V
Coss Output Capacitance ––– 460 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 250 ––– ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– 570 ––– VGS = 0V, VDS = 0V to 60V i, See Fig.11
Coss eff. (TR) Effective Output Capacitance (Time Related) h
––– 700 ––– VGS = 0V, VDS = 0V to 60V h, See Fig. 5
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 130 c A MOSFET symbol D

(Body Diode) showing the


ISM Pulsed Source Current ––– ––– 510 A integral reverse G

(Body Diode) d p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 75A, VGS = 0V g
trr Reverse Recovery Time ––– 38 57 ns TJ = 25°C VR = 64V,
––– 46 69 T = 125°C IF = 75A
g
J
Qrr Reverse Recovery Charge ––– 65 98 nC TJ = 25°C di/dt = 100A/µs
––– 86 130 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.8 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calculated continuous current based on maximum allowable junction † Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Package limitation current is 75A. as Coss while VDS is rising from 0 to 80% VDSS.
‚ Repetitive rating; pulse width limited by max. junction ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.096mH ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use mended footprint and soldering techniques refer to application note #AN-994.
above this value. ‰ Rθ is measured at TJ approximately 90°C.
„ ISD ≤ 75A, di/dt ≤ 530A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
… Pulse width ≤ 400µs; duty cycle ≤ 2%.
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IRFB3307/IRFS3307/IRFSL3307
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)


ID, Drain-to-Source Current (A)

100 6.0V 6.0V


5.5V 5.5V
5.0V 5.0V
4.8V 100 4.8V
BOTTOM 4.5V BOTTOM 4.5V
10

1
10 4.5V

4.5V
0.1
≤60µs PULSE WIDTH ≤60µs PULSE WIDTH
Tj = 25°C Tj = 175°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics


1000 2.5
ID = 75A

RDS(on) , Drain-to-Source On Resistance


VGS = 10V
ID, Drain-to-Source Current (Α)

100 2.0

T J = 175°C
(Normalized)

10 1.5

T J = 25°C

1 1.0

VDS = 25V
≤60µs PULSE WIDTH
0.1 0.5
2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

T J , Junction Temperature (°C)


VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 12.0
VGS = 0V, f = 1 MHZ
ID= 75A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)

10.0 VDS= 60V


C oss = C ds + C gd VDS= 38V
C, Capacitance(pF)

10000 8.0 VDS= 15V


Ciss
6.0

1000 Coss 4.0


Crss
2.0

100 0.0
1 10 100 0 20 40 60 80 100 120 140
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFB3307/IRFS3307/IRFSL3307
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)


ISD, Reverse Drain Current (A)

1000
T J = 175°C
100 100µsec
100 1msec

T J = 25°C 10 10msec
10

DC
1
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)


140 100

120 Limited By Package 95

100
ID, Drain Current (A)

90

80
85
60
80
40

75
20

0 70
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage

1.4 1200
EAS , Single Pulse Avalanche Energy (mJ)

ID
1.2 TOP 8.6A
1000
12A
1.0 BOTTOM 75A
800
Energy (µJ)

0.8
600
0.6

400
0.4

0.2 200

0.0 0
0 10 20 30 40 50 60 70 80 25 50 75 100 125 150 175

Starting T J , Junction Temperature (°C)


VDS, Drain-to-Source Voltage (V)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB3307/IRFS3307/IRFSL3307
1

Thermal Response ( Z thJC ) D = 0.50

0.1
0.20
0.10
0.05
R1 R2
0.01
0.02 R1 R2 Ri (°C/W) τi (sec)
0.01 τJ τC
τJ τ 0.2911 0.000484
τ1 τ2
τ1 τ2 0.3196 0.005529
SINGLE PULSE
( THERMAL RESPONSE ) Ci= τi/Ri
0.001 Ci= i/Ri

Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆ Tj = 150°C
and Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse 0.01
Avalanche Current (A)

10
0.05
0.10

1 Allowed avalanche Current vs avalanche


pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
300 Notes on Repetitive Avalanche Curves , Figures 14, 15:
TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
250
ID = 75A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.


2. Safe operation in Avalanche is allowed as long as neither Tjmax nor
200
Iav (max) is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
150 4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
100 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
50 tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
25 50 75 100 125 150 175
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Starting T J , Junction Temperature (°C) Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRFB3307/IRFS3307/IRFSL3307
5.0 20
VGS(th) Gate threshold Voltage (V)

4.5

15
4.0

IRRM (A)
3.5
10
ID = 150µA
3.0
ID = 250µA
ID = 1.0mA
2.5
IF = 30A
ID = 1.0A 5
V = 64V
R
2.0 T = 25°C _____
J
TJ = 125°C ----------
1.5 0
-75 -50 -25 0 25 50 75 100 125 150 175 200
100 200 300 400 500 600 700 800 900 1000
T J , Temperature ( °C ) dif/dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

20 400

350

15 300

250
IRRM (A)

Qrr (nC)

10 200

150

IF = 45A I = 30A
5 100 F
VR = 64V V = 64V
R
T = 25°C _____ TJ = 25°C _____
J 50
T = 125°C ---------- TJ = 125°C ----------
J
0 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000
dif/dt (A/µs) dif/dt (A/µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

400

350

300

250
Qrr (nC)

200

150
IF = 45A
100
VR = 64V
T = 25°C _____
50 J
T = 125°C ----------
J
0
100 200 300 400 500 600 700 800 900 1000
dif/dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt


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IRFB3307/IRFS3307/IRFSL3307
Driver Gate Drive
D.U.T P.W.
Period D=
P.W.
Period
+

ƒ VGS=10V*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚
-
„ +
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied


• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices


Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 21a. Unclamped Inductive Test Circuit Fig 21b. Unclamped Inductive Waveforms

LD
VDS VDS
90%
+
VDD -

D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf

Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT Vgs(th)
0
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
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IRFB3307/IRFS3307/IRFSL3307

TO-220AB Package Outline


Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

EXAMPLE: T HIS IS AN IRF1010


LOT CODE 1789 INT ERNAT IONAL PART NUMBER
AS S EMBLED ON WW 19, 2000 RECT IFIER
IN T HE AS S EMBLY LINE "C" LOGO
DAT E CODE
YEAR 0 = 2000
Note: "P" in ass embly line position AS S EMBLY
indicates "Lead - Free" LOT CODE WEEK 19
LINE C

TO-220AB packages are not recommended for Surface Mount Application.


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IRFB3307/IRFS3307/IRFSL3307

TO-262 Package Outline


Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information


EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789 PART NUMBER
INT ERNATIONAL
AS S EMBLED ON WW 19, 1997
RECTIFIER
IN T HE AS S EMBLY LINE "C" LOGO
DAT E CODE
YEAR 7 = 1997
AS S EMBLY
LOT CODE WEEK 19
LINE C

OR

PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
DAT E CODE
P = DES IGNAT ES LEAD-FREE
AS S EMBLY
LOT CODE PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE

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IRFB3307/IRFS3307/IRFSL3307
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information


T HIS IS AN IRF530S WITH PART NUMBER
LOT CODE 8024 INT ERNAT IONAL
ASS EMBLED ON WW 02, 2000 RECT IFIER F530S
IN T HE ASS EMBLY LINE "L" LOGO
DAT E CODE
YEAR 0 = 2000
ASS EMBLY
LOT CODE WEEK 02
LINE L

OR
PART NUMBER
INT ERNAT IONAL
RECT IFIER F 530S
LOGO DAT E CODE
P = DES IGNAT ES LEAD - FREE
PRODUCT (OPT IONAL)
AS S EMBLY
YEAR 0 = 2000
LOT CODE
WEEK 02
A = AS S EMBLY SITE CODE

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IRFB3307/IRFS3307/IRFSL3307

D2Pak (TO-263AB) Tape & Reel Information

TRR

1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161)
1.50 (.059) 0.368 (.0145)
3.90 (.153)
0.342 (.0135)

FEED DIRECTION 1.85 (.073) 11.60 (.457)


1.65 (.065) 11.40 (.449) 24.30 (.957)
15.42 (.609)
23.90 (.941)
15.22 (.601)
TRL
1.75 (.069)
10.90 (.429) 1.25 (.049)
10.70 (.421) 4.72 (.136)
16.10 (.634) 4.52 (.178)
15.90 (.626)

FEED DIRECTION

13.50 (.532) 27.40 (1.079)


12.80 (.504) 23.90 (.941)

330.00 60.00 (2.362)


(14.173) MIN.
MAX.

30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

Data and specifications subject to change without notice.


This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 01/06
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/