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RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.

AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.M.Chennakesavulu


SUBJECT: EMBEDDED SYSTEM CONCEPTS
Branch & Year: M.Tech, I-Sem ES Total Hours: 49 Hours
Estimated
S.No Unit Topics to be covered
Periods
INTRODUCTION: Embedded system overview, embedded hardware units, embedded
1 I software in a system, embedded system on chip (SOC), design process, classification of 7
embedded systems.
EMBEDDED COMPUTING PLATFORM: CPU Bus, memory devices, component
2 II interfacing, networks for embedded systems, communication interfacings: RS232/UART, 7
RS422/RS485, IEEE 488 bus.

SURVEY OF SOFTWARE ARCHITECTURE: Round robin, round robin with interrupts,


3 III 6
function queue scheduling architecture, selecting an architecture saving memory space.

EMBEDDED SOFTWARE DEVELOPMENT TOOLS: Host and target machines, linkers,


4 IV locations for embedded software, getting embedded software into target system, 6
debugging technique.

RTOS CONCEPTS: Architecture of the kernel, interrupt service routines, semaphores,


5 V 6
message queues, pipes.

6 VI INSTRUCTION SETS: Introduction, preliminaries, ARM processor, SHARC processor. 5

SYSTEM DESIGN TECHNIQUES: Design methodologies, requirement analysis,


7 VII 5
specifications, system analysis and architecture design.

DESIGN EXAMPLES: Telephone PBX, ink jet printer, water tank monitoring system,
8 VIII 7
GPRS, Personal Digital Assistants, Set Top boxes.

FACULTY HOD PRINCIPAL


RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.C.Venkataiah


SUBJECT: ADVANCED COMPUTER ARCHITECTURE
Branch & Year: M.Tech, I-Sem ES Total Hours: 49 Hours
Estimated
S.No Unit Topics to be covered
Periods

FUNDAMENTALS OF COMPUTER DESIGN: Technology trends, cost- measuring


1 I 6
and reporting performance quantitative principles of computer design.

INSTRUCTION SET PRINCIPLES AND EXAMPLES: classifying instruction set,


memory addressing, type and size of operands, addressing modes for signal
2 II 7
processing, operations in the instruction set- instructions for control flow- encoding
an instruction set.-the role of compiler.
INSTRUCTION LEVEL PARALLELISM (ILP): overcoming data hazards, reducing
3 III branch costs, high performance instruction delivery, hardware based speculation, 7
limitation of ILP.

ILP SOFTWARE APPROACH: Compiler Techniques, Static Branch Protection, VLIW


4 IV 6
Approach, H.W support for more ILP at compile time- H.W verses S.W solutions.

MEMORY HIERARCHY DESIGN: cache performance, reducing cache misses


5 V 6
penalty and miss rate, virtual memory, protection and examples of VM

MULTIPROCESSORS AND THREAD LEVEL PARALLELISM: symmetric shared


6 VI 6
memory architectures, distributed shared memory, Synchronization, multi threading.

STORAGE SYSTEMS: Types, Buses, RAID, errors and failures, bench marking a storage
7 VII 6
device, designing a I/O system

INTER CONNECTION NETWORKS AND CLUSTERS: Interconnection network media,


8 VIII 5
practical issues in interconnecting networks, examples, clusters, designing a cluster.

FACULTY HOD PRINCIPAL


RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.D.Raghunatha Rao


SUBJECT: ADVANCED DSP & APPLICATIONS
Branch & Year: M.Tech, I-Sem ES Total Hours: 54 Hours
Estimated
S.No Unit Topics to be covered
Periods
LTI DISCRETE-TIME SYSTEMS IN THE TRANSFORM DOMAIN: Types of Linear-
1 I Phase transfer functions, Complementary Transfer Functions, Inverse Systems, System 8
identification, Digital Two-Pairs.
DIGITAL FILTER STRUCTURE AND DESIGN: All pass filters, Tunable IIR Digital
2 II filter, IIR & FIR tapped Cascaded Lattice Structures, Parallel All pass realization of IIR 8
Transfer Functions, Digital Sine-Cosine generator
Computational Complexity of Digital filter Structures, Design of IIR filter using pade’
3 III approximation, Least square design methods, Design of computationally efficient FIR 4
filters.
DSP ALGORITHMS: FFT, Sliding Discrete Fourier transform, DFT Computation
4 IV Over a narrow Frequency Band, Split Radix FFT, Linear filtering approach to Computation 6
of DFT using Chirp Z-Transform.
ANALYSIS OF FINITE WORD LENGTH EFFECTS: The Quantization Process and
5 V errors, Quantization of fixed-point Numbers, Analysis of Coefficient quantization effects, 8
A/D conversion Noise Analysis, Analysis of Arithmetic Round of errors.
ADAPTIVE FILTERS
FIR adaptive filters – Adaptive filter based on steepest descent method – Widrow-Hoff
6 VI LMS adaptive algorithms, normalized LMS. Adaptive channel equalization – adaptive echo 8
cancellation – Adaptive noise cancellation – Adaptive recursive (IIR) filters. RLS adaptive
filters – Exponentially weighted RLS – Sliding window RLS.
APPLICATIONS OF DIGITAL SIGNAL PROCESSING: Dual Tone Multi-frequency
Signal Detection, Spectral Analysis of Sinusoidal Signals, Spectral Analysis of
7 VII 8
Nonstationary Signals, Musical Sound Processing, Over Sampling A/D Converter, Over
Sampling D/A Converter.
Applications, architecture, Addressing modes, instruction set of TMS 320 C54XX
8 VIII 4
Processors , simple programmes.

FACULTY HOD PRINCIPAL


RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.N.Ramanjaneyulu


SUBJECT: MICROCONTROLLERS & INTERFACING
Branch & Year: M.Tech, I-Sem ES Total Hours: 56 Hours
Estimated
S.No Unit Topics to be covered
Periods

INTEL 8051: Architecture of 8051, Memory Organization, Register banks, Bit addressing
1 I 10
media, SFR area, addressing modes, Instruction set, Programming examples.

8051 Interrupt structure, Timer modules, Serial Features, Port structure, Power saving
2 II 6
modes.

MOTOROLA 68HC11: Controllers features, Different modes of operation and memory


3 III map, Functions of I/O ports in single chip and expanded multiplexed mode, Timer 6
system.

Input capture, Output compare and pulsed accumulator features of 68HC11, Serial
4 IV 6
peripherals, Serial Communication interface, Analog to digital conversion features.

PIC MICROCONTROLLERS: Program memory, CPU registers, Register file structure,


5 V Block diagram of PIC 16C74, I/O ports. Timer 0,1 and 2 features, Interrupt logic, serial 8
peripheral interface, I2C bus, ADC, UART, PIC family parts.
MICROCONTROLLER INTERFACING: 8051, 68HC11, PIC-16C6X and External
Memory Interfacing – Memory Management Unit, Instruction and data cache, memory
6 VI 8
controller. On Chip Counters, Timers, Serial I/O, Interrupts and their use. PWM, Watch
dog, ISP, IAP features.
INTERRUPT SYNCHRONIZATION: Interrupt vectors & priority, external interrupt
7 VII design. Serial I/O DevicesRS232 Specifications, RS422/Apple Talk/ RS 423/RS435 & other 8
communication protocols. Serial Communication Controller
CASE STUDIES: Design of Embedded Systems using the micro controller 8051, 68HC11,
8 VIII PIC-16C6X for applications in the area of Communications, Automotives, industrial 4
control.

FACULTY HOD PRINCIPAL


RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.G.Kishore Kumar


SUBJECT: OPERATING SYSTEMS
Branch & Year: M.Tech, I-Sem ES Total Hours: 49 Hours
Estimated
S.No Unit Topics to be covered
Periods
INTRODUCTION: Operating system definition, Objective and functions, types, different
1 I parts, Structure of operating system, trends- parallel computing, distributed computing; 5
Open systems, Hardware, software, firmware.
PROCESS SCHEDULING: Definition of a process; process states, transitions, process
control, suspend and process, interrupt processing, nucleus of an operating system;
2 II 10
parallel processing; Mutual exclusion, Critical Section; Solution of mutual exclusion;
Semaphores; Deadlock- occurrence, prevention, detection and recovery

STORAGE MANAGEMENT: Storage organization, management strategies, hierarchy;


3 III 5
virtual storage, paging, segmentation

FILE SYSTEM MANAGEMENT: File system (function of a file system)- data hierarchy,
4 IV blocking and buffering, file organization, queued and basic access methods, backup and 5
recovery

I/O MANAGEMENT: (functions of I/O management subsystem), Distributed computing-


5 V 6
OSI view, OSI network management, MAP, TOP, GOSIP, TCP/IP

OS SECURITY: Requirements, external security, operational security, surveillance,


6 VI 6
threat monitoring; Introduction to Cryptography

CASE STUDIES: UNIX- Shell, Kernel, File System, Process Management, Memory
7 VII 6
Management, I/O System, Distributed UNIX

CASE STUDIES: Example of operating system-MS-DOS, Windows, OS/2, Apple


8 VIII 6
Macintosh & Linux

FACULTY HOD PRINCIPAL


RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.A.Sathish


SUBJECT: VLSI TECHNOLOGY
Branch & Year: M.Tech, I-Sem ES Total Hours: 50 Hours
Estimated
S.No Unit Topics to be covered
Periods
INTRODUCTION TO MOS TECHNOLOGY: Overview of VLSI Design Methodologies,
1 I VLSI Design flow, Styles of VLSI Design, CAD Technology, MOS Transistors and its 5
Trends.
BASIC ELECTRICAL PROPERTIES OF MOS: Ids-Vds Relationships, Threshold voltage
2 II 6
Vt, gm, gds and Wo, Pass Transistor, MOS Zpu/Zpd, MOS Transistor circuit model.
CMOS Design: CMOS Logic, CMOS Gate Design, Transmission Gate Logic Design, Bi-
3 III 6
CMOS Inverters, Latch-up in CMOS circuits.
LAYOUT DESIGN AND TOOLS: Transistor structures, Wires and Vias, Scalable Design
4 IV 7
rules, Layout Design tools.
LOGIC GATES & LAYOUTS: Static Complementary Gates, Switch Logic, Alternative
5 V 7
Gate Circuits, Low Power Gates, Resistive and Inductive Interconnect Delays.
COMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network Delay,
6 VI Interconnect Design, Power Optimization, Switch Logic Networks, Gate and Network 6
Testing.
SEQUENTIAL SYSTEMS: Memory Cells and Arrays, Clocking Disciplines, Design, Power
7 VII 7
Optimization, Design Validation and Testing.
FLOOR PLANNING & ARCHITECTURE DESIGN: Floor Planning Methods, Off-Chip
8 VIII Connections, High level Synthesis, Architecture for Low Power, SOCs and Embedded CPU 6
Architecture Testing.

FACULTY HOD PRINCIPAL