7, JULY 2010


A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
Salvatore Drago, Student Member, IEEE, Domine M. W. Leenaerts, Fellow, IEEE, Bram Nauta, Fellow, IEEE, Fabio Sebastiano, Student Member, IEEE, Kofi A. A. Makinwa, Senior Member, IEEE, and Lucien J. Breems, Senior Member, IEEE
Abstract—The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL’s total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 0.15 mm2 and draws 200 A from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle. Index Terms—CMOS, duty-cycle, frequency stability, frequency synthesizer, fully integrated, PLL, ultra-low-power, wireless sensor networks, WSN.

I. INTRODUCTION NERGY autonomy and form factor are two critical concerns for emerging sensor platforms, particularly for applications based on wireless sensor networks (WSN) [1]. The limited energy from power sources such as micro-fabricated batteries or energy scavengers remains one of the biggest challenges for such systems. Reducing the power consumption of WSN nodes will extend their lifetime, lower the battery size and, consequently, reduce their volume. As for other radio communication systems, high-frequency synthesizers are essential blocks of WSN nodes. The current state-of-the-art of such synthesizers is illustrated in Fig. 1. Conventional PLLs are robust to frequency offset and frequency drifts thanks to the fact that they are locked to a stable reference. Their inaccuracy is then mainly determined by oscillator phase noise and by other sources of in-band noise. Although PLLs can achieve inaccuracies of a few ppm, this is associated with stringent phase noise and jitter requirements [2], [3] and leads to relatively high power consumption. Such PLLs are not suitable for use in WSN nodes. To address this problem, various architectures with relaxed phase noise and accuracy speci-


Fig. 1. Comparison between high-frequency synthesizers in various applications. For PLLs, accuracy is estimated from their rms period jitter. For free-running oscillators the accuracy is defined as the maximum relative frequency deviation due to PVT variations. DCPLL point is given as reference.

Manuscript received November 17, 2009; revised March 05, 2010; accepted March 23, 2010. Current version published June 25, 2010. This paper was approved by Guest Editor Yann Deval. This work was supported by the European Commission in the Marie Curie project TRANDSSAT 2005-020461. S. Drago, F. Sebastiano, L. J. Breems, and D. M. W. Leenaerts are with NXP Semiconductors, Eindhoven, The Netherlands (e-mail: salvatore.drago@nxp. com). B. Nauta is with the IC Design Group, CTIT Research Institute, University of Twente, Enschede, The Netherlands. K. A. A. Makinwa is with the Electronic Instrumentation Laboratory/DIMES, Delft University of Technology, Delft, The Netherlands. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier 10.1109/JSSC.2010.2049458

fications have been proposed to reduce power consumption. In [4] and [5], a free-running, but periodically calibrated, digitally controlled oscillator (DCO) is employed. This approach is extremely low power, but its inaccuracy is limited to only a few percent due to the large and unpredictable frequency drift caused by supply voltage and temperature variations. A node in a WSN typically spends the largest fraction of time in idle mode [6]. The energy wasted while idling can be significantly reduced by switching-off unused parts of the system. This suggests the use of duty-cycled PLLs (DCPLLs) in WSN nodes, i.e., PLLs which are operated in burst mode [7]. The output of a DCPLL consists of short bursts of high-frequency signals separated by long idle periods, during which energy is saved. The resulting lower power dissipation of DCPLLs makes them much more suitable for WSN nodes. Since DCPLLs are not active continuously, they are prone to frequency offset and so they are less accurate than conventional PLLs. The inaccuracy of 0.25% targeted in this work is enough to meet the requirements of WSN applications [5], [6]. Although DCPLLs dissipate more power than simple free-running DCOs, they are more accurate and less prone to frequency drift due to their closed-loop nature. However, they require special architectures to ensure loop stability and fast start-up circuitry to avoid extra power consumption during the transitions from idle to active periods. Fast start-up circuitry enables the use of low duty-cycle ratios, which translates into low average power consumption. The objective of this work is to design a frequency synthesizer capable of burst operation while maintaining a frequency error due to offset and to the DCO noise less than 0.25%. The pro-

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the large delay DCW update does not affect the DCPLL’s dynamics.1306 IEEE JOURNAL OF SOLID-STATE CIRCUITS. the DCO is started up and alof lowed to run for only one reference clock cycle . 2. Duty-cycled PLL. The DCO drives the counter which is reset before each burst generation. which generates the conwith a frequency trol signals for the DCO. there is enough time margin for a proper error estimation. which appears once every th clock cycle. A simplified block diagram of the proposed DCPLL is shown in Fig. sented in Fig. Both loops are controlled in an efficient manner by a finite state machine (FSM). the counter detects the number of DCO rising edges that occur during the reference clock cycle. VOL. a counter. in the thanks to the burst mode operation. The previous condition is well satisfied in the DCPLL implementations since the reference frequency is several times smaller then the generated high-frequency output signal. 2. allowing frequency tracking between two successive bursts. Coarse Acquisition Main Loop Dynamics The dynamics of the coarse acquisition main loop can be analyzed considering it as a discrete time system. demonstrating that a frequency inaccuracy of better than 0. JULY 2010 Fig. 45. are ignored. resulting in area saving and reduced complexity [3]. B. The use of two different banks relaxs the requirements of the DAC. The resulting error signals and updates the DCWs stored in the two accumulators. This is because the DCO’s digital control word (DCW). resulting in a highly energyefficient synthesizer which enables energy autonomous WSN nodes. Moreover. This strategy makes it possible to implement the counter and the digital subtractor as a simple asynchronous D-FF-based counter and a full-adder based subtractor respectively. a short preset period is used to speed-up the DCO’s start-up. including the FSM. As will be explained in the next section. After a sleep time sure that its frequency reference clock cycles. which represents its frequency can then be stored in a memory. This assumption is valid if the reference clock periods are larger than the total delay introduced by the digital gates. DCPLL Architecture In order to enable burst mode operation. 7. The generated frequency ranges from several hundreds of MHz to more than 1 GHz. The DCW update is delayed by one reference cycle . NO. In the following analysis the delays of each block. an All-Digital PLL is preferred over a conventional analog PLL based on a phase frequency detector and a charge pump. The output frequency for the th burst. DCPLL waveforms. Circuit description and fast-start up strategies are discussed in Section III. 3. The DCO is periodically turned on and off. a reference clock drives the FSM. A second fine tuning loop increases the accuracy of the output frequency as explained in the next subsection. As shown in the timing diagram of Fig.A of the output frequency block diagram model of the coarse acquisition loop is repre.25% can be achieved while maintaining a power consumption of only few hundreds of W. posed DCPLL can be operated at low duty-cycle ratios. The resulting integer is stored in the registers of the counter and it is compared with the desired frequency control word by the digital subtractors. since it employs a fast start-up DCO. The DCO consists of a current-controlled ring oscillator and a 16-bit digital-to-analog converter (DAC) segmented in two banks: one 7-bit bank for coarse frequency acquisition and one 9-bit bank for fine tuning. the counter and the accumulators. DUTY-CYCLED PHASE-LOCKED LOOP (DCPLL) A. while the two loops enis locked to . Since is large compared to the counter’s and subtractor’s delays. is given by (1) . experimental results are given in Section IV and conclusions are presented in Section V. The response can be formulated in terms and the input frequency . 3. This leads to a significant power saving with respect to synchronous counters and phase frequency detector based on charge pump. The architecture of the DCPLL is presented in Section II along with a stability analysis. Fig. where the sampling operation is determined by the rising edge of the reference clock which causes the burst generation. II. In doing so. Theoretical analysis and experimental validation of this approach is provided. 4. Its main loop consists of a DCO. an accumulator (ACC1) and one digital subtractor (S1).

the stability condition is difficult to predict on and a theoretical basis. 5. In the general case. integer can be expressed conas the sum of the fractional number of DCO’s period . The DCPLL settles in one step when . 4. This behavior is undesirable because the stability of the loop can be affected at lower frequency. Simulation results . In order to find a simple condition for stability. In conclusion the DCPLL is unconditionally stable if the following stability equation is satisfied: (7) Fig.: A 200 A DUTY-CYCLED PLL FOR WIRELESS SENSOR NODES IN 65 nm CMOS 1307 based on (4) are summarized in Fig. the DCPLL is always unstable if . where offset and is given by: is the DCO gain (MHz/bit). As shown Fig. an implicit function of (4) becomes non-linear. becomes larger. For DCPLL’s step response for different values of the system is always stable and its step response is overdamped. where By combining (1)–(3) the following closed loop finite difference equation can be derived: (4) is constant and known. While the reference clock frequency is known. Fig. it is If the coarse DCO gain possible to predict the exact dynamics of the coarse acquisition loop. in fact. the system is stable only if the is close to one of programmed DCPLL’s output frequency the possible DCO’s free-running frequencies: Fig. the integer number of rising clock edges which fall in one clock reference period in the th burst. It shows the normalized . In this case. the parameter is process technology dependent and it behaves nonlin. which cause the frequency quantization error to increase. 6(b). i. A particular behavior is observed when . is. (6) Finally. a numerical approach has been used. The frequency can change over a broad range. This will early with respect to the digital control word cause the dynamics to vary around the design target. In this case. the DCO has to be carefully designed in order to ensure the sta. (2) When locked. current-controlled delays lines in closed loop can be used to implement a DCO with a fast start-up time. The th programmed frequency represents the counter’s output. and for any as shown in Fig. defined as the th burst’s frequency error. which in turn constrains the operating frequency range.e. DCO gain C. 7 shows an example of its output frequency as a func. However. 6.DRAGO et al. Fine Tuning Secondary Loop Conceptually a single loop performing the coarse frequency acquisition is sufficient to reach the steady-state condition. represented by is equal to: and the quantization error . Fig. (5) Under this condition the response is underdamped and it converges asymptotically to the programmed frequency. As will be explained in Section III. tained in one reference clock period . especially for low bility condition of (7) for each value of is larger. As the operating frequency it is nonlinear with respect to is reduced. is the DCO . Counter quantization noise. Block diagram model of the coarse acquisition loop. theoretical considerations on (4) can be drawn easily only under the hypothesis that the quantization error is very small and negligible. the system is stable if the pole falls inside the unitary circle. where the DCO’s output frequency is closed to the . when the term is large. if the DCO’s frequency differs from the output frequency by more then [see (6)] the output will oscillate around the target frequency with a large quantization error. However. The DCO has a duty-cycle equal to the programmable and the DCPLL’s output frequency is of (8) with falling in the range . (3) . 8(a) shows a typical coarse acquisition steady-state condition. and the integer number of DCO rising edges between two reference edges is . Thus.. For a given tuning range the frequencies where stability condition can be ensured by increasing the resolution of the coarse frequency acquisition bank in order to reduce the . but tion of . 5. Thus.

the fine tuning loop increases or decreases the DCW by 1 LSB depending on th DCO edge leads or lags the reference whether the clock edge. VOL. in conjunction with the main loop. since each burst is generated synchronously every N reference cycles. which handles the coarse frequency acquisition. 6. the last DCO period is also locked to the reference clock thanks to the . This results into an error in . Simulated normalized step responce for different value of K =REF. As depicted in Fig. 7. the bottom plot represents condition (6). Fig. The total error is reduced and the accuracy is improved [Fig. 8(b)]. (b) Fine tuning. an additional loop is employed for fine frequency of the tuning. Notice that the coarse and the fine tuning loops adjust only the centre frequency of the bursts. the generated frequency which can be as high as Significantly better performance can be achieved if. 8. However. 7. the DCO initial phase is locked to the reference phase. NO. DCO rising edge may be delayed by with respect to the reference rising edge. Fig. The last DCO edge is advanced by a time interval given by (9) Before each burst generation.1308 IEEE JOURNAL OF SOLID-STATE CIRCUITS. the frequency then varies by and so the last DCO edge jumps backward and forward around the reference clock edge in a bang-bang fashion. a small increase DCO’s frequency advances all the DCO’s rising edge by small time steps. 8(b). (a) Coarse acquisition. At this point. 45. the fine tuning loop decreases the delay between the last DCO rising edge and the reference clock edge. the fine tuning loop increases the DCW by a least significant bit (LSB) increasing the DCO freuntil the th DCO edge quency by a small step just leads the reference clock edge. Typical DCO transfer characteristic. Burst by burst. While the main loop controls the number of rising edges occurred between two successive reference clock edges. Moreover. JULY 2010 Fig.

10 shows the simulated settling of the coarse and fine tuning values during the frequency acquisition.: A 200 A DUTY-CYCLED PLL FOR WIRELESS SENSOR NODES IN 65 nm CMOS 1309 Fig. (b) Fine tuning. Simulated coarse and fine tuning values settling behavior. been chosen low enough to make the quantization noise negligible with respect to the phase noise. 10. in a low-power implementation. (10) The uncertainity of the edge accumulation after periods is th due to the phase noise ation. In the current design. This error posed dual loop configuration is reduced to can be minimized by increasing the DCO’s fine tuning bank resolution. the gain in the fine loop can be modified to achieve an adaptive bandwidth. The quantization error in the frequency generated by the pro. 9 shows the implemented combined transfer characteristic of the counter and the subtractor for the coarse acquisition and fine tuning loops. This ensures that the fine tuning bank is continuously modified in order to change the DCO’s frequency by small steps around the programmed frequency in a bang-bang fashion. Fig. In doing so. Finally. the combination of the two loops together with the duty-cycling operation transforms the system into a phase-locked loop. thanks to the delay introduced in the DCW update. a vertical dead-band is implemented in its transfer characteristic. In the transfer characteristic of the coarse acquisition loop the horizontal dead-band has been . Transfer characteristic of counter and subtractor. This avoids changes in the coarse freto quency bank when the DCO’s frequency is closed to the desired frequency. When the secthe coarse acquisition loop produces a null error (11) The quantization noise is negligible with respect to the phase noise if the following condition holds: (12) By combining (11) and (12). By means of the bandwidth control block. both a faster PLL settling time and an accurate frequency output can be achieved. In order to realize the bang-bang operation in the fine tuning loop. the fine tuning dynamics are adjusted based on whether the system is in the acquisition or in the steady-state tracking mode. the quantization noise is lower than DCO’s phase noise which is determined has by the total power available.DRAGO et al. Fig. Thus. (a) Coarse acquisition. A modified subtractor has been used in order to realize the bang-bang oper- . the DCPLL does not require a power hungry bang-bang phase detector but only requires simple logic circuits implementing a digital subtractor [9]. 9. This is equivalent to saying that the tractor. However. bang-bang operation. it can be concluded that to neglect the error due to the quantization noise should satisfy the following condition: (13) As said in the previous subsection. When only thermal noise can be is considered the DCO relative period jitter expressed as function of the SSB phase noise PSD at fre[8]: quency offset and the DCO frequency Fig. typical for a conventional subextended from the range . to the range when the integer subtractor produces a null error signal number of the DCO edges falling into one clock cycle is equal or to . Initially only the coarse tuning is operative.

7. the coarse acquisition bank is modified by one LSB. the switches – are closed allowing the generated current to set the voltage and . configures the delay line as an oscillator whose output frequency depends on the conand . which precedes the start-up moment controlled by the switches – .. the DAC is switched ON to read the information stored in the DCPLL accumulators and. To achieve this while maintaining a low power consumption. which begins one reference clock before the DCO is started (Fig. connected to and an opamp. then. 45. If the fine tuning accumulator overflows. The DCO start-up delay must be negligible with respect to the reference period. The simplified circuit schematic of the R/2R current DAC is represented in Fig. which together with the node capacitance introduces a delay of 34 ps. DCO The proposed DCPLL can work only with a fast start-up DCO whose output frequency can settle well within a short reference clock period . and are large capacitors and that the This requires that and are large enough to set currents through the diodes the voltages in a short time. its static power consumption in idle mode should be very low. 11 illustrates the time dia. After a small delay the switches – are opened to preserve the charge in the caand and the DAC is turned off to save power.A order to improve the linearity of the drain current is delivered to the ring oscillator by means scaled copy of . The DCO is kept running for one reference cycle and. after half reference period. It consists of two different R/2R ladders implementing the coarse and the fine banks. Therefore. a preset phase precedes the DCO’s actual start-up. realizing a segmented but overlapping DCO transfer characteristic. is proportional to the desired frequency. 11. 11). Finally. The pacitors different control phases are generated by means of a non-overlapping clock generator. JULY 2010 Fig. So when the DCO is started. which is negligible with respect to the minimum DCO period. the per-stage delay is tuned to 1/8 of the desired RF cycle period by means of the DAC current source which sets the two voltages and . VOL. the fine tuning range is larger than two coarse LSBs. since the DCO will be turned off for a significant fraction of time. Fig. consisting the pMOS transistor of a differential pair. The simulated is 270 Ohm. Additionally. resistance of the switches In order to decrease the and in the signal path. To synthesize switching events (i. NO. all voltages are already preset to their correct values. Schematic of the DCO. shut down by means of the switches – which configure the DCO again as an open-loop delay line. 11. To ensure proper functionality. During the preset phase. Most of its power dissipation is due to trol voltages ). III. Opening and and closing and synchronously. ondary fine tuning loop is activated and the gain is automatically reduced until the “bang-bang” steady-state condition is reached. The frequency is controlled by the comand at the gates of pMOS – plementary voltages and nMOS – which are stored on the two large gate caand .1310 IEEE JOURNAL OF SOLID-STATE CIRCUITS. In order to save power during the idle state. if phase noise is not the main requirement.e. 12(a). These considerations motivate the use of the ring oscillator shown in Fig. where Q is the quality factor of the LC tank [10]. of transistor the enable switches are open and goes to the cut-off region . Each delay stage uses a pseudo-differential architecture. the input gram of the switches of the delay line is connected to and ground by means of the switches and . The fast start-up behavior of the DCO is pacitors achieved by adopting a preset phase implemented by means of the switches – . connects both the ladders in feedback in of . The opamp. During the idle state. Ring oscillators start up faster than LC oscillators. a transmission gate topology has been chosen (Fig. It consists of four delay stages in a closed loop and an R/2R ladder current DAC. while the final stage of the delay line is disconnected from the first stage by means of the switches and . 11). ring oscillators require less power than LC oscillators [5]. which require approximately Q periods to reach steadystate. the oscillator’s power consumption is only determined by the leakage currents of the inverters. thus mitigating output frequency variations.

limit the range of and to . due to the large load resistance. thus. Montecarlo simulations showed that 7 bits are enough to ensure the stability condition of (7) for all the coarse DCWs over the full frequency is chosen to set the fine tuning range larger than two range. By inspecfixed to the reference voltage tion of the equivalent circuit is simple to derive as the sum and : of coarse and fine currents (14) (15) To ensure proper functionality. in the steady-state condition and in the particular case when node (b) is used as output. the multiplication factor is fixed because no additional resolution is required. Since node (a) is connected to the switches and .: A 200 A DUTY-CYCLED PLL FOR WIRELESS SENSOR NODES IN 65 nm CMOS 1311 Fig.DRAGO et al. (a) Schematic of the DAC and (b) its equivalent circuit. the reference frequency multiplication factor can be also be changed by steps of 0. To ensure this. there signal. Finally. Fig. The two R/2R ladders can be represented as the parallel of two digitally and in series with fixed tunable voltage sources and . switches from ground to with negligible delay with respect to the start-up reference rising edge. in principle. The voltage at node A is coarse and fine resistances by the feedback. Fractional multiplication: steady-state signals on (a) the start-up node and (b) the output node. 13 shows the signals nodes (a) and (b) with reference of Fig. the DAC power consumption is only determined by the opamp current. Since node (b) is fed back th rising edge is to the counter in the DCPLL loop. In principle. Therefore. comprising Fig. Fig. however. the adoption of a 4 differential stage DCO allows the generation of 8 different phases and. the maximum value of and should be lower than .25 by selecting one of the four possible quadrature outputs to feedback to the counter with respect to the position of switches – . In this design. 12(b) shows the current DAC equivalent circuit. To test the fractional multiplication of the reference. additional R/2R elements. are used for Miller compensation of the feedback loop and the opamp. However. 13. the area of the resistors is chosen large enough to ensure the monotonicity of the DAC. a fractional multiplication of the reference thanks to the availability and at of multi-phase outputs. The proposed DCO’s architecture allows. 12. its aligned with the reference rising edge generating the switch-off and are normally delayed by . the operation at 1/8 fractional-N. 11. Since DCO periods in one reference period are and the nominal output frequency is given by (16) When required. thanks to the low output capacitance at node A the required curand rent to ensure the closed-loop stability is also low. The adopted circuit topology allows to increase the resolution of the DAC while maintaining fixed the tuning range by adding extra R/2R elements. always connected to ground. coarse LSBs. node (b) has been chosen as output .

17. Fig. The circuit measures 0.3 V supply voltage is 200 A (100 A for the DCO. 16.65 constant phase error with respect to the reference. resulting into a multiplication factor of . Most of the area is occupied by the R/2R network and by the two digital loops (Fig. 14). NO. EXPERIMENTAL RESULTS The oscillator has been realized in a baseline TSMC 65 nm CMOS process. 15. The instantaneous frequency is computed as the reciprocal of the DCO period. The maximum DCO frequency can be increased either by burning more power. The maximum DCO frequency is limited by the interconnections parasitic capacitances which is comparable with the input capacitance of the delay stages. Measured output frequency and offset versus FCW. Measured DCPLL output (top) with zoom-in (bottom). Fig. Measured DCPLL frequency deviation from 1.005 GHz versus time. Each point represents the average frequency within each burst and it has been measured by using a 20 GHz digital sampling scope. Fig.1312 IEEE JOURNAL OF SOLID-STATE CIRCUITS. the total current consumption at 1. since they are implemented with minimum size devices to enable low-power operation. Measured DCPLL settling time. However. When generating 1 GHz. 7.2 GHz. JULY 2010 Fig.2 ns. 15. 45. After the acquisition of each burst. The output frequency can be programmed from 300 MHz to 1. VOL. 18. The delay between tion and with a 10% duty-cycle the reference clock and the generated burst is 1. 60 A for the current DAC. while . 14.03 mm . the DCPLL’s output consists of a train of approximately 1 GHz bursts with 50 ns dura. Die micrograph of the test chip. the DCO periods have been computed by first interpolating the sampled waveform linearly and then estimating the zero-crossing time. The proposed DCO can cover frequencies ranging from 300 MHz up to 1. The PLL’s initial settling transient is shown in Fig. 16. Fig. while being driven by a 20 MHz reference clock. scaling up the devices size. or by employing a 2 differential stage DCO. 40 A for the counter and PLL logic). IV. the last one translates into a lower DCPLL resolution.2 GHz according to (16). which corresponds to a 8. As shown in Fig.

which occurs during the DCO ON time is fixed to FCW by the dual loop architecture. after 15 bursts. the accumulated jitter for the edge is 30 ps (rms) giving a time uncertainty of 0. 0 . Fig.2% and it is reported in Fig. the average frequency within each burst is estimated by averaging the instantaneous frequency. In fact. 19(a). 19(b) shows the zero-crossing point distribution of the 50th rising edge. Measured output spectrum. the DCO’s initial frequency was set to about 300 MHz by loading an estimated DCW into the accumulator while the programmed FCW was 50. The frequency accuracy of a DCPLL is determined by the total contribution of the offset and of the DCO’s phase noise. Consequently. 19(a) shows the distribution of the generated frequency for 1000 con. In the case shown.06% observed in Fig. the average DCO period will be also longer and. After 49 DCO periods. As shown in Fig. also the relative error is independent on is independent on and this on the output frequency in fact is observed in the measurements in Fig. The absence of the syssecutive bursts in the case tematic “bang-bang” frequency jumps confirms that the error due to the DCO’s phase noise is greater than the quantization error. Fig. or equivalently. the correct DCW will be stored in the two accumulators and only needs to be slightly adjusted to compensate for temperature and voltage variations. Fig. 1 MHz offset [(10)]. Consequently. Measured probability density functions (PDF) of (a) the DCPLL output frequency and (b) of the zero-crossing time of the 50th edge in the case FCW = 50.15%. The DCO ON time is longer than one reference period and its frequency is then lower.5 MHz or equivalently 0. This is due to a systematic difference between the delay from the reference clock to the start-up signal and from the reference clock to the switch-off signal. while the two bold lines represent the standard deviation.005 GHz with an error less than 0. the output frequency settles to the programmed frequency of 1. after 7. Fig. 1This value is more reliable than the one reported in [7] of 73 dBc/Hz @ 1 MHz since it is computed on the basis of an higher number of bursts (1000). thus.1 According to (13) the frequency step of the fine tuning bank is less than 140 KHz. the DCO frequency is lower. 20. 18. 21. if the DCO ON time is longer.5 s.: A 200 A DUTY-CYCLED PLL FOR WIRELESS SENSOR NODES IN 65 nm CMOS 1313 Fig. 18. After the PLL’s first settling transient. The measured systematic offset for all the frequencies is less of 0. The average frequency has an offset with respect to the nominal frequency of about 1. This translates into a frequency error due to the noise of 0.25%.06% with respect to the reference. If a systematic error affects the reference period the relative error on the time the DCO is active . 17 shows the frequency for 1000 consecutive bursts for the case . ps ps which correThe DCO period jitter is sponds to a thermal free-running phase noise of 77 dBc/Hz at Fig.DRAGO et al. Measured DCO instantaneous frequency during a burst. the number of DCO periods. 19. 16. Each point represents the average frequency within each burst.

its instantaneous frequency during a burst has been measured and is reported in Fig. pp. Leenaerts. D. 1803–1816. “An overview of design techniques for CMOS phase detectors. 44. S. W. Pletcher. The DCO starts approximately at the correct frequency and takes a few DCO periods to settle.1314 IEEE JOURNAL OF SOLID-STATE CIRCUITS. N. Aarts. Sebastiano. Rabaey. F. Lee. M. E. P. NO. “Impulse based scheme for crystal-less ULP radios. pp. Aug. Yuan. Solid-State Circuits.18 m CMOS. R. After the offset calibration the achieved accuracy is limited by the DCO’s jitter and.4 GHz RF transceiver for wireless sensor networks in 0. 22 summarizes the DCPLL performaces and shows a comparison with a few previously published frequency synthesizers. 258–259. S. and J. [7] S. Klumperink. 269–280. Shah. E. NY: Springer. C. 1. “A 2. pp. Aug. Eliezer. Symp. pp. Feb. 0. A. B. Tech. and E. an error of 20 MHz (2%) would be obtained with only the main loop. New York.25% including frequency offset and error due to the noise . no. Solid-State Circuits. Makinwa. IEEE Int. R. 2005. pp. M. 21 together with the interpolated frequency (2 samples averaging) and the average frequency over a burst period. 392–393. Lanzisera.13 m CMOS with 400 mV supply and an integrated passive RX front-end. Symp. DCPLL performance and comparison with previous work. 0 0 V.” in IEEE ISSCC Dig. Rezeq. Rabaey. Papers.1-to-5 GHz alldigital UWB transmitter in 90 nm CMOS. Muhammad. Chandrakasan. Leenaerts. K.6 mW sub-sampling PLL with 126 dBc/Hz in-band phase noise and 0. Breems. “All-digital PLL and transmitter for mobile phones. Leipold.-M. Rabaey. [4] B. Nauta. pp. and J. vol. Sheets. Conventional PLLs achieve better accuracy (limited by DCO phase noise and by other sources of in-band noise) but with higher power consumption. 2469–2482.” IEEE J. However. ESSCIRC. A. Cruise. Free-running DCOs consume less power but they are prone to large frequency drift. To characterize the DCO’s performance. “Phase noise and jitter in CMOS ring oscillators. [10] D. [2] X. Staszewski. As shown in Fig. D. 45. the deviation from the fixed frequency is kept within few percent thanks to the preset strategy.” in Ambient Intelligence. Bohsali. Lin. 40. It consumes less than 200 A while generating a 1 GHz output frequency with 10% duty-cycled. and D. Ammer. Barton. [9] F. 22. Abidi. K. pp. Weber. 1. Makinwa.” IEEE J. by the total power budget available. IEEE Int. Sep. 132–135. 8. Circuits and Systems (ISCAS). S. Feb. Tech. 2009. pp. Entezari. [6] F. 2009. Nauta. C. Jan. 118–591. May 2008. Vemulapalli. R. 20. It can be seen that the fine tuning loop significantly improves the achieved accuracy. Berny. DCPLLs are good candidates to generate a high frequency in nodes for WSN applications. Cook. Pister. VOL. As shown in Fig. JULY 2010 Fig. 2009.” in Proc. J. “A 52 W wake-up receiver with 72 dBm sensitivity using an uncertain-IF architecture. and B. M. The standard deviation of the frequency error represents an important parameter for burstmode frequency synthesizer since it replaces the closed-loop PLL phase noise. Nauta. Wallberg.-C. A. B. Maggio. 457–460. the latter can be reduced only increasing the power consumption. and B. resulting in an high energy-efficient synthesizer. Gambini. 7. [8] A. 2006.2 GHz 7. Drago. By employing a fast start-up DCO the PLL can operate with a low duty-cycle factor. Staszewski. S. Tech. K. the spectrum of the DCPLL output signal is modulated and it is not possible to derive phase noise information. Soliman and S. M. Eds. Breems. K. less than . M. “Ultra low-power integrated wireless nodes for sensor and actuator networks. The table in Fig. The DCPLL is not sensitive to this systematic variations but it tries to tune the average frequency showed as dashed line. Gao. F. S. no.” in Proc. L. thanks to their moderate accuracy and low power demand. Dec. Solid-State Circuits. 2006. pp. REFERENCES [1] J. May 2002. M. 41. Circuits and Systems (ISCAS). hence. and L. “A 47 pJ/pulse 3. S. O.” in Proc. Wentzloff and A. vol. [3] R. Papers. Burghardt. W. Molnar. “An ultra-low-power 2. M. no.15 ps jitter in 0.” in IEEE ISSCC Dig. In DCPLLs. K. J.” in IEEE ISSCC Dig. power is traded for accuracy. CONCLUSION Duty-cycled PLLs can be used as high-frequency synthesizers in WSN nodes. [5] N. D. A simplified theoretical analysis has been carried out showing the stability conditions for such systems. 2007. Hung. Sebastiano. vol. J. Fabricated in a 65 nm CMOS process the DCPLL shows a total frequency multiplication inaccuracy. 2005.” IEEE J. Drago. Papers. Fernando. 1508–1511. 12. and K. While the first can be calibrated. Otis. “A 200 A duty-cycled PLL for wireless sensor nodes.

E. In 2006. In 2006. His research interests include ultra-low-power radio and RF integrated circuit design. he received a Veni Award from The Netherlands Organization for Scientific Research and the Simon Stevin Gezel Award from the Dutch Technology Foundation. Domine M. ANALOG AND DIGITAL SIGNAL PROCESSING. Breems is a member of the technical program committees of the IEEE International Solid-State Circuits Conference (ISSCC) and the Symposium on VLSI Circuits and has been a technical program committee member of the IEEE International Symposium on Low Power Electronics and Design from 2004 to 2007. where he is now an Antoni van Leuwenhoek Professor in the Faculty of Electrical Engineering. In 2007 he joined NXP Semiconductors where he is currently a Senior Principal in the mixed-signal circuits and systems group and leads a research team working on sigma-delta A/D converters. Eindhoven. Leenaerts (M’94–SM’96–F’05) received the Ph. Sebastiano was a corecipient of the 2008 ISCAS Best Student Paper Award. This has resulted in 1 book. He has coauthored several books. thesis was published as a book: Analog CMOS Filters for Very High Frequencies (Springer.Sc.l. Nigeria. he moved to NXP Semiconductors Research as a Senior Principal Scientist. In 1995. he received the M. Computer Science and Mathematics. The Netherlands.E. In 2006. The Netherlands. The Netherlands and in 2004. He has also served as a guest editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS (July 2009 and 2010). (cum laude) and M. he joined Delft University of Technology. In 1987. He published the book Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers (Kluwer. degree in collaboration with Delft University of Technology. Since 2009 he has served as Associate Editor of the IEEE JOURNAL OF SOLID-SATE CIRCUITS and served as Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II during 2008–2009. he was with Synapto s. He currently serves on the Technical Program Committee of the European Solid-State Circuits Conference. he served as Guest Editor. He was a corecipient of the ISSCC 2002 Van Vessem Outstanding Paper Award. he received the Ph.Sc. Makinwa is on the program committees of several international conferences. Mr. Associate Editor (2001–2006). In 2006. 1993) and he received the Shell Study Tour Award for his Ph. the European Solid State Circuit Conference (ESSCIRC). Dr. Italy. Pisa. In 1998 he returned to the University of Twente. 14 patents and over 100 technical papers. as a Marie Curie Fellow. The Netherlands. Eindhoven. degree from the same university on the subject of analog CMOS filters for very high frequencies. His main research interests are in the design of precision analog circuitry. Eindhoven. In 2005. Switzerland. respectively. he was a Research Scientist with Philips Research Laboratories. Makinwa (M’97–SM’05) received the B. From 1999 to 2006. he was a Visiting Scholar with the Department of Electrical Engineering and Computer Science. he received the Diploma di Licenza from Scuola Superiore Sant’Anna.D. Italy. He is a recipient of the ISSCC 2001 Van Vessem Outstanding Paper Award.DRAGO et al. Dr. Bram Nauta (M’91–SM’03–F’08) was born in Hengelo. Breems (S’97–M’00–SM’07) received the M. W. smart sensors and sensor interfaces. 2001). From 2000 to 2007 he worked as a Senior Scientist with Philips Research. The Netherlands. degree in collaboration with the University of Twente. (cum laude) degrees in electrical engineering from the University of Pisa. Kofi A. and three from the ISSCC. in 1964. and IEEE International Solid-State Circuits Conference (ISSCC). where he worked on EM modeling of embedded passives and interconnections in PCBs. degree (cum laude) in electrical engineering from the University of Twente. degree in electrical engineering from Eindhoven University of Technology. he was a Principal Scientist with Philips Research Laboratories. in 1996 and 2001 respectively. which is part of the CTIT Research Institute. where he is working toward the Ph. in 1992. At such conferences. the IEEE Radio Frequency Integrated Circuits (RFIC). in 1985 and 1988. work. After this. where he worked on high-speed AD converters and analog key modules. From 2004 to 2006. Italy. Lucien J. degrees from Obafemi Awolowo University. Mr. he received the M. A. he was the IEEE Circuits and Systems Society Member representative in the IEEE Solid-State Circuits Society Administrative Committee. sigma-delta modulators. In 1989. His main research interests are ultra-low-power radios for wireless sensor networks and fully integrated crystal-less frequency references. He is also a part-time consultant in industry. Prof. he has presented several invited talks and tutorials. From 1997 until 1999.D. degree in electrical engineering from the Delft University of Technology. 2001). and since 2007 as Editor-in-Chief for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. His current research interest is high-speed analog CMOS circuits. the Ph. Berkeley. he joined the Mixed-Signal Circuits and Systems Department of Philips Research. He is a Distinguished Lecturer of the IEEE and an elected member of IEEE SSCS AdCom. he served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II. In 1991. He is also a member of the technical program committees of the IEEE International Solid State Circuits Conference (ISSCC). His research interests are in the field of mixed-signal circuit design. Fabio Sebastiano (S’10) was born in Teramo..S. respectively. degree (cum laude) in electrical engineering from the University of Catania. Drago was a co-recipient of the 2008 ISCAS Best Student Paper Award. in 1981. he was with Eindhoven University of Technology as an Associate Professor with the Microelectronic Circuit Design group.D. where he worked on interactive displays and on front-ends for optical and magnetic recording systems.Sc. Eindhoven. The Netherlands. During 2005–2008. degree from the Philips International Institute.D. Enschede. Enschede.r. one from the ESSCIRC. Italy. In 1999. The Netherlands. and the Symposium on VLSI Circuits. The Netherlands. Leenaerts served as IEEE Distinguished Lecturer in 2001–2003 and served as Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I (2002–2004) and has been an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS since 2007. From 1992 to 1999.: A 200 A DUTY-CYCLED PLL FOR WIRELESS SENSOR NODES IN 65 nm CMOS 1315 Salvatore Drago (S’10) received the M. The Netherlands. The Netherlands. He received the B. he was an Invited Professor at Ecole Polytechnique Federale de Lausanne. including Circuit Design for RF Transceivers (Kluwer.D. where he was involved in RF integrated transceiver design.Sc. and holds several U. in 2003 and 2005. The Netherlands. His Ph. He is a Distinguished Lecturer of the IEEE Solid-State Circuits Society and a Fellow of the Young Academy of the Royal Netherlands Academy of Arts and Sciences. as a Marie Curie Fellow. and in 2001 he co-founded Chip Design Works.Sc. including the European Solid-State Circuits Conference (ESSCIRC) and the IEEE International Solid-State Circuits Conference (ISSCC). Eindhoven. in 2003.D. as a full Professor heading the IC Design group. University of California. on which he is now an elected member.Sc. .D. Since 2008 he has been a Lecturer at the Delft University of Technology on the topic of sigma-delta modulation. Catania. and M. he joined NXP Semiconductors Research in Eindhoven. In 1991. In 1997. degree from Delft University of Technology. patents. He is a corecipient of several Best Paper Awards. including one from the JSSC. From 1989 to 1999. Italy. He has published over 150 papers in scientific and technical journals and conference proceedings. working toward the Ph. Eindhoven the Netherlands. he joined NXP Semiconductors Research. degree (cum laude) and the Ph.Sc.D.