Design Verification Tutorial: Building Modular, Reusable, Transaction-Level Testbenches in SystemVerilog

Tom Fitzpatrick Verification Technologist Mentor Graphics Corp. 2006 MAPLD International Conference Washington, D.C. September 25, 2006
2006 MAPLD International Conference 1 Design Verification Tutorial

Functional Flaws Driving Need for Re-Spins
IC/ASIC Designs Requiring Re-Spins by Type of Flaw
Logic/Functional Clocking Tuning Analog Circuit Fast Path Yield/Reliability Delays/Glitches Slow Path Mixed-Signal Interface Power Consumption IR Drops Firmware Other 71%

Market Study 2002

0%
Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

20%

40%

60%

80%

100%

Percent of Designs Requiring Two or More Silicon Spins

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Functional Flaws Driving Need for Re-Spins
IC/ASIC Designs Requiring Re-Spins by Type of Flaw
Logic/Functional Clocking Tuning Analog Circuit Fast Path Yield/Reliability Delays/Glitches Slow Path Mixed-Signal Interface Power Consumption IR Drops Firmware Other 71% 75%

Market Study 2002 Market Study 2004
20% 40% 60% 80% 100%

0%
Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

Percent of Designs Requiring Two or More Silicon Spins

The Problem is Getting Worse
2006 MAPLD International Conference 3 Design Verification Tutorial

Design Engineers Are Becoming…

Breakdown of Design Teams by Main Function
Other 14% Design 51%

Verification & Test 35%

Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

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Design Engineers Are Becoming…
Verification Engineers
Breakdown of Design Teams by Main Function
Other 14% Design 51%

Design 51% Verification 49%

Verification & Test 35%

Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

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Design Verification Tutorial

You’ve Seen a Technology Explosion Targeting Verification
• • • • • • • • Assertion-based verification Functional coverage Constrained-random testing Coverage-driven verification Dynamic-formal verification Transaction-level verification Model checking And more . . .

Energy from a black hole NCG 4696

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Transaction Level 2000+ Register Transfer Level 1990+ Gate Level 1980+ • Currently shifting from RTL to TLM – No automated refinement path – Need methodology to assist refinement 2006 MAPLD International Conference 7 Physical Level 1970+ Design Verification Tutorial Verification Problem Continues To Grow Need More Simulators to Run Tests Need More People to Write Tests Need More Tests to Find bugs Bigger Designs = More Bugs New Tests Have Bugs Need More People to Debug Tests 2006 MAPLD International Conference 8 Design Verification Tutorial 4 .raise().Complexity and Abstraction • Moore’s Law drives higher levels of abstraction always @(decade) abstraction.

we integrate – many abstraction levels – many models of computation – many language domains SystemC SystemVerilog PSL Testbench SystemC Wrapper SystemC Wrapper VHDL DUT Verilog DUT Emulator DUT Testbench C++ algorithm ISS Model 2006 MAPLD International Conference 9 Design Verification Tutorial Complexity-Based Requirements St ru Design Complexity gg lin g n me ne efi yR t n sig De b Pr oA ct ive HDL Simulation ABV Constrained-Random Functional Coverage OOP TLM User Skill Set 2006 MAPLD International Conference 10 Design Verification Tutorial 5 .Mix & Match: Languages & Engines • Typically. in one simulation.

and rules used by those who work in a discipline • Knowledge of what works and what doesn’t – Standards enable communication 2006 MAPLD International Conference 12 Design Verification Tutorial 6 .Methodology Basics • People used to think all they needed for better verification was a faster simulator • Then they thought they needed new technologies – Testbench – Assertions Effective Methodology Functional Coverage Old Goal New Technologies Faster Simulator • Now they realize they need to know how to use them effectively – This is “Methodology” 2006 MAPLD International Conference 11 Verification Time Design Verification Tutorial What is “Methodology”? • The study of methods • A body of practices. procedures.

• If a tree falls in the forest and no one hears it. it does NOT make a sound • You have to be paying attention – Assertions – Functional Coverage – Scoreboarding Methodology Lets You Get Information • You have to knock down the right trees – Generate interesting stimulus – Use the right tools • Directed stimulus • Constrained-Random Stimulus • Formal verification 2006 MAPLD International Conference 13 Design Verification Tutorial Verification is a Human Problem Too SOFTWARE ENGINEERS TLM SoC ARCHITECTS Misinterpreting specifications is a prime source of bugs VERIFICATION ENGINEERS RTL HARDWARE ENGINEERS 2006 MAPLD International Conference 14 Design Verification Tutorial 7 .

Mentor Advanced Verification Methodology SOFTWARE ENGINEERS TLM SoC ARCHITECTS Advanced Verification Methodology VERIFICATION ENGINEERS RTL HARDWARE ENGINEERS 2006 MAPLD International Conference 15 Design Verification Tutorial Key Aspects of a Good Methodology • Automation – Let the tools do the work • Reusability – Don’t reinvent the wheel – Reusability is functionalityand/or protocol-specific – Reuse is critical across projects. across teams. and across tools • Observability – Self-checking is critical – Automate self-checking and coverage tracking – Assertion-based Verification • Controllability – Make sure you exercise critical functionality – Constrained-Random stimulus and formal verification automate the control process • Measurability – If you can’t measure it. you can’t improve it – Tools automate the collection of information – Analysis requires tools to provide information in useful ways – All tools must consistently contribute to measurement and analysis 16 Design Verification Tutorial • Verification Planning and coordination 2006 MAPLD International Conference 8 .

e. gate 2006 MAPLD International Conference 18 Design Verification Tutorial 9 . coverage) • Must interact with design at different levels of abstraction Design: • Describes Hardware • Multiple Abstraction Levels – System.Verifying a Design means… • Showing that a system’s behavior matches its designer’s intent Intent Observations =? Need to express intent Need to observe behavior 2006 MAPLD International Conference 17 Design Verification Tutorial Design vs. Verification Verification: • A software model of the environment • Expresses the intended behavior of the design – Assertions describe intent declaratively – Testbench response checkers and golden models describe intent procedurally • Gathers information to measure progress (i. RTL.

Deconstructing Verification Observe response Control stimulus DUT 2006 MAPLD International Conference 19 Design Verification Tutorial Simulation Verification: The Testbench Scoreboard Golden Model Response Checker TL response Test Controller Coverage Stimulus TL Generator stimulus DUT 2006 MAPLD International Conference 20 Design Verification Tutorial 10 .

Refinement Scoreboard Golden Model Response Checker TL response Test Controller Coverage Monitor Stimulus TL Driver Generator stimulus Abstraction Converters RTL DUT 2006 MAPLD International Conference 21 Design Verification Tutorial Reuse Scoreboard Golden Model Response Checker TL response Test Controller Coverage Monitor Stimulus TL Driver Generator stimulus RTL DUT 2006 MAPLD International Conference 22 Design Verification Tutorial 11 .

Formal Verification: Assertions AVM-compliant assertionScoreboard based monitors enable reuse between simulation and formal verification Test Controller Coverage Golden Model Response Checker TL response Defines the behaviors to check Limits the analysis to valid input behaviors Stimulus Assertions should be used throughout the design to define implementationspecific behaviors to check 2006 MAPLD International Conference Monitor TL Driver Generator stimulus RTL DUT Embedded AVM-compliant assertions can also communicate to the testbench 23 Design Verification Tutorial The Verification Process Functional Specification Verification Plan Simulation Testbench Implementation N Y Done Sufficient Coverage? N Bug Found? Y Assertion Based Verification Constraint Simulator Solver Functional Assertion Coverage Engine Design Implementation 100% Standards based 0-in Formal Debug Coverage-Driven Verification • Testbench Automation • Functional Coverage 2006 MAPLD International Conference 24 Design Verification Tutorial 12 .

come out when they're supposed to? Does it fully support all bus protocols it's supposed to? – Does the design do anything it’s not supposed to do? • Will it recover gracefully if something unexpected happens? • Can I be sure it will only do Y when X happens? – When have I successfully answered the first two questions? 2006 MAPLD International Conference 25 Design Verification Tutorial Number of Tests Required to Cover Targeted Methods Complement Simulation 1000 20% Hotspots: • Arbiters • Bus bridges 100 • Elastic buffers • Clock domain crossing Best Practices Reflected in IP Checker Components 10 Things to Test • ABV and exhaustive formal verification – Complete verification of hotspots – Focus formal verification for largest return-on-investment – Replaces millions of cycles of simulation 2006 MAPLD International Conference 26 Design Verification Tutorial 13 .The Verification Plan • The Verification Plan is a list of questions you need to answer about your design • What information do you need to answer the questions? – Does the design do everything it’s supposed to do? • • • • Does it work (whatever "work" means)? Is it fast enough? When X happens. will it do Y? Do all that goes in .

Simulation May Not Be Enough Some blocks are so important they must be verified exhaustively assert always (A==B) <-> E . gate or transistor N Flops • Assertion = Design Behavior? – Block level runs – Many Algorithms – Exhaustive state space exploration of the block 2006 MAPLD International Conference 28 Pass: Design A = Design B Fail: Design A != Design B Debug shows cones of logic that aren’t equal Property Checking Block A Typically rtl 2I+N States prop (A -> B) assert prop.941 years • Formal and simulation complement each other to provide – – – – Exhaustive verification Advanced bug finding Coverage improvement Interface compliance 27 Design Verification Tutorial 2006 MAPLD International Conference Equivalence vs. gate or transistor N Flops Some Design Change Design B rtl. Property Checking • Design A = Design B? – Chip level runs – Specific Algorithm – Explores equivalency of cones of logic between states Equivalency Checking Design A rtl. A [31:0] E B [31:0] How long would it take to exhaustively verify in simulation? 264 vectors * 1 vector every µs = 584. SVA/PSL/OVL/… Proof: Formal Proof for all input conditions Firing: Some condition violates property Debug gives counter example showing firing Design Verification Tutorial 14 .

Formal Verification PCI Bus PHY PCI Bridge System Interconnect 0 DMA DMA System Interconnect 1 µC Static Formal Verification Exhaustive Ethernet Controller RAM RAM RAM RAM Encryption Engine Powerful formal verification that goes broad and deep SDRAM SDRAM Controller checker corner case simulation test case Dynamic Formal Verification Locally exhaustive 2006 MAPLD International Conference 29 Design Verification Tutorial How to Fill In Coverage Holes Combine formal with simulation to expand coverage Design State Space • Constrained-random testing could miss coverage points • Constructing directed tests to hit deep states infeasible • Depth and complexity of coverage points exceed capacity of static formal • Solution: Combine formal and simulation 2006 MAPLD International Conference – Formal verification from specific simulation states 30 Design Verification Tutorial 15 .

the coverage points are coded in the test itself Functional Coverage and Testbench Automation • With a random test. scenarios cannot be predicted.Total Coverage Model • Functional (specification-based) – Checks that all functions of the design are tested – Created by verification team – Makes sure the design does everything it’s supposed to do Specification on cti sa ran l/T na tio nc Fu rag ve Co – Checks that all corner-cases of the design are tested – Created by designers – Makes sure the design doesn’t do anything it’s not supposed to do 2006 MAPLD International Conference 31 Str uc t ur • In a directed test. – Need to track information about what happened – Support queries to determine if targets were hit – Intent captured by self-checking/ scoreboard Coverage Analysis Modify constraints – Test writer must code each specific scenario to specify intent explicitly – Must be able to predict interesting cases in order to code them – Doesn’t scale well al Co ve rag e • Structural (implementation-based) Implementation Design Verification Tutorial e Coverage Recording Test CR Test 2006 MAPLD International Conference 32 Design Verification Tutorial 16 .

TBA is All About Infrastructure • Scaffolding around the design • All the stuff you need to build and verify a design – Software – Programming-centric view of the intent III IV I II • Specified in the verification plan • Can cost as much or more than the design itself • Efficiency. Reuse. etc are important • Must be built from the groundup 2006 MAPLD International Conference 33 Design Verification Tutorial Verification Engineers Building a Testbench Transaction interfaces Gen Basics Driver DUT Slave Pin interface Scoreboard Monitor Control interfaces Test Intent is captured in test and scoreboard 2006 MAPLD International Conference 34 Design Verification Tutorial 17 .

Building a Testbench Modularity Gen Driver TL DUT DUT Slave Scoreboard Monitor Test Intent is captured in test and scoreboard 2006 MAPLD International Conference 35 Design Verification Tutorial Testbench “Plumbing” Reuse Gen Driver DUT Slave Scoreboard Monitor Test 2006 MAPLD International Conference 36 Design Verification Tutorial 18 .

Testbench “Plumbing” Reuse uProc III IV I II DUT TL Reference Model BlkB Regular interfaces allow for mix-n-match 2006 MAPLD International Conference 37 Design Verification Tutorial SystemVerilog Overview 2006 MAPLD International Conference 38 Design Verification Tutorial 19 .

1a 2004 Co-Design Eratta Synopsys P1364-2005B P1364-2005C 1364-2005 Mentor Novas BlueSpec Eratta Cadence Jasper 1800-2005 Eratta 2006 MAPLD International Conference 40 Design Verification Tutorial 20 .1 2003 SV3.0 2002 SV3.Language Explosion Gate Era HILO System HILO Verilog Verilog 2001 SuperLog Vera e SystemC Sugar PSL System Verilog HDL Era Verification Era VHDL ‘87 VHDL ‘93 VHDL 2002 VHDL 200x 1980 1990 2006 MAPLD International Conference 39 2000 Design Verification Tutorial 1364 and P1800 1364-2001 P1364-2005A ? Eratta SV 3.

while..) Hardware concurrency design entity modularization Switch level modeling and timing Gate level modeling and timing ASIC timing Verilog 95 supplies RTL and basic testbench features 2006 MAPLD International Conference 42 Design Verification Tutorial 21 .The Accellera Assertions Process ForSpec Temporal e Sugar CBV Superlog DAS OVA • SystemVerilog is the single Assertions Solution FVTC SV Refinement (SVA) Accellera Unified Assertions 2006 MAPLD International Conference 41 Design Verification Tutorial SystemVerilog Semantics What is the origin of the IEEE 1800 SystemVerilog Semantics? Event handling 4 state logic Basic datatypes (reg. if.. wire) Basic programming (for.

enums Signed numbers Basic programming (for. break.. wire) Gate level modeling and timing ASIC timing 2006 MAPLD International Conference 44 Design Verification Tutorial 22 . continue. +=.) pointers Structs & Unions Void type Further programming (do while. ++. etc) Automatic variables Event handling 4 state logic Hardware concurrency design entity modularization Switch level modeling and timing Basic datatypes (reg.. if.) pointers Structs & Unions Void functions Further programming (do while.. break. if. wire) Gate level modeling and timing ASIC timing 2006 MAPLD International Conference 43 Design Verification Tutorial Verilog 2001 Semantics HDL lot of V adds a g 2001 ll lacks ut sti Verilo nality b tructures functio d data s e advanc Architecture configuration Dynamic generation of hardware multi-D arrays Dynamic memory allocation Advanced data structures. --. while.C Language Semantics extra s ome e has s g featur e C min ar gram all hardw pro cks h as but la epts suc elism conc d parall g an timin Dynamic memory allocation multi-D arrays Advanced data structures enums Signed numbers Basic programming (for. continue. ++. while. +=. --. etc) Automatic variables Event handling 4 state logic Hardware concurrency design entity modularization Switch level modeling and timing Basic datatypes (reg..

++.0 adds da d ructures an st ions for assert design Simple assertions multi-D arrays Dynamic memory allocation Advanced data structures. etc) Automatic variables Event handling 4 state logic Hardware concurrency design entity modularization Switch level modeling and timing Basic datatypes (reg. --. break.SV 3. enums Signed numbers Basic programming (for. wire) Signed numbers Basic programming (for. break.. wire) Gate level modeling and timing ASIC timing Packed structures 2006 MAPLD International Conference 45 Design Verification Tutorial SV 1800 Semantics Classes with methods and inheritance Associative arrays Sparse arrays Coverage monitoring Polymorphic directed random generators Semaphores Queues and lists •fifo modeling •testbenches o Interface protocol specification eril des access control mV interface methods teand ovi g r Sys 800 p ed E1 vanc and Architecture d Dynamic memory allocation pointers IEE a n Simple assertions s configuration atio ature e i fi c ver ling f multi-D Advanced data structures Void type de Dynamic generation arrays Records.) Structs & Unions Void type Further programming (do while..0 Semantics Interface protocol specification access control and interface methods Architecture configuration Dynamic generation of hardware Process spawning Protocol checkers temporal assertions pointers og SystemVeril ta 3. enums mo of hardware Automatic variables Event handling 4 state logic Hardware concurrency design entity modularization Switch level modeling and timing Basic datatypes (reg. while.) Strings Gate level modeling and timing ASIC timing Protocol checkers temporal assertions Process spawning Unions Further programming (do while. if. while. +=. continue. etc) Coverage & Assertion API C interface Packed structures 2006 MAPLD International Conference 46 Design Verification Tutorial 23 ... --. if. +=. continue. ++.

Assertion API and Coverage API Defined by Accellera.SystemVerilog Components Te Ve s t r ilo be g nc h Transaction-Level Full Testbench Language with Coverage Verilog Testbench IEEE Verilog 2005 Design Abstraction: Interface semantics. abstract data types. The Assertion Language Standard for Verilog og n ril tio Ve ser s A 2006 MAPLD International Conference SystemVerilog Technical Committees IEEE P1800 Structure Structure correlates to SystemVerilog components IEEE P1800 SystemVerilog WG Chair: Karen Pieper og ril gn Ve esi D SV-EC (testbench) Direct C interface.Dennis Brophy IEEE 1364 Features are now driven by the IEEE 1800 technical committees: Language issues in SV-BC C-Interface issues in SV-CC P1800 Errata Sub-WG Champions SV-AC (assertions) 48 SV-BC (design) 2006 MAPLD International Conference SV-CC (DPI) Design Verification Tutorial 24 . abstract operators and expressions I AP e & ac PI erf D t In Advanced verification capability for semiformal and formal methods. Completed and standardized under the IEEE 47 Design Verification Tutorial Chair .Johny Srouji Vice chair – Shrenik Mehta Secretary .

Methodology is Not Language • Languages and tools must support a methodology – The language does not define the methodology • The Methodology ties different technologies together effectively – Assertion-Based Verification (ABV) – Testbench Automation (TBA) • Constrained-Random Verification (CRV) – Coverage-Driven Verification (CDV) • Functional Coverage • Code Coverage – Transaction-Level Modeling (TLM) 2006 MAPLD International Conference 49 Design Verification Tutorial Methodology/Language Matrix TBA Legend: Constrained Random TLM ABV RTL Design SystemVerilog Functional Coverage SystemC PSL Verilog VHDL Use the right language for the right job 2006 MAPLD International Conference 50 Design Verification Tutorial 25 .

Broad Industry Support for SystemVerilog VhdlCohen Training WSFDB Consulting 2006 MAPLD International Conference 51 Design Verification Tutorial SystemVerilog Design Constructs ? 2006 MAPLD International Conference 52 Design Verification Tutorial 26 .

logic signed [31:0] i. Verilog reg and integer type bits can contain x and z values Equivalent to these 4-valued SystemVerilog types These SystemVerilog types have two-valued bits (0 and 1) logic a. SystemVerilog bit a. int i.SystemVerilog Type System SystemVerilog Types Singular real c/handle integral int/integer bit/reg/logic Packed struct/union Packed array integral enum Unpacked array Aggregate Unpacked struct/union SystemVerilog Types class Stongly typed for userdefined types 2006 MAPLD International Conference 53 Design Verification Tutorial 2 State and 4 State Data Types Verilog SystemVerilog SystemVerilog reg a. If you don't need the X and Z values then use the SystemVerilog bit and int types which MAKE EXECUTION FASTER 2006 MAPLD International Conference 54 Design Verification Tutorial 27 . integer i.

unused Don’t get them mixed up a0 a1 a2 a3 bit [3:0] p. logic. 55 reg o. and aa (o. always @inv Frame = ~Frame. SystemVerilog reg o. b). wire o. Design Verification Tutorial 2006 MAPLD International Conference Packed And Unpacked Arrays unpacked array of bits packed array of bits 1k 16 bit unpacked memory bit a [3:0]. a. and aa (o. Packed indexes can be sliced bit [15:0] [1023:0] Frame.Easing the reg / wire Duality • Moving from RTL to an instance based description • Replacing regs with wires • Bit. a. and reg types can be assigned as regs or driven by a single instantiation Verilog RTL Gate reg o. b). memory[i] = ~memory[i]. memory[i] [15:8] = 0. always_comb o = a & b. 1k 16 bit packed memory Can operate on entire memory 2006 MAPLD International Conference 56 Design Verification Tutorial 28 . p3 p2 p1 p0 bit [15:0] memory [1023:0]. always @(a or b) o = a & b.

u. bit [23:0] addr. } u_type. like in C structs and unions can be assigned as a whole int real Can be passed through tasks/functions/ports as a whole can contain fixed size packed or unpacked arrays 2006 MAPLD International Conference 58 Design Verification Tutorial 29 .f = 3. $finish(0). opcode. $display("n=%d".n). u_type u.n = 27. u. initial begin u. // anonymous structure Like in C but without the optional structure tags before the { typedef struct { bit [7:0] opcode.opcode = 1. real f. // named structure type instruction IR.Structures struct { bit [7:0] bit [23:0] } IR.f). // define variable // set field in IR 2006 MAPLD International Conference 57 Design Verification Tutorial Unions typedef union { int n. } instruction. $display("f=%f". IR.u. end union provide storage for either int or real again.1415. addr.

iValid = Entry[`Valid] 2 1 0 32 0 Valid Tag Addr 24 23 1615 Valid Tag Address 0 packed struct 2006 MAPLD International Conference 59 Design Verification Tutorial Packed Unions • Many views for same data typedef union packed { ppacket_t f.Tag. upkt[31:0] = packet. always_comb begin upkt.qbyte[7:4] = packet. iValid = Entry. byte Tag. iAddr = Entry[`Addr].f.Packed Structures Represents bit or part selects of vectors struct packed { bit Valid. end 2006 MAPLD International Conference 60 Design Verification Tutorial 30 .dst_addr.payload. iTag = Entry.Addr. } upacket_t.src_adr = node_id.Valid packed struct may contain other packed structs or packed arrays unpacked struct reg [24:0] Entry. bit [15:0] Addr. src_addr 11 10 9 8 7 dst_addr 6 5 4 3 payload 2 1 0 95:0 upacket_t upkt. iAddr = Entry. upkt. bit_t [11:0][7:0] qbyte. } Entry. `define Valid 24 `define Tag 23:16 `define Addr 15:0 iTag = Entry[`Tag].

0) shortint' {8’hFA. gold=4’h5 enum {bronze=3. col = yellow. Colors col. b. gold=5 Syntax error silver=4’h4. B = Packed_s’(A). a=2*3=6 col=3 b=3+1=4 2006 MAPLD International Conference 61 Design Verification Tutorial Type Casting int'(2. bit [15:0] f2. green. c. Array ⇔ Structure typedef struct { bit [7:0] f1. … A = Unpacked_s’(B). yellow. gold} medal. light2. bit [7:0] f3[0:5]. gold} medal. typedef struct packed { bit [15:0][0:2] f1. Packed_s B. b = col + green. bit [7:0] f2. yellow. green} light1. 2006 MAPLD International Conference 62 Objects must have identical bit size A f1 f2 f30 f31 f32 f33 f34 f35 B f10 f11 f12 f2 Design Verification Tutorial 31 .Enumerated Data Types enum {red. a = blue * 3. enum {a=0. silver.0 * 3. blue. } Unpacked_s. typedef enum {red. white. enum {bronze=4’h3. d=8} alphabet. Unpacked_s A. } Packed_s. 8’hCE} 17 A data type can be changed by using a cast (‘) operation ' (x – 2) • Any aggregate bit-level object can be reshaped – Packed ⇔ Unpacked. anonymous int type silver=4. silver. b=7. black} Colors. integer a.

bit_t [Memory::ADDR_SIZE-1:0] dram_adr. package Protocol. if (foo == 22) break. parameter DATA_SIZE = 32. … import Protocol::*. import Protocol::*. data types & functions • Facilitate better organization and reference to global collateral • Prevent collision of names in global scope bit_t [Protocol::ADDR_SIZE-1:0] tmp_address. typedef struct { addr_t src_addr. … Blocking Assignments as expressions Auto increment/ decrement operators continue starts next loop iteration works with: for while forever repeat do while break exits the loop if ( (a=b) ) … while ((a = b || c)) x++. end while (foo != 0). typedef bit_t [DATA_SIZE-1:0] data_t. addr_t dst_addr data_t payload. a =?= b a !?= b 63 Extra parentheses required to distinguish from if(a==b) Wildcard Comparisons X and Z values act as wildcards 2006 MAPLD International Conference Assignment Operators Semantically equivalent to blocking assignment Design Verification Tutorial Re-Use • Packages facilitate sharing of parameters. return ^i. s &= mask. f <<= 3. endfunction endpackage bit_t [Protocol::ADDR_SIZE-1:0] node_adr. 64 Design Verification Tutorial 2006 MAPLD International Conference 32 .Familiar C Features In SystemVerilog do begin if ( (n%3) == 0 ) continue. bit_t [ADDR_SIZE-1:0] tmp_address. if (--c > 17) c=0. function automatic bit_t EvenParity32 (bit_t [31:0] i). parameter ADDR_SIZE = 32. a += 3. typedef bit_t [ADDR_SIZE-1:0] addr_t. } packet_t.

o_pkt.q(o_pkt)..q(q). endmodule packet_t i_pkt.d(d)..clock(clock)).Re-Use • Data Type parameter extends generic capabilities – For modules module dff #(parameter type T = bit_t) (output T q. dff #(. – Create identifiers `define IDENT(arg) inst_``arg Source: dff #(.q(q). Expanded: dff #(...d(d). always_ff @(posedge ck) q <= d. bit_t ck.. input T d. input ck).clock(clock)). • A must when using unpacked structs & arrays • Useful for creating generic code localparam type T = type(i_pkt). • Extends utility of macros to save typing and promote uniformity 2006 MAPLD International Conference 66 Design Verification Tutorial 33 .T(t_bit))`IDENT(o)(.d(i_pkt). 2006 MAPLD International Conference 65 Type operator alleviates need for referring to data type by name Design Verification Tutorial Macros • SystemVerilog improves macros – Insert macro argument into a string `define ATTR(arg) (*myattr=`"arg`"*) Source: `ATTR(decl) bit_t flag.. T tmpfifo[7:0]. always_comb tmpfifo[0] = i_pkt. Expanded: (*attr="decl"*) bit_t flag.T(t_bit)) inst_o (.ck(ck)).T(packet_t)) ff0 (.

SystemVerilog Interfaces ? 2006 MAPLD International Conference 67 Design Verification Tutorial Interconnect: The Old Way module memMod(input logic req. logic rdy). logic [1:0] mode.mode). inout logic [7:0] data.addr. logic rdy. logic start.start. bit clk. logic[1:0] mode. logic[1:0] mode).clk. bit clk = 0. req.gnt.gnt. logic start.rdy). cpuMod cpu(clk.start. addr. always @(posedge clk) gnt <= req & avail. module top.mode.gnt.data. endmodule Top clk req start gnt rdy mode[1:0] addr[7:0] data[7:0] CPU Mem endmodule 2006 MAPLD International Conference 68 Design Verification Tutorial 34 . output logic gnt. logic[7:0] addr. logic[7:0] addr.rdy.data. output logic req. logic req.rdy.data. inout logic[7:0] data.start. logic [7:0] addr. logic gnt. endmodule module cpuMod(input bit clk. memMod mem(req.

Interconnect: Using Interfaces interface simple_bus. endtask task read(output data_type d). while (data_valid !== 1) @(posedge clk). logic [7:0] addr. i++) @(posedge clk) begin if (i==0) data_start <= 1. in interface bit clk = 0. clk). logic [31:0] data_bus. endmodule Top clk Refer to intf signals module cpuMod(interface b. task write(input data_type d). i++) @(negedge clk) d[i] <= data_wire. logic avail.rdy. data_wire = d[i]. input bit clk). i <= 31. for (int i = 0.req & avail. data_bus <= d. endtask endinterface 2006 MAPLD International Conference 70 Design Verification Tutorial 35 . logic req. endmodule interface instance Connect interface Use interface keyword in port list module memMod(interface a. data_valid <= 1. @(posedge clk) data_bus <= 'z. logic data_start=0. else data_start <= 0. input bit clk). i <= 31.gnt.clk(clk)). endtask endinterface Serial Interface interface serial(input bit clk). memMod mem(sb_intf. d = data_bus.b(sb_intf). logic [1:0] mode. logic data_valid=0. . for (int i = 0.data. end endtask task read(output data_type d). logic start. while (data_start !== 1) @(negedge clk). @(posedge clk) . cpuMod cpu(.gnt <= a. logic data_wire. always @(posedge clk) a. task write(input data_type d). endinterface: simple_bus Bundle signals module top. simple_bus sb_intf. endmodule CPU sb_intf Mem 2006 MAPLD International Conference 69 Design Verification Tutorial Encapsulating Communication Parallel Interface interface parallel(input bit clk). data_valid <= 0.

Module inherits . endtask:masterRd module top.b(sb_intf)). bit clk. send s(clk...slaveRd. channel). method from endmodule interface send receive parallel serial interface 2006 MAPLD International Conference 71 Design Verification Tutorial Using Tasks in an Interface interface simple_bus(input bit clk).write(d). logic req. bit clk. task masterRd(input logic[7:0] raddr). interface i). data_type d. parallel channel(clk). channel).data. logic [7:0] addr. communication i. channel). in Interface endtask:slaveRd endinterface: simple_bus module memMod(interface a). Called From endmodule module cpuMod(interface b)... receive r(clk. always #100 clk = !clk. simple_bus sb_intf(clk). all Interface Methods can be called from any module that instantiates the Interface What if we want to restrict “slave” modules from calling the masterRd task? Intantiating Module 2006 MAPLD International Conference 72 Design Verification Tutorial 36 . always @(a. channel). serial channel(clk).start) Interface Method a.. . logic start. cpuMod cpu(. bit clk = 0. memMod mem(sb_intf).rdy.gnt. send s(clk. endmodule Communication task slaveRd. endmodule By default. always #100 clk = !clk. receive r(clk.. logic [1:0] mode. typedef logic [31:0] data_type. Task Encapsulated . module send(input bit clk.Using Different Interfaces typedef logic [31:0] data_type.. ..

slave a)..gnt <= a.addr. logic avail.masterRead(raddr). modport slave(input req.mode..start) if(a. enum {read. tasks inout data..clk) if(instr == read) b. output gnt.Modports: Importing Tasks From an Interface interface simple_bus(input bit clk). cpuMod cpu(sb_intf. . task masterWr(input logic[7:0] waddr)). task slaveWr()). //.. . Import into module that uses the modport Modules using modport initiator(input gnt.start. import task slaveRd().start.clk) a. logic [7:0] raddr.rdy. memMod mem(sb_intf).. endmodule Only has access to slaveRd/slaveWr tasks module omniMod(interface b). always @(a.. logic req. inout data.. endmodule:omniMod module top.masterWrite(raddr). logic [1:0] mode. import task masterRd(input logic[7:0] raddr).slaveRead.. endmodule module cpuMod(interface b). else b. logic [7:0] addr.gnt. endmodule Only has access to masterRd/Wr tasks Has access to all tasks and signals 2006 MAPLD International Conference 74 Design Verification Tutorial 37 .req & avail. logic start. else a. can only call these mode. always @(posedge b. initiator modport output req.data.addr.slaveWrite.mode[0] == 1'b0) a. simple_bus sb_intf(clk). omniMod omni(sb_intf).clk. .clk. logic clk = 0.rdy. endinterface 2006 MAPLD International Conference 73 Design Verification Tutorial Modports: Using Imported Tasks module memMod(interface.write} instr.initiator).rdy. always @(posedge a.

Tasks & Functions in Interfaces • Allows More Abstract Modeling – Transaction can be executed by calling a task without referring to specific signals – “Master” module can just call the tasks • Modports Control Sharing of Methods – Methods defined outside a module are “imported” into a module via modport – Effectively gives “public” and “private” methods based on whether the module uses the interface or the modport 2006 MAPLD International Conference 75 Design Verification Tutorial SystemVerilog Assertions 2006 MAPLD International Conference 76 Design Verification Tutorial 38 .

$time). end begin repeat (2) @(posedge clk). always @(posedge req) Verilog begin repeat (1) @(posedge clk). disable pos_pos. fork: pos_pos begin @(posedge ack) $display("Assertion Success". $display("Assertion Failure". endproperty as_req_ack: assert property(req_ack).$time). end join end // always 0 1 2 3 4 5 req ack Example intended behavior HDL Assertion 2006 MAPLD International Conference 78 Design Verification Tutorial 39 . @(posedge clk) req ##[1:3] $rose(ack).What is an Assertion? A concise description of [un]desired behavior 0 req ack Example intended behavior 1 2 3 4 5 “After the request signal is asserted. the acknowledge signal must come 1 to 3 cycles later” 2006 MAPLD International Conference 77 Design Verification Tutorial Concise and Expressive SVA Assertion property req_ack. disable pos_pos.

ABV Improves Time-To-Bug Design Under Test Reference Model = Lurking bugs: found late in the design cycle = • ABV detects bugs at the source. saving valuable debug time • ABV detects bugs missed by top-level test benches 2006 MAPLD International Conference 79 Design Verification Tutorial ABV Improves Time-To-Coverage Design Under Test Reference Model ? • ABV reveals internal structural coverage • ABV produces actionable metrics to improve coverage 2006 MAPLD International Conference 80 Design Verification Tutorial 40 .

desired or undesiredboolean events • How are related over time • True or False expression Design Verification Tutorial 2006 MAPLD International Conference 82 41 . endproperty PA: assert property (s1).SV Assertions Flexible Use Model module arb (input req. ack. …). @(posedge clk) ((reset == 1) && (mode == 1) && (st == REQ) && (!arb) && (foo)) |=> s1. endprogram Bind arb arb_props arb1 (rdy. property s1. (req && !gnt)[*0:5] ##1 gnt && req ##1 !req . endmodule program verify_arb. cover) Properties Sequences (Sequential Expressions) Boolean Expressions • Checker packaging • Assert. 2006 MAPLD International Conference 81 Design Verification Tutorial • Assertions can be embedded directly in verilog modules • Assertions can be coded in external files and bound to module and/or instance SV Assertion Language Structure Assertion units Directives (assert. property p1. cover • Specification of behavior. gnt …). assume. endproperty DA: assert property (p1).

c b a clk @(posedge clk) a ##1 b ##4 c ##[1:5] z. endsequence 2006 MAPLD International Conference 83 Design Verification Tutorial Assertions in Formal and Simulation • Fundamental requirement for common semantics across tools • Simulation is event-based – Subject to race conditions clk d Q=? clk d d wins Q=1 clk d clk wins Q=0 • Formal (and Synthesis) are cycle-based – Clock always wins In cycle semantics. data is sampled at the beginning of a timestep This is equivalent to sampling the data at the end of the previous timestep 2006 MAPLD International Conference 84 Design Verification Tutorial 42 .Sequential Regular Expressions • Describing a sequence of events – Boolean expressions related over time • Sequence Concatenation – Temporal delay • Concatenation character is ##n or ##[n:m] z sequence atest.

endsequence • Sequences Can Be Built From Other Sequences sequence s2.Sequences Encapsulate Behavior • Can be Declared sequence <name>[(<args>)]. [@(<clocking>)] <sequence>. endsequence • Operations to compose sequences – and. @(posedge clk) c ##1 d. endsequence sequence s1(a. or. throughout 2006 MAPLD International Conference 85 Design Verification Tutorial Sequence Examples Expression Range Basic Sequence a b c …z a b b b c a b b b b c a ##1 b[*3:4] ##1 c Expression Non-Consecutive “Counting” Repetition a ##1 b ##1 c …##1 z Sequence with Delay a b c a …b …b …c a ##1 b ##2 c a ##1 b[=2] ##1 c Expression Repetition Expression “Goto” Repetition a b b b c a ##1 b[*3] ##1 c a …b …b c a ##1 b[->2] ##1 c 2006 MAPLD International Conference 86 Design Verification Tutorial 43 . within. @(posedge clk) s1(e. intersect. @(posedge clk) a[*2] ##3 b. endsequence sequence s3.f) ##1 s2.b).

b. reset_n).|=>) in properties property rule1 (a. sequences and subordinate properties over time (temporal relationships) – Statements of design. And. endproperty • Properties specify relationships between boolean expressions. Conditional (if else) – Recommend use of implication operators (|->. protocol. rst_n). @(posedge clk) disable iff (!rst_n) a |-> b ##1 c. endproperty assert property rule1 (start. c. Or. [@(<clocking>)] <property_expr>. 2006 MAPLD International Conference 88 Design Verification Tutorial 44 . block or interface behavior over time • Properties can be named and parameterized • Properties can contain reset conditions (disable iff) – Evaluation of property is disabled • Properties have their own operators – Implication (same or next cycle). we. Not.matched ##1 s3 2006 MAPLD International Conference 87 Design Verification Tutorial Properties property <name>[(<args>)]. burst.Multiple Clock Support • Event controls must be specified for each subsequence Multi-Clock Sequence Concatenation s2 s1 @(clk1) s1 ##1 @(clk2) s2 Multi-Clock Sequence Matching s2 s1 s3 s1 ##1 s2.

Property implication sequence_expr |-> [not] sequence_expr sequence_expr |=> [not] sequence_expr • |-> is overlapping implication • |=> is non-overlapping implication same as: sequence_expr ##1 `true|-> [not] sequence_expr • Most commonly used to attach a precondition to sequence evaluation 2006 MAPLD International Conference 89 Design Verification Tutorial SV Assertion Directives • assert: Verify that a property holds (matches) assert property (p1)action_block. action_block ::= [statement] [else statement] – Action block • Executes in reactive region • Pass statement executes whenever property evaluates true else failure statement executes – $error is called if fail statement is absent – Recommend use $error instead of $display • cover : Did a property hold (non-vacuously) at least once cover property (p1)(statement_or_null). – Statement executes for each match of property – Can cover a sequence (Recommended) 2006 MAPLD International Conference 90 Design Verification Tutorial 45 .

FSMs • Declarations • Key Operations – Put arithmetic overflow on arithmetic ops – Guard all module I/O – Corner cases • Make sure test exercises difficult scenarios • Make sure illegal situations are handled correctly • Specify environment assumptions – What other blocks are doing – What the testbench should be doing – Avoid debugging false-negative testbench problems 2006 MAPLD International Conference 91 Design Verification Tutorial SystemVerilog Verification Features 2006 MAPLD International Conference 92 Design Verification Tutorial 46 .Strategies for Adopting ABV • Specify design intent – What I thought I designed • Identify high-level elements in your blocks: – FIFOs. Memories. Arbiters.

Arrays • Dynamic sized arrays can be defined – Uses the new[ ] operator to size or re-size at runtime int mymemory []. etc. // clear the dynamic array add 4 new elements – Dynamic arrays are always unpacked 2006 MAPLD International Conference 93 Design Verification Tutorial Associative Arrays • Indexed by content – Useful for modeling sparse memories. look-up tables. mymemory = new[64]. event event_list[MyClass]. associative array of ints indexed by strings associative array of ints unspecified index type associative array of events indexed by MyClass 2006 MAPLD International Conference 94 Design Verification Tutorial 47 .delete. dynamic unpacked array create 64 element array double array size int howbig = size(mymemory). preserve existing content mymemory. datatype array_id[index_type]. mymemory = new[size(mymemory) + 4] (mymemory). int int_table[*]. associative array of ints indexed by ints int int_index_list[int]. mymemory = new[128](mymemory). int string_index_list[string].

Associative Arrays • Indexed by unspecified index (*) – The array can be indexed by any integral data type – 4-state index values containing X or Z are invalid – The ordering is unsigned numerical (smallest to largest) • Indexed by string: – Indices can be strings or string literals of any length – An empty string “” index is valid – The ordering is lexicographical (lesser to greater) • Indexed by class – Indices can be objects of that particular type or derived from that type – A null index is valid – The ordering is arbitrary but deterministic 2006 MAPLD International Conference 95 Design Verification Tutorial Queues • Analogous to variable-sized unpacked array – Grow and shrink automatically – Constant time access to the queue’s elements – Insertion and removal at the beginning and end supported – Elements are identified by an index • 0 represents the first • $ the last • Can be manipulated like arrays 2006 MAPLD International Conference 96 Design Verification Tutorial 48 .

What if you miss something? • Injecting randomness exposes corner cases • Multiple adoption strategies – Basic step: call directed tests in random order • Can’t assume everything happens out of reset – Enhance directed tests to randomize more than just data – Build full CRV environment from scratch • All strategies require functional coverage Let the Tool Find Cases You Haven’t Thought Of 2006 MAPLD International Conference 98 Design Verification Tutorial 49 . Constrained-Random • Directed tests exercise a specific scenario – You direct the test – You explicitly orchestrate the interactions – It’s a random world. 2h’ff}.a.delete. – Can be bounded by specifying the right index int q16int [$:15].etc. – Can be initialized in declaration byte datavalues [$] = ’{2h’00. // delete first entry q[0:$-1]. // delete last entry {q[0:n-2]. // insert a at q[n] – Built-in methods for push.Queues • Declaration – Default size is unbounded int channel [$].insert.pop. // queue limited to 16 integers – Can be manipulated via array/concatenation syntax q q q q = = = = q[1:$].q[n:$]}. //delete nth entry {q[0:n-1]. 2006 MAPLD International Conference 97 Design Verification Tutorial Directed vs.q[n:$]}.

27. the scenario exercised can be randomized as well – Randomly perform reads and writes with data and protocol mode dependent on address range 2006 MAPLD International Conference 99 Design Verification Tutorial Random Stability • The Random Number Generator (RNG) generates a pseudo-random sequence of numbers Changing mySEED allows new int A. $display(A).Terminology • Pseudo-Random Data Generation – Using pseudo-random algorithms to generate “random” (but deterministic) numbers • Directed Random Testing – A directed test in that uses pseudo-random numbers for parameters/data/etc. 3.… Each process has its own statically-calculated seed B stream is now independent of A and vice-versa 100 Design Verification Tutorial 50 . $display(A). repeat(5) begin A = $urandom. end end int A. initial begin A = $urandom(‘mySEED). B = $urandom. $display(B). 41. 41. end 2006 MAPLD International Conference RNG sequence for each run Each run yields the same values: A = 6. 35. 27 B “steals” values from the RNG stream: A = 6. end initial repeat(5) begin B = $urandom. – Write random data to a random address – Read back from same address and compare • Constrained-Random Testing – Random numbers are bound by arithmetic relationships to other variables – By randomizing high-level data types. initial repeat(5) begin A = $urandom.

Randomization Strategies • Depends on your existing strategy and your background • Procedural randomization – Good for enhancing block-level directed tests – Doesn't require a lot of "software" knowledge – Limited reuse Procedural tests Directed Tightly-constrained "random" test Layer constraints via Inheritance randsequence randomize…with More powerful block-level tests Constrained Random Declarative tests based on OOP • Declarative (object-oriented) randomization – "Knobs" are built into verification infrastructure – Requires investment to take advantage of powerful reuse capabilities 2006 MAPLD International Conference 101 Design Verification Tutorial What to Randomize? • Control – instructions – operations – device configuration • Data – – – – addresses packets (src/dst. payload) parameters transaction types • Key is to create constraint sets that thoroughly explore relevant aspects of the design state-space • Parameterized constraints allow scenarios to be tweaked on the fly • Time – clock cycles between events – how long to run test These aspects of a test can be randomized procedurally. or via Object-Oriented mechanisms • Error injection – Make sure the dut responds correctly 2006 MAPLD International Conference 102 Design Verification Tutorial 51 .

Read.Transaction-Based Verification Interacting with the Design Test Transactor Config set_baud(9600).0x04). BFM/ Transactor DUT Pin wiggles • Test interacts with design via transactors – Transactors convert across abstraction layers • TBV keeps test focused on what should happen – Isolates test from low-level implementation changes – Allows randomization of higher-level operations – Captures design intent in a more natural form • Important concept whether using OO or not 2006 MAPLD International Conference 103 Design Verification Tutorial Error Injection Test Inject tx-level errors here Transactor Inject pin-level errors here BFM/ Transactor To Scoreboard High-level transaction descriptor DUT Config Read. Pin wiggles • Don’t build all possible errors into the transaction descriptor – Makes it too big – Not reusable • Inject errors appropriate to the downstream abstraction level of the transactor • Control ports and callbacks let the test coordinate errors – Don’t forget to let your scoreboard know when errors are expected 2006 MAPLD International Conference 104 Design Verification Tutorial 52 . write(0xA0. Write etc. Write etc.

X ≤ Y ≤ Z Find the set of values that meet the given constraints Randomly pick solutions Z Y X 2006 MAPLD International Conference 105 Design Verification Tutorial Computing the Solution Space S o l u t i o n s # # # # # # 21 1d 04 0f 14 07 26 22 0e 28 20 1f 32 91 d0 60 d1 80 X Y Z 8 8 8 255.0.216 42*28+8 = 2.048.512 **224 = 2.255 DUT Z Constraint Y < 42 X≤Y≤Z X[7:4]═Z[3:0] Number of Solutions Y possible solutions that satisfy all constraints 12.0 53 . Y.796.202 24*28+4+4 = 220 1.0 2006 MAPLD International Conference 106 X Design Verification Tutorial 255.777.752.What is a Random Constraint Solver? • • • • Declare a set of random variables – X.477 Unconstrained 28+8+8 = 224 = 16.576 0.255.0. Z Declare a set of constraints – Y < 42.

d) pairs will be (0. s and d are determined together • Possible 9 values in the solution space are : if s = 0 if s = 1 d = 7 or 6 or 5 or 4 or 3 or 2 or 1 or 0 d = 0 – The (s.Random Variables and the Solution Space A 256 values 2<A<9 3.3). (1.4).0). constraint cons { s -> d == 0.} • Constraint reads if “s” is true then d is 0 – as if “s” determines “d” – Actually. rand bit [2:0] d.1). … (0.4.2).(0.5).1).(0.1).0) – Probability of picking s = 1 is 1 in 9 • To keep the solution space the same and pick “s” true with a probability of 50% constraint cons_plus {solve s before d.3).5.3). (1. (0.2).6. (0.0). (0.} 2006 MAPLD International Conference 108 Design Verification Tutorial 54 . -> is bidirectional.8 6 values 8 bit random variable Small set of constraint relationships 16 bit random variable Large Small set of constraint relationships (0. (0.7. (2. … 256 values 32640 values A ==B A< B A 256 values B 256 values • Need to be aware of the complexity of constraints 2006 MAPLD International Conference 107 Design Verification Tutorial Solution Space • Implication operator -> rand bit s.6).(0.(0. (1.2).4).2).7) and (1. (1. (0.

C: do_test3. B: do_test2. D: do_test4. // 10% probability // weight is 3.Random Weighted Case • SystemVerilog allows for a case statement that randomly selects one of its branches • Each case can have a specific weight which can be numeric or an expression int a. A: do_test1. 101. 99. randcase 1 : c = a : c = a-b : c = 5 : c = endcase end 12. 20.c.b. 10% probability // 50% probability – Number of choices is static – Relative probability of each choice can be dynamic 2006 MAPLD International Conference 109 Design Verification Tutorial Sequences • Implemented in a randsequence() block • Functionality of the sequence block described as a grammar – Composed of rules and productions – Productions are classified as terminal or non-terminal – Stream is composed by streaming items This is a procedural statement randsequence() S1: A B S2. S2: C | D := 2. endsequence Start Sequence S1 A B P=1 C ? P=2 D Start Sequence S2 2006 MAPLD International Conference 110 Design Verification Tutorial 55 . initial begin a = 3. b = 2. 30% probability // weight is 1.

case.data). if(addr<16) data[7] == 1’b1. do_read(addr. assert(data == exp[addr]).i++) begin addr = i. repeat. do_write(addr. end for(i=0.i<32.data).Generating Test Scenarios • Random Sequences specify a set of test scenarios that make sense – Multiple control mechanisms for production statements • if. addr_list = ‘{addr_list. assert(data == exp[i]). do_write(addr.i<32. end end • SystemVerilog adds in-line constraint initial begin specification for(i=0.i<32. do_read(addr.data) with {addr < 96.i++) begin addr = pick_addr(addr_list). if(addr < 16) data[7] = 1’b1..else.addr}.i++) begin addr = i. randsequence is easily added to existing directed tests 2006 MAPLD International Conference 111 Design Verification Tutorial Specifying Constraints initial begin for(i=0.i<32. data = $random().}. exit – Control mechanisms and weights use expressions • Can change dynamically during a test • Allow test to react to DUT responses or other criteria • Each “walk” through creates a different test scenario • Each scenario can be as atomic as you want it – Explicit directed test – Execute CPU instruction (generate meaningful code structures) – Send packet of explicit type (send valid stream of random packets) • Since it's a procedural statement. end for(i=0. end end 2006 MAPLD International Conference 112 Design Verification Tutorial 56 .data).data).i++) begin randomize(addr. return.

and data-oriented coverage • Must be able to assemble a verification infrastructure to gather the information to answer the questions 2006 MAPLD International Conference 114 Design Verification Tutorial 57 .SystemVerilog Testbench Automation 2006 MAPLD International Conference 113 Design Verification Tutorial Functional Coverage Analysis • Coverage analysis depends on what you’re looking for – Have I exercised all transaction types on the bus? • Control-Oriented (in bus monitor) – Have I generated packets of every type/length • Data-Oriented (in testbench) – Did I successfully model all transaction types to every interesting address range? • Combination of control.

and Control-oriented functional coverage work together – Properties detect the temporal activity – Covergroup captures transaction attributes – SystemVerilog supports communication between them 2006 MAPLD International Conference 115 Design Verification Tutorial Data-Oriented Coverage Recording 3 2 3 2 1 1 4 3 2 1 2 a 1 2 1 3 5 7 6 5 4 3 2 1 4 Transition Coverage: How many times did a==2 after a==1? Simple Coverage: How many times did a==1? • Records the values of variables at a particular simulation time • Usually captured by the testbench • Many possibilities for analysis 2006 MAPLD International Conference 116 Design Verification Tutorial 58 .• Data-oriented functional coverage – covergroup SystemVerilog Provides Coverage Tools – Records data values at interesting times • Control-oriented functional coverage – cover sequences/properties – Concise description of temporal behaviors • Data.

int dly. kind. endgroup mycov covgrp = new.} coverpoint dly {bins d[] = {[1:4]}. addr range (8 bins) Transaction type vs. coverpoint addr {bins a[4] = {[0:31]}. covergroup mycov @smp_event. delay (8 bins) • Automatically samples data values at specified time/event • Specifies “bins” to count number of samples in a particular value range • Gives information about the recorded data values – You have to know what questions you want to answer – Build your covergroup to answer the questions 2006 MAPLD International Conference 118 Design Verification Tutorial 59 . 4 address ranges of interest 2 kinds of transaction Delay range Transaction type vs. kind_dly: cross kind.Data-Oriented Coverage Recording 3 b 2 1 2 0 2 1 1 1 2 2 a 0 1 1 3 3 1 3 4 Cross Coverage: How many times did a==2 while b==1? • Records the values of variables at a particular simulation time • Usually captured by the testbench • Many possibilities for analysis • The key is to know when to sample the data 2006 MAPLD International Conference 117 Design Verification Tutorial Covergroup bit [7:0] addr.} coverpoint kind {bins k[] = {WRITE. enum {WRITE.READ}.} addr_kind: cross addr. READ} kind. dly.

Type vs. 2006 MAPLD International Conference 119 Design Verification Tutorial Assertion Hooks for Coverage • SystemVerilog lets you capture data at critical points within a sequence/property – Local variables property e.get_inst_coverage() • Global cumulative coverage for all covergroup instances – $get_coverage().a. endproperty valid in out 2006 MAPLD International Conference EA BF EB 120 C0 Design Verification Tutorial 60 .int_var). coverpoint a. Instance Coverage • Type coverage is cumulative for all instances of a covergroup – c1::a.int_var). x = in) |-> ##5 (out == (x+1)). c1 group2 = new(instance2. endgroup initial begin c1 group1 = new(instance1. int x.get_coverage(). (valid. end • Instance coverage is for a particular instance – group2. covergroup c1 (ref int a) @(posedge clk).

dly = dlyval.pdly=0) (as 1'b1 )[*1:4] |=> ((as == 1'b1 && rdy == 1'b1. Capture addr.paddr = ad. (as 1'b0) @(posedge clk) ((as == 1'b0). (as 1'b0) @(posedge clk) ((as == 1'b0). endgroup mycov covgrp = new.} addr_kind: cross addr. tr_t kval. pkind = tr_t'(rwl). int pdly. covgrp. docov(paddr. property trans. ++pdly)[*1:4]) incr delay counter (as 1'b0) . covgrp. addr = aval. endproperty cover property (trans). int dlyval).} coverpoint kind {bins k[] = {WRITE. // immediate sample in covergroup endfunction 2006 MAPLD International Conference 121 Design Verification Tutorial Only called when property is successful Function passes local variables outside property Local Variables Capture Transient Data covergroup mycov @smp_event.pkind. addr = aval. ##1 ((as == 1'b1 && rdy == 1'b0).pkind. kind.sample. pkind = tr_t'(rwl). kind_dly: cross kind. ##1 ((as == 1'b1 && rdy == 1'b0). // immediate sample in covergroup endfunction 2006 MAPLD International Conference 122 Design Verification Tutorial 61 .pdly)). ++pdly)[*1:4]) (as 1'b0) . tr_t kval. tr_t pkind.paddr = ad.pdly)). kind = kval. dly. Call coverage a_t paddr. kind = kval.} coverpoint dly {bins d[] = {[1:4]}. function void docov(input a_t aval. docov(paddr. int pdly. int dlyval). a_t paddr.pdly=0) (as 1'b1 )[*1:4] |=> ((as == 1'b1 && rdy == 1'b1.READ}. function void docov(input a_t aval.sample. endproperty cover property (trans). coverpoint addr {bins a[4] = {[0:31]}. dly = dlyval. init delay kind here here counter tr_t pkind.Local Variables Capture Transient Data clk ad as rwl rdy C0 A5 property trans.

Program Block Program Block Program Block DUV 2006 MAPLD International Conference 124 Design Verification Tutorial 62 . etc.Program Blocks • Used to encapsulate testbench functionality • Always a leaf in the hierarchy • Decouples the verification code from DUT – DUT cannot reference anything in program block – Program blocks can scope into each other and DUT • Avoids DUT dependency on TB • Helps prevent DUT/TB race conditions • No limit on number of program blocks 2006 MAPLD International Conference 123 Design Verification Tutorial Program Blocks • Allows for code reuse – Signal references are local to the ports on the program – Gives multiple threads of execution – initial and final blocks can be defined – Forms heart of the test flow Top Module Interfaces. Wires.

Rd = 1 .Sel = 1 . cpu. task reset. the_CPU.data <= mydata. default input #1ns output #2ns. // AC Timing Characteristics .write(1. //etcetera end endprogram 2006 MAPLD International Conference 125 Design Verification Tutorial Clocking Blocks device bus clk enable full data[7:0] empty Clocking Blocks capture stable values clocking bus @(posedge clk). # t1.. the_CPU. endclocking Clocking Event Default I/O skew Testbench Uses: if (bus.reset. initial begin $write("Starting CPU test\n"). cpu. # t1.rst = 0. static int t1 = 10. … Override Output skew Sample here Drive here clk Input Skew 2006 MAPLD International Conference 126 Output Skew Design Verification Tutorial 63 . full. cpu.. output #6ns empty. cpu. 10). cpu.Data_drive = 16'hzzzz . input enable.data == ‘z) bus. endtask endclass intel_mgmt the_CPU = new(). class intel_mgmt. cpu.Program Blocks • Simple example program cpu_test(interface cpu).Wr = 1 .rst = 1. inout data.

– Encapsulates functionality – Provides a template for building objects • Object – The actual house – An object is an instance of a class • Properties – It has light switches – Variables specific to the class • Methods – Turn on/off the lights – Tasks/functions specific to the class 2006 MAPLD International Conference 127 Design Verification Tutorial Class Basics • Class Definitions Contain Data and Methods • Classes Are Instantiated Dynamically to Create Objects – Static members create a single element shared by all objects of a particular class type • Objects Are Accessed Via Handles – Safe Pointers. each block has a well defined interface • Focuses on the data and what you are trying to do with it rather than on procedural algorithms • Class – A blueprint for a house – Program element “containing” related group of features and functionality.Object-Oriented Programming • Organize programs in the same way that objects are organized in the real world • Break program into blocks that work together to accomplish a task. Like Java • Classes Can Inherit Properties and Methods From Other Classes • Classes Can Be Parameterized 2006 MAPLD International Conference 128 Design Verification Tutorial 64 .

endclass Note: Class declaration does not allocate any storage class Packet... struct Data. endtask endclass 129 Design Verification Tutorial 2006 MAPLD International Conference Instantiating SV Classes • Classes are dynamically created objects – Every object has a built-in “new()” constructor method – Can also create user defined constructor that overloads built-in class Packet. endfunction task SetCommand(input cmd_t a).. function new(input int a). return(Status). Command = IDLE. function int GetStatus().. Command = IDLE.. Command = a. Status = a. . function new().. int Status. <task/function_declarations>. myPkt Command Status Data IDLE IDLE 5 class Packet. . endclass Packet myPkt = new. endfunction endclass Packet myPkt = new. endfunction endclass Packet myPkt = new(5). <data_declarations>. 2006 MAPLD International Conference class Packet. 130 Design Verification Tutorial 65 .The SystemVerilog Class Basic class syntax: class name. cmd_t Command. .

Handling Memory with SV Classes • Object Destruction/De-allocation done automatically when an object is no longer being referenced – NO destructors – NO memory leaks – NO unexpected side effects Packet Pkt1 = new().. Design Verification Tutorial 2006 MAPLD International Conference 132 66 . Packet Pkt2 = new(). Pkt1 = null. bit Error.. endtask endclass Command Status Data GetStatus SetCommand Command = a. Command = a + 1. ErrPkt: Command Status Data Error GetStatus ShowError SetCommand Command = a+1. Pkt2 = null. . .. end • Automatic garbage collection 2006 MAPLD International Conference 131 Design Verification Tutorial Extending SV Classes • Classes inherit properties & methods from other classes – Subclasses can redefine the parent’s methods explicitly – Allows customization without breaking or rewriting known-good functionality in the parent class Packet: class ErrPkt extends Packet... Send_Pkt( Pkt2 ). function bit ShowError(). Send_Pkt( Pkt1 ). endfunction task SetCommand (input cmd_t a). initial begin .. return(Error).

..new().i = 4. set_i(c).d. endfunction task set_a(input int c)...endfunction endclass class Sub extends Base.// legal – set_a is unprotected S. protected task set_i(input int i).. local int i. endfunction task set_a(input int c).. protected task set_i(input int i). int a.. function new(). a = c.a = c+1. a = c. endtask function new(). int a.endfunction endclass class Sub extends Base.// inherited endtask endclass • this pointer refers to current instance • super pointer refers to parent class Sub S = new.. // legal – Base::a is hidden by Sub::a S. // inherited method endtask endclass • this pointer refers to current instance • super pointer refers to parent class 2006 MAPLD International Conference 133 Design Verification Tutorial Class Hierarchy • Class members can be hidden from external access – local members can only be referenced from within the class – protected members can be referenced from within a subclass class Base. initial begin S...d.set_i(4).i = i. super. endtask function new(). this. function new(). int a.i = i. int a. set_i(c).a = 5.Class Hierarchy • Class members can be hidden from external access – local members can only be referenced from within the class – protected members can be referenced from within a subclass class Base.// illegal – set_i is protected S..set_a(5). this. super.new().// legal – d is inherited from Base end 2006 MAPLD International Conference 134 Design Verification Tutorial 67 . super. // illegal – i is local to Base S.a = c+1.. local int i.d = 3. super.

constraint c1 { a < 4'b1100. } constraint c2 { b < 4'b1101. constraint c3 { a > b .c2.. rand logic [3:0] b. . } endclass Add additional constraints Note that c3 and c4 are mutually exclusive • Change constraints on the fly with constraint_mode() and rand_mode() TDerived derived = new(). bit [size-1:0] a. local T items[].).). } constraint c4 { a < b . // stack of classes Avoid Writing Similar Code More than Once 2006 MAPLD International Conference 135 Design Verification Tutorial • Constraints are part of the OO data model class TBase. } endclass Constraints and OOP Declare random variables Declare constraints • Layer with inheritance class TDerived extends TBase.. derived.. // Turn b’s randomization off 2006 MAPLD International Conference 136 Design Verification Tutorial 68 . // c1.c5 active derived. // Class with vector of size 4 class stack #(parameter type T = int. .c4. } constraint c5 { a + b == 4'b1111.constraint_mode(0). endclass vector #(10) vten.b. // object with vector of size 2 typedef vector#(4) Vfour. rand logic [3:0] a.rand_mode(0).c3. // object with vector of size 10 vector #(. task push( T a ). // default: a stack of int’s stack#(bit[1:10]) bs. endtask endclass stack i_s. endtask task pop( ref T a ).size(2)) vtwo.. // a stack of 10-bit vector stack#(real) rs. // Turn c3 off status = randomize(derived). // a stack of real numbers stack#(Vfour) vs.Parameterized Classes • Allows Generic Class to be Instantiated as Objects of Different Types – Uses modulelike parameter passing class vector #(parameter int size = 1.

StType pstate.. only random variables are assigned values • By providing arguments. req == 1.randomize(src. only values within the argument list are randomized class packet { rand byte src. rand StType state = INIT.} endclass • Constraints can specify FSM-like behavior for random variables class myState typedef enum StType {INIT. // returns function success only end 2006 MAPLD International Conference 137 Design Verification Tutorial State-Dependent Constraints • Constraints based on other values allow expressions to change dynamically class myState.randomize(payload).. rand byte dest. else kind == WRITE. // randomizes payload only p1. if(pstate == REQ && rdwr == 1) state == Rd. bit req.. . // randomizes src and dest only p1.randomize(null). bit [7:0] st = 0.randomize(). constraint rdfirst {if (st < 10) kind == READ.}. rand enum kind {READ.}. WRITE}. RD.}.. //payload is not a random byte endclass packet p1 = new. byte payload. initial begin p1. REQ. endclass 2006 MAPLD International Conference 138 Design Verification Tutorial 69 . // randomizes src and payload p1.payload). constraint fsm { if(pstate == INIT) {state == REQ.In-line Random Variable Control • When randomize() is called without arguments.

Built-in Methods
• randomize() automatically calls two built-in methods
– pre_randomize(): Called before randomization – post_randomize(): Called after randomization

• These methods can be used as "hooks" for the user to tap to peform operations such as:
– Setting initial values of variables – Performing functions after the generator has assigned random values
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pre_randomize() Method
• Users can override pre_randomize() in a class to set pre-conditions before the object is randomized
class MyPacket extends Packet { int packet_size; rand byte payload [];

function void pre_randomize(); super.pre_randomize(); packet_size = 10; //initialize packet_size payload = new[packet_size]; … endfunction endclass
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Call to parent’s super.pre_randomize() must be present, otherwise their pre-randomization processing steps shall be skipped

70

post_randomize() Method
• Users can override post_randomize() in a class to perform calculations on generated data, print diagnostics, and check post-conditions
class MyPacket extends Packet { byte parity; Call to parent’s super.post_randomize() must be present, otherwise their post-randomization function void post_randomize(); processing steps shall be super.post_randomize(); skipped parity = calculate_parity(); //calculate parity … endfunction

function byte calculate_parity(); … endfunction endclass
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Virtual Interfaces
• Need a way to connect classes to actual interface signals • Virtual Interface serves as a pointer to physical interface
class BusDriver; virtual myBus bus; task send2bus(...); @(posedge bus.clk) bus.req <= 1’b1; ... endtask endclass program prog(myBus bif); BusDriver myDriver = new(); initial begin myDriver.bus = bif; … end endprogram

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Putting it All Together: The Advanced Verification Methodology

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Chip Baking a Cake

VERIFICATION by MENTOR GRAPHICS

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etc.) – Application-specific stuff (constraints. reusable verification components • Implemented in both SystemVerilog and SystemC • Consistent Transaction-Level interfaces with common semantics – Infrastructure details built-in so you don’t have to worry about them • Simple connections between components • Controllable. etc.Introducing the Advanced Verification Methodology • The Open-Source AVM Library – The Ingredients – Library of modular. coverage. customizable error/message reporting – Open-Source means you are free to use them. stimulus generator. with full access to all the source code • The Verification Cookbook – The Recipes – Open-source runnable examples • Illustrate concepts and serve as templates for your use – Examples build on previous ones to introduce advanced verification concepts incrementally 2006 MAPLD International Conference 145 Design Verification Tutorial Verification Methodology • Understand the process – Compare observed DUT behavior against expected behavior – Many ways to specify expected behavior • Follow the recipe – Assemble the verification components into an environment – Generate proper stimulus and automatically check results – Gather coverage and track progress • Get the ingredients – AVM stocks your shelves – Basic staples (transactions.) • Presentation – Analyze results to identify areas of weakness – Tweak constraints to get better coverage 2006 MAPLD International Conference 146 Design Verification Tutorial 73 .

Key Aspects of a Good Methodology • Automation – Let the tools do the work • Reusability – Don’t reinvent the wheel – Reusability is functionalityand/or protocol-specific – Reuse is critical across projects. across teams. and across tools • Observability – Self-checking is critical – Automate self-checking and coverage tracking – Assertion-based Verification • Measurability – If you can’t measure it. you can’t improve it – Tools automate the collection of information – Analysis requires tools to provide information in useful ways – All tools must consistently contribute to measurement and analysis 147 Design Verification Tutorial • Controllability – Make sure you exercise critical functionality – Constrained-Random stimulus and formal verification automate the control process 2006 MAPLD International Conference AVM Layering Control Untimed Transactions Test Controller TestbenchSpecific Coverage Collectors Golden Models Performance Analyzers DesignSpecific Stimulus Generators Masters Slaves Analysis Untimed or Partially-timed Transactions Environment Scoreboards Transactions ProtocolSpecific Transactors Drivers Monitors Responders Pins DUT 2006 MAPLD International Conference 148 Design Verification Tutorial 74 .

AVM Architecture Scoreboard Transaction Level Components Coverage Test Ctrlr Monitor Monitor Transactors Stimulus Gen/ Master Driver DUT Responder Slave 2006 MAPLD International Conference 149 Design Verification Tutorial Transactors Scoreboard Coverage Test Ctrlr Monitor Monitor Stimulus Gen/ Master Driver DUT Responder Slave 2006 MAPLD International Conference 150 Design Verification Tutorial 75 .

• It identifies a response and forwards it to the slave • It takes the response from the slave and applies it to the bus 2006 MAPLD International Conference 151 Design Verification Tutorial Environment Scoreboard Coverage Test Ctrlr Monitor Monitor Stimulus Gen/ Master Driver DUT Responder Slave 2006 MAPLD International Conference 152 Design Verification Tutorial 76 .Transactors • A Transactor – Converts traffic between signal and transaction domains • A Monitor – Converts signal level traffic to a stream of transactions • Checks for protocol violations • Moves traffic from the design to analysis portion of the TB • A Driver – Is a Transactor that takes an active part in the protocol • Interprets transactions and drives signal level bus • May be bi-directional • A Responder – Is the mirror image of a Driver. It plays an active part in the protocol.

Environment • Stimulus Generator – Generates sequences of transactions that are sent into the testbench – Generate constrained random stimulus. or – Generate directed stimulus • Master – Bi-directional component – Initiates activity • Slave – Bi-directional component – Response to activity 2006 MAPLD International Conference 153 Design Verification Tutorial Analysis Components Scoreboard Coverage Test Ctrlr Monitor Monitor Stimulus Gen/ Master Driver DUT Responder Slave 2006 MAPLD International Conference 154 Design Verification Tutorial 77 .

Analysis • Consume transactions from monitors • Perform data reduction of some sort • Operate at the transaction level • Scoreboard – Checks the intended functionality of the DUT • Coverage Collector – Counts things 2006 MAPLD International Conference 155 Design Verification Tutorial Controller Scoreboard Coverage Test Ctrlr Monitor Monitor Stimulus Gen/ Master Driver DUT Responder Slave 2006 MAPLD International Conference 156 Design Verification Tutorial 78 .

Control • Supplies configuration information to verification components • Schedules the different stimulus generators • Monitors the functional coverage – Are we done? • Tests the state of the scoreboards – To detect functional errors • Design-specific component 2006 MAPLD International Conference 157 Design Verification Tutorial Design Intent • Design representation is well understood… • How to represent intent? • Expression of intent must: – be easier/faster to build than the design – be at a higher abstraction level than the design – communicate with the design 2006 MAPLD International Conference 158 Design Verification Tutorial 79 .

get( rsp ).put( req ). 2006 MAPLD International Conference 160 Design Verification Tutorial TLM also has equivalent non blocking APIs for speed OR p. rsp ).transport( req .TLM in a Nutshell • Initiator puts/gets transaction to/from a target – Initiator port requires an interface – Target export provides the implementation of the interface Interfaces = Modularity put Block A Interface1 Block B get Block A Interface2 Block C • Completion Model can be blocking or nonblocking – Blocking methods may be tasks – Nonblocking must be functions 2006 MAPLD International Conference 159 Completion Model Blocking Nonblocking Design Verification Tutorial Direction • Unidirectional Dataflow – Choose put. get or peek to move data between Verification Components p. • Bidirectional Dataflow layered on top of unidirectional – put + get for pipelined buses – transport for non pipelined p.put( req ). p. 80 .get( rsp ). p. p.peek( rsp ).

get_export. This is a valid tlm_put_if type This is NOT a valid tlm_put_if type This IS a valid tlm_get_if type Request Response ← get tlm_put_imp tlm_get_imp tlm_put_if tlm_get_if Initiator Target1 Target2 class initiator. TLM Port requires endclass an implementation class target1.. .put_port = t.Also tlm_get_if. rand logic[15:0] data. i. etc. // illegal: type mismatch endfunction i. initiator i = new(“initiator”)... target2 tt = new(“target”).put_export. tlm_peek_if. … i.get_port endfunction … endclass endclass 2006 MAPLD International Conference 161 Design Verification Tutorial Analysis Port Description • Subscribers register with Publisher • Publisher passes data to each Subscriber Device0 Subscriber write(tr) Analysis components: scoreboards. coverage collectors. tlm_put_imp put_export = new(this).put_port = t. target1 = new(“target”). class Request. function void connect.. rand logic[31:0] addr. tlm_put_if Understanding TLM tlm_put_imp put→ extends tlm_put_if. function new(…). . TLM Export provides endclass an implementation A transaction contains the information to be communicated between components class my_env extends avm_env. tlm_put_if put_port. Device1 Subscriber write(tr) DeviceN Subscriber write(tr) analysis export analysis port Publisher q[N] … q[1] q[0] Monitor write(tr) write() methods must be nonblocking 2006 MAPLD International Conference Publisher may have 0. 1 or many subscribers 162 Design Verification Tutorial 81 . etc.

Elaboration initial begin env.i).blocking_put_export. task run(). tlm_put_if #( int ) put_port. producer p = new. for( int i = 0. tlm_put_if #( int ) put_port. endfunction endclass class consumer extends verif_component. $display( "Just got %d" . c. Binding function void connect. end endtask endclass 2006 MAPLD International Conference 163 Design Verification Tutorial Simple Fifo Example program top. forever begin get_port. i < 10. i ). tlm_get_if #( int ) get_port. endclass class consumer extends verif_component.blocking_get_export.put( i ).put_port = f. tlm_get_if #( int ) get_port.connect().get( i ). $display( "Just got %d" .put( i ). task run(). end endtask. int i. end endtask. end Execution endprogram class env. task run(). forever begin get_port.i). i < 10. tlm_fifo #( int ) f = new. p.get_port = f. i++ ) begin $display("about to put %d". consumer c = new. put_port. verif_component::run_all_threads(). i ). for( int i = 0. put_port. end endtask endclass class producer extends verif_component.Simple Fifo Example producer tlm_fifo consumer class producer extends verif_component.get( i ). env = new(). i++ ) begin $display("about to put %d". task run(). endclass 2006 MAPLD International Conference 164 Design Verification Tutorial 82 . int i.

tlm_fifo #(RSP. .get(rspt). int BOUND=1). tlm_fifo #(REQ. BOUND) req = new(). local mailbox #(T) m. . output RSP rspt). tlm_fifo #(REQ. RSP. RSP). rsp.. int BOUND=1).TLM Channels • tlm_fifo – unidirectional transactions between free-running independent components class tlm_fifo #(type T. 1) rsp = new().. extern task peek(output T t). BOUND) rsp = new().. 1) req = new(). endclass 165 Design Verification Tutorial • tlm_req_rsp_channel – two back-to-back tlm_fifos – pipelined or out-of-order protocols • tlm_transport_channel – tlm_req_rsp_channel with fifo size = 1 – non-pipelined and in-order 2006 MAPLD International Conference TLM Channels put_req put put tlm_fifo get get_req get tlm_req_rsp_channel get_rsp get tlm_fifo put put_rsp 2006 MAPLD International Conference 166 Design Verification Tutorial 83 ... . tlm_fifo #(RSP. endclass class tlm_transport_channel #(type REQ... extern task put(input T t). endclass class tlm_req_rsp_channel #(type REQ. .put(reqt). task transport(input REQ reqt. extern task get(output T t). req..

. stimulus #(trans) stim1 = new().blocking_put_export. super.. task send( input T t ). underlying mailbox . … endtask endclass class stimulus #(T = int).new( nm . try_put( t ). T ) blocking_put_export = new( this ). endfunction endclass Analysis fifo HAS A write method Design Verification Tutorial 2006 MAPLD International Conference 168 84 .blocking_put_export. tlm_fifo #(trans) fifo = new(). named_component p = null ).blocking_put_port = fifo. stim2. T ) analysis_export. Analysis fifo is analysis_export = new( this ). Analysis fifo IMPLEMENTS the analysis interface (wrapper) analysis_imp #( analysis_fifo #( T ) .blocking_put_port = fifo. function new( string nm . end class tlm_fifo #( T = int ) endprogram tlm_blocking_put_imp #( this_type . stimulus #(trans) stim2 = new().Exports in tlm_fifo • May have multiple ports connected to them program test.put(t). unbounded endfunction function void write( input T t ). blocking_put_port. p . task put( input T t ). Multiple puts will get resolved and interleaved automatically by the fifo Fairness of interleaving initial begin is determined by the stim1. endtask endclass stim1 fifo stim2 User may also control interleaving by turning generators on and off via the test controller 167 Design Verification Tutorial 2006 MAPLD International Conference Analysis Fifo in SystemVerilog • Specialization of tlm_fifo – Infinite fifo to ensure nonblocking writes – Still has tlm_*_get exports on the other side Analysis fifo IS A tlm_fifo class analysis_fifo #( type T = int ) extends tlm_fifo #( T ). tlm_blocking_put_if #(T) blocking_put_port. 0 ).

resume.The Advanced Verification Library 2006 MAPLD International Conference 169 Design Verification Tutorial AVM Components • All components are extended from one of two base classes • avm_named_component – Maintains name hierarchy based on instantiation – Manages hierarchical connections of ports and exports – Includes built-in message handling and reporting • avm_verification_component – – – – Extended from avm_named_component Adds a user-defined run() method Includes process control for suspend. kill Defines static run_all() method that calls run() on every avm_verification_component 170 Design Verification Tutorial 2006 MAPLD International Conference 85 .

.m2 t2. top_c t1 = new(“t1”). top.m2 t1.m2. top.m2.leaf.m2.. bot_c b2 = new(“b2”. .mid...b2 Design Verification Tutorial 86 .m1 t1.this)..mid.this).m2.b1 t1.b1 t1. LeafClass m_leaf.b2 t1..b2 t2 t2.m1 t2.The Need For Class Instance Naming top mid leaf MidClass m_mid.this). bot_c b1 = new(“b1”.. . mid_c m1 = new(“m1”..m1.b1 t2. .m1. endclass class top_c extends avm_named_component. mid_c m2 = new(“m2”.this). top_c t2 = new(“t2”).m1. endclass t1 t1. • Classes have handles TopClass m_top. • Modules have hierarchical names top. 2006 MAPLD International Conference 171 Design Verification Tutorial avm_named_component • Base class from which all components are derived • Builds static associative array of component names – Each child appends its name to that of its parent – Name for each component passed in via new() • Names are used when issuing messages for components class bot_c extends avm_named_component.b2 t2. endclass class mid_c extends avm_named_component. endclass 2006 MAPLD International Conference 172 class my_env extends avm_env. .b1 t2.m1.

the list of names is shared by all instances • Important so that instances can be uniquely identified • Provides the reporting infrastructure – Every avm_named_component has its own local message handler – Together with the naming facilities. provides per-instance configuration of VIP reporting actions • Provides access to the connectivity infrastructure • All verification objects are extended from avm_named_component 2006 MAPLD International Conference 173 Design Verification Tutorial avm_named_component (Contd. this is a static associative array indexed by string • Since it is static.) • An avm_named_component derivative has – – – – List of children (which may be empty) A parent (but see avm_env for caveat) A unique user-defined name Methods to manage connectivity • To the children • Imports and exports of the TLM interfaces • There are several methods the user must define – Constructor • Name and parent are set here • Any children should be initialized – – – – connect() export_connections() import_connections() report() (optional definition) 174 Design Verification Tutorial 2006 MAPLD International Conference 87 .g. for messaging and configuration – avm_named_component provides a mechanism for instance naming • Internally.avm_named_component • Provides hierarchical naming throughout the environment – Class instance names are essentially invisible – HDL modules have an automatic hierarchy of instance names – Need to be able to identify and control specific class instances • E.

parent ). avm_named_component parent = null). parent is "this" – Local instance "name" must be unique class pipelined_bus_hierarchical_monitor extends avm_named_component.new( name . Children function new( string name. address_phase_component m_address_component. – parent is omitted for children of avm_env – otherwise. set name of childen m_data_component = new("data_component" . avm_named_component parent = null ). super. this ).avm_named_component Constructor • User must define the constructor of avm_named_component derivative – Also remember to call the parent constructor function new(string name. this ). data_phase_component m_data_component. // register name and parent Initialize m_address_component = new("address_component" . set parent of children to "this" endfunction endclass 2006 MAPLD International Conference 175 Design Verification Tutorial • VIP creator must define the connection methods – Three different classes of connections avm_named_component Connection methods • Function void connect() – Connects child ports and exports • export_connections() – For interfaces provided by this VIP • import_connections() – For interfaces required by this VIP • Following transactor example illustrates what is required to be defined 2006 MAPLD International Conference 176 Design Verification Tutorial 88 .

endfunction function void import_connections sub_block.. Fine-grained process control for run method to registry function new( string name = "" .m_main_process = process::self. endfunction avm_env ensures correct ordering 1. local static avm_verification_component s_component_registry[$]. run . endtask static task kill_all. s_component_registry[j].new( name .blocking_put_port = blocking_put_port..blocking_put_export. s_component_registry[i]... endfunction static task run_all. Down and In – import connections 2006 MAPLD International Conference 177 Design Verification Tutorial avm_verification_component • Base class from which all runnable components are Extended from derived avm_named_component virtual class avm_verification_component extends avm_named_component...blocking_put_port = driver. endtask virtual task run().blocking_put_export. Add self s_component_registry. ..run().. endfunction function void export_connections blocking_put_export = fifo.. super.. parent ). Up and Out – export connections 2.m_main_process.Hierarchical Binding function void connect stimulus. endtask endclass 2006 MAPLD International Conference 178 Get process ID for each method Invoke all run methods Kill all run methods All verification components must define their own run method Design Verification Tutorial 89 . fork s_component_registry[j]. join_none . process m_main_process. .push_back( this ).kill. Across – connect 3. avm_named_component parent = null ) .

• AVM includes examples and base classes – Users are free to use them as-is or extend them as needed AVM Transactors • avm_stimulus: Generic constrained-random stimulus generator – Uses “factory pattern” to create randomized stimulus – User is free to modify and/or extend constraints to guide stimulus • Scoreboarding – avm_in_order_comparator • Compares two transaction streams of the same type – avm_algorithmic_comparator • Converts one transaction type to another and then compares • Drivers.) • comp(): defines which fields are relevant when comparing two transaction – clone() and comp() methods are used by other AVM components to handle the transaction correctly 2006 MAPLD International Conference 180 Design Verification Tutorial 90 . responders. shallow copy. etc. deep copy. monitors – Several protocol-specific examples that can be used or extended 2006 MAPLD International Conference 179 Design Verification Tutorial AVM Transactions • The avm_transaction base class is the basis for all transaction objects – Requires the user to define transaction-specific methods called by other components • convert2string(): generate a string that gets displayed by print() • clone(): defines the action to be performed when copying the transaction (handle-only.

virtual interfaces. 2006 MAPLD International Conference 181 Design Verification Tutorial AVM Environment Class • Base avm_env class controls the environment – Constructor instantiates and ‘new’s all components – virtual do_test() method controls building and execution • • • • • • Connects all components. function rps_c clone. return rps.name.AVM Transaction Class • avm_transaction class is a base class – AVM and TLM libraries needs it and a few methods – Required to print.. PAPER.. compare and clone transactions • Transactions are handles – Transactions needs to cloned before they are “sent” typedef enum bit[1:0] {IDLE. clone. ROCK. etc.rps.rps = this. . SCISSORS} rps_t. clone = new. class rps_c extends avm_transaction.. rand rps_t rps. function string convert2string. Configures components and DUT Starts all avm_verification_components Runs the test Reports results Stops everything and exits – User defines all application-specific behavior by extending the avm_env class and defining the method bodies 2006 MAPLD International Conference 182 Design Verification Tutorial 91 . ..

avm_report_message("avm_env" . It connects // up the top level objects of the testbench. execute. if this // is required. virtual function void configure.avm_env virtual class avm_env. // configure is a function . configure. // then propagate port connections down through the // hierarchy ( top down ) avm_named_component::import_top_level_connections. // connect up exports first ( bottom up ) avm_named_component::export_top_level_connections. // execution phases avm_verification_component::run_all. return. pure virtual task execute. "Finished Test"). endfunction endclass 2006 MAPLD International Conference 184 Design Verification Tutorial 92 . // execute phase // The report function is used to report on the status of // the avm_env subclass at the end of simulation.ie no interaction with the // scheduler is allowed. and scoreboards and coverage // objects are examined from within the testbench. avm_named_component::report_all. avm_verification_component::kill_all. endtask 2006 MAPLD International Conference 183 Design Verification Tutorial avm_env(2) // connect must be overloaded in any subclass. return. virtual function void report. // then connect "my" children's ports to their siblings' exports connect(). endfunction // The execute task is where stimulus generation is // started and stopped. // finish report. virtual task do_test. pure virtual function void connect.

id.new(). FATAL • Four potential actions: DISPLAY. comparator • Virtual interfaces for pin-level connection to the DUT Stimulus analysis_fifo analysis_fifo Monitor tlm_fifo Driver Memory DUT 2006 MAPLD International Conference 186 Design Verification Tutorial 93 . – Connections made via avm_env. WARNING.id) pair – Verbosity argument allows for filtering – Actions and verbosity can be defined and overridden hierarchically • Reporting is built into avm_named_component – All reporting methods can also be called directly 2006 MAPLD International Conference 185 Design Verification Tutorial AVM Example • All verification components are classes • Instantiated within an environment class – Allocated via avm_env. or (severity. LOG. COUNT.AVM Messaging • Four levels of Severity: MESSAGE.connect(). EXIT – Actions defined by severity. ERROR.

comparator tlm_fifo #( trans_type ) f.master_mp.put_ap. f = new("fifo").connect.analysis_export ). d. m = new(“monitor”). local driver_state m_state.nonblocking_get_port = f.ack == 1 ) begin m_state <= READY_TO_SEND_REQ. end endcase endtask protected virtual task send_to_bus( T req ). class mem_env extends avm_env. T t.master_mp.act_blocking_get_port = a. analysis_fifo #( trans_type ) b. endclass function new(virtual mem_if bus). m. b = new(“before”). c.req <= 1. endfunction Monitor program mem_tb( mem_if my_if ).register( a. f. m_state <= WAIT_FOR_ACK. endfunction analysis_fifo #( trans_type ) a.nonblocking_get_export.clk) case( m_state ) READY_TO_SEND_REQ: if( nonblocking_get_port. end endprogram Stimulus tlm_fifo Driver Memory DUT 2006 MAPLD International Conference 187 Design Verification Tutorial AVM Example: Driver class driver #(type T = transaction)extends avm_verification_component..blocking_put_port = f. forever begin @(posedge m_bus_if. c.AVM Example function void connect. initial begin m_env. tlm_nonblocking_get_if #(T) nonblocking_get_port. s. m_bus_if. stimulus #( trans_type ) s. d. analysis_fifo analysis_fifo a = new(“after”). m.register( b. c = new(“comparator”).exp_blocking_get_port = b. mem_env m_env = new(my_if). m_env. avm_class_comp(trans_type)) c.master_mp.blocking_put_export.analysis_export ). comparator #(trans_type.ap.blocking_get_export. endtask endclass 2006 MAPLD International Conference 188 Design Verification Tutorial 94 . T t.req <= 0..run.m_bus_if = my_if. s = new(“stimulus”).try_get( t )) begin send_to_bus( t ). my_if = bus. . virtual mem_if my_if.blocking_get_export. typedef enum { READY_TO_SEND_REQ . WAIT_FOR_ACK driver_state. d = new(“driver”). driver #(trans_type) d.m_bus_if = my_if. end WAIT_FOR_ACK:begin if( m_bus_if. monitor #(mem_cov_t) m. Overload to do error injection task run. master_mp. virtual mem_if m_bus_if.

. new_x virtual task send_trans(trans t).send_trans(t).. endfunction endclass Both driver and error_driver have a nonblocking_get_port so the same connection still works 2006 MAPLD International Conference 190 Design Verification Tutorial 95 .a[0] == 0 && t..req <= 1’b1.d += 3.a[0] == 0 && req..send_to_bus(req). endtask endclass Overload to do error injection class env. d. . endtask virtual task send_trans(trans t).d += 3.. if(t. super. if(req. m_bus_if. .nonblocking_get_port = f.OOP Customization • This is what Inheritance is for class my_x... super. protected virtual task send_to_bus( T req ).t = WRITE) t. endtask – virtual methods • Modified behavior lives with the component 2006 MAPLD International Conference 189 Design Verification Tutorial AVM Example: Error Injection class error_driver #(type T = transaction) extends driver#(T)...nonblocking_get_export.t = WRITE) req. record_transaction(t). extends my_x... . error_driver #(trans_type) d. . function void connect.

Randomizing Error Injection
class rerror_driver #(type T = transaction) extends driver#(T); int dly; class err_des; bit par; rand enum {XDATA, DELAY, PARITY, ...} t; local err_des err = new(); rand int dly; ... protected virtual task send_to_bus( T req ); endclass inject_error( req ); m_bus_if.master_mp.par <= par; modify transaction contents m_bus_if.master_mp.req <= 1; and/or set protocol violations wait(m_bus_if.master_mp.gnt == 1); for(int i=0; i<dly; i++); ... modified procedural code to endtask

drive transaction onto bus error type

protected virtual task inject_error(ref T req); assert(randomize(err)); randomize case(err.t) XDATA: if(req.a[0] == 0 && req.t = WRITE) req.d += 3; DELAY: assert(randomize(dly) with {dly < err.dly;}); PARITY: par = !^req.d; // inject parity error ... endcase endtask endclass

modify transaction contents or protocol parameters based on error type
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avm_stimulus class
• avm_stimulus is a generic stimulus generator
– Also as prototype for other stimulus generators

• Complete with a put port
– Connects to channels such as tlm_fifo

• Parameters of sub type avm_transaction
– One to define the type of transaction sent out across to the put port – Optional class containing constraints / used for generation
• Basically a sub class of the transaction type

• generate_stimulus task generates transactions
– – – – Base type transactions With optional sub class constraints Uncounted or counted Send transactions to the put port
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AVM Stimulus Generator
class avm_stimulus #( type trans_type = avm_transaction ) extends avm_named_component; tlm_blocking_put_if #( trans_type ) blocking_put_port; local bit m_stop = 0; virtual task generate_stimulus( trans_type t = null , input int max_count = 0 ); trans_type temp; if( t == null ) t = new; for( int i = 0; (max_count == 0 || i < max_count) && !m_stop; i++ ) begin assert( t.randomize() ); temp = t.clone(); blocking_put_port.put( temp ); end endtask virtual function void stop_stimulus_generation; m_stop = 1; endfunction endclass : avm_stimulus

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Directing Stimulus(1)
• Extend and constrain base transaction
class my_env extends avm_env; avm_stimulus #(mem_request) m_stimulus = new(); class write_request #( int ADDRESS_WIDTH = 8 , int DATA_WIDTH = 8 ) extends mem_request #( ADDRESS_WIDTH , DATA_WIDTH ); constraint write_only { this.m_type == MEM_WRITE; } endclass // write_request write_request #( ADDRESS_WIDTH , DATA_WIDTH ) m_write_gen = new(); task execute; m_stimulus.generate_stimulus( m_write_gen , 10 ); m_stimulus.generate_stimulus(); // randomize requests endtask

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Directing Stimulus(2)
• Define “convenience layer”
class my_env extends avm_env; class my_stimulus #(type T = mem_request) extends avm_stimulus #(T); task write( input address_t address , input data_t data ); request_t request = new( address , MEM_WRITE , data ); put_port.put( request ); endtask endclass my_stimulus #(mem_request) m_stimulus = new(); task execute; m_stimulus.write( CSR , 16’hA5A5 ); m_stimulus.write( CLKDIV , 16’h0004 ); m_stimulus.generate_stimulus(); // randomize requests endtask

convenience functions for directed stimulus

randomized generation from base class

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Basic Transaction-Level Testbench
Request Coverage

Master

FPU TLM

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// execute phase fork master.Testbench Environment: SystemVerilog class fpu_env extends avm_env.master_port = dut. master.blocking_master_export. }. dut.master_port(t. fpu_tlm dut. fpu_operator_coverpoint rq_cov.analysis_export). fpu_req_cov rqcov. Request Coverage Master FPU TLM 2006 MAPLD International Conference 198 Design Verification Tutorial 99 .register(rqcov. endtask endclass 2006 MAPLD International Conference 197 Design Verification Tutorial Testbench Environment: SystemC class top : public sc_module { public: top(sc_module_name nm) : sc_module(nm).ap(rq_cov.stop(). endfunction task execute. fpu_master m. t.master_export). endfunction // new Master FPU TLM Request Coverage function void connect(). rqcov = new(“rqcov”). join_any master. function new. wait_for_coverage(). dut = new(“fpu_tlm”).go().ap. m("master"). fpu_master master. } fpu_tlm t. master = new(“master”).analysis_export). dut("fpu_tlm"). rq_cov(“request_coverage") { m.

m_fpu_pins.blocking_master_export. Request fpu_req_cov rqcov. function new(virtual fpu_pin_if pins. apreq. endfunction endclass 2006 MAPLD International Conference Master Driver clock 200 Design Verification Tutorial 100 . rq_ap_t apreq).analysis_export ). rq_ap_t apreq.register( rqcov. rqcov = new(“rqcov”). master = new(“master”).m_fpu_pins = this. Monitor driver = new(“driver”). Monitor Request Coverage fpu_master master. virtual Coveragefpu_pin_if m_fpu_pins.m_fpu_pins = pins.apreq. this. this. typedef analysis_port #(fpu_request) rq_ap_t. endfunction // new FPU Master Driver FPU RTL clock RTL function void connect().Transaction-Level → RTL Testbench Request Coverage Monitor Master Driver FPU RTL clock 2006 MAPLD International Conference 199 Design Verification Tutorial Transaction-Level → RTL Testbench class fpu_env extends avm_env. driver. master.master_port = driver. fpu_driver driver.

transaction type round_t r.b. req = new($bitstoshortreal(a). send_rqap(a.clk) (pins. bit clk. // drive clk fpu_pin_if fpu_pins(clk).). op. r = round_t’(pins. Class parameterized by op_t op. . property mon_request. initial my_env. endproperty assert property (mon_request). op_t op. op=op_t’(pins.do_test(). clkgen clkgen(clk).op. endmodule function void send_rqap(logic[31:0] a. round_t r)...b.fpu_op). Monitor Request Coverage analysis_port #(fpu_request) req_ap = new().clk).opa. $bitstoshortreal(b). 2006 MAPLD International Conference 201 Design Verification Tutorial endfunction Master Driver FPU RTL clock Capture bus signals to local variables within assertion Send captured transaction to analysis_port Top-Level Testbench module top.opb. req_ap. logic [31:0] a.clk_i(fpu_pins.rmode)) |-> (pins. a=pins. b=pins.opa_i(fpu_pins. round).write(req).ready[->1]. @(posedge pins.b.Module-Based Monitor module fpu_monitor_mon(interface. fpu_env my_env = new(fpu_pins.. fpu_request req. monitor.opa).r)).monitor_mp pins). fpu_monitor_mon monitor(fpu_pins). bit clk. endmodule RTL DUT can even be a VHDL model Master Driver FPU RTL Request Coverage Monitor clock 2006 MAPLD International Conference 202 Design Verification Tutorial 101 . fpu fpu_dut(.start.req_ap ).

Monitors and Assertions • Module-based monitors are the perfect place to put assertions – Assertions can automatically check proper DUT behavior on the interface – Assertions can automatically collect coverage information – Assertions are not allowed in classes • AVM Module-based monitors communicate with the rest of the testbench via TLM interfaces – Monitors can be protocol checkers and/or transaction monitors – Coverage and assertions fully integrated into the testbench – Can still be used in formal verification 2006 MAPLD International Conference 203 Design Verification Tutorial Golden TLM in Testbench Analysis export for requests Request Coverage Reuse most of the RTL testbench TLM Adapter FPU TLM Master port Analysis port for responses Compare responses from RTL and TLM Monitor Response Compare Master Driver FPU RTL Match Coverage clock 2006 MAPLD International Conference 204 Design Verification Tutorial 102 .

Practical Example Rock-Paper-Scissors Arbiter 2006 MAPLD International Conference 205 Design Verification Tutorial RPS AVM Architecture Scoreboard Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master Checker Checker 2006 MAPLD International Conference 206 Design Verification Tutorial 103 .

pins1_if.clk_if. pins2_if). if (win1) pins1_if. (pins2_if.s) | (pins1_if. end endmodule 2006 MAPLD International Conference 207 clk_if dut_pins_if DUT dut_pins_if Design Verification Tutorial RPS .p & pins2_if. win2. // For debug win1 <= ((pins1_if.go & win2 <= ((pins2_if. fork cr. else if (win2) pins2_if. tie_score <= 0.s & pins1_if. 2? Consume time or // int tie_score.clk_if.score + 1.p) | assign (pins1_if. always @(posedge both_ready) begin bit win1.clk).clk_if.dut_busy <= 1.go). check1(pins1_if).p & pins1_if. $finish. end endmodule 2006 MAPLD International Conference 208 Design Verification Tutorial 104 . @(posedge pins1_if. import rps_env_pkg::*.r)). rps_clock_reset cr(clk_if).s) | pins2_if. checker checker clk_if clock_reset ENV initial begin env = new(pins1_if.r)). pins2_if). // Who wins? 1 #3.score + 1. else tie_score <= tie_score + 1.do_test.s & pins2_if.p) | initial (pins2_if. join_none env. check2(pins2_if).score <= pins1_if.run(). rps_dut rps_checker rps_checker rps_env dut(pins1_if.DUT module rps_dut( rps_dut_pins_if pins1_if. pins2_if).score <= pins2_if. rps_dut_pins_if pins1_if(clk_if). both_ready = (pins1_if.RPS – top module top_class_based.r & pins1_if. rps_dut_pins_if pins2_if(clk_if).r & pins2_if. rps_clk_if clk_if(). Scoreboard Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master pins1_if. env.dut_busy <= 0.

Scissors.rst) pins_if.pins_if. Only one of RPS is 1 property valid_play.score}) == 0. // Rock. reg go. property no_meta. p.p. endproperty assert_valid_play: assert property (valid_play). s. Paper. @(posedge clk_if. int score.pins_if.go |=> $isunknown({pins_if.RPS – DUT Pins Interface interface rps_dut_pins_if(rps_clk_if clk_if). // 1.p}) == 1. // Posedge -> the DUT should // start calculating. // Mutually exclusive.pins_if. // 2.r. rps_t play.s.rst) pins_if.r. // # of times THIS player has won. pins_if. RPS and score are never unknown on // posedge of clk.clk) disable iff (clk_if.pins_if.go |=> $countones({pins_if.s. Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 209 Design Verification Tutorial RPS – DUT Protocol Checkers module rps_checker(rps_dut_pins_if pins_if). endproperty assert_no_meta: assert property (no_meta). import rps_env_pkg::*. endinterface Scoreboard // Enum used only in debug. @(posedge clk_if. reg r. endmodule Scoreboard Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 210 Design Verification Tutorial 105 .clk) disable iff (clk_if.

rps = this. if (a. clone.rps. ROCK. endfunction function rps_c clone. endfunction endclass 2006 MAPLD International Conference 211 Design Verification Tutorial RPS . return rps. class rps_c extends avm_transaction. else return 0.Transactors Scoreboard Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 212 Design Verification Tutorial 106 . } int score. PAPER.name. clone = new.Transaction typedef enum bit[1:0] {IDLE. constraint illegal { rps != IDLE. rand rps_t rps.rps) return 1.rps == this. endfunction function bit comp(input rps_c a).RPS . function string convert2string. SCISSORS} rps_t.

pins_if.rps.clk_if.r = 1.clk_if.clk_if.p. {pins_if.rps) ROCK: pins_if. rps_c transaction. endcase pins_if.p = 1.s} = 3'b000. forever @(posedge pins_if. pins_if. end endtask endclass 2006 MAPLD International Conference 214 Design Verification Tutorial 107 .clk) if (nb_get_port.p.go = 1. endfunction Scoreboard Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 213 Design Verification Tutorial RPS .r. PAPER: pins_if.clk).RPS .go = 0. case (transaction. function new(string nm = "".new(nm.Driver task run. pins_if.go = 0.s = 1. @(posedge pins_if. tlm_nonblocking_get_if #(rps_c) nb_get_port. pins_if.s} = 3'b000.p. avm_named_component p = null). SCISSORS: pins_if. pins_if. {pins_if. pins_if. p).s} = 3'b000.try_get(transaction)) begin pins_if. super. pins_if. pins_if. @(negedge pins_if.r. virtual rps_dut_pins_if pins_if.r.Driver class rps_driver extends avm_verification_component. @(posedge pins_if. //Debug.play = transaction.clk).rst). {pins_if.clk_if.

p).r.dut_busy) ap.rps = ROCK.clk_if. forever @(posedge pins_if. rps_c transaction = new.write(pins2transaction()). case ({pins_if. endfunction task run.s}) 3'b100: transaction.rps = PAPER. avm_named_component p = null).Coverage & Scoreboard Scoreboard Coverage Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 216 Design Verification Tutorial 108 .score = pins_if.pins_if.p. endtask endclass Stimulus Gen/ Master FIFO Scoreboard Coverage Monitor Monitor Driver DUT Driver Stimulus Gen/ Master FIFO 2006 MAPLD International Conference 215 Design Verification Tutorial RPS .Monitor class rps_monitor extends avm_verification_component. 3'b001: transaction.rps = SCISSORS.RPS . ap = new.pins_if. virtual rps_dut_pins_if pins_if. super. 3'b010: transaction. return transaction. endfunction function rps_c pins2transaction.new(nm. analysis_port #(rps_c) ap. function new(string nm = "". endcase transaction.score.

t2rps.new(nm. t2rps = t2. t1rps = t1. rps_t t1rps. report_the_play("COV". t2). analysis_export2 = fifo2.Coverage function new(string nm = "". coverpoint t1rps { ignore_bins illegal = { IDLE }.analysis_export. this).RPS . analysis_export1 = fifo1. fifo2. t2. fifo2 = new("fifo2". local analysis_fifo #(rps_c) fifo1. endfunction task run. forever begin fifo1.sample. t2rps. this).rps. } coverpoint t2rps { ignore_bins illegal = { IDLE }.Coverage class rps_coverage extends avm_verification_component. super. endfunction 2006 MAPLD International Conference 217 Design Verification Tutorial RPS . rps_c t1. rps_cover.get(t1). end endtask endclass Coverage Scoreboard Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 218 Design Verification Tutorial 109 .rps. fifo1 = new("fifo1". fifo2. p).analysis_export.get(t2). rps_cover = new. } cross t1rps. analysis_export2. analysis_if #(rps_c) analysis_export1. t1. avm_named_component p = null). Coverage Scoreboard covergroup rps_cover. endgroup Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master function void export_connections.

analysis_if #(rps_c) analysis_export1. else if (win2) score2 += 1. ROCK && t2. t2. if ((t1. tie_score = 0.rps == SCISSORS) | (t2. analysis_export2 = fifo2. update_and_check_score(). Stimulus Gen/ Master FIFO Coverage Scoreboard Monitor Monitor Driver DUT Driver FIFO Stimulus Gen/ Master int limit.score >= limit)) test_done = 1.score >= limit) || (t2. score1 = 0. if (score1 != t1.score=%0d". endfunction task run. fifo2. this). //Gets waited on externally.RPS . 2006 MAPLD International Conference 220 Design Verification Tutorial 110 . t2). Monitor Monitor Stimulus Gen/ Master FIFO Driver DUT Driver FIFO Stimulus Gen/ Master if (win1) score1 += 1.rps == SCISSORS) | SCISSORS && t2. function void export_connections.score) begin $sformat(str. analysis_export1 = fifo1. super. analysis_export2.rps == ROCK && t1. forever begin fifo1.new(nm. reg test_done.analysis_export.score). bit win1.rps == new score. t2.score) begin $sformat(str. // Check for done. "MISMATCH . int score1. string str.rps == (t1. win2. Coverage Scoreboard // Validate the score.Scoreboard class rps_scoreboard extends avm_verification_component. avm_report_message("SBD".score2=%0d. t1. score2. end endtask 219 Design Verification Tutorial 2006 MAPLD International Conference RPS – Scoreboard(2) local function void update_and_check_score. avm_named_component p = null). score2. t2. tie_score.rps == PAPER) | (t2. end if (score2 != t2. local analysis_fifo #(rps_c) fifo1. report_the_play("SBD".get(t2).rps == PAPER && t1.analysis_export. score1.rps == PAPER) | PAPER && t2. end // Calculate win1 = ((t1. endfunction endclass win2 = ((t2.score=%0d". str). this). test_done = 0. //Gets set at configure time. str). avm_report_message("SBD".rps == ROCK)).rps == ROCK)). "MISMATCH . rps_c t1. t1. t1. function new(string nm = "". fifo2.score1=%0d. endfunction fifo1 = new("fifo1". score2 = 0.rps == (t1. else tie_score +=1. p).score).get(t1). fifo2 = new("fifo2".rps == SCISSORS && t1.

function new( virtual rps_dut_pins_if pins1_if. = m_pins2_if.analysis_export1). avm_stimulus #(rps_c) tlm_fifo #(rps_c) rps_driver rps_monitor rps_scoreboard rps_coverage s1.register(sb. d1 = new("rps_driver1").analysis_export1).pins_if m2.pins_if m1.blocking_put_port = f2. s2. endfunction 2006 MAPLD International Conference 222 Stimulus Gen/ Master FIFO Monitor Monitor Driver DUT Driver FIFO Stimulus Gen/ Master Design Verification Tutorial 111 .analysis_export2). m1 = new("rps_monitor1").blocking_put_export.analysis_export2).register(c.register(c. d2. c.nonblocking_get_export.nonblocking_get_export. f2. f1.pins_if = m_pins2_if. // Hook up 2 s2. m1. m2. d1. s2 = new("rps_stimulus2"). m_pins2_if.pins_if = m_pins1_if. d2 = new("rps_driver2").ap. m1.blocking_put_port = f1.nb_get_port = f2. Scoreboard Coverage m2.RPS – rps_env class rps_env extends avm_env. = m_pins1_if.blocking_put_export. endfunction 2006 MAPLD International Conference 221 Design Verification Tutorial RPS – rps_env function void connect. f2 = new("rps_fifo2"). c = new("rps_coverage"). m2 = new("rps_monitor2"). s1 = new("rps_stimulus1"). sb. m2.register(sb. sb. d1. f1 = new("rps_fifo1"). pins2_if). // Hook up 1 s1.nb_get_port = f1.limit = 10. endfunction function void configure. m_pins2_if = pins2_if. Stimulus FIFO Gen/ Master Stimulus Gen/ Master Driver DUT Driver FIFO m_pins1_if = pins1_if. local virtual rps_dut_pins_if m_pins1_if. d2. d2.ap. Monitor Monitor Scoreboard Coverage sb = new("rps_scoreboard").ap.ap. d1. m1.

s1. join endtask task terminate.RPS – rps_env task execute. s2. avm_report_message("coverage report".test_done).stop_stimulus_generation(). @(posedge sb. fork s1.generate_stimulus()..stop_stimulus_generation(). s2. str). "%d %% covered". endtask function void report. terminate. endfunction Stimulus Gen/ Master FIFO Scoreboard Coverage Monitor Monitor Driver DUT Driver FIFO Stimulus Gen/ Master 2006 MAPLD International Conference 223 Design Verification Tutorial Summary 2006 MAPLD International Conference 224 Design Verification Tutorial 112 . string str..get_inst_coverage()).generate_stimulus(). c.rps_cover. $sformat(str.

• Productivity means better coverage in less time • Faster simulation = same coverage in less time • New technologies help find more bugs

Verification Productivity

– Functional Coverage, Testbench Automation, Assertions

• Focused methodology applies these technologies more effectively
Effective Methodology
Real Goal Goal

Functional Coverage

Faster Simulator

New Technologies

Verification Time
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The Advanced Verification Methodology (AVM) • Purpose:
– To help users build verification environments to take advantage of our technology
Scoreboards

Coverage

• The Ingredients:
– A library of modular, reusable Verification Components – Examples – Documentation

Stimulus Generators

Protocol Drivers

Monitors & Assertions

• Infrastructure details built-in so you don’t have to worry about them • Open-Source means you are free to use them, with full access to all the source code
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AVM Value Statement
• Shorten the development time of the TB infrastructure
– The Verification Cookbook shows you how to do this – Verification IP – Coding guidelines – Multiple abstraction levels
Slope = Test effectiveness

• Improve the effectiveness of tests at verifying features
– – – – CR simulation (incl. solver) Functional coverage ABV, Formal Model Checking Dynamic Formal

TB Development time

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Assumptions:
10 .75

AVM ROI
Debug time
.9 man-days/bug Find bugs sooner

Gates/loc Bugs/100loc Bugs/M gates
750

Labor
$800/man-day $16,000/man-month

Actual Results:

Description ABV TLM TLM TB TBA
Debug savings

Factor
25% avg. reduction

Example

Impact

Savings
34 manmonths 63 manmonths 16 manmonths 128 manmonths

3000 bugs/ 3000 x .25 x .9= 4M gates 675 man-days 3000 x .07 ≈ (3000 – 200) x .07 Bug design & 200 bugs/4M .9 = reduction verification gates 2520 m-d 32 man-months Productivity 2x 32/2 = (Verilog directed tests) CR test 5x 3.2 man-months (16-3.2) x 10 = generation 10 engineers 100% Coverage

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AVM ROI Summary
• Assertion-Based Verification
– Find bugs earlier; Fix bugs faster – 34m-m * $16k = $540,000

• Transaction Level Modeling
– Reduce verification time; Improve Reuse – 79m-m * $16K = $1,264,000

• Testbench Automation
– Improve verification productivity – 128m-m * $16K = $2,048,000

• Reinvest savings to improve quality and completeness • Being able to sleep the night you tape-out
– Priceless
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Reuse Across Projects
AHB PCI Coverage

• Testbench topology is application-specific
– Reuse TLM components – Same connections between TLM components

Scoreboard

Test Controller

AHB PCI Monitor

• Transactors are protocolspecific
– Scoreboard tracks correct behavior – Coverage tracks protocol corner-cases

Stimulus

AHB PCI Driver

AHB PCI DUT

• Components can easily be swapped since they use the same interfaces
Design Verification Tutorial

2006 MAPLD International Conference

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active/passive Harness4 Harness3 Harness2 … System/ Subsystem BlkB DUT Block Harness 2006 MAPLD International Conference 232 Design Verification Tutorial 116 .Reuse Within Projects • Reuse block-level TB in system TB • Gather block-level TB into a “harness” – Contains all necessary block-level verification components • Extend harness as necessary to communicate with system-level testbench Configuration Interface Block-level test controller DUT Block Harness 2006 MAPLD International Conference 231 Design Verification Tutorial “Block-to-Top” Reuse • System-Level testbench coordinates behavior of block-level harnesses • Configuration interfaces customize behavior of each harness – How many and what components to instantiate – Turn components on/off.

2 AVM Infrastructure Questa Vanguard Program Need All Three to Accelerate Adoption of New Flows 2006 MAPLD International Conference 233 Design Verification Tutorial Questa Summary Mentor’s Functional Verification Platform Questa Vanguard Partners Questa Verification Library (QVL) Advanced Verification Methodology C-R Coverage Test Generation TLM Assertions Sfw Test Of Hdw High Performance Mixed Language Kernel Reusable Verification IP for Productivity VHDL PSL • Mentor’s solutions have proven ROI in real designs 2006 MAPLD International Conference 234 Design Verification Tutorial 117 .Questa Verification Advances on Three Fronts Tools Methodology Questa 6.

Questa Vanguard Program • A group of well established companies from around the world working with Mentor Graphics to accelerate the adoption of advanced verification techniques and methodologies • QVP Partners offer – – – – Integrations into Questa Training Verification IP Consulting. Conversion and Migration services • QVP Partners all support Questa and the AVM 2006 MAPLD International Conference 235 Design Verification Tutorial Questa Vanguard Program Company Listing (July 2006) • • • • • • • • • • • • • Ace Verification ARM Ltd Averant Doulos Denali Software eInfoChips Expert I/O HDL Design House hd Lab Interra Systems Intrinsix Mu Electronics Nobug 2006 MAPLD International Conference • • • • • • • • • • • Novas nSys PSI Electronics Paradigm Works Real Intent Scaleo Chip SiMantis Sonics SpiraTech Sunburst Design Sutherland HDL 236 • • • • • • • Summit SyoSil TrustIC Design VeriEZ Solutions Vericine Verilab Vhdl Cohen Publishing • XtremeEDA • Willamette HDL Design Verification Tutorial 118 .

com/go/cookbook 2006 MAPLD International Conference 238 Design Verification Tutorial 119 .Advanced Verification Methodology Adoption AVM Overview AVM Jumpstart Consulting • Verification Analysis • Subject Matter Knowledge Transfer • Methodology Planning • Implementation & Mentoring Deploy AVM to Design Teams Pilot Environment Configured AVM Assessment • • • • • Verification Goals Requirements Current State Recommendations IP Migration Plan Installation IP Migration Consulting • Pilot AVM • Capture “lessons learned” Phase 2 Phase 3 Production Use Phase 1 2006 MAPLD International Conference 237 Design Verification Tutorial The Verification Cookbook • The Recipes you need to know • Introduces Advanced Verification topics incrementally • Use or modify the examples provided as needed • To download the AVM Cookbook please go to www.mentor.

Questions? 2006 MAPLD International Conference 239 Design Verification Tutorial 120 .

test_done = 0. bit win1.score. super. if (a.rps == SCISSORS && t2. See the License for the // specific language governing permissions and // limitations under the License. analysis_export2 = fifo2. reg test_done. if (score1 != t1. fifo1 = new("fifo1".analysis_export. avm_named_component p = null). report_the_play("SBD". bit clk. endfunction function rps_c clone.score). t1. analysis_if #(rps_c) analysis_export1. function new(string nm = "". analysis_export1 = fifo1.new(nm.rps) return 1.rps == PAPER && t1.rps == PAPER) | (t2. rps_c t1.rps == PAPER) | (t1. t1. return rps.rps. end // Calculate new score. t2. rst. endfunction function void export_connections. //Gets waited on externally. Issue 1.rps = this. t2.score) begin $sformat(str.analysis_export.name. end endtask endclass 8 class rps_scoreboard extends avm_verification_component. typedef enum bit[1:0] {IDLE.rps == SCISSORS && t1.rps == ROCK && t2. software distributed under the License is // distributed on an "AS IS" BASIS. function string convert2string. .get(t2).09/01/06 13:35:26 //<>=================================================<> // solution08-rps/t. endgroup Solutions.sv //<>=================================================<> // $Id: t. end if (score2 != t2. Score2=%0d".analysis_export. endfunction task run.rps.score). PAPER. t1. rand rps_t rps.org/licenses/LICENSE-2.v 1.score). t1. rps_c t1. local analysis_fifo #(rps_c) fifo1. you may not use this file except // in compliance with the License.apache. t2). avm_report_message(where. endfunction endclass function void report_the_play( string where. analysis_export1 = fifo1. t1. } int score. str). string str. avm_named_component p = null).rps. WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND. fifo2.score=%0d". clone = new. fifo2.rps == SCISSORS) | (t1. t2. forever begin fifo1. //----------------------------------------------------/* * rps-class-based . * Based on code created by David Jones at Xtreme EDA * for an article in Verification Horizons Q4 2005 * Vol. win1 = ((t1. score2.name. endfunction class rps_coverage extends avm_verification_component.score1=%0d. endfunction function new(string nm = "". update_and_check_score(). tie_score = 0. win2 = ((t2. this). endfunction function bit comp(input rps_c a).score) begin $sformat(str. clone. dut_busy. either // express or implied.1 2006/09/01 16:09:50 redelman Exp $ //----------------------------------------------------// Copyright 2005-2006 Mentor Graphics Corporation // // Licensed under the Apache License. Paper. fifo2. else return 0. rps_t t1rps. forever begin fifo1. win2. p). */ interface rps_clk_if. rps_c t2). score1 = 0. covergroup rps_cover.0 // (the "License").sv function void export_connections. score2. endinterface package rps_env_pkg. this).rps.rps == ROCK)).rps == SCISSORS) | (t2.get(t1). str). // Validate the score. "MISMATCH . analysis_export2. class rps_c extends avm_transaction.rps.rps == PAPER && t2. this). t2). t2.Rock. fifo2. SCISSORS} rps_t. analysis_export2 = fifo2. t2. fifo2 = new("fifo2". this).Score1=%0d. You may obtain a // copy of the License at // // http://www. rps_cover. local analysis_fifo #(rps_c) fifo1.rps == ROCK && t1. } coverpoint t2rps { ignore_bins illegal = { IDLE }.new(nm.0 // // Unless required by applicable law or agreed to in // writing. t1. t2rps.score=%0d". tie_score. str). t2. "(%s. super. end endtask local function void update_and_check_score. constraint illegal { rps != IDLE.analysis_export.rps == this. Version 2. int score1. fifo1 = new("fifo1". Scissors Example. 1. fifo2 = new("fifo2".get(t2). t2rps. score1. rps_c t1. coverpoint t1rps { ignore_bins illegal = { IDLE }. string str. } cross t1rps.sv. p). score2 = 0. avm_report_message("SBD".rps == ROCK)). ROCK. analysis_export2.sample. int limit. import avm_pkg::*. endfunction task run. //Gets set at configure time.score2=%0d. $sformat(str. entitled "A Reusable SystemVerilog * Testbench in Only 300 Lines of Code".name. t1rps = t1. analysis_if #(rps_c) analysis_export1. %s) .get(t1). "MISMATCH . rps_cover = new. t2rps = t2. report_the_play("COV". avm_report_message("SBD".

m2. task run( int reset_hold = 4 . rps_driver d1.clk_if. p). pins_if.register(sb. SCISSORS: pins_if.pins_if.nonblocking_get_export.register(c.analysis_export1). return transaction. case (transaction. c. endfunction task run. i. {pins_if.clk_if. c.s = 1.r. = m_pins1_if.rps = PAPER. endfunction task run.clk). m1 = new("rps_monitor1"). else tie_score +=1. super.clk = !i.ap.. super. join endtask task terminate.p. pins_if.blocking_put_export. 3’b001: transaction. pins_if.go = 0. $sformat(str. f1 = new("rps_fifo1").score. rps_monitor m1. @(negedge pins_if.pins_if = m_pins1_if. m_pins2_if = pins2_if.clk = 0. if ((t1.play = transaction. m_pins2_if. m2. = m_pins2_if.sv rps_scoreboard rps_coverage sb. p). tlm_fifo #(rps_c) f1. f2 = new("rps_fifo2").try_get(transaction)) begin pins_if. int count = 0 ).rps = SCISSORS. #half_period. forever @(posedge pins_if. {pins_if. endfunction endclass Solutions.dut_busy) ap. endfunction function rps_c pins2transaction. avm_named_component p = null).p.blocking_put_port = f1.clk). c = new("rps_coverage"). endcase transaction.clk. virtual rps_dut_pins_if pins_if. s2. rps_c transaction = new. avm_report_message("coverage report". "%d %% covered". m2 = new("rps_monitor2"). endtask endclass class rps_env extends avm_env.r.clk_if. s1 = new("rps_stimulus1").new(nm.ap.s} = 3’b000. sb. i. pins_if.clk) if (nb_get_port.s} = 3’b000. class rps_driver extends avm_verification_component. parameter bit ACTIVE_RESET = 1. f2. s1. d2. fork s1. avm_named_component p = null).generate_stimulus(). case ({pins_if.analysis_export2).r. 9 m1.blocking_put_export.score = pins_if.pins_if = m_pins2_if. local virtual rps_dut_pins_if m_pins1_if.rst).pins_if m1. tlm_nonblocking_get_if #(rps_c) nb_get_port.clk_if.rps_cover. pins_if. d1. endfunction function new( virtual rps_dut_pins_if pins1_if. terminate. m1.rps = ROCK.clk = !i.new(nm.limit = 10. endfunction function void configure.nb_get_port = f1.pins_if m2.score >= limit) || (t2. {pins_if. rst_i++ ) begin #half_period.get_inst_coverage()).generate_stimulus(). // Check to see if we are done. d1 = new("rps_driver1").rps) ROCK: pins_if. virtual rps_dut_pins_if pins_if. rps_c transaction.r = 1. @(posedge pins_if.clk_if. int half_period = 10 .stop_stimulus_generation(). else if (win2) score2 += 1. forever @(posedge pins_if. for(int rst_i = 0.blocking_put_port = f2. pins_if. s2.p = 1.09/01/06 13:35:26 if (win1) score1 += 1.s} = 3’b000. pins_if. pins_if. str). endfunction task execute. analysis_port #(rps_c) ap.test_done).nonblocking_get_export.. end endtask endclass m2. d2.ap. // Hook up 1 s1.s}) 3’b100: transaction. ap = new. @(posedge sb.ap. function new(string nm = "".p.nb_get_port = f2. @(posedge pins_if. i.write(pins2transaction()). function new(string nm = "".pins_if. string str.analysis_export1). endtask function void report.r. end class rps_monitor extends avm_verification_component. 3’b010: transaction. i. endfunction endclass endpackage // ----------------------------------------------module rps_clock_reset(interface i ). d2.clk. // Hook up 2 s2. s2 = new("rps_stimulus2"). . //Debug. s2. function void connect.rps.p.register(sb.go = 0. PAPER: pins_if.go = 1. d1. m_pins1_if = pins1_if.score >= limit)) test_done = 1. avm_stimulus #(rps_c) s1. sb = new("rps_scoreboard").analysis_export2). d2 = new("rps_driver2"). endcase pins_if.register(c. rst_i < reset_hold. pins2_if).stop_stimulus_generation().rst = ACTIVE_RESET.

pins_if.go |=> $countones({pins_if. p.score <= pins1_if.p}) == 1.do_test.rst) pins_if.s) | (pins2_if. Paper. rps_t play.pins_if. . 10 interface rps_dut_pins_if(rps_clk_if clk_if). reg go.r. always @(posedge both_ready) begin #3. if (win1) pins1_if. bit win1.r & pins2_if. // ******************************************** endmodule initial begin env = new(pins1_if. s. RPS and score are never unknown on // posedge of clk. @(posedge clk_if.p & pins1_if. $finish.score}) == 0.r)). Only one of RPS is 1 property valid_play. env. // # of times THIS player has won.p & pins2_if.s) | (pins1_if.run(). win2.r & pins1_if.go |=> $isunknown({pins_if.s & pins1_if. pins2_if). end endtask endmodule Solutions.p) | (pins2_if.r.r)). // Consume time win1 <= ((pins1_if.go).score + 1. fork cr. pins1_if. end endmodule module rps_dut( rps_dut_pins_if pins1_if.pins_if.s.09/01/06 13:35:26 i.rst.dut_busy <= 0.p. // Posedge -> the DUT should // start calculating. rps_clock_reset cr(clk_if). endproperty assert_valid_play: assert property (valid_play).rst) pins_if. rps_dut_pins_if pins1_if(clk_if).score + 1.dut_busy <= 1.p) | (pins1_if. pins2_if). // Rock. (clk_i < count || count == 0). initial tie_score <= 0.sv rps_dut_pins_if pins2_if(clk_if). // Who wins? 1 or 2? int tie_score. end endmodule module top_class_based.rst <= !i.clk_if. rps_dut rps_checker rps_checker rps_env dut(pins1_if.clk_if. rps_clk_if clk_if(). join_none env. checker2(pins2_if).pins_if. import rps_env_pkg::*.score <= pins2_if. else if (win2) pins2_if. // ******************************************** // 2. else tie_score <= tie_score + 1. // Run the clock for(int clk_i = 0.clk) disable iff (clk_if.go & pins2_if.clk. win2 <= ((pins2_if. pins1_if. // Mutually exclusive. pins2_if). Scissors. // Enum used only in debug. endinterface module rps_checker(rps_dut_pins_if pins_if). import rps_env_pkg::*. endproperty assert_no_meta: assert property (no_meta). assign both_ready = (pins1_if. reg r. checker1(pins1_if).s & pins2_if.clk) disable iff (clk_if.clk = !i. int score.pins_if. @(posedge pins1_if. @(posedge clk_if. // For debug and reporting. clk_i++ ) begin #half_period.clk_if. // ******************************************** // Assertions ********************************* // ******************************************** // 1. property no_meta. i.clk).s.