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APB Protocol Design

CHAPTER 1
INTRODUCTION

1.1 PROJECT INTRODUCTION

The APB is part of the AMBA 3 protocol family. It provides a low-cost interface
that is optimized for minimal power consumption and reduced interface complexity.

The APB interfaces to any peripherals that are low-bandwidth and do not require
the high performance of a pipelined bus interface.

The APB has unpipelined protocol. All signal transitions are only related to the
rising edge of the clock to enable the integration of APB peripherals easily into any
design flow. Every transfer takes at least two cycles.

The APB can interface with the AMBA Advanced High-performance Bus Lite
(AHB-Lite) and AMBA Advanced Extensible Interface (AXI). You can use it to
provide access to the programmable control registers of peripheral devices

1.2 OBJECTIVE
Most of the students of Electronics Engineering are exposed to Integrated
Circuits (IC's) at a very basic level, involving SSI (small scale integration) circuits like
logic gates or MSI (medium scale integration) circuits like multiplexers, parity encoders
etc. But there is a lot bigger world out there involving miniaturization at levels so great,
that a micrometer and a microsecond are literally considered huge! This is the world of
VLSI - Very Large Scale Integration. The article aims at trying to introduce Electronics
Engineering students to the possibilities and the work involved in this field.
VLSI stands for "Very Large Scale Integration". This is the field which involves
packing more and more logic devices into smaller and smaller areas. Thanks to VLSI,
circuits that would have taken boardfulls of space can now be put into a small space
few millimetres across! This has opened up a big opportunity to do things that were not
possible before. VLSI circuits are everywhere ... your computer, your car, your brand
new state-of-the-art digital camera, the cell-phones, and what have you. All this
involves a lot of expertise on many fronts within the same field, which we will look at
in later sections. VLSI has been around for a long time, there is nothing new about it ...

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but as a side effect of advances in the world of computers, there has been a dramatic
proliferation of tools that can be used to design VLSI circuits. Alongside, obeying
Moore's law, the capability of an IC has increased exponentially over the years, in terms
of computation power, utilization of available area, yield. The combined effect of these
two advances is that people can now put diverse functionality into the IC's, opening up
new frontiers. Examples are embedded systems, where intelligent devices are put inside
everyday objects, and ubiquitous computing where small computing devices proliferate
to such an extent that even the shoes you wear may actually do something useful like
monitoring your heartbeats! These two fields are kind a related and getting into their
description can easily lead to another article.

1.3 DEALING WITH VLSI CIRCUITS


Digital VLSI circuits are predominantly CMOS based. The way normal blocks
like latches and gates are implemented is different from what students have seen so far,
but the behaviour remains the same. All the miniaturisation involves new things to
consider. A lot of thought has to go into actual implementations as well as design. Let
us look at some of the factorsinvolved.

1. Circuit Delays. Large complicated circuits running at very high frequencies have one
big problem to tackle - the problem of delays in propagation of signals through gates
and wire even for areas a few micrometers across! The operation speed is so large that
as the delays add up, they can actually become comparable to the clock speeds.
2. Power. Another effect of high operation frequencies is increased consumption of
power. This has two-fold effect - devices consume batteries faster, and heat dissipation
increases. Coupled with the fact that surface areas have decreased, heat poses a major
threat to the stability of the circuit itself.
3. Layout. Laying out the circuit components is task common to all branches of
electronics. What so special in our case is that there are many possible ways to do this;
there can be multiple layers of different materials on the same silicon, there can be
different arrangements of the smaller parts for the same component and so on.
The power dissipation and speed in a circuit present a trade-off; if we try to optimize
on one, the other is affected. The choice between the two is determined by the way we

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chose the layout the circuit components. Layout can also affect the fabrication of VLSI
chips, making it either easy or difficult to implement the components on the silicon.

1.4 INTRODUCTION TO VLSI


Very-large-scale integration (VLSI) is the process of creating integrated circuits
by combining thousands of transistor-based circuits into a single chip. VLSI began in
the Nineteen Seventies when tricky semiconductor and conversation technologies were
being developed. The microprocessor is a VLSI gadget. The term is now not as
customary as it once was, as chips have expanded in situation into the enormous
quantities of thousands of transistors. The first semiconductor chips held one transistor
each. Subsequent advances brought increasingly transistors, and, as a outcome, more
character services or techniques have been integrated above time. The primary
integrated circuits held just a few devices, possibly as many as ten diodes, transistors,
resistors and capacitors, making it possible to manufacture a number of logic gates on
a single gadget. Now known retrospectively as "small-scale integration" (SSI),
development in system ended in instruments with hundreds of common sense gates,
recognized as large-scale integration (LSI), i.E. Present technological know-how has
inspired far previous this mark and modern day microprocessors have a few hundreds
of thousands of gates and hundreds and hundreds of hundreds of thousands of special
transistors.
As of early 2008, billion-transistor processors are commercially to be had, an
instance of which is Intel's Montecito Itanium chip. That is anticipated to grow to be
more common as semiconductor fabrication strikes from the present new release of 65
nm strategies to the subsequent forty five nm generations (whilst experiencing new
challenges akin to increased version throughout process corners). A different terrific
example is NVIDIA’s 280 series GPU. This microprocessor is exact in the truth that its
1.4 Billion transistor rely, capable of a teraflop of executeance, is roughly utterly
committed to logic (Itanium's transistor rely is basically as a result of the 24MB L3
cache). Current designs, versus the earliest gadgets, use large design automation and
automatic good judgment synthesis to put out the transistors, enabling better levels of
obstacle in the resulting logic functionality. Specific excessive-executeance common
sense blocks like the SRAM phone, nevertheless, are nonetheless designed by means
of hand to make sure the absolute best effectivity (normally by way of bending or

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breaking established design ideas to receive the last little bit of executeance through
buying and selling balance).
What is VLSI?
• Integrated circuit (IC) may contain millions of transistors, both a few mm in
size
• Applications wide ranging: most electronic logic devices
Advantages of ICs above discrete components
While we will be able to be aware of integrated circuits , the houses of integrated
circuits-what we can and cannot appropriately put in an integrated circuit-mostly verify
the architecture of the complete approach. Built-in circuits strengthen procedure
characteristics in a couple of imperative methods. ICs have three key advantages above
digital circuits built from discrete components:
Measurement. Built-in circuits are so much smaller-both transistors and wires are
reduced in size to micrometer sizes, evaluated to the millimeter or centimeter scales of
discrete add-ons. Small size results in advantages in pace and power consumption,
when you consider that smaller components have smaller parasitic resistances,
capacitances, and inductances.
Speed Signals can be switched amongst logic zero and good
judgment 1 much faster within a chip than they may be able to amongst chips. Statement
inside of a chip can occur 1000's of times prior than communique amongst chips on a
printed circuit board. The excessive pace of circuits on-chip is due to their small
measurement-smaller constituent and wires have smaller parasitic capacitance to slow
down the signal.
Power consumption. Common sense operations inside a chip
also take so much less power. As soon as again, curb vigour consumption is essentially
due to the small measurement of circuits on the chip-smaller parasitic capacitances and
resistances require much less vigor to pressure them.

1.5 VLSI and SYSTEMS


These advantages of integrated circuits translate into advantages at the system level:
• Smaller physical size. Smallness is frequently an benefit in itself-consider
portable televisions or handheld cellular telephones.

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• Lower power consumption. Substitute a handful of normal parts with a single


chip decreases total power utilization. Reducing power consumption has a ripple
effect on the rest of the system: a smaller, cheaper power supply can be used;
since less power consumption means less heat, a fan may no longer be essential;
a simpler cabinet with less shielding for electromagnetic shielding may be
feasible, too.
• Reduced cost. Dropping the number of components, the power supply
requirements, cabinet costs, and so on, will inevitably reduce system cost. The
ripple effect of integration is such that the cost of a system built from custom
ICs can be less, even though the individual ICs cost more than the standard parts
they replace.
Understanding why integrated circuit technology has such profound influence
on the design of digital systems requires understanding both the technology of IC
Manufacturing and the economics of ICs and digital programs. The growing
sophistication of applications consistently pushes the design and manufacturing of
integrated circuits and electronic systems to new levels of problem. And maybe
probably the most potent characteristic of this assortment of programs is its sort-as
techniques turn out to be more difficult, we construct no longer a number of normal-
intent computer systems however an ever wider variety of designated-purpose
techniques. Our potential to take action is a testomony to our developing mastery of
each integrated circuit manufacturing and design, however the growing demands of
customers continue to test the limits of design and manufacturing

1.5.1 Asic
An Application-Exact Integrated Circuit (ASIC) is an integrated circuit (IC)
Customized for a designated use, as a substitute than supposed for general-intent use.
For illustration, a chip designed exclusively to run a cell phone is an ASIC. Intermediate
amongst ASICs and enterprise general built-in circuits, like the 7400 or the 4000 series,
are utility detailed normal merchandise (ASSPs).
As characteristic sizes have gotten smaller and design tools improved above the
years, the highest trouble (and as a consequence performance) feasible in an ASIC has
grown from 5,000 gates to above one hundred million. Cutting-edge ASICs almost
always include entire 32-bit processors, memory blocks in conjunction with ROM,

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RAM, EEPROM, Flash and different big building blocks. Such an ASIC is traditionally
termed a SoC (procedure-on-a-chip). Designers of digital ASICs use a hardware
description language (HDL), corresponding to Verilog or VHDL, to describe the
functionality of ASICs.
Field-programmable gate arrays (FPGA) are the present day-day technological
know-how for building a breadboard or prototype from common materials;
programmable good judgment blocks and programmable interconnects permit the
identical FPGA to be used in many one-of-a-kind applications. For smaller designs
and/or lower production volumes, FPGAs may be more cost effective than an ASIC
design even in production.
• An application-exact integrated circuit (ASIC) is an integrated circuit (IC) customized
for a particular use, rather than intended for general-purpose use.
• A Structured ASIC falls among an FPGA and a Standard Cell-based ASIC
• Structured ASIC’s are used mainly for mid-volume level designs
• The design task for structured ASIC’s is to map the circuit into a fixed arrangement
of known cells.
Among different arithmetic blocks, the multiplier is one of the main blocks,
which is widely used in different applications especially signal processing applications.
There are two general architectures for the multipliers, which are sequential and
parallel. While sequential architectures are low power, their latency is very large. On
the other hand, parallel architectures (such as Wallace tree and Dadda) are fast while
having high-power consumptions. The parallel multipliers are used in high-
performance applications where their large power consumptions may create hot-spot
locations on the die. Since the power consumption and speed are critical parameters in
the design of digital circuits, the optimizations of these parameters for multipliers
become critically important. Very often, the optimization of one parameter is performed
considering a constraint for the other parameter. Specifically, achieving the desired
performance (speed) considering the limited power budget of portable systems is
challenging task. In addition, having a given level of reliability may be another obstacle
in reaching the system target performance.
To meet the power and speed specifications, a variety of methods at different
design abstraction levels have been suggested. Approximate computing approaches are
based on achieving the target specifications at the cost of reducing the computation

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accuracy. The approach may be used for applications where there is not a unique answer
and/or a set of answers near the accurate result can be considered acceptable. These
applications include multimedia processing, machine learning, signal processing, and
other error resilient computations. Approximate arithmetic units are mainly based on
the simplification of the arithmetic units circuits. There are many prior works focusing
on approximate multipliers which provide higher speeds and lower power
consumptions at the cost of lower accuracies. Almost, all of the proposed approximate
multipliers are based on having a fixed level of accuracy during the runtime. The
runtime accuracy re configurability, however, is considered as a useful feature for
providing different levels of quality of service during the system operation. Here, by
reducing the quality (accuracy), the delay and/or power consumption of the unit may
be reduced. In addition, some digital systems, such as general purpose processors, may
be utilized for both approximate and exact computation modes. An approach for
achieving this feature is to use an approximate unit along with a corresponding
correction unit. The correction unit, however, increases the delay, power, and area
overhead of the circuit. Also, the error correction procedure may require more than one
clock cycle, which could, in turn, slowdown the processing further.
In this paper, we present four dual-quality reconfigurable approximate 4:2
compressors, which provide the ability of switching between the exact and approximate
operating modes during the runtime. The compressors may be utilized in the
architectures of dynamic quality configurable parallel multipliers .The basic structures
of the proposed compressors consist of two parts of approximate and supplementary.
In the approximate mode, only the approximate part is active whereas in the exact
operating mode, the supplementary part along with some components of the
approximate part is invoked.

1.6 APPROXIMATE COMPUTING


ATPG is an electronic design automation method/technology used to recognize
whether the circuit is fault free or faulty. To verify the functionality of the circuit/device
after manufacturing some test patterns are applied to the CUT. As the technology is
shrinking in the IC manufacturing process multiple processing units (cores) are placed
on a single chip as well as large amounts of on chip memory but these developments
offer high processing power. While previously proposed procedures are very effective
they are inherently non-parallel and thus, cannot perform automatic parallelization
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using sophisticated compilers. In the fault portioning is focused to increase the fault
coverage. After that parallel ATPG has been proposed which uses on-chip multi-core
era, but the ATPG components among multiple processing units are placed on the same
chip. Next various parallel ATPG methods such as circular pipeline parallel and GPU
based ATPGs are came into existence but they are having some disadvantages like same
test sets are re-generating each time and limits the speed-up scalability.
In this work we propose a parallel test pattern generation methodology which
uses the shared-memory multi-core systems geared towards high speed. To generate
the pseudo random test patterns Low Power LFSR is used which consumes less power
and delay. In Low Power LFSR the patterns are in Gray code by which switching
activity less compared to LFSR.

1.7 DIGITAL SIGNAL PROCESSING

Digital signal processing (DSP) is the use of digital processing, such as by


computers or more specialized digital signal processors, to perform a wide variety of
signal processing operations. The signals processed in this manner are a sequence of
numbers that represent samples of a continuous variable in a domain such as time,
space, or frequency.

Digital signal processing and analog signal processing are subfields of signal
processing. DSP applications include audio and speech processing, sonar, radar and
other sensor array processing, spectral density estimation, statistical signal processing,
digital image processing, signal processing for telecommunications, control systems,
biomedical engineering, seismology, among others.

DSP can involve linear or nonlinear operations. Nonlinear signal processing is


closely related to nonlinear system identification[1] and can be implemented in the time,
frequency, and spatio-temporal domains.

The application of digital computation to signal processing allows for many advantages
over analog processing in many applications, such as error detection and correction in
transmission as well as data compression.[2] DSP is applicable to both streaming data
and static (stored) data.

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CHAPTER 2

XILINX SOFTWARE

2.1 SOFTWARE REQUIREMENTS

The following requirements are used in this project

2.1.1 Personal Computer

Pc with windows 10, windows 8, and windows 7 are used to install the
software which we used to implement the project. In our project we implemented on
windows 8 and windows 10 of 64 kb.

2.1.2 About Xilinx

Xilinx ISE (Integrated Synthesis Environment) is a software tool produced


by Xilinx for synthesis and analysis of HDL designs, enabling the developer
to synthesize ("compile") their designs, perform timing analysis examine RTL
diagrams, simulate a design's reaction to different stimuli, and configure the target
device with the programmer

Xilinx ISE is a design environment for FPGA products from Xilinx, and is
tightly-coupled to the architecture of such chips, and cannot be used with FPGA
products from other vendors. The Xilinx ISE is primarily used for circuit synthesis and
design, while ISIM or the Models in sim logic simulator is used for system-level
testing. Other components shipped with the Xilinx ISE include the Embedded
Development Kit (EDK), a Software Development Kit (SDK) and Chip Scope Pro.

Since 2012, Xilinx ISE has been discontinued in favor of Viva do Design Suite, that
serves the same roles as ISE with additional features for system on a chip development.
Xilinx released the last version of ISE in October 2013 (version 14.7), and states that
"ISE has moved into the sustaining phase of its product life cycle, and there are no more
planned ISE releases."

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2.1.3 Systems Requirements

Fig 2.1 Hardware and Software requirement

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2.1.4 Xilinx Family

List of family which are present in the Xilinx software

• XA Spartan-7 FPGA Family


• Virtex UltraScale+
• Kintex UltraScale+
• Virtex UltraScale
• Kintex UltraScale
• Virtex-7
• Virtex-7Q
• Kintex-7
• Kintex-7Q
• Artix-7
• Artix-7Q
• Spartan-6
• Spartan-7 FPGA Family
• Spartan-3
• Virtex-6Q
• Spartan-6Q
• Virtex-5Q
• Virtex-5QV
• Virtex-4Q
• Virtex-4QV
• XA Artix-7 FPGA
• XA Spartan-6
• XA Spartan-3A
• XA Spartan-3A DSP
• XA Spartan-3E

2.2 CODE LANGUAGE


Verilog, standardized as IEEE 1364, is a hardware description language (HDL)
used to model electronic systems. It is most commonly used in the design and
verification of digital circuits at the register-transfer level of abstraction. It is also used
in the verification of analog circuits and mixed-signal circuits, as well as in the design
of genetic circuits.

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2.2.1 Verilog Overview

Hardware description languages such as Verilog are similar


to software programming languages because they include ways of describing the
propagation time and signal strengths (sensitivity). There are two types of assignment
operators; a blocking assignment (=), and a non-blocking (<=) assignment. The non-
blocking assignment allows designers to describe a state-machine update without
needing to declare and use temporary storage variables. Since these concepts are part
of Verilog's language semantics, designers could quickly write descriptions of large
circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit
designers who were already using graphical schematic capture software and specially
written software programs to document and simulate electronic circuits.

The designers of Verilog wanted a language with syntax similar to the C


programming language, which was already widely used in engineering software
development. Like C, Verilog is case-sensitive and has a basic preprocessor (though
less sophisticated than that of ANSI C/C++). Its control flow keywords (if/else, for,
while, case, etc.) are equivalent, and its operator precedence is compatible with C.
Syntactic differences include: required bit-widths for variable declarations,
demarcation of procedural blocks (Verilog uses begin/end instead of curly braces {}),
and many other minor differences. Verilog requires that variables be given a definite
size. In C these sizes are assumed from the 'type' of the variable (for instance an integer
type may be 8 bits).

A Verilog design consists of a hierarchy of modules. Modules


encapsulate design hierarchy, and communicate with other modules through a set of
declared input, output, and bidirectional ports. Internally, a module can contain any
combination of the following: net/variable declarations (wire, reg, integer,
etc.), concurrent and sequential statement blocks, and instances of other modules (sub-
hierarchies). Sequential statements are placed inside a begin/end block and executed in
sequential order within the block. However, the blocks themselves are executed
concurrently, making Verilog a dataflow language.

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Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and signal strengths (strong, weak, etc.). This system allows abstract
modeling of shared signal lines, where multiple sources drive a common net. When a
wire has multiple drivers, the wire's (readable) value is resolved by a function of the
source drivers and their strengths.

A subset of statements in the Verilog language are synthesizable. Verilog


modules that conform to a synthesizable coding style, known as RTL (register-transfer
level), can be physically realized by synthesis software. Synthesis software
algorithmically transforms the (abstract) Verilog source into a net list, a logically
equivalent description consisting only of elementary logic primitives (AND, OR, NOT,
flip-flops, etc.) that are available in a specific FPGA or VLSI technology. Further
manipulations to the net list ultimately lead to a circuit fabrication blueprint (such as
a photo mask set for an ASIC or a bit stream file for an FPGA).

2.3 SPECIFICATIONS OF CODE

2.3.1 Begining

Verilog was one of the first popular hardware description languages to be


invented. It was created by Prabhu Goel, Phil Moorby and Chi-Lai Huang and Douglas
Warmke between late 1983 and early 1984. Chi-Lai Huang had earlier worked on a
hardware description LALSD, a language developed by Professor S.Y.H. Su, for his
PhD work. The wording for this process was "Automated Integrated Design Systems"
(later renamed to Gateway Design Automation in 1985) as a hardware modeling
language. Gateway Design Automation was purchased by Cadence Design Systems in
1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-
XL, the HDL-simulator that would become the de facto standard (of Verilog logic
simulators) for the next decade. Originally, Verilog was only intended to describe and
allow simulation, the automated synthesis of subsets of the language to physically
realizable structures (gates etc.) was developed after the language had achieved
widespread usage.

Verilog is a portmanteau of the words "verification" and "logic".

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2.3.2 Verilog– 95

With the increasing success of VHDL at the time, Cadence decided to make the
language available for open standardization. Cadence transferred Verilog into the
public domain under the Open Verilog International (OVI) (now known as Accellera)
organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-
1995, commonly referred to as Verilog-95.

In the same time frame Cadence initiated the creation of Verilog-A to put
standards support behind its analog simulator Spectre. Verilog-A was never intended
to be a standalone language and is a subset of Verilog-AMS which encompassed
Verilog-95.

2.3.3 V 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies


that users had found in the original Verilog standard. These extensions became IEEE
Standard 1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit


support for (2's complement) signed nets and variables. Previously, code authors had to
perform signed operations using awkward bit-level manipulations (for example, the
carry-out bit of a simple 8-bit addition required an explicit description of the Boolean
algebra to determine its correct value). The same function under Verilog-2001 can be
more succinctly described by one of the built-in operators: +, -, /, *, >>>. A
generate/end generate construct (similar to VHDL's generate/end generate) allows.

Verilog-2001 to control instance and statement instantiation through normal


decision operators (case/if/else). Using generate/end generate, Verilog-2001 can
instantiate an array of instances, with control over the connectivity of the individual
instances. File I/O has been improved by several new system tasks. And finally, a few
syntax additions were introduced to improve code readability (e.g. always, @*, named
parameter override, C-style function/task/module header declaration).

Verilog-2001 is the version of Verilog supported by the majority of


commercial EDA software packages.

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2.3.4 Verilog 2005

Not to be confused with System Verilog , Verilog 2005 (IEEE Standard 1364-
2005) consists of minor corrections, spec clarifications, and a few new language
features (such as the uwire keyword).

A separate part of the Verilog standard, Verilog-AMS, attempts to integrate


analog and mixed signal modeling with traditional Verilog.

2.3.5 System Verilog

The advent of hardware verification languages such as Open Vera, and


Verisity's e language encouraged the development of Superlog by Co-Design
Automation Inc (acquired by Synopsys). The foundations of Superlog and Vera were
donated to Accellera, which later became the IEEE standard P1800-2005: System
Verilog.

System Verilog is a superset of Verilog-2005, with many new features and


capabilities to aid design verification and design modeling. As of 2009, the System
Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE
Standard 1800-2009). The current version is IEEE standard 1800-2017.

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2.4 VERILOG OPERATORS

2.4.1 List Of Verilog Operators

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Fig 2.2 Verilog Operators

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CHAPTER 3
BLOCK DIAGRAM AND ITS TRANSFER STATES

3.1 AMBA BUS ARCHITECTURE

Fig:3.1 AMBA Bus Architecture


The block diagram consists of following blocks such as AHB, ASB,
UART,PIO, APB Bridge.
The APB is the member of the AMBA 3 protocol family which implements a low cost
interface which minimizes the power consumption and reduces the interface
complexity. Since APB has unpipelined protocol. Therefore, it interfaces to the low
bandwidth peripherals that do not demand the high performance of the pipelined bus
interface. All the signal transitions are associated with the rising edge of the clock
which makes it simple to integrate APB peripherals into any design flow. APB can
interface with the AMBA AHB-Lite and AMBA Advanced Extensible
Interface(AXI). APB can As seen in the Figure.1, AMBA bus architecture consists of
three components, namely Advanced High Performance Bus (AHB), Advanced
System Bus (ASB), Advanced Peripheral Bus (APB)[3]. AMBA AHB or ASB is high
performance bus and has higher bandwidth. So the components requiring higher
bandwidth like High Bandwidth on chip RAM, High performance ARM processor,
High Bandwidth Memory Interface and DMA bus master are connected to the AHB
or ASB. AMBA APB is low bandwidth and low performance bus. So, the
components requiring lower bandwidth like the peripheral devices such as UART,

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Keypad, Timer and PIO (Peripheral Input Output) devices are connected to the APB.
The bridge connects the high performance AHB or ASB bus to the APB bus[4]. So,
for APB the bridge acts as the master and all the devices connected on the APB bus
acts as the slave. The component on the high performance bus initiates the
transactions and transfer them to the peripherals connected on the APB. So, at a time
the bridge is used for communication between the high performance bus and the
peripheral devices.

3.1.1 Basic Block Diagram of APB

Fig:3.2 Basic block diagram of APB


The APB slave takes PCLK, PRESET, PSEL, PENABLE, PWRITE
as input control signals and PADDR, PWDATA as 32 bits inputs from the bridge and
provides 32 bits PRDATA as output.

3.2 TRANSFERS
This data describes typical AMBA 3 APB write and read transfers, and the error
response. It contains the following sections:
• Write transfers
• Read transfers
• Error response

3.2.1 Write Transfer With no Wait State

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The write transfer starts with the address, write data, write signal and select signal all
changing after the rising edge of the clock. The first clock cycle of the transfer is called
the Setup phase. After the following clock edge the enable signal is asserted,
PENABLE, and this indicates that the Access phase is taking place. The address, data
and control signals all remain valid throughout the Access phase. The transfer
completes at the end of this cycle.
The enable signal, PENABLE, is deasserted at the end of the transfer. The select signal,
PSELx, also goes LOW unless the transfer is to be followed immediately by another
transfer to the same peripheral.

Fig:3.3 Write Transfer with no wait states

3.2.2 Write Transfer With Wait State


The PREADY signal from the slave can extend the transfer. During an Access phase,
when PENABLE is HIGH, the transfer can be extended by driving PREADY LOW. The
following signals remain unchanged for the additional cycles:
• address, PADDR
• write signal, PWRITE
PREADY can take any value when PENABLE is LOW. This ensures that peripherals
that have a fixed two cycle access can tie PREADY HIGH.

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It is recommended that the address and write signals are not changed immediately after
a transfer but remain stable until another access occurs. This reduces power
consumption.

Fig:3.4 Write Transfer with wait states

3.3 READ TRANSFER


Two types of read transfer are described in this section:
• With no wait states
• With wait states
3.3.1 Read Transfer With no Wait States
The timing of the address, write, select, and enable signals are as described in Write
transfers. The slave must provide the data before the end of the read transfer.

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Fig:3.5 Read Transfer with no wait states

3.3.2 Read Transfer With Wait States


The PREADY signal can extend the transfer. The transfer is extended if
PREADY is driven LOW during an Access phase. The protocol ensures that the
following remain unchanged for the additional cycle.
• address, PADDR
• write signal, PWRITE
• select signal, PSEL
• enable signal, PENABLE.
The two cycles above mentioned are added using the PREADY signal.
However, you can add any number of additional cycles, from zero upwards.

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Fig:3.6 Read Transfer with wait states

3.4 ERROR RESPONSE


You can use PSLVERR to indicate an error condition on an APB transfer. Error
conditions can occur on both read and write transactions.
PSLVERR is only considered valid during the last cycle of an APB transfer, when
PSEL, PENABLE, and PREADY are all HIGH.
It is recommended, but not mandatory, that you drive PSLVERR LOW when it
is not being sampled. That is, when any of PSEL, PENABLE, or PREADY are LOW.
Transactions that receive an error, might or might not have changed the state of the
peripheral. This is peripheral-specific and either is acceptable. When a write transaction
receives an error this does not mean that the register within the peripheral has not been
updated. Read transactions that receive an error can return invalid data. There is no
requirement for the peripheral to drive the data bus to all 0s for a read error.
APB peripherals are not required to support the PSLVERR pin. This is true for
both existing and new APB peripheral designs. Where a peripheral does not include this
pin then the appropriate input to the APB bridge is tied LOW.

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3.4.1 Failing Write transfer

Fig:3.7 Example failing write transfer

3.4.2 Failing Read transfer


A read transfer can also complete with an error response, indicating that there is no
valid read data available. Figure 3.5 and 3.6 shows a read transfer completing with an
error response

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Fig:3.8 Example failing read transfer

3.5 MAPPING OF PSLVERR


When bridging:
From AXI to APB An APB error is mapped back to RRESP/BRESP =
SLVERR. This is achieved by mapping PSLVERR to the AXI signals RRESP[1] for
reads and BRESP[1] for writes.
From AHB to APB PSLVERR is mapped back to HRESP = ERROR for both reads and
writes. This is achieved by mapping PSLVERR to the AHB signal HRESP[0].

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CHAPTER 4
OPERATING STATES
4.1 LIST OF APB SIGNALS

Fig:4.1 List of APB signals

PCLK Clock source Clock. The rising edge of PCLK times all transfers on the APB.
PRESETn System bus equivalent Reset. The APB reset signal is active LOW. This
signal is normally connected directly to the system bus reset signal.
PADDR APB bridge Address. This is the APB address bus. It can be up to 32 bits wide
and is driven by the peripheral bus bridge unit.

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PSELx APB bridge Select. The APB bridge unit generates this signal to each peripheral
bus slave. It indicates that the slave device is selected and that a data transfer is required.
There is a PSELx signal for each slave.
PENABLE APB bridge Enable. This signal indicates the second and subsequent cycles
of an APB transfer.
PWRITE APB bridge Direction. This signal indicates an APB write access when HIGH
and an APB read access when LOW.
PWDATA APB bridge Write data. This bus is driven by the peripheral bus bridge unit
during write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide.
PREADY Slave interface Ready. The slave uses this signal to extend an APB transfer.
PRDATA Slave interface Read Data. The selected slave drives this bus during read
cycles when PWRITE is LOW. This bus can be up to 32-bits wide.
PSLVERR Slave interface This signal indicates a transfer failure. APB peripherals are
not required to support the PSLVERR pin. This is true for both existing and new APB
peripheral designs. Where a peripheral does not include this pin then the appropriate
input to the APB bridge is tied LOW.
4.2 OPERATING STATES
T he basic state machine that represents operation of the peripheral bus. There are
three states namely, IDLE, SETUP and ACCESS state.
IDLE state is the default state in which no operation is being performed. The
assertion of the PSEL signal indicates the beginning of the SETUP phase. The bus
enters into the SETUP phase when the data transfer is required. The PWRITE, PADDR
and PWDATA are also provided during this phase. The bus remains in the SETUP
phase for one clock cycle and on the next rising edge of the clock, the bus will move to
the ACCESS state.
The assertion of the PENABLE signal indicates the start of the ACCESS phase.
All the control signals, address, and the data signals remains stable during the transition
from the SETUP phase to the ACCESS phase. In case of read operation the PRDATA
is present on the bus during this phase. PENABLE signal also remain high for one clock
cycle. If no further data transfer is required, the bus will move the IDLE state. But, if
further data transfer is required then the bus will move to the SETUP phase.

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Fig:4.2 State Diagram

During the write transfer operation, the PSEL, PWRITE, PADDR and
PWDATA signals are asserted at the T1 clock edge which is called the SETUP cycle.
At the next rising edge of the clock T2, the PENABLE signal and PREADY signal are
asserted. This is called the ACCESS cycle. At the clock edge T3, PENABLE signal is
disabled and if further data transfer is required, a high to low transition occurs on the
PREADY signal.

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CHAPTER 5
SOFTWARE REQUIREMENTS
5.1 XILINX ISE
XILINX 14.7
Xilinx software is required for both VHDL and VERILOG designers to perform
synthesis operation. Any simulated code is synthesized and configured on FPGA. The
process of changing VHDL code into gate level net list is called synthesis. It is the main
part of current design flows.

Fig 5.1. Creation of a new project

5.1.1 ALGORITHM OF XILINX


Click on XILINX ISE icon to start the Xilinx
• To create New Project. The below Figure 5.1 shows the new project creation, where
the name is to be given and should select the corresponding location and shows the
same directory as the location of project.
• The following properties are displayed and set the properties according to our
requirement.
Figure 5.2 shows the settings of project, where the device and design flow of
project is to be selected. Set the category of product as all, family as Spartan 3e, and
device is xc3s100e and the language preferred is verilog. After the properties are
selected, then it click next.

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Fig 5.2. Project settings

Select the Verilog Source by giving the required inputs, outputs and buffers, and a
window is displayed to write the verilog code and is synthesized.

Fig 5.3. Creation of a new source

The Figure 5.3 shows creating a new source, where select the project menu and
then select new source. Therefore, the new source is created depends on given
conditions and requirements.
• Select source type as Verilog module

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Fig 5.4 Selection of type of source

Figure 5.4 shows type of source selection where select source type as verilog
module and write file name and it gives location of filename in the particular drive.
Select add to project and click next.

Fig 5.5. Summary of new source


Figure 5.5 shows the summary of source where it displays source type and name and
module name. It also displays the port definitions. Then click finish. It displays the
editor where the program is written and then save it.
• When the verilog code is completed the check for syntax errors.
• Click on RTL schematic and click on technology and after that go for the synthesis
report.

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Fig 5.6: Checking for the syntax


Figure 5.6 shows the syntax errors, where select project source file and in the
process window, select synthesis XST and it displays the properties. In this select the
syntax. By right clicking on the check syntax, select the run option so it displaythe
errors in the program in console window.
Correcting HDL Errors
The syntax of added files and the files which are saved to project can be verified.
Console displays error messages and Parser Messages indicate the success or failure
when each file is parsed. If any of the modules contains syntax error correct it before
further proceeding. An “ERROR” in Console indicates the failure and line number of
line where the syntax problem has occurred.For displaying errors required steps are-
1. When we click the file name in the error message of Console Panel or error panel,
the source code will be opened in the Workspace .The line with the error is indicated
by a yellow arrow icon next to the line.
2. Then one needs to correct any errors in the HDL source file. The comments which
are placed above error help to fix the errors.
3. After correcting the errors go to Filemenu and then press Save to save the file.
4. The parsing message should then indicate that file is error free and should display
that file is checked successfully.

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Verilog synthesis tools could create logical circuit structures directly from verilog
behavioral description and target them to a selected technology for realization (i.e.,
convert verilog to actual hardware).
By using verilog, design, simulation and synthesis are performed by a simple
combinational circuit to complete microprocessor on chip.
Verilog HDL is a standard hardware description language. Verilog HDL is having many
useful features for hardware design.
Verilog HDL is a general purpose hardware description language, which is to learn and
use easily. The syntax for Verilog is same as C programming language. Designer says
that who has experience with C programming they can easily learn Verilog HDL.
It allows different levels of modeling mixed in the same model. Hence, switches, gates,
RTL, or behavioral code of modeling hardware are defined by designer. Also, designer
learns easily one language for incentive and hierarchical design.
Verilog HDL supports the popular logic synthesis. This makes the designers can choose
any language.
The Programming Language Interface (PLI) is feature in which C code is written to
interact with Verilog data structures.

5.1.2 VERILOG HDL


Verilog HDL is a hardware description language that can model digital system
at many abstract levels ranging from the algorithmic level to the gate level and to the
switch level. The modeling of the digital system difficulties changes from simple gate
to complete digital electronic system. The digital system is described hierarchically and
timing can be highly modeled within the same description.
The Verilog language includes the behavioral, the dataflow and structural
model, delays and mechanism of generating waveform including monitoring response
and verification is modeled by one single language. In addition to this, the internal
design is accessed and simulation run is controlled by simulation because language has
programming language interface.
This language defines not only the
simulations emantics construct for each language. Therefore, models written in this
language can be verified by Verilog simulator. The language inherits many of its
operator symbols and obtained from C programming language. This provides large

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capabilities of modeling, some of them are difficult to understand initially. Hence, a


core language is easy to learn and use. This is sufficient to model many applications.

5.1.3 VERILOG CAPABILITIES


The following are the major capabilities of the verilog:
Primitive logic gates like AND, OR and NAND, are built in the language.
• Creating a user-defined primitive (UDP) is flexible. Such primitive is
nothing but either combinational logic or a sequential logic.
• PMOS and NMOS are the gates for switch-level modeling and also in built
in the language.
• Simple language constructs are required to specify pin-to-pin & path delays
and timing verification of a design.
• A design is modeled in three different styles or in a mixed style. These are
nothing but: behavioral model-is modeled by procedures; dataflow model -
continuous assignments are modeled; and structural model – modeled using
gate and instantaneous of module.
• kinds of data types present in Verilog HDL; net and register data type. The
physical connections between structured elements represent net type and
data storage elements represent register type.
• The capacity of verilog in mixed-level modeling in one design; different
level of modeling is done at each module. In this, different level of modeling
is formed such as switch level, gate level, algorithm level and RTL level of
modeling.
• Verilog HDL also consists of logical built-in functions such as & (bitwise-
and) and I (bitwise-or).
• High-level language constructs such as condition- else, case statements, and
loops are available in the language.
• The idea of timing and concurrency are unambiguously modeled.
• Capability of reading and writing powerful files.

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Fig 5.7. Mixed-Level Modeling


• It is in deterministic language in some cases, because different simulators
produce different results in a model; for eg., the ordering of events on queue
is not defined by the standard.

5.1.4 SYNTHESIS
It is the process of building gate level from register-transfer level circuit model
explained in Verilog HDL. This system is an intermediate step to produce a netlist
comprising of register-transfer level blocks like flip flops, arithmetic &logical units,
and multiplexers, which is interconnected with wires. In this case, the second program
is called the RTL module, which is necessary. The purpose of this is to acquire the
predefined components from a library and each RTL block is used in the user-specified
target technology.
Verilog HDL consists of synthesis and RTL module, where the parameters such
as power consumption, delay, area and the usage of memory are found. RTL module
gives the project overview in the form of figure.
Having produced gate level netlist, logic optimizer reads the netlist and reduces
the circuit sis satisfied for specified area and timing constraints. These parameters may
also be used by the module builder for appropriate selection or generation of RTL
blocks. In this, we assume that the target net list is at the gate level. The logic gates are
used.

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Fig:5.8. Synthesis Process


Figure 5.8 shows elements in Verilog HDL and the elements used in hardware.
The elements of verilog are converted in to hardware elements by using a mechanism
called mapping or construction mechanism.
Write the program in the verilog language and check for syntax errors and then
modify the errors. Then verify the design, after that go for the synthesis where the RTL
and technology schematic are to be known.

Fig:5.9 Typical Design Process

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5.1.5 XILINX ISE Design Tools:


XilinxISEis the design tool provide by Xilinx. Xilinx would virtually identical
for our purposes.
They are 4 fundamental steps in every digital logic design.
1. Design – The schematic or code can describe the circuit.
2. Synthesis – The intermediate alteration of human readable circuit portrayal to FPGA
code format. It includes syntax check and combine of all the divide design files into a
single file.
3. Place &Route– Where the layout of the circuit is finalized. This is the translation of
the FPGA code into logic gates on the FPGA.
4. Program – The FPGA is efficient to reflect the devise through the use of
programming (.bit) files.
Test bench simulation is in the second step. ISE has the capability to do adiversity of
unlike design methodologies including: Finite State Machine, Schematic Capture, and
HDL(VHDL or Verilog).

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CHAPTER 6
SIMULATION & SYNTHESIS RESULTS

6.1 PROPOSED SYSTEM READ TRANSFER

6.2 PROPOSED SYSTEM WRITE TRANSFER

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6.3 PROPOSED SYSTEM SIMULATION READ AND WRITE


TRANSFERS

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6.4 PROPOSED SYSTEM AREA DELAY

6.5 PROPOSED SYSTEM TIME DELAY

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6.6 APB WRITE TRANSFER RTL SCHEMATIC:

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6.7 APB READ TRANSFER RTL SCHEMATIC:

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CONCLUSION
This paper gives an overview of the AMBA bus architecture and discusses the APB bus
in detail. The APB bus is designed using the verilog HDL according to the specification
and is verified using Universal Verification Methodology. The simulation results show
that the data read from a particular memory location is same as the data written to the
given memory location. Hence, the design is functionally correct. The UVM report
summary also ensures the functional correctness of the design.
The electronic system level model of the same design will be created in the future since
ESL is the requirement of the future because of increasing design complexity. The ESL
model of the APB design will be created using System C. Then the design will be
verified using UVM testbench. The results obtained after the simulation will be
compared with the results obtained in this paper.

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REFERENCES
[1] ARM, “AMBA Specification Overview”, http://www.arm.com/. .

[2] ARM, “AMBA APB3 Specification Overview”, http://www.arm.com/

[3] Akhilesh Kumar, Richa Sinha, “Design and Verification analysis of APB3
Protocol with Coverage,” IJAET, Nov 2011.

[4] Santhi Priya Sarekokku, K. Rajasekhar, “Design and Implementation of APB


Bridge based on AMBA AXI 4.0,” IJERT, Vol.1, Issue 9, Nov 2012.

[5] UVM Reference Manual, http://www.accellera.com

[6] Samir Palnitkar, “Verilog HDL: A guide to Digital Design and Synthesis (2nd
Edition), Pearson, 2008.

[7] Chris Spear, “SystemVerilog for verification (2nd Edition): A guide to learning
the testbench features, Springer, 2008.

[8] URL:http://www.testbench.com.

[9] Bergeron, “Writing testbenches using SystemVerilog,” Springer, 2009.

[10] Vanessa R. Cooper, “Getting Started with UVM: A Beginner’s Guide,” Verilab,
2013.

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APPENDIX
READ TRANSFER MODULE:
module read_transfer(clk,addr,write,sel,enable,wdata,rdata,ready);
input clk;
input [7:0]addr;
input write;
input sel;
input enable;
input [7:0]wdata;
output reg [7:0]rdata;
output reg ready;
reg [7:0]ram[0:255];
always@(posedge clk)
begin
if(write&&!sel)
begin
rdata=8'b0;
ready=1'b0;
ram[addr]=wdata;
end
else if(!write&&sel)
rdata=ram[addr];
else if(enable)
begin
ready = 1'b1;
end
end

endmodule

READ TRANSFER TEST BENCH:

module tb_rd_trtansfer;

// Inputs
reg clk;
reg [7:0]addr;
reg write;
reg sel;
reg enable;
reg [7:0] wdata;

// Outputs
wire [7:0] rdata;
wire ready;

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// Instantiate the Unit Under Test (UUT)


read_transfer uut (
.clk(clk),
.addr(addr),
.write(write),
.sel(sel),
.enable(enable),
.wdata(wdata),
.rdata(rdata),
.ready(ready)
);

always
#50 clk=~clk;

initial begin
// Initialize Inputs
clk = 0;
addr = 8'h45;
write = 1;
sel = 0;
enable = 0;
wdata = 8'hab;

// Wait 100 ns for global reset to finish


#100
write = 0;
sel = 1;

#100
enable = 1;

// Add stimulus here

end

endmodule

WRITE TRANSFER MODULE:


module
write_transfer(clk,addr,write,sel,enable,data_in,wdata,ready);
input clk;
input [7:0]addr;
input write;
input sel;
input enable;
input [7:0]data_in;
output reg [7:0]wdata;
output reg ready;
reg [7:0]ram[0:255];
always@(posedge clk)
begin
if(!write&&!sel)

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begin
wdata=8'b0;
ready=1'b0;
ram[addr]=data_in;
end
else if(write&&sel)
wdata=ram[addr];
else if(enable)
ready = 1'b1;

end

WRITE TRANSFER TESTBENCH:

module tb_wr_trtansfer;

// Inputs
reg clk;
reg [7:0]addr;
reg write;
reg sel;
reg enable;
reg [7:0] data_in;

// Outputs
wire [7:0] wdata;
wire ready;

// Instantiate the Unit Under Test (UUT)


write_transfer uut (
.clk(clk),
.addr(addr),
.write(write),
.sel(sel),
.enable(enable),
.data_in(data_in),
.wdata(wdata),
.ready(ready)
);

always
#50 clk=~clk;

initial begin
// Initialize Inputs
clk = 0;
addr = 8'h45;
write = 0;
sel = 0;
enable = 0;
data_in = 8'hab;

// Wait 100 ns for global reset to finish


#100

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write = 1;
sel = 1;

#100
enable = 1;

// Add stimulus here

end

endmodule

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