Micro Exit Bank Reviewer 1

1.
2. The pattern of the statement below follows which propositional statement?

―p implies q‖
―p is sufficient for q‖
a. Biconditional Proposition
b. Bi-Implication
c. Conditional Proposition
d. All of the Above
3. Determine the truth value of ________ if the universe of discourse for all variables is the set of
integer.
a. True
b. Maybe True or False
c. False.
d. Neither True or False
4. The function of f(x)= + sqrt (x^2+1) from R to R is classified as what type?

a. One-to-one Function
b. Onto Function
c. One-to-one and onto function
d. Neither one-to-one nor onto
5. Which of the following relations on (0,1,2,3) is classified as equivalence relation

a.{(0,0), (1,1), (1,3), (2,2), (2,3),(3,1)(3,2),(3,3)}
b. {(0,0), (1,1), (1,2), (2,1), (2,3),(2,2)(3,3)}
c.{(0,0),(0,1),(0,2),(1,0),(1,1),(1,2)(2,0),(2,2),(3,3)}
d. All of these.
6. Which of the following statements are logically equivalent?

a. (a),(b),(c) and (d)
b. (a),(b) and (c)
c. (a) and (b)
d. None of the choices
7. Can the following series be proven using mathematical induction whenever is a non-negative integer?
3+(3)(5)+(3)(5)2++…+ (3)(5)n = 3(5n+1-1)/4
a. Yes
b. No
c. Maybe
d. It depends
8. The following quantified statements are logically equivalent by applying which law?
¬ƎxP(x) ≡ x¬P(x)
¬xP(x) ≡ Ǝx¬P(x)
a. De morgan‘s Law
b. Negation Law
c. Complementation Law
d. Quantifier Law
9. Given the adjacency list (table 1). Determine the in-degree of vertex b
Initial Vertex Terminal vertex
A a(e1),b(e2),c(e3),d(e4)
B d(e5)
C a(e6),b(e7)
D b(a5),c(e9),d(e10)
a. 3
b. 2
c. 4
d. 1
10. Based from the given state table, determine the final state and output for the sequence ____starting
from state e. (BCDDCD)
a. State d,0
b. State d,1
c. State b, 0
d. None of the above
11. After the first press in a bubble sort, determine the arrangement of the items listed as
5,1,4,2,8,7,10,12 is sorted started from the highest value
a. 1 4 2 5 7 8 10 12
b. 8 7 5 4 12 10 1 2
c. 5 4 2 8 7 10 12 1
d. 1 4 2 5 8 7 10 12
12. Determine the boolean expression at the output F
a. AB+AC+BC+ABC
b. A‘BC‘+A‘B‘C+AB‘C‘+ABC
c. (AB+AC+BC)+ABC
d. A‘B‘C‘+ABC+ABC+B‘C
14. A switch that is connected in parallel with the load is the simplest representation of this logic gate
a. NOT gate
b. OR gate
c. AND gate
15. Determine the canonical form of the simplified Boolean Expression: F=x‘y ‘z‘ + xz
a. Em(0,5,7)
b. Em(2, 4, 7)
c. Em (0,2,3,&)
d. Em(1,6,7)
16. Determine the essential prime implicants of the function: F(w,x,y,z) = E( 0,2,4,5,6,7,8,10,13,15)
a. x‘y z and w‘y ‘
b. xz and x‘z‘
c. xyz‘ and wy
d. w‘x and w‘z
17. What is the canonical form of the simp lified function, F= C‘D + ABC‘ + ABD + A‘B‘D
a. M ( 0,1,2,3,5,9,11,12,13,14)
b. M (1,3,4,5,6,7,9,10,12,14,15)
c. M (0,2,4,6,7,8,10,11,15)
d. M ( 1,3,5,9,12,13,14)
18. It is a flow graph that enumerates the sequence of operation together with the conditions necessary
for their execution
a. Flow Chart
b. ASM Chart
c. Sequence Control chart
19. If the inputs of a NAND gate are fled together as 1 input, the gate function like
a. An AND gate
b. An OR gate
c. A NOT gate
20. The sequential circuit in figure 6 has an input of a bit string x of 1110 that stats from an initial state
of 0 for TA and T
a) Determine the final state of the T flip-flops A and B from the Sequential Circuit
a. 00
b. 01
c. 10
d. 11
21. From the sequential circuit in figure 6. Determine the final state and output (right side AND gate) of
the bit string x sequence 1010
a. 00 / 0
b. 01 / 0
c. 10 / 0
d. 11 / 1
22. It is a binary code 2 but 5 5 representation of the decimal value 3

a. 01001
b. 01100
c. 01000
d. 01010
23. It is described as the logic gate that has an output value of 1 when both input variables have the
same input value and is false otherwise
a. AND gate
b. OR gate
c. NOR gate
d. XNOR gate
24. Determine the product of 1110 and 10

a. 11100
b. 10100
c. 10011
d. Overflow
25. It is a table that contains the enumerated timing sequence of inputs, outputs and flip-flip states
a. Sequence Table
b. State Table
c. Characteristic Table
d. Excitation Table
26. It is a flip-flop that has the characteristic that if the inputs are both 1 it gives an invalid input
a. S-R flip flop
b. D flip-flop
c. J-K flip flop
d. T Flip-flop
27. This category of processing utilizes few instructions and has a simpler addressing mode
a. CISC
b. PENTIUM 1
c. RISC
d. EPIC
28. This allows the pipeline to be clocked at a higher speed and can use less logic in each stage
a. Burst Cycle
b. Super Pipelined
c. Loop Unrolling
d. Branch Prediction
29. In the real mode what is the ending address of the segment located by the segment register value
2500H
a. 350C
b. 250CF
c. 1250C
d. 350CF
30. Suppose that ES= 30FF, DS=43DC, SS=ABE7, AX=E7F, DI= AF9, BP=13D, SI=9CA, REN= 40F, YEN=DC2
accessed by instruction MOV REN[DI][AX][36], DX
a. 3FD77
b. 3FDAD
c. 3F99E
d. 4587D
31. Assuming AX=128D and BX= DE98, what is the content of register BX alter execution of the
instruction ADD AX, BX ( Di ko Makita ng ayos yung given )
a. 128D
b. C8D8
c. F155
d. DE98
32. This is used for the I/O port to directly access the memory.
a. Bus
b. DMA
c. I/O PL
d. Control Signal
33. What flags are affected after executing the third instruction? Assuming initial content of the flags is
zero
MOVE AL, AD
MOVE BL, BC
ADD AL, BL
a. CF & AF
b. FF & ZF
c. CF & 8F
d. ZF & DF
34. The number of cycles it would take to finish seven instructions in a 9-stage pipeline processor
a. 56
b. 17
c. 72
d. 15
35. This signal indicates when the Pentium is in the HOLD state
a. HLDA
b. HLT
c. BOFF
d. NUM
36. This processor introduced streaming extensions with 128-bit registers designed to move large data
a. Pentium 1
b. Pentium 2
c. Pentium 3
d. Pentium 4
37. If the base pointer addresses memory, which of the segment contains the data
a. CS
b. ES
c. DS
d. SS
38. This address defines the beginning address of any 64-Kbyte memory segment that is located within
one of the segment registers
a. Physical Address
b. Effective Address
c. Segment Address
d. Offset Address
39. This method of storing 16-bit numbers in memory, wherein the lower byte is already read/write to
the lower memory address
a. Non-Bye swapping
b. Big Endian
c. High Endian
d. Little Endian
40. What is the new memory Address of the next instruction executed by the microprocessor, when
operated in the real mode, for the combination CS=263A and IP=D9B2
a. DC15A
b. 33D52
c. FFEC
d. 43D51
41. This determines the address of the information or data needed for execution
a. Control Bus
b. Data Bus
c. System Bus
d. Address Bus
42. This is used to store only the most important system variables in the event of power outage
a. NVM
b. RAM
c. Cache Memory
d. ROM
43. A set of lines connects two or more elements of a computer system

a. Internal Bus
b. External bus
c. Address bus
d. Control Bus
44. Whenever a word data is pushed onto the stack the high order-8-bits are placed by what location
address?
a. SP+1
b. SP+2
c. SP-1
d. SP-2
45. The total memory access time for a series of instructions in a system with RAM access time of 105ns
and cache access time of 10ms. Assume hit ratio of 0.75
a. 45.00 ns
b. 42.50 ns
c. 38.75 ns
d. 36.25 ns
46. These cycles are used to maintain cache coherency in a multiprocessor system
a. Pipelined cycles
b. Bus hold cycles
c. Inquire Cycles
d. Cache Flush Cycle
1. A music instructor surveyed his students on their favorite classical composer, 125 students
appreciates Mozart, 98 student appreciates Beethoven, 109 appreciates Bach, 65 appreciates both
Mozart and Beethoven, 48 appreciates both Mozart and Bach, 39 appreciates both Bach and Beethoven
and 19 appreciates all three. If a student is selected at random out of 400 student music student, how
many students prefer at least two classical composers?
a. 95
b. 114
c. 85
d. 94
2. Determine the bitwise AND of the bit of the bit string 11110000 and 10101010
a. 00100011
b. 11111010
c. 10101001
d. 10100000
3. Derive the truth table of the following compound proposition, (q→r)↔(¬p˄q)

p q r a b c d
T T T T F F F
T T F T F T F
T F T T F F F
T F F T F F F
F T T T F T F
F T F T F F F
F F T T F F F
F F F T F F T
4. What is the truth value of the formula Ø = (¬(p˄q) →r)↔ ¬ (r→s) if I(p)=T, I(q)=F, I(r)=T, I(s)=F?
a. I(Ø) = T
b. I(Ø) = T
c. Both a and b
d. None of the choice
5. Is (p→ (r→q)) and ((p˄r)→q) logically equivalent?

a. Maybe
b. No
c. Sometimes
d. Yes
6. Let Q(x,y) be the statement xy=1 if the universe set is all natural numbers, which of the following is
quantified formula is true?
a. xƎy (xy=1)
b. x(x≠0→Ǝy (xy=1))
c. yQ(1, y)
d. xQ(1, x)
7. Determine the truth table of the following compound proposition (-p˅ (r→(s↔q)))
p q r s a b c d
T T T T T F T
T T T F T F T
T T F T T T T
T T F F T F T
T F T T T F T
None of the above
T F T F T F T
T F F T T T T
T F F F T F T
F T T T T F T
F T T F T F F
F T F T T F T
F T F F T F T
F F T T T F F
F F T F T T T
F F F T T F T
F F F F T F T
8. What is the Pre-Order transversal of the tree below
a. JPALEGDKRHCMQNFBIO
b. JPALGDKREHCMQBIOFN
c. JPALGDKREHCMQNFBIO
9. What is the postorder transversal of the tree in question#8

a. LKDRGAEPIQBOFMCNHJ
b. LKDRGAPEQIBOFMNCHJ
c. LKRDGAEPIOSQFMNCHJ
d. None of the Choice
10. How many edges does a graph have if it has vertices of degree 2, 2, 3, 3, and 4 respectively
a. 14
b. 7
c. 10
d. 5
11. What is the result of the postfix expression given below? 5 2 1 - - 3 1 4 + + *

a. 32
b. 24
c. -3
d. None of the Choices
12. Does the directed graph below have a Hamiltonian cycle?
a. I don‘t know
b. Maybe
c. No
d. Yes
13. Given the algorithm below

INPUT: The number of values n and an array a[1,n] contains them
OUTPUT:..?
x=0
for i = 1 to n do
x = x + a[i]
print x/n
What is the output of the algorithm?
a. The sum of the values of a[1,,n]
b. The sum of x and a[i]
c. The mean of the values of a[1,,n]
14. What will be the output of the algorithm below if n=5?

Procedure Algo2(n: positive integer)
if n = 1 then Algo2(n) != 1
else Algo2(n) != n*Algo2(n-1)
a. 20
b. 24
c. 120
d. The procedure can‘t be simulated
15. Let V= {S, A, B, a, b} and T = {a, b}. Find the language generated by the grammar if
P ={S→AB, A→aB, A→a→B→ba}
a. abaa
b. aaba
c. aabaa
16. Determine the BCD representation of the sum of 1101 base 2 and 1011 base 4.
a. 10000000
b. 10000001
c. 10000011
d. None of the Above
17. Specifies the number of standard loads that the output of a typical gate can drive without impairing
its normal operation
a. Fan-In
b. Noise Margin
c. Fan-Out
d. Propagation Delay
18. What is the equivalent of 64k byte in hexadecimal?

a. FFFF
b. 1000
c. 10000
19. The simplified Boolean expression of (A+B)(A+C)+AB+BC+B‘C is:

a. A + C
b. B
c. A‘ + BC
d. C‘ D
20. Use a K-map to find the minimum sum of products expression for the following function:
F(w,x,y,z) = ΠM(1,3,7,9,11,15).
a. xyz‘ + x
b. yz + x‘
c. z‘ + xy‘
d. xz + x‘y‘
21. Reduced the Boolean expression WXZ + YX +XW + WYZ to 1 literal – MALABO
a. W
b. X
c. Y
d. Z
22. Using a K-map, simplify the Boolean function F(A,B,C,D,E) = Σ(0,2,4,6,8,_,21,23,25,28,31)
a. F = B‘C‘D‘ + AB‘D + ABC
b. F = A‘B‘E‘ + BD‘E + ACE
c. F = A‘B‘C‘ + A‘CE + ABD
23. What is the decimal equivalent of the largest binary integer that can be obtained with 16-bits?
a. 65535
b. 65536
c. 11111111111111111
24. Which of the following defines de Morgan‘s Theorem

a. (A + B)‘ = A‘B‘
b. (AB)‘ = A‘ + B‘
c. A + B = (A‘B‘)‘
d. All of the above
25. The table that lists the required inputs for a given change of state
a. Truth Table
b. State Table
c. Excitation Table
26. What circuit technology is preferable in systems requiring low power consumption?
a. TTL
b. RTL
c. CMOS
27. A multiplexer with a 4-bit SELECT signal (63, 62, 61, 60) can accommodate a maximum of how many
input signals?
a. 2
b. 4
c. 8
d. 10
28. It is a connection from the output of one gate to the input of the second gate that forms part of this
input to the first gate gate.
a. Combinational Circuit
b. Latch
c. Feedback Path
d. Flip-Flop
29. In a serial transfer from shift register A to shift register B, what would be the contents of shift
register B before the third clock pulse from which the initial values of shift register A=1011 and shift
register B = 0010?
a. 0111
b. 1011
c. 1100
30. A negative edge triggered T flip-flop has an initial state of 0. What will be its next state when a high
input signal is injected and the falling edge of the clock arrives?
a. Flip-flop Resets
b. Flip-flop doesn‘t change state
c. Flip-flop becomes unpredictable
d. Flip-flop sets
31. If a particular processor has a cache memory with a RAM access time of 85ns and the cache access
time of 15ns, determine the average memory access time if the hit ratio is 0.75.
a. 75ns
b. 32.5ns
c. 15ns
d. 36.25ns
32. The execution time for mov instruction going from memory to register requires how many clock
cycles?
a. 10+EA
b. 9+EA
c. 8+EA
d. 16+EA
33. Among the following flags, which is classified as a status flag?

a. IF
b. DF
c. TF
d. CF
34. Determine the number of cycles needed to execute the program fragment in RISC
mov ax, 0
mov bx, 10
mov cx, 5
begin add ax, bx
loop begin
a. 13 cycles
b. 22 cycles
c. 18 cycles
d. 32 cycles
35. Which operation according to RISC architecture is the most frequently used?
a. Conditional branch
b. Load
c. Store
d. Add
36. Each instruction with a major opcode in an IA-64 contains how many bits?
a. 31 bits
b. 41 bits
c. 35 bits
d. 32 bits
37. In an IA-64 architecture, out of 128 general and floating point registers how many are always
available
a. 96
b. 32
c. 128
d. 95
38. What is the result of NOT AL if AL contains 3Eh?

a. C1h
b. 34h
c. F6D0
39. It is defined as the time required completing one operation

a. T states cycle
b. Instruction cycle
c. Machine cycle
40. The 8086 instruction are all pretty straightforward; they load their respective registers with the
specified hexadecimal constant
a. Register direct addressing mode
b. Immediate addressing mode
c. Indexed addressing mode
d. Base index with displacement addressing mode
41. If BX=30h, SI=20h, array=100h, and DS=10h the instruction mov[bx], cl generates an address equal to
a. 100h
b. 120h
c. 130h
d. 40h
42. If register AX=1000h and register BL=80h, what is the result of mov AL, BL
a. 1080h
b. 1000h
c. 80h
43. What type of addressing is described by the instruction, mov cl, [bx +4]?
a. Register indirect
b. Base plus index
c. Base relative plus index
d. Register relative
44. A processor running in this mode can exploit only the lowest 20 bits of its address bus and is
therefore limited to the meager 1MB memory space
a. Real-mode
b. Protected mode
c. Virtual mode
45. If AX and BX contains 1234h and 2345h, respectively, what is the content of register BX for ADD
AX,BX?
a. 1234h
b. 2345h
c. 3579h
46. In this mode an operation system piece of code handles these exceptions and emulates the
offending instructions which ensures a smooth fall-safe operation tasks running on the system
a. Real-mode
b. Protected mode
c. Virtual mode
47. What is in DX after CWD executes, with AX containing 4000h

a. 0400h
b. 0000h
c. 0099h
48. What is the result of NEG AX if AX contains FFECh?

a. F7D8h
b. 0020h
c. 0014h
49. This register usually points to the default segment that contains the global and statistic variables of
the active application
a. Code segment
b. Extra segment
c. Data segment
d. Stack segment
50. What is the result of IMUL CL if AL = 20h and CL = 80h

a. F000h
b. F6E9h
c. 1000h
1. The complexity notation Q(bn) where b>1

a. Constant complexity
b. Polynomial complexity
c. Exponential complexity
d. Linear complexity
2. After a second pass in a bubble sort, determine the arrangement of the items listed as 5 1 4 2 8 7 10
12 is sorted starting from the highest value
a. 1 4 2 5 7 8 10 12
b. 8 7 5 4 12 10 1 2
c. 5 4 2 8 7 10 12 1
d. 5 4 8 7 10 12 2 1
3. It is a mathematical instruction sometimes used to design digital logic computer programs

a. Natural language
b. Pseudocode
c. Finite state automata
d. Algorithm
4. The complexity notation Q(nb) where b 1?

a. Constant complexity
b. Polynomial complexity
c. Exponential complexity
d. Linear complexity
5. It is dichromatic way of looking up an element in the list that is otherwise known as dichotomic divide
and conquer
a. Bubble sort
b. Linear search
c. Sequential search
d. Binary search
6. The ASCII character with the binary number 1111111 from B7 to B1 designations
a. ASCII #
b. ASCII DEL
c. ASCII M
d. ASCII Z
7. How many possible logic functions can be created from two variables
a. 4
b. 8
c. 16
d. 32
8. Digital IC are categorized according to the complexity of their circuits, is measured by the number of
logic gates in a single package Decoders, adders, and multiplexers are classified as
a. SSI
b. MSI
c. LSI
d. VLSI
9. Determine the 16‘s compliment of B2FA

a. 4D05
b. 4D06
c. 3CD6
d. 3CD5
10. Simplify (x+y)(x+y‘)

a. x + y
b. y
c. x
d. none of the choice
11. Simplify ABCD + A‘BD + ABC‘D

a. ABD + A‘BD
b. BD
c. ABD
12. Simplify (xy‘ + zy‘ +z + xy + wz) – MALABO

a. z + wx + x + xy + y
b. x + y + z
c. w + x + y
13. Determine the complement of the function F = (x‘ + y + z‘)(x + y‘)(x + z)

a. xy‘z + x‘y +xz‘
b. xyz + xy‘
c. x‘yz + x‘z + xz‘
14. Determine the quotient of 10000100 and 1100
a. 1001
b. 1011
c. 1101
15. If A = 1011_0001 and B = 1010_1100 then evaluate A XOR B

a. 1010_0000
b. 1011_1101
c. 0001_1101
16. If A = 1011_0001 and B = 1010_1100 then evaluate A AND B

a. 1010_0000
b. 1011_1101
c. 0001_1101
17. It is the bit representation from the set U = {1, 3, 4, 7, 8, 9, 10, 11, 12, 15}
if set A = {15, 7, 9, 11, 3} and set B = {12, 8, 11, 4, 10, 15} of (B – A)U
a. 00 1010 1010
b. 11 0101 0101
c. 01 0110 1001
d. 11 0101 1110
18. Let Q(x,y) be the statement xy=1, if the universal set is all natural numbers, which of the following
a. xƎy (xy=1)
b. x(x≠0→y (xy=1))
c. yQ(1, y)
d. xQ(1, x)
19. Translate the statement ―All your friends are perfect‖ into a logic expression.
Let P(x) be ―x is perfect and F(x) be ―x is your friend‖ and the universe of discourse be all people
a. xF(x) xP(x)
b. x(F(x) →P(x))
c. x F(x) →xP(x)
d. x F(x) xP(x)
20. Consider the following relations on {1, 2, 3, 4} Which of the following relation is symmetric
a. R = {(1,3),(2,2),(3,1)}
b. R = {(1,2),(3,4),(4,4)}
c. R = {(1,2),(1,3),(2,3)}
d. R = {(2,2),(2,3),(2,4)}
21. How many vertices does a regular graph of degree 4 with 10 edges have?
a. 14
b. 7
c. 20
d. 5
22. It is a simple graph that contains exactly one edge between each pair of distinct vertices
a. Complete graph
b. Bipartile graph
c. Regular graph
d. Pseudo Graph
23. Let V = {S A B a b} and T = {a, b}. Find the language generated by the grammar if
P = {SAB, Aab, Bbb}
a. AB
b. abbb
c. ababbb
24. It is analysis that is expressed in terms of the number of operation used by the entire algorithm
when the input has a particular size n(bits)
a. Space complexity
b. Time complexity
c. Computational complexity
d. Algorithmic complexity
25. How many comparisons were made by binary search algorithm before the correct location of 19 is
given from a list containing values 1,2,3,5,6,7,8,10,12,13,15,16,18,19,20,22.
a. 2
b. 5
c. 4
d. 3
26. Let  = (p r)(q  s), what is I() is if I(p) = T, I(q) = T, I(r) = F, and I(s) = F?
a. I() = T
b. I() = F
c. Both (a) and (b)
27. The minimum hypothetical block diagram of an asynchronous sequential circuit consist of
a. Sequential circuit with feedbacks and counters
b. Combinational circuit with feedbacks and flip-flops
c. Combinational circuit with feedback and delay elements
d. Sequential circuit with latches and counters
28. It is an adder circuit that utilizes the number of full adders same as the number of bits to be added in
the binary numbers (addends)
a. Half adder
b. Full adder
c. Serial adder
d. Parallel adder
29. It is basically a chain of flip-flops in cascade with n bit of flip-flop being set to provide n up to 2n
distinguishable states with the complement of the last flip-flop connected to the input of the first
a. Binary ripple counter
b. Johnson counter
c. Synchronous BCD counter
d. Ring counter
30. A weighted code used to represent the decimal 6 to 1001

a. Excess of 3 code
b. Binary coded decimal
c. 8-4-2-1 code
d. Gray code
31. Suppose that CS = 1A9BH, an instruction JMP[E2H] occurs which is located at 8BB80H, what address
will the program jump to assuming real mode
a. 1AA92
b. 1AA93
c. 1A992
d. 1A993
32. What is the memory address of the next instruction executed by the microprocessor, when operated
in the real mode for the combination CS = 8AF2H and IP = AB37H
a. 95A57H
b. A5A56H
c. 13529H
d. B3E62H
33. An instruction PUSH [AX + SI + D4] which is located at 0082 ABCDH occurs in real mode. From what
address/es will the data be coming from? Assuming DS=CBA5h, ES=CBAB, Var3=E697h, ECX=D276
2AA6h, ESI=8BAD 2A9Ah, EDI=ECDE 665Bh, EAX=91FC AD65h.
a. D9350H
b. D9383H
c. DDBFAH
d. DD92DH
34. For a Pentium IV descriptor that contains an address of 00E6 ACBEH, a limit of 0D5BCH, and G=1,
what is the ending address location addressed by this descriptor?
a. 00E7 827AH
b. 00E7 827A0H
c. 0E42 7CBD0H
d. 0E42 7CBDH
35. For a Pentium IV descriptor that contains base address of 002C 3A7DH and Ending Address is 006C
87B5. What is the limit assuming protected mode?
a. 0040H
b. 4D36H
c. 00404H
d. 04D36H
36. In a descriptor table, the memory begins at location 000F 12ADH and ends at location 00D2 9FEDH.
The memory segment is a code segment and can‘t be read. The privilege level is second to the lowest. It
is also assumed that the size of instruction that was utilized is 16-bit and the segment is not available.
What is byte number 1?
a. C3H
b. 0CH
c. 38H
d. D0H
37. What is byte number 3? Refer to problem #36

a. 12H
b. 0CH
c. 38H
d. ADH
38. What is byte number 6? Refer to problem #36

a. D0H
b. 90H
c. C0H
d. 80H
39. Which about the choice is true about direct program memory addressing?
a. It is a jump to any memory location within the entire system
b. It is a jump to anywhere within the current code segment
c. This happens when a relative register holds the address
d. This is also called intrasegment
For numbers 40-41, A SUB instruction stores a value 3C67h at offset value A978H. The computed
address is D359Ah, assuming real mode
40. What is the starting address?
a. C8C220H
b. C8C22H
c. D2B02BH
d. D2B02B0H
41. What is the ending address?

a. E8C20H
b. 38C200H
c. D8C21H
d. D8C210H
42. If SS=D639h in protected mode system which entry is selected?
a. 6855h
b. 6855
c. 3427h
d. 3427
43. What is the RPL refer to problem #42

a. 00
b. 10
c. 01
d. 11
44. What table is selected? Refer to problem #42

a. Universal
b. Real
c. Global
d. Local
45. What segment register is accessed by the instruction MOV CH, Var1[DI][BX]
a. Code segment
b. Stack segment
c. Data segment
d. Extra segment
46. Which among the choices is not true about access rights byte?
a. This is used to control the access to the protected mode
b. This describes how the segment function in the system
c. This is used to allow complete control over the segment
d. This is used to determine which table is accessed
47. Simulate the given program and determine the final content of the register AX
MOV AX, 3ED9
MOV BX, AA39
MOV CX, 12DB
MOV DX, FA98
PUSH BX
PUSH AX
PUSH CX
PUSH DX
POP BX
POP CX
POP DX
POP AX
a. 3ED9
b. AA39
c. FA98
d. 12DB
48. Which of the following is not true about RISC
a. It makes good use of the register
b. It utilize the compiler extensively
c. It keeps instruction and addressing modes simple
d. It maximizes accesses to main memory
49. There are 23 instructions to be executed in a hyper pipeline technology. How many clock cycles
is/are needed to execute the given instruction?
a. 42
b. 460
c. 30
d. 25
50. Which of the following is not part of U and V pipelining?

a. D2
b. WT
c. PF
d. EX
1) What is the minimum cost spanning tree of the given weighed graph in Figure 2?
a. 18
b. 19
c. 20
d. 21
2) Find the value of the prefix + -  3 2  2 3 / 6 – 4 2

a. 4
b. 8
c. 2
d. none of the choices
3) Determine the truth value of nm (n+m=0) if the universe discourse for all variables is the set of
integer
a. True
b. Maybe true or false
c. False
d. Neither true nor false
4) The function f(x) = sqrt(x2+1) from R to R is classified as what type?

a. one-to-one function
b. onto function
c. one-to-one and onto function
d. neither one-to-one nor onto
5) Which of the following relations in {0,1,2,3} is classified as an equivalent relation?
a. {(0,0),(1,1),(1,3),(2,2),(2,3),(3,1),(3,2),(3,3)}
b. {(0,0),(1,1),(1,2),(2,1),(2,2),(3,3)}
c. {(0,0),(0,1),(0,2),(1,0),(1,1),(1,2),(2,0),(2,2),(3,3)}
d. all of the choices
6) Determine the least total airfare cost route that visit each of the cities and back to the start city
a. $1365
b. $1305
c.$946
d. 1045
7) The Graph below is classified as

a. Eulerian path
b. Eulerian cycle
c. Hamilton cycle
8) Determine the value of the prefix *+ 3 + 3 3 + 3 3 3

a. 2305
b. 2206
c. 2306
d. 2205
9) Given the adjacency list (table 1). Determine the in-degree of the vertex b
Vertex Terminal Vertex
a a (e1), b (e2), c (e3), d(e4)
b d (e5)
c a (e6), b (e7)
d b (e8), c(e9), d(e10)
a. 3
b. 2
c. 4
d. 1
10) How many edges does a graph have if it has vertices and degree 2, 2, 3, 3, and 4 respectively?
a. 14
b. 7
c. 10
d. 15
11) Determine the production of the phase structured gramm if the generated set of all bit strings
containing an even number of 0‘s.
a. P = {SA1, A000}
b. P = {S100S, S, A00}
c. P = { S0A1, A00, AA}
12. Let F: XY be defined as F(x) = 3x + 2 if x = {0,1,2,3}, which of the following is the list of ordered
pairs that defines it?
a. {0,1,2,3}
b. {(0,2),(1,5),(2,8),(3,11)}
c. {(0,1,2,3),(2,5,8,11)}
13) Given the state table 2 below

Present Next State Output
State X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Determine the final state value for the bit sequence 110101 if it starts from state a
a. state a
b. state c
c. state d
d. state e
14) Based from the given state table 2, determine the final state and output for the bit sequence
101101starting from state a
a. state d, 0
b. state d, 1
c. state b, 0
15) After the first pass in a bubble sort, determine the arrangement of the items listed as
5,1,4,2,8,7,10,12 sorted starting from the highest value.
a. 1 4 2 5 7 8 10 12
b. 8 7 5 4 12 10 1 2
c. 5 4 2 8 7 10 12 1
d. 1 4 2 5 8 7 10 12
16) From the given combinational circuit(fig.2) determine Boolean expression at the output F1
a. A‘B + D
b. ABC + A‘D + BD
c. A + B‘C + B‘CD + BD‘
d. A + B‘C + B‘D + BD‘
17) From the combinational circuit(fig.2), determine the Boolean Expression at F2.
a. A‘B + D
b. ABC + A‘D + BD
c. A + B‘C + B‘CD + BD‘
d. A + B‘C + B‘D + BD‘
18) Determine the canonical form of the simplified Boolean expression F2 = xy‘z‘ + x‘y
a. m(0,5,7)
b. m(2,4,7)
c. m(2,3,4)
d.m(1,6,7)
19) Determine the essential prime impl

a. B‘CD and A‘C‘
b. AB and A‘C‘D
c. BC‘ and AC
d. AB‘D and B‘C
20) Switches that are connected in series with each other are the simplest representation of this logic
gate.
a. NOT gate
b. OR gate
c. AND gate
21) What is the canonical form of the simplified function of F = xy +yz + xy‘z
a. M(0,1,3,5)
b. M(1,3,4,6)
c. M(3,5,6,7)
d. M(0,1,2,4)
22) It is a combinational circuit that selects binary information from one of the many input lines and
directs it to a single output line
a. decoder
b. multiplexer
c. encoder
d. demultiplexer
23) If the inputs of a NOR gate are inverted, the gate function like
a. an AND gate
b. an OR gate
c. a NOT gate
24) For the given sequential circuit below(fig.1), determine the input values for x and y that will have a
next state of 1 if the given present state is 0
a. x = 0, y = 0
b. x = 1, y = 1
c. x = 0, y = 1
d.none of the choice
25) From the given sequential circuit in fig.1, determine the input values for x and y that will have the
next state of 0 if the given present state is 1.
a. x = 0, y = 0
b. x = 1, y = 0
c. x = 1, y = 1
26) The 2‘s compliment representing the value -12 is

a. 1110
b. 10100
c. 10011
d. 10101
27) It is describe as the logic gate that has an output value of 0 if and only if both input variable is 1 and
is 1 otherwise.
a. AND gate
b. XNOR gate
c. NOR gate
d. NAND gate
28) The quotient from 100100012 / 1012
a. 10111
b. 10110
c. 11001
d. 11101
29) It is a table that defines the logic properties of a flip-flop by describing its operation in tabular form.
a. State Table
b. Sequence Table
c. Excitation Table
d. Characteristic Table
30) The key to a proper operation in a flip-flop is to trigger it only during a signal transition. Which of the
following triggering is used for sequential circuit?
a. Level Triggering
b. Control/Enable Trigger
c. Edge Triggering
31) What is the effective address if the instruction SUB var5 [BX][SI], BP is executed under real mode.
Assume SI=378Ah, BP=89CDh, BX=32DEh, var5=AD21h, SS=67FE and DS=BC67h
a. 7976Ah
b. 79769h
c. CDDFAh
d. CDDF9h
For number 32-35. Refer to Figure.1(TABLE)

32) Suppose that DS=003Fh, what will be the address accessed by the instruction MOV JM[EBX]{EDI-
1977h], ESI Assuming protected mode? JM=0A29h, EBX=3477 CDBEh, ESI=ABFE 7338h, EDI=37AA
DE88h.
a. DD57 DAA9 – DD7 DAAC
b. DD57 C133 – DD57 C136
c. DD57 C132 – DD57 C135
d. DD57 DAAA – DD57 DAAD
33) Suppose that CS=4000h and an instruction JMP[4C2F 5555h] occurs which is located at 78FFFh, what
will be the new value of IP, assuming protected mode? RPL is third to the lowest.
a. CS=002Eh
b. CS=002Dh
c. CS=0029h
d. CS=002Ah
34) Suppose that CS=943Bh and instruction JMP[CA] occurs which is located at 39BFFh, what address
will the program jump to assuming real mode
a. 94378h
b. 94379h
c. 9437Bh
d. 9437Ah
35) What is the new value of the selector for instruction JMP[941C 3210h] is executed currently located
at 0001 0123? Assume DS = 0002h and RPL is second to the highest.
a. 0015h
b. 0015
c. 0016h
d. 0016
For number 36-38. Code a descriptor that describes a memory segment that begins at location 000A
54DBh and end in location 00DA 35FEh. The memory segment is a code segment and can be read. The
RPL is fourth to the Highest
36) What is the Limit?
a. 0E123h
b. FE123h
c. 00CFEh
d. CFE12h
37) What is the Access Rights Byte?

a. F6h
b. DEh
c. FEh
d. F2h
38) What is the Value if the G-bit?

a. 0
b. 1
c. 0h
d. 1h
39) For Pentium V descriptor that contains an address of 00EC 98AEh, a limit of 0BCD7h and G=1. What
is the ending address locations addressed by this descriptor?
a. 0CBA 18ADh
b. 0CBA 18AEh
c. 00ED 5585h
d. 00ED 5586h
40) The type of addressing mode for the Intel assembly language instruction SUB SS:[BP][SI], OFFSET
VAR2?
a. Based Index
b. Based Indexed with displacement
c. Immediate
d. Direct
41) If the base pointer addresses the memory, which of the following segment contains the data?
a. CS
b. ES
c. DD
d. SS
42) This address defines the beginning address if any 64k—byte memory segment that is located one of
the segment registers.
a. Physical Address
b. Effective Address
c. Segment Address
d. Offset Address
43) This method of storing 16-bit number in memory, where the lowest byte is always read/written to
the lower memory address
a. Non-byte Swapping
b. Big Endian
c. High Endian
d. Little Endian
44) What is the memory address of the next instruction executed by the microprocessor, when operated
in the real mode, for combinations CS=263A and IP=D9B2.
a. DC15A
b. 33D52
c. FFEC
d. 43D51
45) This determine the address of the information of data needed for execution
a. Control Bus
b. Data Bus
c. System Bus
d. Address Bus
46) This is used to store only the most important system variable in the event of power outage.
a. NVM
b. RAM
c. Cache Memory
d. ROM
47) A set of lines connects two or more elements of a computer system

a. Internal Bus
b. External Bus
c. Address Bus
d. Control Bus
48) History bits are initially set to ___ when a new target address is placed into the branch target buffer
a. 00
b. 01
c. 10
d. 11
49) What is the result if the instruction MUL BL is executed if AX=0ECAh, CX=BA35h, and BX=3A9Dh
a. 031E
b. 7BE2
c. 29D2
d. 2DC4
50) What is the result of XOR AX, CX if AX contains 1234h, and CX contains 4567h?
a. 5357h
b. 5753h
c. 31C8h
d.C831Dh
1. What is the equivalent machine code of the instruction MOV AX, 1000?
a. B81000
b. B80010
c. B88
d. B0800
2. EPIC stand for

a. Explicitly Parallel Instruction Coding
b. Explicitly Parallel Instruction Computing
c. Explicitly Parallel Instruction Calculation
d. Explicitly Parallel Instruction Calculating
3. It is a technique that duplicates the instruction found within a loop in such a way that one pass
through the new loop produces two or more results
a. Loop Rolling
b. Loop Unrolling
c. Looping
d. Loop Increment
4. Byte1 = 1000 1010

Byte2 = 0001 0110
Byte3 = 1101 0111
Byte4 = 0101 1100
a. MOV DL,[5CD7]
b. MOV SS:[BP],DL
c. MOV [BP+5CD7], DL
d. MOV DL, SS[BP]
5. Choose the appropriate AND instruction to preserve bits 0, 3, 9 and 13 of the register BX, and clear all
others. Assuming BX has FE1Fh
a. AND BX, 23E9h
b. AND BX, 0209h
c. AND BX, 23FAh
d. AND BX, 23EAh
6. If the base pointer addresses memory, which of the segment contains the data?
a. CS
b. ES
c. DS
d. SS
7. This addressing move a byte or a word between register and the memory location addressed by an
index or base register plus a displacement.
a. Indirect
b. Base Plus Index
c. Register Relative
d. Base relative plus
8. This flag enables trapping through on-chip debugging feature.

a. Interrupt
b. Tap
c. Trap
d. Error
9. This microprocessor is ten times faster than Intel 8008

a. Intel 8800
b. Intel 8088
c. Intel 8018
d. Intel 8080
10. This determines the address of the information or data needed for execution
a. Address Bus
b. Data Bus
c. Control Bus
d. System Bus
11. It is also called Little Endian

a. Motorola CPU
b. Intel CPU
c. Intel 8008
d. Intel 4004
12. If SS=FEEEh in a protected mode system which is selected?

a. 8157h
b. 8157
c. 8156
d. 8156h
13. This was originally offered as a lower cost alternative to Pentium II.
a. Xeon
b. Celeron
c. EM64T
d. EM64KB
14. What is the result of MUL CH if AX = 0A98h, CX = 9EBCh and DX = 727Bh?
a. 062C
b. 0758
c. 6FA0
d. 5DD0
15. What is the type of data dependency of the following instruction for the UV pipeline?
MOV CX, BX
MOV DX, CX
a. No Data Dependency
b. Read after Write
c. Write after Read
d. Write after Write
16. What do you call the address placed within the bracket?
a. Offset address
b. Displacement
c. Relatives
d. Segment Addresses
17. This refers to the location that is called or jumped to instead of the actual numeric
a. Label
b. Directive
c. Heading
d. Instruction
18. This register defines the starting address of the section of memory holding code.
a. Instruction Pointer
b. Code Segment
c. Memory Location
d. Register Memory
19. This indicates how operand or section of a program is to be processed by the assembler.
a. Instruction
b. Opcode
c. Directive
d. Mnemonic
20. This category of processor utilizes few instruction and simpler addressing mode.
a. Processor
b. RISC
c. CISC
d. Math Coprocessor
21. The register that works closely with the ALU is
a. Index Register
b. Stack Pointer
c. Accumulator
d. Instruction Pointer
22. Assuming AL = 73 and CL = 29, what will be the content of register AL after executing the following
instruction?
ADD AL, CL
DAA
a. 73
b. 9C
c. 29
d. 02
23. This is an additional byte that appends the front of an instruction to select an alternate segment
register.
a. Segment Override Prefix
b. Segment Register
c. Displacement
d. Operand
24. What is the MOD field of the Instruction MOV[1000h], DL

a. 11
b. 10
c. 01
d. 00
25. This describes the location length and access rights of the segment of memory.
a. Selector
b. Descriptor
c. Access Right Bytes
d. Protected Mode System
26. This technique helps possible interruptions to the normal flow of instruction through the U and V
pipeline.
a. Bus Cycle State
b. Branch Prediction
c. Atomic Operation
d. Pipelining
27. What is the average access time for a system that contains 5ns cache and 28ns RAM? Hit ratio is 0.78
a. 132
b. 132h
c. 12.15
d. 12.15h
28. Suppose that CS = 1973H,an instruction JMP[DBH] occurs which is located at 88BB80H, what address
will the program jump to assuming real mode?
a. 1970C
b. 194E
c. 1970B
d. 19706
29. Suppose that CS = 3000H, an instruction JMP[30CC 5432h] occurs which is located at 00052388h,
what will be the new value of the CS assuming protected mode? Privilege Level is third to the highest.
a. 300 6000
b. 0016
c. 0016H
d. 3000 6000H
30. What is the IP? Refer to problem #29

a. F432h
b. 00CBh
c. 0CBFh
d. 432h
31. This is used in protected mode operation to select the privilege level for input/output devices.
a. IOPL
b. I/O prot
c. DPL
d. RPL
32. If the instruction XOR AX,, 0098 is executed, what will be the result, assuming AX = 2C0E?
a. 0008h
b. 2C9Eh
c. 2CA6
d. 0000H
33. What will be the content of Al, after executing the instruction SHL AL, CL? Assuming AL = AD, CL = 6
and CF has 1
a. ADh
b. 6Bh
c. 75h
d. 40h
34. What does the instruction IN AL, 13 accomplishes?

a. 8 bits are input to AL from I/O port 13
b. Hexadecimal 13 will be stored in AL
c. 8 bits are output from AL to I/O port 13
d. AL content will be equal to decimal 13
35. This instruction is used to convert the result of the addition of two packed BCD numbers to a valid
BCD number.
a. AAM
b. AAD
c. CBW
d. DAA
36. What is the memory address of the next instruction executed by the microprocessor, when operated
in the real mode, for the combinational CS = 6BC3h and IP = E6B8h
a. 1527Bh
b. 1527Ch
c. 7A2E8h
d. 7A2E9h
37. Suppose that CS = 7200h and instruction JMP[28] occurs which is located at 72AB0h, what address
a. 72029h
b. 72028h
c. 71FD9h
d. 71FD8h
38. For Pentium IV descriptor that contains an address of 009C13B4h, a limit of 007D3h, and G = 1, what
is the ending address location addressed by this descriptor?
a. 009C1B87h
b. 009C1B88h
c. 011953B3h
d. 011953B4h
39. In real mode, this jump accesses any location within the first 1M byte of memory by changing both
CS and IP.
a. Short Jump
b. Near Jump
c. Intrasegment Jump
d. Far Jump
40. This is the first manufacturer of the microprocessor

a. BUSYCOM
b. BUSICOM
c. BISUICOMM
d. BUSSICOM
41. For a Pentium IV descriptor that contains a base address of 00CD 36C8h, a limit of 00927h and G is
equal to 1, what is the starting address assuming protected mode?
a. SA = 00CD 36C8h
b. SA = 00CD 3FEFh
c. SA = 015F B6C7h
d. SA = 015F B6C7h
42. In a 16-bit multiplication where does the most significant 16 bits of the product go?
a. AX
b. DX
c. CX
d. AH
43. What segment register is accessed by the instruction MOV AX, [BP]?
a. Data Segment
b. Extra Segment
c. Code Segment
d. Stack Segment
For number 44-46. Code a descriptor that describes a memory segment which begins at location 0007
B27Ah and ends at location 0036 FE73h. The memory segment is a code segment and can‘t be read. The
privilege level is second to the lowest
44. What is the limit
a. 002F4h
b. 2F4BFh
c. 002F4h
d. F4BF9h
45. What is the Access Right Byte?

a. 98h
b. 9Ch
c. D8h
d. DCh
46. What is the Value of G-bit?

a. 0
b. 1
c. 0h
d. 1h
47. Suppose that DS = CB79h SS = AB73h ES = D729 BX = 0018h DI = 09BAh BP = CABCh SI = 078Ch she =
6Bh and he = CBh. What is the address accessed by the instruction MOV BX, he[BP + SI +CABh]?
a. B7D98h – B7D9Ah
b. B7D98h
c. D7DF8h – D7DF9h
d. D7DF8h
48. What is the address accessed by the Instruction MOV CH, she[SI][BX]? Use all information given in
number 47
a. CBF9Fh
b. CBF9Fh – CBFA0h
c. D7A9Fh - D7AA0h
d. D7A9Fh
49. This instruction is used to convert the result of subtraction of two packed BCD numbers to a valid
BCD number.
a. DAS
b. CBW
c. AAM
d. DAA
50. What is the Mnemonic form of the given machine code

Byte1 = 1100 0110 Byte2 = 1000 0000
Byte3 = 1001 1010 Byte4 = 0101 0111
Byte5 = 1111 1010 Byte6 = 0111 0011
a. MOV DS[BX+SI+579A], 73FA
b. MOV DS[BX+SI+579A], FA
c. MOV DS[BX+SI+9A], FA
d. MOV DS[BX+SI+9A], 73FA
19. Derive the truth table of the following compound proposition. ((pvq)(pr)(qr))r
p q r a b c d
T T T T F T
None of the choices
T T F T F T
T F T T F F
T F F T F F
F T T T F T
F T F T F T
F F T T F F
F F F T F F
20. Derive the truth table of the following coumpound proposition.

((pq)^(qr))  (pr)
p q r a b c d
None of the choices
T T T T T T
T T F T T F
T F T F T F
T F F F T F
F T T T T T
F T F T T F
F F T T T T
F F F T T T
21. Which of the following statements are logically equivalent?
(a) pq
(b) (pq)(qp)
(c) pq
(d) (pq) (pq)
a. (a), b, c, and d
b. a, b and c
c. a and b
22. The pattern of the statements below follows which propositional statement?
―p implies q‖
―p is sufficient for q‖
a. Biconditional Proposition
b. Bi-implication
c. Conditional Proposition
d. All of the choices
23. Let Q(x,y) be the statement ―x+y = x-y‖ If the universe of discourse for both variables consists of all
integers, what is the truth value of AxEyQ(x,y)
a. Either true or false depending on the value
b. Neither true nor false
c. True
d. False
24. The following quantified statements are logically equivalent by applying which law?
xP(x) xP(x)
xP(x)xP(x)
a. De Morgan’s Law
b. Negation Law
c. Complementation Law
d. Quantifier Law
26.Can the following series be proven using mathematical induction whenever n is a non-negative
integer?
3+(3)(5)+ (3)(5)2+…+(3)(5)n=3(5n+1-1)/4
a. Yes
b. No
c. Maybe
d. It depends
27. Which of the following Venn diagram representation of the statement (A - B) U (C  B)
28. What can you say about sets A and B if we know that A int B = A?
a. Set A is equal to set B
b. Set B is equal to set A
c. Set A is equal to the universal set
d. Set B is equal to the universal set
29. Twelve people in a town have decided to form three clubs. The clubs are chosen so that half of the
people belong to each club, one-third of the people to each pair of clubs, and one-fourth of the people
to all three clubs. How many people belong to at least one of the clubs?
a. 3
b. 6
c. 9
30. What is the value of 1/2 + 1/2+ 1/2

a. 1
b. 2
c. 3
31. This refers to the location that is called or jumped to instead of the actual numeric address.
a. Directive
b. Label
c. Heading
d. Address Name
32. This is a special type of high-speed RAM where data and its address are stored.
a. NVM
b. Cache
c. ROM
d. RAM
33. This category of processing that utilizes few instructions and a simpler addressing mode.
a. RISC
b. Processor
c. CISC
d. Math coprocessor
34. This is used to preload data before it is needed while other instructions are also being executed.
a. Speculation Loading
b. Speculative Loading
c. Loading
d. Post Loading
35. Whenever a word data is pushed onto the stack the low order 8 bits are placed by what locations
address?
a. SP+1
b. SP -2
c. SP+2
d. SP-1
36. In real mode, what is the ending address of the segment located by the segment register value
234FH?
a. 1234EH
b. 244EFH
c. 334E0H
d. 334EFH
37. If SS=BEEDH In a protected mode system, which entry is selected?

a. 3054
b. 6109H
c. 6109
d. 3054H
38. This is responsible in producing control signals as the instruction is determined.

a. Control Unit
b. Control Logic
c. Control Signal
d. Control system
39. If DS = 0063H, what is the ending address assuming protected mode? *

a. AB20B010H
b. 001FFFFFH
c. AB20B011H
d. AB00B011H
40. Suppose that CS = 9500H, an instruction JMP [80EEEH] occurs which is located at 35555H, what will
be the new value of CS and IP, assuming real mode?
a. CS=72000H and IP=EEEEH
b. CS=7200H and IP=EEEEH
c. CS=7200H and IP=0EEEEH
d. CS=7200H and IP=EABCH
1. It is a system by which certain data or information is represented in numerical pattern.

a. system presentation
b. digital system
c. analog system
2. The equivalent of the decimal number BAD.0011 in the octal numbering system is
a. 5566104000
b. 5655 000104
c. 5655 104000
d. 5566 000104
3. A data path, when combined with the control unit, forms a component referred to as.
a.CPU
b. Input Unit
c. Output Unit
d. Memory Unit
4. The decimal number 47.1248, when converted to base 9 is?

a. 43.05241
b. 44.05241
c. 43.14250
d. 44.14250
5. Using the 2‘s complement method, the result of subtracting 11011101 from 10100110 is
a. -00010111
b. 00110111
c. 00110111
d. -00100101
6. Each of the following 4 numbers has a different base, which of the four numbers have the same value
in decimal?
(a) 20225 (b) 120113 (c) 33124 (d) 19A12
a. b & d
b. c & d
c. a & c
d. a & d
7. Given two decimal numbers 694 and 835. Their sum in BCD is
a. 00 1111 1100 1001
b. 01 0111 1100 1001
c. 0001 0101 0010 1001
d. 1001 0101 0010 1001
8. The 2-4-2-1 code of 7 is

a. 1100
b. 1101
c. 1110
d. 0001
9. The Boolean expression (X+Y+Z)‘ = X‘Y‘Z‘ is an example of which Law/Theorem?

a. Commulative Law
b. Involution Law
c. De Morgan’s Theorem
d. Idempotent Theorem
10. The Boolean expression (X‘‘‘)‘ is an example of which Law/Theorem?

a. Involution Law
b. Consensus Law
c. Idempotent Law
d. Inversion Law
11. This is used in applications to eliminate the errors of ambiguity during the transition of binary
numbers.
a. Gray Code
b. 2-4-2-1 Code
c. 2-4-8-1 Code
d. 2- of -5 Code
12. This is the basic mathematics needed for the study of the logic design of digital systems.
a. Combinational Design
b. Sequential Design
c. Boolean Algebra
d. Quine-McClusky
13. The minterm expansion of the Boolean expression A‘B;C;D;+ AC‘D‘+B‘CD‘+A‘BCD+BC‘D is

a. m(1,2,3,6,9,10,12,14)
b. m(0,1,5,7,9,10,12,13)
c.m(0,2,5,7,8,10,12,13)
d. m (1,2,3,7,8,10,12,13)
14. The simplest form of the Boolean expression (a+b‘+c‘)(a‘+c‘) in product-of-sums form is
a. (a + c‘)(c‘ +b)
b. (a’ + c’)(c’ + b’)
c. (a‘ + c‘)(c‘ + b)
d. (a + b)(a‘ + b‘)
15. The reduced form of the Boolean expression (A‘ + C)(A‘ + C‘)(A + B + C‘D) is
a. A’B + A’C’D
b. A‘B‘ + AC‘D‘
c. AB‘ + A‘CD‘
d. ABD + C‘D
16. Refer to the following system specifications

―the diagnostic message is stored in the buffer or it is retransmitted.‖
―the diagnostic message is not stored in the buffer.‖
―if the diagnostic message is stored in the buffer, then it is retransmitted,‖
Are the statements consistent?
a. Partially
b. Yes
c. No
d. Maybe
17. Find the bitwise XOR of the following bit strings:

0110110110 XOR 1100011101 XOR 1101011110
a. 0101010100
b. 1110111111
c. 0111110101
d. 0110010100
18. Derive the truth table of the following compound proposition, (p q) ^ (p(rvq))
p q r a b c d
T T T T F T F
T T F T F T F
T F T F F T F
T F F F F T F
F T T T F T F
F T F T F T F
F F T T F F F
F F F T F F T
14. Determine the essential prime implicants of the function F(w,x,yz) = (0,2,4,5,6,7,8,10,13,15)
A. x‘yz and w‘y‘
B. XZ and X’Z’
C. xyz‘and wy
D. w‘x and w‘z‘
15. Determine the simplified Boolean expression of the function F(A,B,C,D) with
F = m(5,6,7,8,9) with d(10,11,12,13,14,15)
a. A+ BC + BD
b. BD + B‘D‘
c. CD + C‘D‘
d. AB‘C + B‘D + BC‘D‘
16. Simplify the Boolean function F(A,B.C.D) with F= Em(0,6,8,13,14) with Ed(2,4,10)
a. ABD + B‘C + BC‘D
b. B’D’ + CD’ + ABC’D
c. A‘B‘D + ABD‘ + B‘CD‘
17. The sequential circuit in figure 6 has an input of a bit string x of 1110 that starts from an initial state
of 0 (from TA and TB). Determine the final state of the T flip flops A and B from the sequential circuit
A. 00
B. 01
C. 10
D. 11
18. It consists of a series of connection of complementing flip-flops, with the output of each flip-flop
connected to the C input of the next higher order flip-flop and goes through a prescribed sequence of
transition.
a. BCD counter
b. binary ripple counter
c. up-down counter
d. ring counter
19. What is the canonical form of the simplified function F = C‘D + ABC‘ + ABD‘ + A‘B‘D
a. M(0,1,2,3,5,9,11,12,14)
b. M(1,3,4,5,6,7,9,10,12,14,15)
c. M(0,2,4,6,7,8,10,11,15)
d. M(1,3,5,9,12,13,14)
20. Determine the canonical form of the simplified Boolean expression F = x‘y‘z +xy
a. m(0,5,7)
b. m(2,4,7)
c. m(2,3,7)
d. m(1,6,7)
22. Derive the truth table of the following compound proposition (p(qr))q
p q r a b c d
T T T T T T
None of the Choices

T T F T T F
T F T T F F
T F F T F F
F T T T T T
F T F T T F
F F T T T T
F F F T T T
23. Derive the truth table of the following compound proposition. (pq)(qr)(qr)
p q r a b c d
T T T T F F
None of the Choices
T T F T F T
T F T T F T
T F F T F F
F T T T F F
F T F T F T
F F T T F T
F F F T F F
41. Di ko mahanap yung question

a. Indirect Jump
b. Direct Jump
c. Relative Jump
d. Intersegment Jump
42. In a 16-bit multiplication, where does the most significant 16 bits of the product go?
a. AX
b. DX
c. CX
d. AH
43. What segmebt register is accessed by the instruction MOV AX, ES:[DI]?
a. Data Segment
b. Extra Segment
c. Code Segment
d. Stack Segment
For numbers 44-46. Code a descriptor that describes a memory segment which begins at location 0006
C4B3H and ends at location 0035 8DyCH. The memory segment is a data segment that grows downward
and cannot be written. The privilege level is second to the lowest.
44. What is the limit?
a. C8C9H
b. EC8C9H
c. 02ECH
d. 002ECH
45. What is the Access Right Byte?

a. D8H
b. D9H
c. D4H
d. D6H
46. What is the value of G-bit?

a. 0
b. 1
c. 0H
d. 1H
47. Suppose that DS=CADAH, SS=CAFAH, BX=00E3H, DI=09BAH, BP=DADEH, SI-6FEH, she=BCH and
he=AD. What is the address accessed by the instruction MOV CX, he[DP+SI-EEEH]
a. D833BH – D833CH
b. D833BH
c. D813BH-D813CH
d. D813B
49. Suppose that CS=3651H, an instruction JMP [3228 AEEEH] occurs which is located at 7226 EEEEH
what will the new value of CS and IP, assuming protected mode? Privilege level is third to the highest.
a. CS=00360H and IP=EEE0H
b. CS=00360H and IP=0EEEH
c. CS=0036H and IP=EEEH
d. CS=0036H and IP=0EEEH
50. Suppose that CS=6300H, an instruction JMP [ECH] occurs which is located at 63BC1H, what address
a. 62FEDH
b. 62FEADH
c. 62FECH
d. 62FEACH
19. Determine the canonical form of the simplified Boolean expression F = x‘y‘z + xz.
a. m(0,5,7)
b. m(2,4,7)
c.m(0,2,3,7)
d. m(1,6,7)
A. x‘yz and w‘y‘
B. XZ and X’Z’
C. xyz‘and wy
D. w‘x and w‘z‘
21. What is the canonical form of the simplified function F = C‘D +ABC‘ +ABD‘ +A‘B‘D
a. M(0,1,2,3,5,9,11,12,14)
b. M(1,3,4,5,6,7,9,10,12,14,15)
c. M(0,2,4,6,7,8,10,11,15)
d. M(1,3,5,9,12,13,14)
22. It is a flow graph that enumerates the sequence of operation together with the conditions necessary
for their execution.
a. Flow Chart
b. ASM chart
c. Sequence control chart
23. If the inputs of a NAND gate are tied together as 1 output the gate functions like
a. an AND gate
b. an OR gate
c. a NOT gate
24. The sequential circuit in figure 6 has an input of a bit string x of 1110 that starts from an initial state
of 0 (from TA and TB). Determine the final state of the T flip flops A and B from the sequential circuit
A. 00
B. 01
C. 10
D. 11
25. From the sequential circuit above. Determine the final state and output (right side AND gate) of the
bit string x sequence 1010
a. 00 / 0
b. 01 / 0
c. 10 / 0
d. 11 / 1
26. It is the binary code 2 out 5 representation of the decimal value 3
a. 01001
b. 01100
c. 01000
d. 01010
27. It is described as the logic gate that has an output value of 1 when both input variables have the
same input value and is false otherwise
a. AND gate
b. OR gate
c. XOR gate
d. XNOR gate

a. 11100
b. 10100
c. 10011
d. overflow
29. It is a table that contains the enumerated timing sequenc of inputs, outputs, and flip-flop states.
a. Sequence Table
b. State Table
d. Excitation Table
30. It is a flip-flop that has the characteristic that if the inputs are both 1 it gives an invalid output
a. S-R flip-flop
b. D flip-flop
c. K-K flip-flop
d. T flip-flop
31. This category of processing utilizes few instructions and has a simpler addressing mode
a. CISC
b. PENTIUM 1
c. RISC
d. EPIC
32. This allows the pipeline to be clocked at a higher speed and can use less logic in each stage.
a. Burst Cycle
b. Super Pipelined
c. Loop Unrolling
d. Branch Prediction
33. In the real mode, what is the ending address of the segment located by the segment register value
25DDH
a. 35DC
b. 26DCF
c. 125DC
d. 35DCF
34. Suppose that ES=3DFF, DS = 43DC, SS = ABE7, AX=E7F, DI=AF9, BP = 13D, SI = 9CA, REN = 40F and
YEN = DC2. Determine the address accesed by instruction MOV REN[DI][AX][36], DX,
a. 37D77
b. 3FDAD
c. 3F99E
d. 45B7D
35. Assuming AX = 12B- and BX=DE98. What is the content of register BX after execution of the
instruction ADD AX, BX?
a. 12BD
b. CBDB
c. F155
d. DE98
36. This is used for the I/O port to directly access the memory
a. Bus
b. DMA
c. IOPL
d. Control Signal
37. What flags are affected after executing the third instruction? Assuming initial content of the flags is
zero MOV AL,AD MOV BL, BC? ADD AL, BL
a. CF & AF
b. PF & 2F
c. CF & SF
d. ZF & SF
38. The number of cycles it would take to finish seven instructions in a 9-stage pipeline processor
a. 56
b. 17
c. 72
d. 15
39. This signal indicates when the Pentium is in the HOLD state
a. HLDA
b. HLT
c. BOFF
d. NMI
40. This processor introduced streaming extensions with 128-bit registers designed to move large data
a. Pentium 1
b. Pentium 2
c. Pentium 3
d. Pentium 4
41. If the base pointer addresses memory, which of the segment contains the data?
a. Physical address
b. Effective address
c. Segment address
d. Offset address
1. How many 2 x 4 decoders are needed to create a decoder with 4 inputs and 16 outputs?
a. 2
b. 4
c. 6
d. 8
2. It consists of a series of connection of complementing flip-flops with the output of each flip-flop
connected to the C input of the next higher order flip-flop and goes through a prescribed sequence of
transition.
a. BCD Counter
b. Binary Ripple Counter
c. Up-Down Counter
d. Ring Counter
3. The maximum value number of addresses available for FFF is?

a. 256
b. 1024
c. 32
d. 64
4. If the inputs of a NOR gate are inverted the gate function like
a. an AND gate
b. an OR gate
c. a NOT gate
5. Determine the canonical form of the simplified Boolean expression F = x‘y‘z + xy

a. m(0,5,7)
b. m(2,4,7)
c. m(2,3,7)
d. m(1,6,7)
6. It is a table that contains the enumerated timing sequence of inputs, outputs and flip-flop states.
a. Sequence Table
b. State Table
d. Excitation Table
7. What is the canonical form of the simplified function F = C‘D + ABC‘ + ABD‘ + A‘B‘D
a. M(0,1,2,3,5,9,11,12,14)
b. M(1,3,4,5,6,7,9,10,12,14,15)
c. M(0,2,4,6,7,8,10,11,15)
d. M(1,3,5,9,12,13,14)

a. 11100
b. 10100
c. 10011
d. overflow
9. It is a clocked sequential circuit consisting of n flip-flops and is capable of storing n-bits of information
a. Counter
b. Memory
c. Register
10. It is a table that defines the logical properties of a flip-flop by describing its operation in tabular form
a. State table
b. Sequence table
c. Excitation table
d. Characteristic table
11. It is a flip-flop that has the characteristic that if the inputs are both 1 it gives an invalid output
a. S-R flip-flop
b. D flip-flop
c. J-K flip-flop
d. T flip-flop
12. It is a cascade of interconnected chain of flip-flops with the output of one flip-flop connected to the
input of the next flip-flop and all the flip-flops receives a common cluck pulse
a. BCD Counter
c. Up-Down Counter
d. Shift Register
13. Simplify the Boolean function F(A,B,C,D) with F = Em(0,6,8,13,14) with Ed(2,4,10)
a. ABD + B‘C + BC‘D‘
b. B’D’ + CD’ + ABC’D
c. A‘B‘D + ABD‘ + B‘CD‘
14. The quotient from 10010001/101
a. 10111
b. 10110
c. 11001
d. 11101
15. It is a circular shift register with only 1 flip-flop being set at any particular time, all others are cleared
a. BCD counter
c. Up-Down Counter
d. Ring Counter
16. It is a mathematical abstraction sometimes used to design digital logic of computer programs
a. Natural Language
b. Pseudo-Code
c. Finite State Automata
d. Algorithm
17. How many comparisons were made by the linear search algorithm before the correct location of 19
is given from a list containing values 1,2,3,5,6,7,8,10,12,13,15,16,18,19,20,22
a. 15
b. 14
c. 16
d. 13
18. If a bubble sort is used, what will be the order of the items listed as 5,1,4,2,8,7,10,12 after the first
pass (if it is sorted starting from the highest value)
a. 1 4 2 5 7 8 10 12
b. 8 7 5 4 12 10 1 2
c. 5 3 2 8 7 10 12 1
d. 1 4 2 5 8 7 10 12
19. It is a finite set of instructions for performing computations for solving a problem in a structured
manner
a. Flowchart
b. Pseudo code
c. Control tables
d. All of the choices
20. If the binary search algorithm is used to locate 19, how many comparisons will be made before the
correct location is obtained from a list containing values 1,2,3,5,6,7,8,10,12,13,15,16,18,19,20,22
a. 2
b. 5
c. 4
d. 3
21. What will be the output of the algorithm for x = 02 if the pseudocode is
Procedure:
if x< 0 then
A = -x
else
=x
a. 4
b. -2
c. 0
d. 2
22. It is a representation containing directed labeled edges and circles often used for reactive systems
a. Algorithm
b. Flow graph
c. Flowchart
d. State diagram
23. The pseudo code below sets distinct values for the variables A, B, and C. Determine the output of the
pseudocode if the inputs are A= 5, 8 = b, C=2
Procedure:
If(A>B or B>C) then
If (A>B) then swap (A,B)
If (B>C) then swap (B, C)
If (A>B) then swap (A,B)
Print A,B,C
a. 5,8,2
b. 2,5,8
c. 8,5,2
d. 2,5,8
24. Given the adjacency list (table 1). Determine the in-degree of the vertex b
Vertex Terminal Vertex
a a (e1), b (e2), c (e3), d(e4)
b d (e5)
c a (e6), b (e7)
d b (e8), c(e9), d(e10)
a. 3
b. 2
c. 4
d. 1
25. The graph below is classified as
a. Eulerian Path
b. Eulerian Cycle
c. Hamiltonian cycle
26. it is a simple graph that contains exactly one edge between each pair of distinct vertices
a. complete graph
b. bipartile graph
c. regular graph
d. pseudo graph
27. How many edges does a graph have if it has vertices of degree 2, 2, 3, 3, and 4
a. 14
b. 7
c. 10
d. 5
28. If a directed pseudo graph contains V={d, a, b, c} and A={(d,a),(b,a),(d,b),(b,c),(a,a),(d,c),(c,d)} How

many out degrees at vertex b are there?
a. 3
b. 2
c. 1
d. 0
29. It is a path in a graph that passes through each of edges in the graph once
a. simple path
b. Hamiltonian cycle
c. Eulerian path
d. Eulerian cycle
30. A regular graph contains 6 vertices and 30 edges contains how many degrees?
a. 15
b. 10
c. 12
d. 5
31. What segment register is accessed by the instruction MOV AX, ES[DI]?
a. Data Segment
b. Extra Segment
c. Code Segment
d. Stack Segment
32. for a Pentium III descriptor that contains a base address of 00AD 2345H, a limit of 0082FH, and G is
equal to 1. What is the starting address?
a. 00AD 2345H
b. 00AD 23450H
c. 01302344H
d. 01302343H
33. This is responsible for decoding instruction after it has been fetched
a. Control unit
b. Control logic
c. Instruction decoder
d. Decode cycle
34. In real mode, this jump accesses any location within the first 1M byte of memory by changing both CS and IP
a. Far Jump
b. Intrasegment Jmp
c. Short Jump
d. Near Jump
35. This register defines, the starting address of the section of memory holding code
a. Memory
b. Code segment
c. Program address
d. Segment address
36. In real mode, what is the ending address of the segment located by the segment register value 56ADH?
a. 156ACH
b. 66ACF0H
c. 66ACFH
d. 156AC0H
37. If SS=BAACH in protected mode system, which entry is selected?

a. 5973
b. 5973H
c. 2986
d. 2986H
38. This is responsible in producing control signals as the instruction is determined

a. control unit
b. control logic
c. control signal
d. control system
39. If DS=006BH, what is the ending address assuming protected mode

a. 3228EFFF0H
b. 3228FFFFH
c. 3328DFFF0H
d. 3328DFFFH
40. Suppose that CS=3500H, an instruction JMP[75EEEH] occurs which is located at 35555H, what will be
the new value of CS and IP, assuming real mode?
a. CS=72000H and IP=3EEEH
b. CS=7200H and IP=3EEEH
c. CS=72000H and IP=C111H
d. CS=7200H and IP=C111H
41. This refers to the location that is called or jumped to instead of the actual numeric address
a. Directive
b. Label
c. Heading
d. Address Name
42. What will be the content of AL after executing the instruction SAR AL,3? If AL has 1001 1001 and C has 1
a. 73H
b. F3H
c. E6H
d. F9H
43. This addressing mode moves a byte or a word between a register and a memory location addressed
by an index register, base register plus a displacement
a. Register relative
b. Base plus index
c. Base relative plus index
d. Direct addressing mode
For numbers 44-46, code a descriptor that describes a memory segment which begins at location 0008
D6ACH and ends at location –27 3DACH. The memory segment is a data segment that grows downward
and cannot be written. The privilege level is second to the lowest
44. What is the limit
a. 1E670H
b. E6700H
c. D1E57H
d. 001E6H
45. What is the Access Rights Byte?

a. D1H
b. B1H
c. D0H
d. D4H
46. What is the value of G-bit?

a. 0
b. 1
c. 0H
d. 1H
47. Suppose that DS=CADEH, SS=CAFEH, BX=00E3H, DI=09BAH, BP=DADEH, SI=06FEH, MAN=BCH, AND
ONTI=AD. What is the address accesses by the instruction MOV AL, ONTI[BP+SI-3EEH]?
a. D8E7BH-D8E7CH
b. D8E7BH
c. D8C7BH-D8C7CH
d. D8C7BH
48. What is the address accessed by the instruction MOV DX, MAN[DI][BX]? Use the information given in
number 47.
a. CBB39H
b. CB939H-CB93AH
c. CBB39H-CBB3AH
d. CB939
49. Suppose that CS = 3651H, an instruction JMP[3228 6123H] occurs which is located at 7228 EEEEH
what will be the new value of CS and IP, assuming protected mode? Privilege level is third to the highest.
a. CS=00260H and IP=1230H
b. CS=00260H and IP=0123H
c. CS=0026H and IP=0123H
d. CS=0026H and IP=1230H
50. Suppose that CS=C290H, an instruction JMP[ACH] occurs, which is located at 63BC1H, what address
a. C29540H
b. C2954H
c. C2BACH
d. C28AC0H
15. Suppose that CS=4000H an instruction JMP[4C2F 5555H] occurs which is located at 78FFFH, what will
be the new value of CS assuming protected mode? RPL is third to the lowest
a. CS = 002EH
b. CS = 0020H
c. CS = 0029H
d. CS = 002AH
16. Suppose that CS = 943BH, an instruction JMP[CA] occurs which is located at 39BFFH, what address
a. 94378H
b. 94379H
c. 9437BH
d. 9437AH
17. What is the new value of the selector for an instruction JMP [941C 3210H] is executed currently
located at 0001 0123? Assuming DS=0002h and RPL is second to the highest
a. 0015H
b. 0015
c. 0016H
d. 0016
21. For a Pentium V descriptor that contains an address of 00EC 9BAE, a limit of 0BCD7H and G = 1 what
is the ending address location addressed by this descriptor?
a. 0CBA 18ADH
b. 0CBA 1BAEH
c. 00ED 5585H
d. 00ED 5888H
22. This register usually points to the default segment that contains the global and static variables of the
active application
a. Code Segment
b. Extra Segment
c. Data Segment
d. Stack Segment
23. Suppose that DS=BADAH, ES=DEABH, SS=BEAFH, BX=CADEH, DI=0BBAH, BP=77DEH, SI=9DCAH,
GG=9FH, and RB=DC. What are the address/es accessed by the instruction mov EBX, GG[BP+SI+C67H]?
a. D0D9FH-D0DA2H
b. D0D9EH-D0DA1H
c. D0D9EH-D0D9FH
d. D0D9FH-D0DA0H
24. What is the address accessed by the instruction MOV DL, RB(DI-1997) assuming real mode? Use the
given instruction in previous question
a. DDDCEH
b. DDDD0H
c. DDDCFH
d. DDDD1H
25. The total memory access time for a series of instructions in a system with RAM access time of 89 ns
and cache time of 15 ns. Assume hit ratio of 0.65.
a. 45.00 ns
b. 16.64 ns
c. 236.5 ns
d. 46.15 ns
26. What is the type of data dependency of the following instructions for UV pipeline?
MOV AX, BX
MOV DX, CX
a. No data dependency
b. Read after Write
c. Write after Read
d. Write after Write
27. What is the best instruction to use to efficiently initialize the count register to a value of zero?
a. MOV CX, 0d
b. SUB CX, CX
c. AND CX, 0
d. XOR CX, CX
28. The corresponding machine code for the instruction MOV [BP+SI+1936h], DI
a. 89BB3619
b. 8ABA1936
c. 89BB1936
d. 8ABA3619
29. What is the result if the instruction MUL BL is executed if AX = 0ECAh, CX = BA35h and BX = 3A9Dh?
a. 031E
b. 7BE2
c. 29D2
d. 2DC4
30. Calculate the sum using the intel 80386 processor operating under protected mode given the
following arithmetic operation SUB AX, [EBX – EDI + 32Dah] if initially AX = BEFDh, CS = 0010h, DS =
009Ch, and SS = 001Fh. Let EBX = 8645 683Ah, ESP = FADE CBEFh, ESI = 0000 D589h, EDI = 8645 799Bh
a. 8534H
b. BEFDH
c. 39C9H
d. 1161H
31. What does AX contain after execution of CBW if AL initially contains B7h?
a. 0037h
b. 96h
c. FFB7h
d. 00C8h
32. What is the result of XOR AX, CX if AX contains 1234h and CX contains 4567h?
a. 5357H
b. 5753H
c. 31C8H
d. C331DH
33. This instruction rotates the register content to the left, it changes too, the carry flag content with the
most significant bit
a. ROL
b. ROR
c. RCL
d. RCR
34. If it has a value of 0, it selects the global descriptor table and a value of 1 selects the local descriptor
table
a. AV bit
b. G bit
c. D bit
d. TI bit
35. The type of addressing mode for the Intel assembly language Instruction SUB SS:[BP][SI], OFFSET
VAR2?
a. Based Indexed
b. Based Indexed with replacement
c. Immediate
d. Indirect
36. What will be the word value to be copied from address 0x1977BADF given the following memory
content? Implement Big-Endian byte swapping.
1977BADE AF
1977BADF 3D
1977BAE0 BA
1977BAE1 36
1977BAE2 96
a. AB3D
b. BA3D
c. 3DBA
d. D3AB
37.The instruction that if simulated, will clear the content of the accumulator register containing any
value
a. SAR AX, 8h
b. SAR AX, 10h
c. SHR AX, 8h
d. SHR AX, 10h
38. Choose the correct representation for the following instruction

MOV EAX, VAR1
MOV EBX, 9
DIV EBX
MOV EBX, VAR2
SUB EBX, 10
MUL EBX
MOV VAR3, EAX
a. Var3=var1*(9/(var2-10))
b. Var3=(var1*9)/(var2-10)
c. Var3=(var1/9)*(var2-10))
d. Var3=var1*(9/(var2-10))
39.The value of the history bits if the sequence of branch prediction are as follows:
TakenNot TakenTakenNot TakenNot TakenNot TakenNot Taken
a. 11
b. 10
c. 01
d. 00
40. What is the OpCode of the instruction MOV CS, DX?
a. 8E08H
b. 8E0AH
c. 8ECAH
d. 8EC8H
41. This is an additional byte that appends to the front of an instruction to select an alternate segment register.
a. Segment Register
b. Operand
c. Displacement
d. Segment Override Prefix
42. In this technique, multiple instructions are fetched and executed, possibly out of order, in to keep
the pipeline busy
a. Speculative Loading
b. Speculative Execution
c. Speculation Loading
d. Speculation Execution
43. History Bits are initially set to ____ when a new target address is placed into the branch target buffer
a. 00
b. 01
c. 10
d. 11
44. This cycle is used to maintain cache coherency in a microprocessor system

a. Bus Cycle
b. Inquire Cycle
c. Pipelined Cycle
d. Burst Cycle
45. This cycle is used to transfer up to 8 bytes of non-cacheable data between the processor and
memory
a. Bus Cycle
b. Single-Transfer Cycle
c. Burst Cycle
d. Inquire Cycle
46. This is a special cache that stores the instruction and target addresses of any branch instruction that
have been encountered in the instruction stream
a. Branch Target Buffer
b. History Bits
c. Branch Prediction
d. Target Address
47. These 8086 instructions are all pretty straightforward; they load their respective registers with the
specified hexadecimal constant.
a. Register Direct Addressing Mode
b. Immediate Addressing Mode
c. Indexed Addressing Mode
d. Base Relative Plus Index Addressing Mode
48. It is a special 8086 instruction used to compute for the effective addresses
a. LOAD
b. LEA
c. LOADEA
d. MOV
49. This instruction does not require microcode (Malabo) control to execute and generally takes one
clock cycle to complete
a. Miscellaneous Instruction
b. Arithmetic Instruction
c. Data Transfer Instruction
d. Simple
50. What is the value in register CX if CH contains 10h and the instruction mov CX, 7 was executed
a. 0710h
b. 0007h
c. 1007h
d. 0701h
1. The Boolean expression (x,y) for a borrow (binary subtractor) of a half-subtractor circuit circuit is
a. x + y
b. xy
c. x‘ + y‘
d. x‘y
2. Determine the canonical form of the simplified Boolean expression F=x‘y‘z‘ + xz

a. m(0,5,7)
b. m(2,4,7)
c. m(0,2,3,7)
d. m(1,6,7)
3. For the given sequential circuit below(fig.1), determine the input values for x and y that will have a
next state of 1 if the given present state is 0]
a. x = 0, y = 0
b. x = 1, y = 1
c. x = 0, y = 1
4. From the given sequential circuit in fig.1, determine the input values for x and y that will have the
next state of 0 if the given present state is 1.
a. x = 0, y = 0
b. x = 1, y = 0
c. x = 1, y = 1
5
a. B‘CD and A‘C‘
b. AB and A‘C‘D
c. BC’ and AC
d. AB‘D and B‘C
6. From the given combinational circuit, determine the Boolean expression at the output
a. A + B‘C‘ + BC‘D‘
b. A(B‘ + C)(B + C‘ + D‘)
c. A + B‘C + BCD‘
d. A + (B‘ + C)‘ + (B + C‘ + D)‘
7. Simplify th
a. B‘D‘E + CD‘ + ABC‘D
b. AB‘D‘ + AD‘E + B‘C‘D‘
c. B‘D + A‘BD + ABC‘E
d. BD + B‘DE + AB‘C
F = m(0,2,4,6,8) and d(10,11,12,13,14,15)
a. A + BC + BD
b. D’
c. CD + C‘D‘
d. B‘C + B‘D + BC‘D‘
10. From the given combinational circuit, determine the output exressing at F
a. (A‘B‘C‘ + A‘BC + A‘CD‘)‘

b. A(B‘ + C‘)(B + C‘ + D‘)
c. A +B‘C + BC‘D‘
d. A + (B‘ +C)‘ + (B + C‘ + D‘)‘
F = m(0,3,4,7,8) with d(10,11,12,13,14,15)
a. (A+BC+BD)‘
b. D + D‘
c. CD + C’D’
d. B‘C + B‘D + BC‘D
13. Determine the function F from the given combinational circuit
a. (ab)‘ + (cd)‘ + e
b. e + ab‘ + c‘d‘
24. Derived the truth table of the following compound proposition
((p(qr)) (qp))
p q r a b c d
None of the choices

T T T F T T
T T F F T F
T F T F T T
T F F T F T
F T T T F F
F T F T F F
F F T F F F
F F F F F F
25. Derive the truth table of the following compound proposition

(pq) ((pq)(qp))
p q a b c d
T T T F T
None of the choices
T F T F F
F T T F T
F F T F T
26. Which of the following statement are logically equivalent?

(e) pq
(f) (pq)(qp)
(g) pq
(h) (pq) (pq)
a. (a), b, c, and d
b. a, b and c
c. a and b
27. Let P(x,y) be the statement xy=x, if the universal set is all real numbers, which of the following
a. xy( xy = x )
b. xy( xy = x )
c. xP( 1, y )
d. xP( x, 0 )
For nos 28-30, refer to the figure below
28. What will be the inorder traversal of the tree?

a. LAKDRGPEJQIBOFMCNH
b. LAKDRGPEJIBOQMFCNH
c. LAKDRGPEJQIBOMFCNH
29. What will be the preorder traversal of the tree?

a. JPALEGDKRHCMQNFBIO
b. JPALGDKREHCMQBIOFN
c. JPALGDKREHCMQNFBIO
30. What will be the postorder traversal of the tree?

a. LKDRDGAEPIOBQFMNCHJ
b. LKDRGAEPIQBOFMCNHJ
c. LKDRGAPEQIBOFMNCHJ
31. Evaluate 9 3 / 5 + 7 2 - *
a. 10
b. 20
c. 30
d. 40
32. Using the algorithm below, if the input is N = 72, what is the output?
Procedure Algo(N, positive integer)
While (Mod(N,2)=0)
N=N/2
a. 3
b. 7
c. 9
1. When an odd parity generator is used to append the parity bit for an ASCII character whose bit value
is 1000001, the resulting word becomes 01000001.
a. False
b. True
2. A decimal number can be converted to a number with base n by using the repeated multiplication-by-
n method.
a. False
b. True
3. What is the equivalent of the BCD number 1001 into gray code?
a. 1001
b. 1011
c. 1101
d. none of these
4. Convert the number (4310)5 to decimal

a. 580
b. 581
c. 578
d. 579
5. Perform the indicated operation ACEH*2411

a. 194F7H
b. 174F9H
c. 184F8H
d. None of these
6. Subtract 1120 base 32 from BAE2F base 16 using 16‘s complement. What is the difference?
a. -7890 D2H
b. -7890 D1H
c. – 7890 D3H
d. none of the above
7. What is the difference between binary coding and binary coded decimal?
a. BCD is pure binary
b. Binary Coding has a decimal format
c. BCD has no decimal format
d. Binary coding is pure binary
8. How does the computer determine the sign of the number?

a. The leftmost position of a number has a sign convention of 0 as positive and 1 as negative.
b. The computer converts it into signed numbers
c. The computer is just guessing the sign of the numbers
9. The exclusive-OR gate output is high when the inputs are not the same
a. False
b. True
10. All sum of products (SOP) can be called Sum of Minterms (SOM)
a. False
b. True
11. The output of the function F=(a(a‘b + b‘c‘))‘ + (ac‘)‘

a. 0,1,2,5,6,7
b. 0,1,2,3,5,6,7
c. 0,1,2,3,5,6
12. Find the simplest form in sum of products of the function F=fg, where f and g are wxy‘ + y‘z + w‘yz‘ +
x‘yz‘ and (w+x+y‘+z‘)(x‘+y‘+z)(w‘+y+z‘) respectively
a. F = w‘y‘z + x‘yz‘ + wxy‘z‘
b. F = w‘y‘z + x‘yz‘ + wxyz‘
c. F = w‘y‘z + x‘yz‘ + wxy‘z‘
13. What is the equivalent gate of two input NAND gates connected in series?
a. Inverter
b. AND
c. NAND
d. Buffer
14. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a. AND,OR,NOT
b. OR gates only
c. AND, NOT
d. OR and NOT gates
15. What is the form in which the function is expressed as a sum of minterms or product of maxterms?
a. Simplified Form
b. Primitive Form
c. Canonical Form
d. Standard Form
16. Convert the function C = x‘yz‘ + (x‘z)‘ in product of sum (POS)

a. C = x‘y
b. C = x‘z
c. None of the choices
d. C = x + y‘
For 17 – 19 refer to the truth table below
Inputs Outputs
A B C X Y
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
17. What Boolean expression is equal to X?

a. AB + A‘C + BC
b. AB + A‘C
c. AB + AC + BC
d. ABC + A‘BC‘
18. Which of the following is equal to Y?

a. A‘B + A‘C‘ + B‘C‘
b. A + B + C
c. AB + AC + BC
d. ABC + A‘BC + AB‘C‘
19. Which of the following is equal to X + Y?

a. ABC
b. A + B + C
c. A + B + C
d. 1
21. Design a combinational circuit with three inputs and one output. The output is 1 when the binary
value of the input is less than 3. The output is 0 otherwise. Fine the equation for the output F.
a. xy‘ + x‘z‘
b. x‘y + x‘z‘
c. x‘y‘ + xz‘
d. x‘y‘ + x‘z‘
22. You are to design a combinational circuit with a mode input M. If M=0, the circuit should act as a 4
bit adder and if M=1 the circuit should act as a 4 bit subtractor. 7486 – Quad 2 input XOR gate (30
Php/IC), 7408 – Quad 2 input AND gate (25Php/IC) and 7483 – 4 bit adder (35Php/IC) are the only
available IC‘s. Find the least probable cost for the design.
a. 100 Php
b. 65.00 Php
c. 95 Php
23. Determine the output functions of a combinational circuit that converts 2,4,2,1 code to 8,4,-2,-1
code. The inputs and outputs of the CLC are A,B,C,D and w,x,y,z respectively.
a. w=AB‘ + BD + BC, x=B‘D + BCD‘, y=C‘D + CD, z=A
b. w= AB‘ + BD + BC, x=B‘D + BCD‘, y=C‘D + CD, z=C
c. w=AC‘ + BD + BC, x=B‘D + BCD‘, y=C‘D + CD, z=C
24. Which is the output (S,C) of a full-adder if the inputs A,B and C are 1,1, and 1?
a. S=0,C=0
b. S=1,C=1
c. S=1,C=0
d. S=0,C=1
25. The 74LS83 is an example of a 4 bit parallel adder. To expand this device to an 8 bit adder, you must:
a. Use two adders with the carry output of one connected to the carry input of the other.
b. Use four adders with no interconnections
c. Use two adders and connect the sum outputs of one to the bit input of the other
d. use eight adders with no interconnections
26. This principle states that every algebraic expression deducible from the postulates of Boolean
Algebra remains valid if the operators and identity elements are interchanged.
a. Boolean Algebra
b. De Morgan‘s Theorem
c. Duality Principle
27. Binary logic deals with binary variables that take on two discrete values and with the operations of
mathematical logic applied to these variables
a. True
b. False
28. A combinational circuit with four inputs (a,b,c,d) and one output (F) has the following specifications.
The output is high if b=c=d=0 or a=c=d=1. The output is low if a=0 and c=1 provided that d=0 or b=0. The
output is don‘t care for the other combinations of the input variables
a. F = a‘ + c
b. F = a + c‘
c. F = a‘b + c
29. A multiplexer with a 4bit SELECT signal (S3,S2,S1,S0) can accommodate a maximum of how many
input signals?
a. 8
b. 2
c. 16
d. 4
30. The procedure for implementing a combinational circuit by means of a Decoder and OR gates
requires that the Boolean functions for the circuit be expressed as a Sum of minterms
a. True
b. False
31. A 2x4 Decoder with enable input (active low) is constructed with four AND gates and three Inverter
gates. What are the values of the four input lines (D0, D1, D2, D3) if the inputs A and B and the enable
input are 0, 1, and 0 respectively?
a. D0 = 0, D1 = 1, D2 = 0, D3 = 0
b. D0 = 1, D1 = 0, D2 = 0, D3 = 0
c. D0 = 0, D1 = 0, D2 = 1, D3 = 0
32. In general, a multiplexer has

a. one data input, one data output and one select input
b. multiple data inputs, multiple data outputs, and selection inputs
c. multiple data inputs, one data output and selection inputs
d. one data input, several data outputs and selection inputs
33. Determine the flip-flop input functions of a sequential circuit that follows the repeated state
sequence 0, 1, 2, 3, 4 and 6. Use D-flipflops.
a. DA=A‘B + AB‘, DB=A‘B + C, DC = A‘B‘C‘
b. DA=A‘B + AB‘, DB=AB + C, DC = A‘B‘C‘
c. DA=A‘B + AB‘, DB=AB + C, DC = A‘B‘C
34. A PN flip-flop has four operations clear to 0, no change, complement and set to 1, when inputs P and
N are 00, 01, 10, and 11 respectively. Derive the characteristic equation of PN flip-flop.
a. Qn = P‘Q + P‘Q‘
b. Qn = PQ‘ + NQ
c. Qn = PQ‘ + NQ‘
35. A 4 bit binary up/down counter is in the binary state of zero. If It is in the DOWN mode, what should
be its next state?
a. 0001
b. 1000
c. 1110
d. 1111
36. A positive edge-triggered T flip-flop has an initial state of 0. What will be its next state when a high
input signal is injected and the falling edge of the clock arrives?
a. Flip-flop does not change state
b. flip-flop resets
c. flip-flop sets
d. flip-flop becomes unpredictable
37. In an SR Flip-flop, when the signal in the S line is 1 and the signal in the R then the output signal
a. becomes 0
b. becomes 1
c. does not change
d. becomes undefined
38. The group of bits 10110101 is serially shifter (rightmost bit first) into an 8 bit parallel output shift
register with an initial state of 11100100. After two clock pulses, the register contains
a. 01011110
b. 10110101
c. 00101101
d. 01111001
39. A feature that distinguishes the JK flip flop from the SR flip-flop is the
a. clear input
b. toggle condition
c. present input
d. type of clock
40. Asynchronous counters are also known as

a. modulus counters
b. ripple counter
c. multiple clock counters
d. decade counter
41. The behavior of a synchronous sequential circuit depends upon the inputs at any instant of time and
the order in continuous time in which the inputs change.
a. false
b. true
42. As asynchronous counter differs from the synchronous counter in

a. the no. of states in its sequence
b. the type of flip flops used
c. the value of the modulus
d. the method of clocking
43. How many states are there in a 3 bit ripple counter?

a. 4
b. 2
c. 6
d. 8
44. A set of flip flops that goes through a predetermined sequence of states upon the application of
clock pulses
a. Register
b. Memory
c. Counter
45. How will you design an n-bit register with m number of operations?
a. using nx1 multiplexer with m select input lines
b. using mx1 multiplexer with n select input lines
c. using 2nx1 multiplexer with n select input lines
d. using 2mx1 multiplexer with m select input lines
46. The 74LS1941 IC has _____ pins

a. 18
b. 16
c. 12
d. 14
47. What is the r‘s complement of 23368?

a. 5442
b. 5441
c. 5440
d. 5443
48. If a particular processor has a cache memory with a RAM access time of 85ns and a cache access
time of 15ns, determine the average memory access time if the hit ratio is 0.75.
a. 75ns
b. 32.5ns
c. 15ns
d. 36.25ns
49. The execution time for a mov instruction going from memory to register requires how many clock
cycles?
a. 10+EA
b. 9+EA
c. 8+EA
d. 16+EA
50. Among the following flags, which is classified as a status flag?

a. IF
b. DF
c. TF
d. CF
51. Determine the number of cycles needed to execute the program fragment in RISC.
mov ax, 0
mov bx , 10
mov cx, 5
begin add ax, bx
loop begin
a. 13 cycles
b. 22 cycles
c. 18 cycles
d. 32 cycles
52. Which operation according to RISC architecture is the most frequently used?
a. conditional branch
b. load
c. store
d. add
53. Each instruction with a major opcode in an IA-64 contains how many bits?
a. 31 bits
b. 41 bits
c. 35bits
d. 32 bits
54. In an IA-64 architecture, out of 128 general and floating point registers how many are always
available
a. 96
b. 32
c. 128
d. 95
55. What is the result of NOT AL if AL contains 3Eh?

a. C1h
b. 34h
c. F6D0
56. It is defined as the time required completing one operation.

a. T states cycle
b. Instruction cycle
c. machine cycle
57. These 8086 instructions are all pretty straightforward; they load their respective registers with the
a. register direct addressing mode
d. base index with displacement addressing mode
58. If bx is 30h, si with 20h, array is 100h and ds is 10h the instruction mov [bx], cl generates an address
equal to
a. 100h
b. 120h
c. 130h
d. 40h
59. If register AX contains the value 1000h and register BL contains 80h, what is the result of mov AL, BL
a. 1080h
b. 1000h
c. 80h
60. What type of addressing is described by the instruction, mov cl, [bx + 4]?
a. register indirect
b. base plus index
c. base relative plus index
d. register relative
61. A processor running in this mode can exploit only the lowest 20 bits of its address bus and is
therefore limited to the meager 1MB memory space.
a. real-mode
b. protected mode
c. virtual mode
62. If AX and BX contains 1234h and 2345h, respectively, what is the content of register BX for ADD AX,
BX?
a. 1234h
b. 2345h
c. 3579h
63. In this mode an operating system piece of code handles these exceptions and emulates the
offending instructions which ensures a smooth fail-safe operation tasks running on the system.
a. real-mode
b. protected mode
c. virtual mode
64. What is in DX after CWD executes, with AX containing 4000h?

a. 0400h
b. 0000h
c. 0099h
65. What is the result of NEG AX if AX contains FFECh?

a. F7D8h
b. 0020h
c. 0014h
66. This register usually points to the default segment that contains the global and static variables of the
active application.
a. code segment
b. extra segment
c. data segment
d. stack segment
67. What is the result of IMUL CL if AL contains 20h and CL contains 80h?
a. F000h
b. F6E9h
c. 1000h
68. This is responsible in producing control signals as the instruction is determined.

a. Control Unit
b. control logic
c. control signal
d. control system
69. This segment register is used for anything the programmer wishes.
a. code segment
b. data segment
c. stack segment
d. extra segment
70. If SS = EEECH in a protected mode system, which entry, table and privilege level are selected?
a. 7645
b. 7645H
c. 7644H
d. 7644
71. If DS = 002EH, what is the ending address assuming protected mode?

a. 0102 4FFFH
b. 0002 5000H
c. 0000 212FH
d. 0000 2128H
72. In this technique, data is preloaded before it is needed, while the other instructions are also being
executed.
a. Speculation
b. Speculative
c. Inspection
d. Loading
73. This is the binary equivalent of the worded instruction inside the microprocessor.
a. Machine language
b. binary language
c. Operation Code
d. OPCODE
74. This refers to the location that is called or jumped to instead of the actual numeric addresses.
a. Directive
b. Label
c. Heading
d. Address name
75. In real mode, what is the ending address of the segment located by the segment register value
BFFFH?
a. CFFFE0H
b. CFFEFH
c. CFFEF0H
d. CFFFEH
76. Suppose that DS=004CH, what will be the address/es accessed by the instruction MOV
ANT[EBP][EDI+AABBH], ESI, assuming protected mode? ANT = 0A29H, EBP = 3058 FACEH, ESI = DEAC
6491H, EDI = 36ED CA37H.
a. 674F99E8 – 674f99EB
b. 674F99EB – 674F99EE
c. 674F99EA – 674F99ED
d. 674F99E9 – 674F99EC
77. Suppose that CS = 7200H an instruction JMP

[3EEEEEH] occurs which is located at 72FFFH, what will be the new value of CS and IP, assuming real
mode?
a. CS=3001H and IP=EEDEEH
b. CS=30010H and IP=EEDEEH
c. CS=30010H and IP=EEDEE0H
d. CS=3001H and IP=EEDEH
78. Suppose that CS=7200H an instruction JMP[EE] occurs which is located at 72CEEH, what address will
the program jump to assuming real mode?
a. 71FE0H
b. 71FEH
c. 71FEEH
d. 71FEE0H
79. Suppose that CS = 7228H, an instruction JMP [7228 EECCH] occurs which is located at 7228 EEEEH,
what will be the new value of CS and IP, assuming protected mode? Privilege level is third to the lowest.
a. CS=0041H and IP=CC00H
b. CS=0410 and IP=0ECCH
c. CS=0041H and IP=0EC0H
d. CS=0041H and IP=0ECCH
For numbers 80 – 82, code a descriptor that describes a memory segment that begins at location 000E
3AEEH and ends at location 008E 6EEEH. The memory segment is a code segment and can‘t be read. The
privilege level is second to the lowest.
80. What is the limit?
a. 00803H
b. 80340H
c. 03400H
d. 08030H
81. What is the access rights byte?

a. D8H
b. D9H
c. DCH
d. D6H
82. What is the value of the G-bit?

a. 0
b. 1
c. 0H
d. 1H
83. For a Pentium V descriptor that contains an address of 00EE CCEEH, a limit of 00EEEH, and G = 1,
what is the ending address locations addressed by the descriptor?
a. DDBCED0H
b. DDBCEDH
c. 01DDBCED0H
d. 01DDBCEDH
84. Suppose that CS=1500H and DX=EECCH, an instruction JMP [DX] occurs which is located at 23FFFH.
What address will the program jump to assuming real mode?
a. 23ECCH and 23CEDH
b. 103CCH and 103CDH
c. FECEH
d. 12ADH
85. Suppose that DS = CADAH, SS=CAFAH, BX=00E3H, DI=09BAH, BP=DADEH, SI=06FEH, LIER=BCH and
YOU=AD. What is the content of the destination register in the instruction MOV CX, YOU[BP+SI-DEEH]?
a. D843CH
b. D922AH
c.D843BH
d. D9229H
86. What is the address accessed by the instruction MOV DL, LIER[DI][BX]? Use the given information in
the previous question.
a. CB8F9H
b. D8FFBH
c. D9B2FH
d. D843BH
87. Assuming AL=9FH and DL=20H, what will be the content of register AL after executing the following
instructions?
ADD AL,DL
DAA
a. 09
b. 05
c. 09H
d. 05H
88. Choose the appropriate AND instruction to preserve its 1, 7, 10, and 15 of the register DX and clear
all others. Assuming DX=DEAFH
a. AND DX, 5B3DH
b. AND DX, A4C2H
c. AND DX, 5BC2H
d. AND DX, A43DH
89. What is the equivalent MOV instruction of the given byte size information?
Byte 1 – 10001011
Byte 2 – 00110110
Byte 3 – 11011110
Byte 4 – 11111010
a. MOV SI, SS:[BP+FADEH]
b. MOV SI,[FADEH]
c. MOV SS:[BP+FADEH], SI
d. MOV [FADEH], SI
90. This is used to select data memory addressing mode

a. MOD Field
b. REG Field
c. R/M Field
d. Direction Bit
91. What segment register is accessed by the instruction MOV AX,ES:[DI]?

a. Data Segment
b. Extra Segment
c. Code Segment
d. Stack Segment
For numbers 92-94, lines 1-10 is an entire program
(1) STC (6) ADD AL, BL
(2) STD (7) CLC
(3) STI (8) MOV CL, AL
(4) MOV AL, ED (9) MOV AL, F1
(5) MOV BL, 67 (10) SUB CL, AL
92. What is the final content of the register CL after executing the 10th line?
a. 63
b. 54H
c. 54
d. 63H
93. What is the content of carry flag after executing the 8th line?
a. 0H
b. 0
c. 1H
d. 1
94. What is the content of the auxiliary flag after executing the 6th line?
a. 0H
b. 0
c. 1H
d. 1
95. Other term for Double Indirect

a. Twice indirect
b. Indirect double
c. Double register
d. Indirect-Indirect
96. This flag enables trapping through an on-chip debugging feature.

a. Interrupt
b. Trap
c. Tap
d. Error
97. This is responsible for decoding an instruction after it has been fetched.
a. Control Unit
b. Control Logic
c. Instruction Decoder
d. Decode Cycle
98. What is the opcode of the instruction MOV AX,[SI]?

a. 8B04H
b. 8B00H
c. 8904H
d. 8900H
99. This is an additional byte that appends to the front of an instruction to select an alternate segment
register.
a. segment register
b. operand
c. displacement
d. segment override prefix
100. During this operation, the instruction pointer increments.

a. Decode
b. reset
c. Fetch
d. Execute
101. This category of processing utilize few instructions and a simpler addressing mode.
a. RISC
b. Processor
c. CISC
d. Math Coprocessor
102. This is a special type of high speed RAM where data and its address are stored.
a. NVM
b. Cache
c. ROM
d. RAM
103. This technique helps identify possible interruptions to the normal flow of instructions through the
U and V pipeline.
a. Pipelining
b. Bus Cycle State
c. Branch Prediction
d. Atomic Operation
104. This is a small portion of a program

a. Threading
b. Hyperthreading
c. Thread
d. MicroOps
105. These 8086 instruction are all pretty straightforward, they load their respective registers with the
a. Register direct addressing mode
d. Base Index with displacement addressing mode

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1.

2. The pattern of the statement below follows which propositional statement?

4. The function of f(x)= + sqrt (x^2+1) from R to R is classified as what type?

5. Which of the following relations on (0,1,2,3) is classified as equivalence relation

6. Which of the following statements are logically equivalent?

12. Determine the boolean expression at the output F

22. It is a binary code 2 but 5 5 representation of the decimal value 3

24. Determine the product of 1110 and 10

43. A set of lines connects two or more elements of a computer system

3. Derive the truth table of the following compound proposition, (q→r)↔(¬p˄q)

5. Is (p→ (r→q)) and ((p˄r)→q) logically equivalent?

8. What is the Pre-Order transversal of the tree below

9. What is the postorder transversal of the tree in question#8

11. What is the result of the postfix expression given below? 5 2 1 - - 3 1 4 + + *

12. Does the directed graph below have a Hamiltonian cycle?

13. Given the algorithm below

14. What will be the output of the algorithm below if n=5?

18. What is the equivalent of 64k byte in hexadecimal?

19. The simplified Boolean expression of (A+B)(A+C)+AB+BC+B‘C is:

24. Which of the following defines de Morgan‘s Theorem

33. Among the following flags, which is classified as a status flag?

38. What is the result of NOT AL if AL contains 3Eh?

39. It is defined as the time required completing one operation

47. What is in DX after CWD executes, with AX containing 4000h

48. What is the result of NEG AX if AX contains FFECh?

50. What is the result of IMUL CL if AL = 20h and CL = 80h

1. The complexity notation Q(bn) where b>1

3. It is a mathematical instruction sometimes used to design digital logic computer programs

4. The complexity notation Q(nb) where b 1?

9. Determine the 16‘s compliment of B2FA

10. Simplify (x+y)(x+y‘)

11. Simplify ABCD + A‘BD + ABC‘D

12. Simplify (xy‘ + zy‘ +z + xy + wz) – MALABO

13. Determine the complement of the function F = (x‘ + y + z‘)(x + y‘)(x + z)

15. If A = 1011_0001 and B = 1010_1100 then evaluate A XOR B

16. If A = 1011_0001 and B = 1010_1100 then evaluate A AND B

30. A weighted code used to represent the decimal 6 to 1001

37. What is byte number 3? Refer to problem #36

38. What is byte number 6? Refer to problem #36

41. What is the ending address?

43. What is the RPL refer to problem #42

44. What table is selected? Refer to problem #42

50. Which of the following is not part of U and V pipelining?

2) Find the value of the prefix + -  3 2  2 3 / 6 – 4 2

4) The function f(x) = sqrt(x2+1) from R to R is classified as what type?

7) The Graph below is classified as

8) Determine the value of the prefix *+ 3 + 3 3 + 3 3 3

13) Given the state table 2 below

19) Determine the essential prime impl

26) The 2‘s compliment representing the value -12 is

For number 32-35. Refer to Figure.1(TABLE)

37) What is the Access Rights Byte?

38) What is the Value if the G-bit?

47) A set of lines connects two or more elements of a computer system

2. EPIC stand for

4. Byte1 = 1000 1010

8. This flag enables trapping through on-chip debugging feature.

9. This microprocessor is ten times faster than Intel 8008

11. It is also called Little Endian

12. If SS=FEEEh in a protected mode system which is selected?

24. What is the MOD field of the Instruction MOV[1000h], DL

30. What is the IP? Refer to problem #29

34. What does the instruction IN AL, 13 accomplishes?

40. This is the first manufacturer of the microprocessor