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Synchronisation Architectures, Algorithms and Demodulation Performances for the

EuroSkyWay Payload based on Symbol-Synchronous MF-TDMA

D. Giancristofaro(1), R. Ardoino (2)

Alenia Aerospazio,
Via Saccomuro 24, 00131 Roma, ITALY
Tel. 06-4151 2669, Fax. 06-4151 2507
Alenia Aerospazio,
Via Saccomuro 24, 00131 Roma, ITALY
Tel. 06-4151 2695,


The present paper introduces the EuroSkyWay (ESW) user link synchronisation strategies and User Multi-Carrier
Demodulator (UMCD) algorithms, also providing the performances (both individual and overall) obtained using the
above mentioned choices. In order to maximise frame efficiency, the user link is based on Symbol-Synchronous MF
TDMA, which will soon be introduced.


EuroSkyWay (ESW) envisages a high number of active users, high flexibility of capacity allocation (16 kbps to 2
Mbps), while maintaining a high frame efficiency. The latter can be achieved using Symbol-Synchronous MF-TDMA.
The key feature of Symbol-Synchronous MF-TDMA consists in the User Terminal (UT) synchronising its frequency
and clock timing to the onboard demodulator references. During the Acquisition Phase this is done by means of
Acquisition Bursts (AB); afterwards, during transmission, the UT maintains synchronisation steady state using the
Steady State Synchronisation Bursts (SSSB). The adopted procedure allows the onboard demodulator’s algorithms to
work at a single sample per symbol. Furthermore, the selected technique does not require use of Traffic Burst guard
times or Unique word (UW), since synchronization is achieved on SSSBs, sent on a multi-frame basis (once every ten
frames). Alignment of the optimum sampling point for all of the users removes the need for individual user link
interpolation at the onboard receiver.

MF-TDMA Architecture: Acquisition & Synchronisation strategies based on Service Bursts (AB’s & SSSB’s):

The following are the synchronisation phases which a UT undergoes to initiate a connection:
• Acquisition Phase: the UT accesses the network via a slotted-Aloha protocol, on specific frequency and time slot:
AB’s are sent by the UT to onboard UMCD unit which:
• Estimates the Frequency error over an a priori 0,0,π,π known pattern1 (coarse frequency estimation
algorithm, soon introduced)
• Estimates the timing offset (in symbols) by means of UW correlation
• Estimates the timing phase misalignment over the 0,0,π,π pattern (IF algorithm, soon introduced)
• Estimates Eb/N0 to allow implementing Up Path Power Control (UPPC).
• Above described estimates are sent back to the UT, by means of the Acquisition Loop Back Message
Figure 1, Figure 2 and Figure 3 depict the conceptual processing which is executed on-board by the UMCD, which is
different for the Service and Traffic bursts.
Once the above acquisition phase, one or more traffic channels are granted to the UT, which transitions to the
synchronisation steady state phase:

It is constituted by a periodic 0,0,1,1 bit sequence (there are overall 164 symbols in ABs and 68 in SSSBs), the same
pattern is simultaneously sent on both I and Q components.

generation* Burst Buffer Latency Memory
Data-Mode RAMP
V&V Phase
Frequency UW
Estimator detector

From demultiplexer / memory


at a rate Rs
( IF SAMPLING ) Timing Offset
Frequency Estimator Estimator

Figure 1: UMCD conceptual processing Figure 2: UMCD Service Carrier processing

From demultiplexer


Burst Buffer Latency Memory
at a rate Rs

Data-Mode RAMP
V&V Phase

Figure 3: UMCD Traffic Carrier processing

• Steady State Phase: UT starts communication by sending Traffic Bursts (TBs) and continues to maintain itself
synchronised to the UMCD by sending SSSBs over which: Frequency Error, Timing Phase and E b/N0 are estimated.
Eb/N0 estimation allows continuing operation of Up Path Power Control (UPPC).
During the Synchronisation Steady State Phase just the presence of the UW (not its position) is checked: if UMCD
does not find the UW where it is expected, a specific flag is set and the UT restarts the Acquisition Phase to avoid
collision with other users. Frequency, timing and Eb/N0 estimates, plus the above mentioned UW detect flag are
sent to the UT by means of the Synchronisation Loop Back Message (SLBM).
Traffic Bursts are demodulated and FEC decoded, then they are sent to Base-Band Processor (BBP) for switching
and re-transmission in the wide-band Down-Link stream. Thanks to UT assisted Frequency and Timing correction
strategy TB’s arrive to the UMCD already time-synchronised with just a limited residual frequency error so they
are processed by:
• a fine frequency correction algorithm, Fine Frequency Estimation Algorithm soon introduced, which
tracks short-term frequency variations,
• a phase estimation and correction algorithm based on the Viterbi and Viterbi (V&V) algorithm.
Let us now summarize the above concepts. For the initial acquisition of the user terminal communication link, with
reference to the operation of the onboard UMCD estimators for frequency, symbol timing and carrier phase, the
following guidelines have been followed:
1) Carrier frequency estimation can be executed in absence of other synchronisation information (i.e., symbol
timing and carrier phase). Hence, it will be executed first, on the known 0, 0, π, π pattern of the first AB using
data aided (DA) estimation. This will be performed operating at one sample per symbol, at the output of the
receive matched filter.
2) Once the carrier frequency has been estimated, frequency error is corrected onboard, on the same buffered
burst (first AB), allowing extraction of symbol timing phase of the received signal. This means that optimum
sampling instant of received signal is identified, so that user terminals can be instructed to adjust both their
transmission frequency and symbol timing to match UMCD timing. Timing is estimated using one sample per
3) The user terminal sends the second AB onboard with adjusted symbol timing (and carrier frequency).
Frequency and Timing estimators reveal values within traffic-mode required accuracy. Simultaneously, burst
residual frequency error is estimated by DA frequency estimator and open loop corrected on the buffered burst,
so that feed-forward phase estimation can be executed. This occurs with the information provided by a single
sample per symbol (V&V algorithm will be used). These two actions will nominally happen onto the second
received burst, whose UW is demodulated and UW offset identified. (Note that on a traffic burst instead than
the DA frequency estimator a specific Traffic-mode estimator will be used).
Hence, as already mentioned, steady state synchronisation maintenance will start, requiring cyclic estimation of
frequency and symbol timing onto the SSSB bursts.


The modulation scheme envisages for the Up-Link Differentially Encoded QPSK modulation (De-QPSK).
Differential Encoding is extremely useful since it avoids, in TBs, the use of a UW pattern to recover absolute phase
(UW based ambiguity resolution). Additionally, De-QPSK is very advisable due to its robustness to cycle slips in
the recovered Carrier phase. As a matter of fact, a cycle slip on a De-QPSK stream only causes two bits in error (in
most of cases, thanks to Gray encoding) instead of a burst loss as it happens when Absolute QPSK is used.
Hence, on the basis of the BER requirements imposed, and of the chosen the modulation and coding scheme (De-
QPSK or standard QPSK) the specific requirement on cycle slipping results. To achieve it, the phase estimator
integration time must be selected, keeping into account the Eb/No operating point.
FEC coding scheme is based on concatenation of a shortened Reed-Solomon (76,60, 2t = 16) code with a 10/9 Soft
Decision Parity Check Code (10/9 SDPCC). The SDPCC is simply obtained by adding a Parity Check bit for every
9 bits (on both the I & Q branches): this allows, on the receiver side, the easy correction of the least reliable symbol
(i.e. that one with smaller amplitude). The Differential Encoding is performed after the Reed-Solomon encoder but
before the SDPCC encoder: as a matter fact, being the SDPCC rotationally invariant - since it is a linear code and
the all ones word belongs to the code [1] - the Parity Check decoding can be performed before Differential
SDPCC has been introduced as an additional means of adding coding gain, allowing Reed Solomon to work at
lower Eb/N0.


This section deals with the description of the algorithms implemented within the UMCD.
Due to the nature of messages, segmented in TDMA bursts, feed-forward algorithms have been preferred for all of
the synchronisation functions; refer to [2] about implementation within then UMCD Application Specific Integrated
Circuit (ASIC).

Frequency De-Multiplexing & Rx Matched Filtering

The first action to be performed is the frequency de-multiplexing of the Multi-Carrier signal received onboard
(having a gross bandwidth of about 17.5 MHz). After three down-conversion steps (the 1st LO is at 17.28 GHz,
the 2nd at 11.5 GHz and the last one at about 350 MHz), the signal is brought down to a central IF of about 50 MHz.
At this point, a Surface Acoustic Wave (SAW)filter acts as anti-aliasing filter; the signal is then IF sampled by a 40
MHz A/D.
Three configurations are selectable for the Carrier Group:
• Sat-A: 102 Carriers of 171 KHz each carrying a 160 Kbit/s net bit rate.
• Sat-B: 32 Carriers of 547 KHz each carrying a 512 Kbit/s net bit rate.
• Sat-C: 8 Carriers of 2.19 MHz each carrying a 2048 Kbit/s bit rate .
Carriers are frequency de-multiplexed by means of a polyphase network (using a re-configurable Fast Fourier
Transform (FFT) implemented using a Winograd algorithm). A Square Root Raised Cosine (SRRC) impulse
response (with 1/3 roll-off) has been used as a prototype filter for the polyphase network: this allows the polyphase
network performing also the matched filtering.
The polyphase network outputs signal streams sampled at 1 sample per symbol .

Frequency Estimation Algorithms – Service Bursts estimator

The ESW system envisages the use of low cost, mobile user terminals. A wide range estimator is required during
the acquisition phase: it must cope with up to a ± 26.5 kHz carrier frequency error on the first acquisition burst. The
specified carrier frequency error on the successive traffic bursts reduces to ± 2 kHz. Furthermore, carrier frequency
error estimation accuracy must be better than 0.003/Ts (3σ value) at an 8.0 dB Eb/No.
This section provides description and simulation results for the onboard frequency estimation techniques. Two
different kinds of data aided (DA) estimators have been devised, the first operates on the AB while the other
operates on the SSSB. The third frequency estimator, or Traffic-Mode Frequency Estimator has to cope with the
random-data modulated signal (non data aided, NDA).
Z -2 (x)*
Rate Rs-Sampled
Matched Filter ∑
H −2
s ( nTs )

Figure 4: Modified DA, doubled-step Phase Incremental Estimator

Estimator Sensitivity To Es/No



Estimate Std. Dev. and Bias, f/Rs

Bias, @ef=0
Std. Dev., @ef=0
Bias, @ ef=27/128 Rs
0.003 Std. Dev., @ef=27/128 Rs



0 2 4 6 8 10 12 14

Figure 5: Simulation Results for the dependency from Es/No; estimate standard deviation and bias expressed
as fractional frequency, f/Rs. The above performances are for a 27/128 RS frequency error.
A phase increment-based estimator for wide frequency estimation ranges, which is capable also of operating
without timing information has been devised. In order to cope with the specific pattern used on the ABs and SSSBs,
allowing also joint estimation of timing error, a proper the time spacing between the two samples used for phasor
product has been selected, providing a DA estimator. An additional periodic sign inversion has also been
introduced. With this trick, also DA operation becomes very easy and light to implement. The estimator
architecture is shown in Figure 4 and its performances are depicted in Figure 5. It is possible to demonstrate that the
resulting DA frequency estimate is independent of timing. The 0,0,π,π pattern allows frequency and timing
estimation for closed loop correction in order to keep synchronized traffic bursts; hence, demodulation
performances are tightly bound to the performances of the estimations executed on SSSB. On the other hand, the
use of short clock and frequency synchronization patterns is desirable, e.g., to increase the number of users that can
be synchronized for a specified resource employment. The specifications assign to each SSSB 68 symbols, since it
is quite short an enhanced version the above presented frequency estimation algorithm is required. Since the V&V
estimator requires a residual frequency error, efre , of about 0.001 of the Symbol Rate (RS) for a performance
compliant to the specifications, it is highly recommended that the frequency estimate has a 3σ performance better
than 0.001 Rs. This allows to guarantee that deviations higher than 3σ only happen with a probability lower than
2.7 10-3. This probability applies to a Gaussian r.v., which has been demonstrated via simulation to model very
accurately the estimate p.d.f.. With the devised estimator for SSSB, using 68 symbols, at a 9 dB Es/No, the
following values apply for residual frequency error efre as seen by the V&V phase estimator (Table 1).

Table 1: Probabilities for the residual Frequency Error after Frequency Correction
p(efre > 2σ ) = p( efre > 9.6 10-4 Rs ) = 4. 10 -2
p(efre > 3σ ) = p( efre > 1.44 10-3 Rs ) = 2.7 10 -3
p(efre > 4σ ) = p( efre > 1.92 10-3 Rs ) = 6.3 10-5
Frequency Estimation Algorithms – Traffic Burst estimator

This paragraph presents the results obtained for the estimator dedicated to small-range frequency estimation on
traffic bursts. Symbol timing synchronization is assumed to be achieved, hence, this estimator can operate with
knowledge of timing information, differently than the estimators presented in the former paragraph. On the other
hand, the Traffic-Mode Frequency Estimator must operate in presence of random data modulation. Hence, the
selected estimation algorithm – phase increment based - employs ad-hoc modifications of the V&V feed-forward
phase estimator. The estimator algorithm selected allows reasonable robustness to cycle slipping, excellent standard
deviation performance, wide range, and limited implementation complexity. In its design, minimization of the noise
per noise products and amplification of the entity to be estimated has been kept in mind, introducing an additional
Moving Average Filter (MAF). The maximum frequency error than can be estimated is expressed by:
ef ≤ , (1)
where the parameter H is the number of symbols in the estimator internal accumulator. The behavior of the
estimator, in terms of standard deviation is presented in Figure 6. Estimator range is clearly reflected by the
behavior of standard deviation curves.

Viterbi and Viterbi Algorithm

The V&V algorithm is a well-known technique employed in carrier phase estimation for TDMA burst carrier
recovery [3] . Its mechanism is very simple: for each symbol sk a complex phasor is obtained (the symbol phase is
multiplied by four in order to eliminate data modulation), phasors are summed and then the phase estimate is
 NV &V 
 ∑ exp ( j ⋅ 4 arg (s k ))
V& V = ⋅ arg (2)
4  k =1 
where arg (•) indicates the argument (i.e. the phase) of a complex number.
The Estimated phase standard deviation is given by the following formula:
1 N0 E 
σ Φ ,V& V = ⋅ ⋅ Γ S ; ∆f  (3)
N V& V 2ES  N0 

Estimator Standard Deviation for different values of H

(estimator limit smaller for higher H)

Estimator Std. Dev.


1.E-04 H=7


0.00E+00 5.00E-03 1.00E-02 1.50E-02 2.00E-02 2.50E-02 3.00E-02 3.50E-02 4.00E-02

Frequency Error Normalised to Symbol Rate, ef

Figure 6: Estimator standard deviation normalised to RS for different values of H

The first term is the well-known Cramer-Rao Bound (CRB) for Phase Estimation (NV&V is equal to 17 and it is the
window length in the V&V estimator) and Γ( E S / N 0 ; ∆f ) is the loss w.r.t. the CRB (calculated in [3]) which is
function of the symbol SNR and of Carrier Frequency error ∆f / R S .
In Figure 7 V&V performances are depicted vs. ES/N0 at different values of the frequency error normalised to the
Symbol Rate RS.
Timing Estimation Algorithm

The timing estimation algorithm (said IF algorithm since it is independent from the carrier phase) takes a timing
estimate over the 0, 0,0,π,π pattern (the pattern is NB symbols long). Since the 0,0,π,π pattern, once passed through
the SRRC Transmit filter becomes in practice a sinusoid with frequency RS/4 (since it is cleaned of higher order
components), by estimating its phase the Clock (CK) timing phase can be obtained thanks to the following
2π ⋅ (R S / 4) ⋅ τ CK = φCK (4)
The phase estimation over the SSSB pattern is performed in two steps:
1. The 4-points DFTs X(1) and X(3) are taken over (NSSSB/4) chunks of complex samples
2. DFT couples are multiplied and then accumulated and summed.
The 4-points DFT makes the estimation φ CK robust w.r.t. to frequency errors whereas the trick to multiply DFT’s
outputs makes it independent by the knowledge of the carrier phase.
Even if the timing estimation algorithm operates in non-Gaussian Noise (due to the non linear DFT’s product), its
performances are close to the CRB for ES/N0 > 0 dB, so the Timing estimate (normalised w.r.t. the Symbol period
TS) is:
στ 1 2 N0
≅ ⋅ ⋅ (5)
TS π N B E S
Table 2 reports timing estimation performances for ABs and SSSBs.


8 ∆F Ts==0"0.

∆F Ts==0.003
DFTs 0.003
∆F Ts==0.005
σΦ [degs]

DFTs 0.005

5 6 7 8 9 10 11 12 13 14 15
Es/No [dB]

Figure 7 V&V algorithm phase estimation performances

Table 2: Timing Algorithm Performances

Burst type AB SSSB
NB (useful samples number in 0,0,ππ pattern) 164 68
ES/N0 [dB] 9 9
Resulting στ ~ 1.25 % TS ~ 2 % TS


The system has been first simulated at symbol level (i.e. at 1 sample symbol): this first simulation had the goal to
individuate the Coding Scheme performances: i.e. Reed-Solomon + De-QPSK + 10/9 SDPCC.
Figure 8 depicts simulation results: BER curves shown are obtained respectively at channel level, inner decoder
level and outer decoder level; by extrapolating the obtained Reed-Solomon BER curve, it is predictable that the
wanted 10-10 BER is achieved at about 10 dB of the channel ES/N0.
We remind that:
Synchronisation patterns in ABs and SBs have different size since a greater accuracy is required in acquisition
phase (during acquisition the frequency error is also greater than in successive phase so timing estimation presents
some losses).
ES 2 RE b ES Eb   76   10   E
= ⇒ =
+ 3.01 − 10 ⋅ LOG 10    ⋅    ≅ b + 1.5 (6)
N0 N0 N 0 dB N 0 dB   60   9   N 0 dB
so we have that @ 10 dB channel ES/N0 means about @ 8.5 dB Eb/N0: this figure could appear poor if compared
with BER performances of standard concatenated schemes, however it has to be reminded that:
1. De-QPSK modulation causes some degradation due to the correlation between bytes at SDPCC decoder output.
2. The bursty nature of data is such that just one Reed-Solomon word is contained per burst, so interleaving is not
The second set of simulations has been performed at signal level (i.e. at 32 samples/symbol). An UMCD model
with all Synchronisation blocks has been implemented (the polyphase network was the only section not considered)
and within the Transmission channel model not only AWGN has been considered but also increasing frequency and
time delay error, to take into account for UT mobility: in this way the implementation loss due to synchronisation
algorithms has been verified by computer simulations.
The synchronisation procedure has also been simulated, according with Figure 9: each simulation has been
partitioned in several runs and during each run an AB is transmitted (in Acquisition Phase) or a SSSB followed by
some TBs (in Steady State Phase), at the end of the run parameter estimates are written to file, from which they are
read at the start of the successive run. During the reception of TBs the BER has been also evaluated (by error
counting) at the output of the inner decoder (e.g. the SDPCC), Reed-Solomon co-decoding was not implemented in
simulations at signal level.
Finally, the signal samples produced in simulations have been also used in Very High-Speed-Integrated-Circuit
Description Language (VHDL) simulations (during simulations signal bursts have been written on file and then
passed to the Alenia Spazio (ALS) VLSI group which used them as input test vector in the UMCD VHDL model).
BER results are shown in Figure 10: the BER at SDPCC is shown, the first curves refers to simulations performed
at symbol level (i.e. in perfect demodulation conditions), the second one refer to signal simulations (i.e. they present
the impact of residual synchronisation errors due to non ideal demodulation) and the third one refers to VHDL (i.e.
bit-true) simulations. The degradation caused by Synchronisation algorithms is about 0.5 dB, while VHDL
simulations show an additional worsening of 0.3 dB.







BER [QPSK Channel]

BER [After SDPCC Decoding]

1.E-09 BER [After Reed-Solomon Decoding]

8 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11 11.25 11.5 11.75 12

Figure 8 Simulated performances of the ESW coding Scheme (simulations performed at symbol level)
IF Signal
(I and Q components)


• Frequency errors • Service burst processing
• Time delay 1. Frequency estimation
• Noise 2. Timing Estimation
SAT-TERMINAL 3. UW search and detection
• Esw bursts generation (Service and Traffic) • Traffic burst processing
• Frequency and Timing adjustment 1. Demodulation
• Nyquist shaping • ALBM 2. 10/9 SPCC Decoding
1. Frequency Estimate 3. Differential Decoding
2. Timing Estimate 4. BER Evaluation
3. UW Flag
4. UW offset
1. Frequency Estimate
2. Timing Estimate
3. UW flag

(written to and read from file)

Figure 9 Signal level Simulation Scenario


BER Simulated
(Symbol level 1 sample/symbol)

BER Simulated
(Signal level 32 samples/symbol )

1.E-02 BER Simulated by VLSI group over VHDL UMCD model

(TEST signal input by simulation S/W)


7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5
Es/No [dB]

Figure 10 Results of simulations performed at signal level

The ESW system based on Symbol-Synchronous MF-TDMA has been presented. Synchronisation Algorithms
involved in onboard demodulation have been introduced (with a synthetic summary of their performances). The
ESW Coding Scheme has been exhaustively simulated in order to clearly define performances in ideal clock &
carrier recovery conditions. Finally, an overall system (with only exclusion of Reed-Solomon co-decoding)
simulation has been carried out to verify Synchronisation algorithms impact on BER degradation.


[1] S. B. Wicker “Error Control Systems for Digital Communication and Storage,” Prentice Hall, pp. 286-287,
[2] F. Quaranta, I Martinazzo, A. Bernardi, M. Livi, D. Giancristofaro, R. Ardoino “A Novel ASIC for all-digital
onboard Multicarrier Demodulation of Symbol-Synchronous MF-TDMA,” in press [7th International
Workshop on Digital Signal Processing Techniques for Space Communications] .
[3] A. J. Viterbi, A. M. Viterbi “Nonlinear Estimation of PSK-Modulated Carrier Phase with Application to Burst
Digital Transmission,” IEEE Trans. On Info. Theory, vol. IT-29, July 1983.