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CONFIDENTIAL CS/OCT 2006/ITT430

UNIVERSITI TEKNOLOGI MARA


FINAL EXAMINATION

COURSE : MICROPROCESSOR
COURSE CODE : ITT430
EXAMINATION : OCTOBER 2006
TIME : 3 HOURS

INSTRUCTIONS TO CANDIDATES

1. This question paper consists of three (3) parts : PART A (25 Questions)
PART B (25 Questions)
PART C (6 Questions)

2. Answer ALL questions from all three (3) parts.

i) Answer PART A in the Objective Answer Sheet.


ii) Answer PART B in the True/False Answer Sheet.
iii) Answer PART C in the Answer Booklet. Start each answer on a new page.

3. Do not bring any material into the examination room unless permission is given by the
invigilator.

4. Please check to make sure that this examination pack consists of:

i) the Question Paper


ii) an Answer Booklet - provided by the Faculty
iii) a True/False Answer Sheet - provided by the Faculty
iv) an Objective Answer Sheet - provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO


This examination paper consists of 13 printed pages
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CONFIDENTIAL 2 CS/OCT 2006/ITT430

PART A (25 marks)

For each of the following questions, choose ONE suitable answer and mark the answer on
the Objective Answer Sheet provided.

1. Nine bits of the status register indicate conditions that are produced as the result of
executing an instruction. How many of them represent status flags ?

A. 3
B. 4
C. 5
D. 6

2. The condition tested for the following pairs of jump instruction is similar EXCEPT

A. JP and JPE
B. JPO and JNP
C. JNC and JNB
D. JB and JAE

3. Which of the following timing properties defined for the read cycle of an EPROM ?

I Access time (tAcc)


II Chip-enable time (tCE)
III Chip-deselect time (tDF)

A. I & II
B. l&lll
C. II & III
D. none of the above

4. What is the content of AH register to invoke the interrupt 21H so that it inputs a string
of data from the keyboard ?

A. (AH)=01H
B. (AH)=02H
C. (AH)=09H
D. (AH)=0AH

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5. In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the


address put on the bus during an output bus cycle is 800816, which output port the
data will be written to ?

A. port 0
B. port 2
C. port 4
D. port 8

6. What is the size of memory allocated by the DQ directive?

A. 2 words
B. 4 words
C. 8 words
D. 10 words

7. The following interrupt signals can be used by an external device to signal that it
need to be serviced EXCEPT

A. NMI
B. RESET
C. TEST
D. READY

8. Which of the following status flags will be shown after executing the following
instructions in the DEBUG trace ?

MOV AL, C
CMP AL, -1
CMP AL, -C
A. NV UP El PL NZ NA PE CY
B. NV UP Dl NG NZ NA PO NC
C. NV UP El PL ZR NA PE NC
D. NV UP Dl NG ZR AC PO CY

9. Assuming that (AX)=0010H, (BX)=0100H, and (DS)=1000H, what happens if the


XLAT instruction is executed ?

A. (AL)=00H
B. (AL)=01H
C. (AL)=10H
D. none of the above

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10. What is the address from where the first instruction is fetched by the MPU after the
reset has been applied ?

A. 00000H
B. OFFFFH
C. FFFFOH
D. FFFFFH

11. The original contents of AX, BL, word-size memory location SUM, and carry flag (CF)
are 1234H, ABH, 00CDH, and OH respectively. Describe the result of executing the
following sequence of instructions:

ADD AX, SUM


ADC BL, 05H
INC WORD PTR SUM

A. (SUM)=1301H
B. (SUM)=00B0H
C. (SUM)=00CEH
D. (SUM)=CD01H

12. What is the value of AX after executing the following instructions ?

MOV AX, 00FFH


MOV CL, 3
CLC
RCL AX, CL

A. (AX)=07F8H
B. (AX)=EF0FH
C. (AX)=F0FEH
D. (AX)=FFE0H

13. What should be the control word if ports A, B, and C of an 82C55A are to be
configured for mode 0 operation ? Moreover, ports A and B are to be used as inputs
and C as an output.

A. 80H
B. 84H
C. 92H
D. 9AH

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14. What value must be written to the control register of the 82C55A to configure the
device such that port A is configured for bi-directional operation and port B is set up
for mode 1 output operation ?

A. 82H
B. C4H
C. 88H
D. C8H

15. The program that follows implements what is known as a delay loop. How many
times does the "JNZ DLY" instruction get executed ?

MOVCX, 1EABH
DLY: DECCX
NOP
JNZ DLY
NXT:

A. 7851 times.
B. 7951 times
C. 8851 times
D. 8951 times

16. State the value of the flag register after executing the following instructions.

MOVAH, 45H
XOR AH, AH

A. CF=0, PF=0, OF=0, ZF=1 and SF=0


B. CF=0, PF=1, OF=0 ZF=1 and SF=0
C. CF=0, PF=1, OF=0, ZF=0 and SF=0
D. CF=0, PF=0, OF=0, ZF=0 and SF=1

17. What is the content of AX after executing the following sequence of instructions ?

MOV AX, -3
MOV BL, 2
IDIV BL
MOV AX, -9
SAR AX, 1

A. (AX)=FFFAH
B. (AX)=FFFBH
C. (AX)=FFFCH
D. (AX)=FFFDH

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18. Specify the mode of the first four bits, B3B2BiB0(LSB) for DMA channel 2 if it is to
transfer data from an input peripheral device to a memory buffer starting at address
A00016 and ending at AFFFi 6 . Ensure that the microprocessor is not completely
locked off the bus during the DMA cycle. Moreover, at the end of each DMA cycle,
the channel is to be reinitialized so that the same buffer is filled when the next DMA
operation is initiated.

A. 0010
B. 0111
C. 0110
D. 1001

19. Which parallel I/O port in memory-mapped 82C55A of the 8088-based


microcomputer is selected for operation when the memory address output on the bus
is 0041216?

A. port B on PPI 2
B. port B on PPI 4
C. port B on PPI 6
D. port B on PPI 8

20. When the instruction PUSH AX is executed, what address bus status code and
memory bus cycle code are output by the 8088 in a maximum mode microcomputer
system ?

A. S4S3=01 and S2S1S0=100


B. S4S3=01 and S^St^HO
C. S4S3=1OandS2S1So=1O1
D. S4S3=1OandS2S1So=11O

21. NMI is different from the external hardware interrupts in three ways EXCEPT

A. NMI is masked out by IF.


B. NMI is initiated from the NMI input lead instead of from the INTR input.
C. NMI input is edge-triggered instead of level sensitive like INTR.
D. NMI occurrence is latched inside the 8088/8086 as it switches to its active 1
logic level.

22. The data transfer across an asynchronous serial data communication line is
observed and the bit time is measured as 0.833 ms. What is the baud rate ?

A. 1200 bps
B. 1400 bps
C. 1600 bps
D. 1800 bps

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23. If the value 0316 is written to the control register of an 82C55A set for mode 2
operation, which bit at port C is affected by the bit set/reset operation and what is the
value ?

A. PC! and logic 0


B. PC! and logic 1
C. PC2 and logic 0
D. PC2 and logic 1

24. What is/are the source/sources for applying a non-maskable interrupt to the 8088
microprocessor ?

I 8087 Numeric Coprocessor (NPI)


II Memory Parity Check (MPI)
III I/O Channel Check (PCK)

A. I
B. I, II
C . II, III
D. I. II, III

25. What is the name of the microarchitecture used to design the Pentium IV processor ?

A. NetBurst microarchitecture
B. P6 microarchitecture
C. P4 microarchitecture
D. Crusoe microarchitecture

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PARTB (25 marks)

For each of the following questions, answer either TRUE or FALSE and mark your answer
on the TRUE/FALSE Answer Sheet provided.

1. T F If a character size is to be 8 bits, parity is odd; and one stop bit is used
then a value, 5E, must be written into the mode-control register in order
to configure the 8251A such that it works as an asynchronous
communication controller with the baud rate clock internally divided by
16.

2. T F The dedicated memory (00000H - 00013H) are used for the storage of
the pointers to 8088's internal interrupt service routines and exceptions.

3. T F If the ASCII representation for character "E" is 45H then the ASCII
representation for character "U" is 55H.

4. T F The 8255A PPI has three 8-bit ports for implementing inputs or outputs.
The I/O addresses where the ports PA, PB, and PC reside are 006016,
0061 16 , and 006216 respectively.

5. T F The maximum number of repeats that can be implemented with a loop


instruction is 65535.

6. T F One bus cycle is required to read the word from memory address
0148816 of an 8086-based microcomputer.

7. T F The instruction fetch CPU cycle occurs when the status inputs of the
8288 bus controller reads 101.

8. T F If the contents of registers BX and CX are ABCDH and 0ABCH


respectively, and the carry flag is 1, the content of BX is A111H after
executing the instruction "SBB BX, CX".

9. T F The stack pointer is used to access data within the stack segment of
memory and commonly used to reference subroutine parameters.

10. T F DMA channel 1 is dedicated to RAM refresh and that channel 2 is used
by the floppy disk subsystem.

11. T F Pentium processors are implemented with 8-Kbyte data and 16-Kbyte
code caches on chip that is also a feature designed to improve
processing speed.

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12. T F The operating configuration of the 8259A needs to be initialized at


power-on of the system by writing to the 8259A's internal registers over
the local bus.

13. T F The two bits S2 and Si of the status signal are used to form a binary
code that identifies which of the internal segment registers is used to
generate the physical address.

14. T F Each register in Pentium processors can be addressed in 1, 8, 16, 32 or


64 bit modes.

15. T F The I/O chip select circuitry encodes the I/O address from the LSI
peripheral devices, such as the DMA controller, interrupt controller,
programmable interval timer, and PPI controller.

16. T F The IO/M, DT/R and SSO control signals indicate the type of bus cycle
in progress and the direction data are to be transferred over the bus.

17. T F The advanced computing technique used in Pentium where educated


guess for the next instruction following a conditional instruction will be is
branch prediction.

18. T F If the contents of registers AX and BL are -21 and 2 respectively, then
the content of AL is FFH after executing the instruction "IDIV BL".

19. T F If (AL)=AFH, the new contents of AX are FFAFH after executing the
instruction "CBW".

20. T F All 386SX, 386DX, 486SX and 486DX microprocessors have 32 bits
address bus and 32 bits data bus.

21. T F To access a register within one of the peripheral devices, an I/O


instruction of the 8088 microprocessor must be executed to read from or
write to the register. The address output on the address line Ao through
A8 during the I/O bus cycle is used to both chip-select the peripheral
device and select the appropriate register.

22. T F One byte is required to encode the instruction "NOT AX".

23. T F Unlike the 8086 and 8088 microprocessor, the 80386DX has a
demultiplexed address/data bus.

24. T F The 386 addresses 4 Gbytes, the 286 addresses 32 Mbytes, and the
8088/8086 addresses 1 Mbyte.

25. T F In the real mode, the X86's memory management is used to allow the
processor to address physical memory greater than 1 Mbyte and to
allow the programmer to use virtual memory.

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PARTC (50 marks)

Answer ALL questions.

QUESTION 1

Encode (in hexadecimal) the following instructions using the information given in Table 1 and
Table 2. Assume that the opcode for the MOV, ROL and ADD operations are 1100011,
110100 and 000000 respectively.

a) MOV WORD PTR [BP][DI] + 6789, DCABH


b) ROL BL, CL
c) ADD [BX][DI] + ABCDH, AX

Tablei

REG w=o W=l


000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

Table 2

MOD=11 EFFECTIVE ADDRESS CALCULATION


R/M w=o W=l R/M MOD=00 MOD=01 MOD=10
000 AL AX 000 (BX)+(SI) (BX)+(SI)+D8 (BX)+(SI)+D16
001 CL CX 001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16
010 DL DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16
011 BL BX 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16
100 AH SP 100 (SI) (SI)+D8 (SI)+D16
101 CH BP 101 (DI) (DI)+D8 (DI)+D16
110 DH SI 110 Dir. address (BP)+D8 (BP)+D16
111 BH DI 111 (BX) (BX)+D8 (BX)+D16

(6 marks)

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QUESTION 2

a) Explain (using diagrams) how the even and odd addresses of word transfer are done
by the 8086.
(4 marks)

b) In the 8086, pins AD0-AD15 are used for both data and addresses. How does the CPU
indicate whether the information on these pins is data or an address?
(2 marks)

c) Indicate if each of the following pins are input pins, output pins, or both,
i) HOLD
ii) HOLDA
iii) READY
(3 marks)

QUESTION 3

a) Modify the following subprogram by using the ADC instruction.

BACK: ADD AL, [SI]


JNC OVER
INC AH
OVER: INC SI
(3 marks)

b) Fix the error for the following program which is meant to set the cursor at position
row=11 and column=33.

MOV AH, 02
MOV BH, 00
MOV DH, 33H
MOV DL, 11H
INT21H

(3 marks)

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CONFIDENTIAL 12 CS/OCT 2006/ITT430

QUESTION 4

Design a memory system consisting of 32 Kbytes of R/W memory and 32 Kbytes of ROM
memory. Use SRAM devices to implement R/W memory and EPROM devices to implement
ROM memory. The memory devices to be used are shown in Figure 1. R/W memory is to
reside over the address range 0000016 through 07FFF16 and the address range of ROM
memory is to be F800016 through FFFFF16. Assume that the 8088 microprocessor system
bus signals that follow are available for use: Ao through A19, Do through D7, MEMR, and
MEMW.

SRAM gRROM

}4

2712&

_ 01
6

' IK
-

Figure 1

(9 marks)

QUESTION 5

a) Name EIGHT general purpose registers commonly used by all Pentium processors.

(4 marks)

b) Addressing modes are an integral part of each computer instruction set. They allow
different ways of specifying source or destination operand addresses depending on
the programming situation. State the EIGHT addressing modes used in 8051
Instruction Set.

(4 marks)

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CONFIDENTIAL 13 CS/OCT 2006/ITT430

QUESTION 6

a) Explain the main difference between full segment and simplified segment definition ?

(2 marks)

b) Write a complete program using simplified segment definition to sound the bell
continuously until a 'Q' or 'q' key is pressed. Assume that the ASCII value for the bell
is 07H.
(10 marks)

END OF QUESTION PAPER

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