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# MICROCONTROLLER

Lecturer: Dr. Bui Ha Duc
Dept. of Mechatronics
Email: ducbh@hcmute.edu.vn

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Digital system

## Interfacing a digital system to the analog world

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Signals
Analog Signal:
1 1
𝑥 𝑡 = sin 2𝜋𝑡 + 2 sin 4𝜋𝑡 + 3 sin 6𝜋𝑡 + 1.5
Losing information!

## Analog Signal Discrete Signal Digital Signal

• Continuous time • Discrete in time (4-bit ADC)
& amplitude • Discrete in time & amplitude

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Discrete signal vs Digital signal

Different from
original value !

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• Losing information

## Why do we need ADC?

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The Digital Age in an Analog World

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Antialiasing
filter

Sampling Quantization

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Aliasing

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Nyquist – Shannon Sampling
• An analog signal can be in theory perfectly recovered as
long as the sampling rate is at least twice as large as the
highest-frequency component (Nyquist rate) of the
analog signal to be sampled.
𝑓𝑠 ≥ 2𝑓𝑚𝑎𝑥

## • E.g. signal containing frequencies up to 1 Hz the

minimum sampling rate is 2 Hz ?

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Antialiasing
filter

Sampling Quantization

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Sampling
• Sampling converts a continuous variable to
discrete.
• Periodic sampling:
• for given sampling interval T
𝑥𝑛 = 𝑥 𝑛𝑇 , 𝑛 𝑖𝑠 𝑖𝑛𝑡𝑒𝑔𝑒𝑟
• Sample frequency
1
𝑓𝑠 = (𝐻𝑧)
𝑇

## • The sampling process may cause aliasing or folding

distortion.

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SAMPLE-AND HOLD CIRCUIT

## Unity-gain buffer amplifier:

makes a copy - at the output -
of the the input voltage

## Simplified diagram of a sample-and hold circuit

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Sampling

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Antialiasing
filter

Sampling Quantization

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Quantization
amplitude to digital code.

## Quantization error: Difference between the actual (analog) quantity

and the digital value assigned to it.
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Quantization
Comparator output:
1: if VA > VAX
0: if VA < VAX

## VAX = Step size x digital input

tC = conversion time 16
Quantization
• Number of steps (quantization levels)
𝐿 = 2𝑛 (1)
n: number of bits used in ADC
• Quantization step size (Vmin; LSB)

𝑥𝑚𝑎𝑥 − 𝑥𝑚𝑖𝑛
∆= (2)
𝐿

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Quantization
Example:
to 5 volts, determine
a. the number of quantization levels?
b. the step size of the quantizer or resolution?
c. the quantization level when the analog voltage is 3.2 volts?
d. the binary code produced by the ADC?

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• AN0 – AN12
• Shared with Port A, B, E
• Power by
• VDD and Vss

• Reference Voltage
• VREF+, VREF-
• AVDD, AVss
• Select by configuring bit [5:4] in ADCON1 register

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## VCFG1: Voltage Reference PCFG3:PCFG0: A/D Port Configuration Control bits:

Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS

## VCFG0: Voltage Reference

Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD

Example:

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Example:

## Only convert 1 channel

at a time

Reference Voltage

Channel select

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CHS3:CHS0: Analog Channel Select bits GO/DONE: A/D Conversion Status bit
0000 = Channel 0 (AN0) When ADON = 1:
0001 = Channel 1 (AN1) 1 = A/D conversion in progress
0010 = Channel 2 (AN2)
0 = A/D Idle
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2) ADON: A/D On bit
0110 = Channel 6 (AN6)(1,2) 1 = A/D converter module is enabled
0111 = Channel 7 (AN7)(1,2) 0 = A/D converter module is disabled
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)

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A/D Sample/Conversion Sequence
Total A/D Conversion Time

## Sample Time Conversion Time

Acquisition analog signal Convert analog value to digital
(tsampling > 2.45 µs) (tc >11 TAD per 10-bit conversion)

## A/D conversion complete, result is loaded into

A/D result buffer. Optionally generate interrupt.
Hardware set bit ADCON0bits.GO = 0;

## S/H amplifier is disconnected from input and holds signal lever.

A/D conversion is started by the conversion trigger source.

## S/H amplifier is connected to the analog input pin for sampling

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A/D Acqusition
• Minimum acquisition time (sampling time)
• TACQ = Amplifier Settling Time + Holding Capacitor Charging Time +
Temperature Coefficient
= TAMP + TC + TCOFF
Where:
• TAMP = 0.2 µs
• TC = 1.05 µs TACQ = 2.45 µs
• TCOFF = 1.2 µs
(refer page 270 in the datasheet for more detail)

## • Acquisition time can be set by bit [5:3] (ACQT) in ADCON2

register

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A/D Conversion
• Conversion time > 11 TAD

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1 = Right justified bits
0 = Left justified 111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
ACQT2:ACQT0: A/D Acquisition Time 101 = FOSC/16
Select bits 100 = FOSC/4
111 = 20 TAD 011 = FRC (clock derived from A/D RC oscillator)(1)
110 = 16 TAD 010 = FOSC/32
101 = 12 TAD 001 = FOSC/8
100 = 8 TAD 000 = FOSC/2
011 = 6 TAD If the A/D FRC clock source is selected, a delay of one TCY
010 = 4 TAD (instruction cycle) is added before the A/D clock starts.

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A/D Sample/Conversion Sequence

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A/D Sample/Conversion Sequence

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The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)

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CHS3:CHS0: Analog Channel Select bits GO/DONE: A/D Conversion Status bit
0000 = Channel 0 (AN0) When ADON = 1:
0001 = Channel 1 (AN1) 1 = A/D conversion in progress
0010 = Channel 2 (AN2)
0 = A/D Idle
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2) ADON: A/D On bit
0110 = Channel 6 (AN6)(1,2) 1 = A/D converter module is enabled
0111 = Channel 7 (AN7)(1,2) 0 = A/D converter module is disabled
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)

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## VCFG1: Voltage Reference PCFG3:PCFG0: A/D Port Configuration Control bits:

Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS

## VCFG0: Voltage Reference

Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD

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1 = Right justified bits
0 = Left justified 111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
ACQT2:ACQT0: A/D Acquisition Time 101 = FOSC/16
Select bits 100 = FOSC/4
111 = 20 TAD 011 = FRC (clock derived from A/D RC oscillator)(1)
110 = 16 TAD 010 = FOSC/32
101 = 12 TAD 001 = FOSC/8
100 = 8 TAD 000 = FOSC/2
011 = 6 TAD If the A/D FRC clock source is selected, a delay of one TCY
010 = 4 TAD (instruction cycle) is added before the A/D clock starts.

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Setting up A/D conversion
1. Set TRIS bits of the port pins
2. Configure the A/D module:
• Configure analog pins, voltage reference and
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
3. Configure A/D interrupt (if desired):
• Set GIE bit

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Setting up A/D conversion
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
required.
7. For next conversion, go to step 1 or step 2, as required. The A/D
conversion time per bit is defined as TAD. A minimum wait of 3
TAD is required before the next acquisition starts.

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Example