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PCS-978

Transformer Relay
Instruction Manual

NR Electric Co., Ltd.


Preface

Preface

Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.

Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.

Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.

This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.

Health and Safety


The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.

When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.

Before working in the terminal strip area, the equipment must be isolated.

Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.

Qualified personnel are individuals who:

 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;

 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;

 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;

 Are trained in emergency procedures (first aid).

Instructions and Warnings


The following indicators and standard definitions are used:

PCS-978 Transformer Relay i


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Preface

DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.

WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.

CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.

NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.

DANGER!

NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.

WARNING!

ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.

WARNING!

Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.

WARNING!

Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.

CAUTION!

 Earthing

Securely earthed the earthing terminal of the device.

 Operating environment

ONLY use the device within the range of ambient environment and in an

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Preface

environment free of abnormal vibration.

 Ratings

Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.

 Printed circuit board

Do NOT attach or remove printed circuit board if the device is powered on.

 External circuit

Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.

 Connection cable

Carefully handle connection cables without applying excessive force.

NOTICE!

The firmware may be upgraded to add new features or enhance/modify existing


features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.

Copyright © 2016 NR. All rights reserved.

We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.

The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.

We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD. Tel: +86-25-87178888


Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Fax: +86-25-87178999
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China Website: www.nrelect.com, www.nrec.com

P/N: ZL_PCS-978_X_Instruction Manual_EN_Overseas General_X Version: R2.10

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Date: 2016-06-22
Preface

Documentation Structure

The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.

All contents provided by this manual are summarized as below:

1 Introduction
Briefly introduce the application, functions and features about this device.

2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.

3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.

4 Supervision
Introduce the automatic self-supervision function of this device.

5 Management
Introduce the management function (measurement and recording) of this device.

6 Hardware
Introduce the main function carried out by each plug-in module of this device and providing the
definition of pins of each plug-in module.

7 Settings
List settings including system settings, communication settings, label settings, logic links and etc.,
and some notes about the setting application.

8 Human Machine Interface


Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.

9 Configurable Function
Introduce configurable function of the device and all configurable signals are listed.

10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.

11 Installation
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Preface

Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this relay is indicated.

12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.

13 Maintenance
A general maintenance policy for this relay is outlined.

14 Decommissioning and Disposal


A general decommissioning and disposal policy for this relay is outlined.

15 Manual Version History


List the instruction manual version and the modification history records.

Typographic and Graphical Conventions

Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.

The following symbols are used in drawings:

&
AND gate

≥1

OR gate

Comparator

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

SIG Input of binary signal except those signals via opto-coupler

Input of other signal


OTH

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Preface

XXX Output signal

Timer
t
Timer (optional definite-time or inverse-time characteristic)
t

xxms xxms
Timer [delay pickup (xxms), delay dropoff (xxms), non-settable]

[t1] 0ms
Timer (t1: delay pickup, settable)

0ms [t2]
Timer (t2: delay dropoff, settable)

[t1] [t2]
Timer (t1: delay pickup, t2: delay dropoff, settable)

IDMT Timer (inverse-time characteristic)


*

Instrument current transformer


*

Instrument voltage transformer

---xxx is the symbol

Symbol Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U

Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2

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1 Introduction

1 Introduction

Table of Contents
1 Introduction 1-a
1.1 Application ....................................................................................................... 1-1
1.2 Functions ......................................................................................................... 1-5
1.2.1 Protection Functions ............................................................................................................ 1-5

1.2.2 Measurements ...................................................................................................................... 1-9

1.2.3 Configurable Functions ........................................................................................................ 1-9

1.2.4 Miscellaneous Functions ...................................................................................................... 1-9

1.2.5 Communication .................................................................................................................. 1-10

1.2.6 User Interface ..................................................................................................................... 1-10

1.3 Features ......................................................................................................... 1-10

List of Figures
Figure 1.1-1 2-winding transformer ........................................................................................... 1-1

Figure 1.1-2 3-winding transformer ........................................................................................... 1-1

Figure 1.1-3 autotransformer with two sides ........................................................................... 1-2

Figure 1.1-4 autotransformer with three sides ......................................................................... 1-2

Figure 1.1-5 Typical application of a 3-windings transformer................................................ 1-3

Figure 1.1-6 Typical application of an auto-transformer......................................................... 1-3

Figure 1.1-7 Typical application of a shunt reactor ................................................................. 1-4

PCS-978 Transformer Relay 1-a


Date: 2015-01-12
1 Introduction

1-b PCS-978 Transformer Relay

Date: 2015-01-12
1 Introduction

1.1 Application

PCS-978 can be applied for a two-winding transformer, three-winding transformer or


auto-transformer in any voltage level, or a shunt reactor. PCS-978 provides full transformer
protections which are configurable by user. Ancillary functions of fault diagnostic, disturbance
records, event records and communication function are integrated in the device.

PCS-978 is adaptive to the following 2/3-windings transformers or autotransformer.

Figure 1.1-1 2-winding transformer

Figure 1.1-2 3-winding transformer

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1 Introduction

Figure 1.1-3 autotransformer with two sides

Figure 1.1-4 autotransformer with three sides

The function diagrams for protecting a 3-windings transformer, an auto-transformer and a reactor
are respectively shown below.

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1 Introduction

3I0
HVS

49 62PD 50BF 50/51G

87T 50/51Q 51PAlm 21


*
50/51P
LVS
*

*
MR
Mechanical signals or transducer
* * signals from transformer
26

24 59P 81U
MVS

59G 27P 81O 59GAlm 64REF


3U0

Figure 1.1-5 Typical application of a 3-windings transformer


3I0

HVS

49 62PD 50/51Q 50BF


*

87W 51PAlm 87T 64REF 50/51G


*
*

* MR 21
*

Mechanical signals or transducer


signals from transformer
26
*

MVS
81O 81U 24 50/51P

* 59G 27P 59P 59GAlm


3U0

LVS

Figure 1.1-6 Typical application of an auto-transformer

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1 Introduction

52 Bus1

3U0
Line
* * *

3I0
50/51P 21IT 87R
52

49 50/51G
Shunt reactor
Mechanical signals or
MR
transducer signals from reactor
52

3I0

Bus2 * * *

Neutral earthing reactor

Figure 1.1-7 Typical application of a shunt reactor

NOTICE!

DPFC is the abbreviation of “Deviation of Power Frequency Component”. In case of a


fault occurred in the power system, the fault component could be analyzed into three
parts: the power frequency components before the fault, the power frequency variables
during the fault and the transient variables during the fault. DPFC is the power frequency
variable during the fault.

1. Transformer

No. Function ANSI


1 Transformer differential protection 87T
2 Restricted earth-fault protection 64REF
3 Winding differential protection 87W
4 Phase overcurrent protection 50/51P
5 Earth fault protection 50/51G
6 Negative-sequence overcurrent protection 50/51Q
7 Overfrequency protection 81O
8 Underfrequency protection 81U

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9 Overexcitation protection 24
10 Impedance protection 21
11 Overvoltage protection 59P
12 Undervoltage protection 27P
13 Residual overvoltage protection 59G
14 Residual overvoltage alarm 59GAlm
15 Thermal overload protection 49
16 Breaker failure protection 50BF
17 Pole disagreement protection 62PD
18 Phase overcurrent alarm 51PAlm
19 Mechanical protection MR
20 Temperature protection 26
21 VT circuit failure supervision VTS
22 CT circuit failure supervision CTS

2. Reactor

No. Function ANSI


1 Reactor biased current differential protection 87R
2 Inter-turn fault protection 21IT
3 Phase overcurrent protection 50/51P
4 Earth fault protection 50/51G
5 Thermal overload protection 49
6 Mechanical protection MR
7 VT circuit failure supervision VTS
8 CT circuit failure supervision CTS

1.2 Functions

1.2.1 Protection Functions


1. Transformer

 Transformer differential protection

 Biased DPFC differential protection

 Biased differential protection with three slopes

 Unrestrained instantaneous differential protection

 Optional inrush current distinguished principles: harmonic criterion or waveform distortion

 Optional harmonic blocking modes: self-adaptive blocking mode and phase-to-phase


cross blocking mode

 Overexciation detection: fifth harmonic or third harmonic criterion

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1 Introduction

 Optional transfer methods: △ →Y or Y→△

 Independent CT saturation criterion

 Differential CT circuit failure supervision

 Restricted earth-fault protection (REF)

 CT transient detection

 CT saturation detection based on 2nd and 3rd harmonics

 Winding differential protection

 CT transient detection

 CT saturation detection based on 2nd and 3rd harmonics

 Phase Overcurrent Protection

 Four stages phase overcurrent protection with independent logic, voltage control element
and directionality (forward direction, reverse direction or non-directional)

 Stage 1, 2 and 3 are definite-time characteristic.

 Stage 4 can be selected as definite-time or inverse-time characteristic.

 Second harmonic blocking

 Earth fault protection

 Four stages earth fault protection with independent logic and directionality (forward
direction, reverse direction or non-directional)

 Stage 1, 2 and 3 are definite-time characteristic.

 Stage 4 can be selected as definite-time or inverse-time characteristic.

 Second harmonic blocking

 Negative-sequence overcurrent protection

 Two stages negative-sequence overcurrent protection with independent logic

 Stage 1 is definite-time characteristic.

 Stage 2 can be selected as definite-time or inverse-time characteristic.

 Phase overvoltage protection

 Two stages phase overvoltage protection with independent logic

 Stage 1 is definite-time characteristic.

 Stage 2 can be selected as definite-time or inverse-time characteristic.

 Optional phase voltage or phase-to-phase voltage

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1 Introduction

 Optional “1-out-of-3” or “3-out-of-3” logic

 Residual overvoltage protection

 Two-stage residual overvoltage protection with independent logic

 Stage 1 is definite-time characteristic.

 Stage 2 can be selected as definite-time or inverse-time characteristic.

 Undervoltage protection

 Four stages definite-time undervoltage protection with independent logic

 du/dt blocking

 Thermal overload protection

 Two stages thermal overload protection, and one stage for alarm purpose and the other
stage for trip purpose.

 Impedance protection

 Two stages phase-to-phase impedance elements

 Two stages phase-to-ground impedance elements

 Power swing blocking releasing

 Frequency protection

 Four stages overfrequency protection

 Four stages underfrequency protection

 df/dt block criterion for underfrequency protection

 Overexcitation protection

 Two stages definite-time overexcitation protection

 Stage 1 of definite-time overexcitation protection for trip purpose

 Stage 2 of definite-time overexcitation protection for alarm purpose

 One stage inverse-time overexcitation protection for both alarm purpose and trip purpose

 Residual overvoltage alarm

 One stage residual overvoltage alarm

 Optional definite-time or inverse-time characteristic

 Phase overcurrent alarm

 Two stages definite-time phase overcurrent alarm function with independent logic

 Breaker failure protection

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Date: 2012-10-08
1 Introduction

 Pole discrepancy protection

 Mechanical Protection

 4 mechanical signal input channels for tripping instantaneously or with time delay

 Temperature Protection

 6 DC signals (4~20mA or 0~5V) from external temperature transducers

2. Reactor

 Reactor differential protection

 Biased DPFC differential protection

 Biased current differential protection

 Independent CT saturation criterion

 Harmonic blocking criterion

 Differential CT circuit failure supervision

 Inter-turn fault protection

 Zero-sequence power directional element and zero-sequence impedance element

 CT and VT circuit failure blocking

 Phase Overcurrent Protection

 Four stages phase overcurrent protection with independent logic and voltage control
element

 Stage 1, 2 and 3 are definite-time characteristic.

 Stage 4 can be selected as definite-time or inverse-time characteristic.

 Second harmonic blocking

 Earth fault protection

 Four stages earth fault protection with independent logic

 Stage 1, 2 and 3 are definite-time characteristic.

 Stage 4 can be selected as definite-time or inverse-time characteristic.

 Second harmonic blocking

 Thermal overload protection

 Two stages thermal overload protection, and one stage for alarm purpose and the other
stage for trip purpose.

 Mechanical Protection

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1 Introduction

 4 mechanical signal input channels for tripping instantaneously or with time delay

1.2.2 Measurements

 24 samples per cycle for current and voltage measurement

 Power metering (active and reactive power are calculated)

1.2.3 Configurable Functions


 User programmable logic

 Programmable tripping output matrix

 Programmable binary input

 Programmable binary output

 Programmable LED indicators

1.2.4 Miscellaneous Functions


 VT circuit supervision

 CT circuit supervision

 Frequency supervision

 Self diagnostic

 DC power supply supervision

 Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.

 Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.), triggering by
protection element pickup, manual trigger on keypad and remote trigger through
PCS-Explorer

 Four kinds of clock synchronization methods

 Conventional

 PPS (RS-485): Pulse per second (PPS) via RS-485 differential level

 IRIG-B (RS-485): IRIG-B via RS-485 differential level

 PPM (DIN): Pulse per minute (PPM) via the optical coupler

 PPS (DIN): Pulse per second (PPS) via the optical coupler

 SAS

 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network

 SNTP (BC): Broadcast SNTP mode via Ethernet network

PCS-978 Transformer Relay 1-9


Date: 2012-10-08
1 Introduction

 Message (IEC103): Clock messages through IEC103 protocol

 Advanced

 IEEE1588: Clock message via IEEE1588

 IRIG-B (Fiber): IRIG-B via optical-fibre interface

 PPS (Fiber): Pulse per second (PPS) via optical-fibre interface

 NoTimeSync

1.2.5 Communication
 Optional 2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol

 1 RS-485 communication rear ports for clock synchronization

 Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP

 Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP

1.2.6 User Interface

 Friendly HMI interface with LCD and 9-button keypad on the front panel.

 1 front multiplex RJ45 port for testing and setting

 1 RS-232 or RS-485 rear ports for printer

 Language switchover—English+ selected language

 Auxiliary software—PCS-Explorer

1.3 Features

 PCS-978 adopts intelligent design, and the amount of AC input module, binary input module
and binary output module are configurable, and terminals of those modules can be defined
according to actual requirement. Besides, protection elements not used can be hided and
new protection elements can be added not in standard configuration.

 The hardware comprises a32-bit microprocessor and two 32-bit digital signal processors
(DSP). Those processor can operate in parallel companied by fast A/D converter. The 32-bit
microprocessor performs logic calculation and DSP performs the protection calculation. High
performance hardware ensures real time calculation of all protection relays within a sampling
interval.

 High-performance hardware platform and modularized design, fault detector DSP+protection


DSP. Fault detector DSP manages fault detector and protection DSP manages protection
calucation. Their data acquisition system is completely independent in electronic circuit. DC

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1 Introduction

power supply of output relay is controlled by the operation of fault detector element, which
prevents maloperation due to error from ADC or damage of any apparatus.

 On the premise of 24 samples per cycle, all data measurement, calculation and logic
discrimination could be done within one sampling period. The event recording and protection
logic calculation are completed simultaneously.

 Biased DPFC differential protection is regardless of load current and is sensitive to small
internal fault current within the transformer. Its performance against CT saturation is also
good.

 The tripping output contacts can be configured by tripping matrix and suitable to any mode of
tripping.

 Self-adaptive floating threshold which only reflects deviation of power frequency component
improves the protection sensitivity and stability under the condition of load fluctuation and
system disturbance.

 Advanced and reliable power swing blocking releasing feature which ensure impedance
protection operate correctly for internal fault during power swing and prevent impedance
protection from maloperation during power swing

 Multiple setting groups with password protection and setting value saved permanently before
modification

 Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.

PCS-978 Transformer Relay 1-11


Date: 2012-10-08
1 Introduction

1-12 PCS-978 Transformer Relay


Date: 2012-12-08
2 Technical Data

2 Technical Data

Table of Contents
2 Technical Data .................................................................................... 2-a
2.1 Electrical Specifications ................................................................................. 2-1
2.1.1 AC Current Input................................................................................................................... 2-1

2.1.2 AC Voltage Input................................................................................................................... 2-1

2.1.3 Power Supply ....................................................................................................................... 2-1

2.1.4 Transducer Input .................................................................................................................. 2-2

2.1.5 Binary Input .......................................................................................................................... 2-2

2.1.6 Binary Output ....................................................................................................................... 2-2

2.2 Mechanical Specifications .............................................................................. 2-4


2.3 Ambient Temperature and Humidity Range .................................................. 2-4
2.4 Communication Port ....................................................................................... 2-5
2.4.1 EIA-485 Port ......................................................................................................................... 2-5

2.4.2 Ethernet Port ........................................................................................................................ 2-5

2.4.3 Optical Fibre Port ................................................................................................................. 2-5

2.4.4 Print Port .............................................................................................................................. 2-5

2.4.5 Clock Synchronization Port .................................................................................................. 2-6

2.5 Type Tests ........................................................................................................ 2-6


2.5.1 Environmental Tests ............................................................................................................. 2-6

2.5.2 Mechanical Tests .................................................................................................................. 2-6

2.5.3 Electrical Tests ..................................................................................................................... 2-6

2.5.4 Electromagnetic Compatibility .............................................................................................. 2-6

2.6 Certifications.................................................................................................... 2-7


2.7 Terminals .......................................................................................................... 2-7
2.8 Measurement Scope and Accuracy ............................................................... 2-8
2.9 Management Function .................................................................................... 2-8

PCS-978 Transformer Relay 2-a


Date: 2016-06-22
2 Technical Data

2.9.1 Clock Performance............................................................................................................... 2-8

2.9.2 Fault and Disturbance Recording ........................................................................................ 2-8

2.9.3 Binary Input Signal ............................................................................................................... 2-8

2.10 Protective Functions ..................................................................................... 2-8


2.10.1 Transformer Current Differential Protection ....................................................................... 2-9

2.10.2 Restricted Earth Fault Protection ..................................................................................... 2-10

2.10.3 Winding Differential Protection ......................................................................................... 2-10

2.10.4 Reactor Differential Protection ..........................................................................................2-11

2.10.5 Inter-turn Fault Protection .................................................................................................2-11

2.10.6 Overexcitation Protection ..................................................................................................2-11

2.10.7 Impedance Protection ...................................................................................................... 2-12

2.10.8 Phase Overcurrent protection .......................................................................................... 2-12

2.10.9 Earth Fault Protection ...................................................................................................... 2-13

2.10.10 Negative-sequence Overcurrent Protection................................................................... 2-14

2.10.11 Phase Overvoltage Protection........................................................................................ 2-15

2.10.12 Residual Overvoltage Protection ................................................................................... 2-15

2.10.13 Undervoltage Protection................................................................................................. 2-16

2.10.14 Overfrequency Protection .............................................................................................. 2-16

2.10.15 Underfrequency Protection ............................................................................................ 2-16

2.10.16 Thermal Overload Protection ......................................................................................... 2-17

2.10.17 Breaker Failure Initiation ................................................................................................ 2-17

2.10.18 Pole Disagreement Protection ....................................................................................... 2-17

2.10.19 Phase Overcurrent Alarm Element ................................................................................ 2-17

2.10.20 Residual Overvoltage Alarm Element ............................................................................ 2-18

2.10.21 Mechanical Protection .................................................................................................... 2-18

2.10.22 Temperature Protection .................................................................................................. 2-18

2-b PCS-978 Transformer Relay


Date: 2016-06-22
2 Technical Data

2.1 Electrical Specifications

NOTICE!

“System phase sequence”, which can be set by PCS-Explorer, this setting informs the
device of the actual system phase sequence, either ABC or ACB. CT and VT inputs on
the device, labeled as A, B and C, must be connected to system phase A, B and C for
correct operation.

2.1.1 AC Current Input


Phase rotation ABC
Nominal frequency 50Hz, 60Hz
Rated Current (In) 1A 5A
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden <0.15VA/phase @In <0.25VA/phase @In
Current input channel Maximum 36

2.1.2 AC Voltage Input


Phase rotation ABC
Nominal frequency 50Hz, 60Hz
Rated Voltage (Un) 100V~130V 200V (residual voltage input)
Linear to 1~170V 1-233V
Thermal withstand
-continuously 200V 220
-10s 260V 380
-1s 300V 420
Burden at rated <0.20VA/phase @Un <0.80VA/phase @Un
Voltage input channel Maximum 18 Maximum 9

2.1.3 Power Supply


Standard IEC 60255-11:2008
Rated Voltage 110Vdc/125Vdc/220Vdc/250Vdc 110Vac/220Vac
Variation 88~300Vdc 88~264Vac
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <25W
Operation condition <35W

PCS-978 Transformer Relay 2-1


Date: 2016-06-22
2 Technical Data

2.1.4 Transducer Input


Standard IEC 60255-1: 2009
Input range 0-20mA 0-5V
Input resistance 235Ω 20kΩ
Accuracy 0.5% 0.5%
Transducer input channel Maximum 6

2.1.5 Binary Input


1. Settable pickup voltage and dropoff voltage

Rated voltage 110Vdc 220Vdc


Rated current drain 1.1mA 2.2mA
On value 85-132Vdc (default set) 170-264Vdc (default set)
Off value <66Vdc <132Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Number Maximum 36

2. Fixed pickup voltage and dropoff voltage

Rated voltage 110Vdc 125Vdc 220Vdc 220Vdc


Rated current drain 1.1mA 1.25mA 2.2mA 2.85mA
On value 77-132Vdc 87.5-150Vdc 154-264Vdc 176-264Vdc
Off value <55Vdc <62.5Vdc <110Vdc <140Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Number Maximum 36

2.1.6 Binary Output


1. Tripping/signaling contact

Output mode Potential free contact


Maximal system voltage 380Vac, 250Vdc
Continuous carry 8A
Pickup time (Typical Value) <5ms
Dropoff time <5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
12A@3s
Short duration current
18A@1s

2-2 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

24A@0.5s
40A@0.2s
Durability (Loaded contact) 10000 operations
Number Maximum 55

2. Heavy-capacity tripping contact

Output mode Potential free contact


Maximal system voltage 250Vdc
Continuous carry 10A
Pickup time <1ms
Dropoff time <10ms
Breaking capacity (L/R=40ms) 10A
15A@3s
Short duration current
30A@1s
Durability (Loaded contact) 10000 operations
Number Maximum 12

3. Signaling contact

Output mode Potential free contact Potential free contact


Maximal system voltage 380Vac, 250Vdc 380Vac, 250Vdc
Continuous carry 8A 8A
Pickup time <10ms <10ms
Dropoff time <6ms <10ms
0.7A@48Vdc 1.00A@48Vdc
0.4A@110Vdc 0.50A@110Vdc
Breaking capacity (L/R=40ms) 0.3A@125Vdc 0.40A@125Vdc
0.2A@220Vdc 0.25A@220Vdc
0.15A@250Vdc 0.20A@250Vdc
12A@3s 12A@3s
15A@1s 15A@1s
Short duration current
20A@0.5s 20A@0.5s
30A@0.2s 30A@0.2s
Durability (Loaded contact) 10000 operations 10000 operations
Number Maximum 8 Maximum 3

4. Fast signaling contact

Output mode Potential free contact


Maximal system voltage 380Vac, 250Vdc
Continuous carry 5A
Pickup time <1ms
Dropoff time <5ms
0.65A@48Vdc
Breaking capacity (L/R=0ms)
0.35A@110Vdc

PCS-978 Transformer Relay 2-3


Date: 2016-06-22
2 Technical Data

0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
8A@3s
12A@1s
Short duration current
16A@0.5s
30A@0.2s
Durability (Loaded contact) 10000 operations
Number Maximum 8

NOTICE!

Except heavy-capacity tripping contact, common tripping output contacts are not
connected to trip circuit breakers directly. They are connected to interposing relays or
lockout relays contacts which are connected to trip circuit breakers.

2.2 Mechanical Specifications

Mounting Way Flush mounted


Chassis color Silver grey
Weight per device Approx. 19kg
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated frontplate
Protection class
Standard IEC 60225-1:2009
Front side IP51
Other sides IP30
Rear side, connection terminals IP20

2.3 Ambient Temperature and Humidity Range

Standard IEC 60225-1: 2009


Operating temperature -40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage
-40°C to +70°C
temperature range
Permissible humidity 5%-95%, without condensation
Pollution degree Ⅱ
Altitude <3000m

2-4 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

2.4 Communication Port

2.4.1 EIA-485 Port


Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Max. transmission distance 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable

2.4.2 Ethernet Port


Connector type RJ-45 ST, SC (Multi mode)
Transmission rate 100Mbits/s
Transmission standard 10Base-T/100Base-TX 100Base-FX
Max. transmission distance 100m 2km (1310nm)
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
Safety level Isolation to ELV level

2.4.3 Optical Fibre Port


2.4.3.1 For Station Level

Characteristic Glass optical fiber


Connector type ST
Fibre type Multi mode
Max. transmission distance 2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB

2.4.3.2 For Process Level

Characteristic Glass optical fiber


Connector type LC
Fibre type Multi mode
Max. transmission distance 2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB

2.4.4 Print Port


Type RS-232

PCS-978 Transformer Relay 2-5


Date: 2016-06-22
2 Technical Data

Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s


®
Printer type EPSON 300K printer
Safety level Isolation to ELV level

2.4.5 Clock Synchronization Port


Type RS-485
Max. transmission distance 500m
Maximal capacity 32
Timing standard PPS, IRIG-B
Safety level Isolation to ELV level

2.5 Type Tests

2.5.1 Environmental Tests


Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005

2.5.2 Mechanical Tests


Vibration IEC 60255-21-1:1988 ClassⅠ
Shock and bump IEC 60255-21-2:1988 ClassⅠ

2.5.3 Electrical Tests


Standard IEC 60255-27:2013
Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ
Insulation resistance
Isolation resistance >100MΩ@500VDC
measurements

2.5.4 Electromagnetic Compatibility


IEC 60255-26:2013
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 60255-26:2013 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radio frequency interference
Radiated amplitude-modulated
tests
10V/m (rms), f=80~1000MHz
Spot frequency

2-6 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-26:2013
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 2.5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-26:2013
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us
Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-26:2013
Conducted RF Electromagnetic
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10Vrms, 150
Disturbance
kHz~80MHz
Power Frequency Magnetic IEC 61000-4-8:2001
Field Immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic IEC 61000-4-10:2001
field immunity class Ⅴ, 100kHz & 1MHz–100A/m

Auxiliary power supply


IEC 60255-26:2013
performance
Up to 200ms for dips to 40% of rated voltage without reset
- Voltage dips
100ms for interruption without rebooting
-Voltage short interruptions

2.6 Certifications

 ISO9001:2008

 ISO14001:2004

 OHSAS18001:2007

 ISO10012:2003

 CMMI L5

 EMC: 2014/30/EU, EN60255-26:2013

 Products safety (LVD): 2014/35/EU, EN60255-27:2014

2.7 Terminals

Connection Type Wire Size


2
AC current Screw terminals, 2.5mm lead

PCS-978 Transformer Relay 2-7


Date: 2016-06-22
2 Technical Data
2
AC voltage Screw terminals, 1.5mm lead
Power supply Screw terminals, 1.0mm2~2.5mm2 lead
2 2
Contact I/O Screw terminals, 1.0mm ~2.5mm lead
Grounding (Earthing) Connection BVR type, 2.5mm²~6.0mm2 lead

2.8 Measurement Scope and Accuracy

Item Range Accuracy


Phase range 0°~ 360° ≤±3°
Frequency fn±3 Hz ≤ 0.02Hz
Currents from protection measurement current transformers
≤ 2.0% of rating (0.05~1.00In)
Current 0.05~5.00In
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
Voltage 0.05~1.50Un
≤ 1.0% of applied quantities (1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Active power (W)
0.05~5.00In ≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Reactive power (VAr)
0.05~5.00In ≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Apparent power (VA)
0.05~5.00In ≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)

2.9 Management Function

2.9.1 Clock Performance

Real time clock accuracy ≤ 3s/day


Accuracy of GPS synchronization ≤ 1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol

2.9.2 Fault and Disturbance Recording


Maximum duration 10000 sampled points (24 sampled points per cycle)
Recording position 10 cycles before pickup of trigger element

2.9.3 Binary Input Signal


Resolution of binary input signal ≤ 1ms
Binary input mode Potential-free contact
Resolution of SOE ≤ 2ms

2.10 Protective Functions

There are some symbols mentioned in the following sections and the meaning of them is given

2-8 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

here.

Un——VT rated secondary voltage

In——CT rated secondary current

p.u.——per unit value of settings and currents for current differential protection

Id——differential current

3I0d——residual differential current

Iwd——winding differential current

ΔId——DPFC differential current

U*/f*——the overexcitation multiple

2.10.1 Transformer Current Differential Protection


2.10.1.1 Biased Differential Protection

Current setting of knee point 1 0.1~1p.u.

Current setting of knee point 2 4~8p.u.

Pickup up setting 0.05~5p.u.

Slope 1 setting 0.1~0.9

Slope 2 setting 0.1~0.9

Slope 3 setting 0.1~0.9

2nd harmonic setting for inrush current 0.05~0.3

3rd harmonic setting for inrush current 0.05~0.3


rd th
3 or 5 harmonic setting for overexcitation 0.05~0.3
nd rd
Tolerance of 2 and 3 harmonic settings 0.01
th
Tolerance of 5 harmonic settings 0.02

Tolerance of operating current ≤5% of operating current or 0.02p.u., whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤ 30ms (Id>2 times current setting)


Operating time (without blocking criteria)
60Hz: ≤ 25ms (Id>2 times current setting)

Drop-off time ≤30ms

2.10.1.2 Instantaneous Differential Protection

Current setting 0.05~20p.u.

Tolerance of current setting ≤2.5% of setting or 0.02p.u., whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤ 20ms (Id>1.5 times current setting)


Operating time
60Hz: ≤ 20ms (Id>1.5 times current setting)

PCS-978 Transformer Relay 2-9


Date: 2016-06-22
2 Technical Data

Drop-off time ≤30ms

2.10.1.3 DPFC Current Differential Protection

Pickup current value 0.2p.u.

Tolerance of operating current ≤10%

Fixed value of slope 1 0.6

Fixed value of slope 2 0.75

Drop-off to pickup ratio ≥95%

50Hz: ≤30ms (ΔId >2x0.2p.u.)


Operating time
60Hz: ≤25ms (ΔId >2x0.2p.u.)

Drop-off time ≤30ms

2.10.2 Restricted Earth Fault Protection

Current setting of knee point 0.1~4In (A)

Pickup up setting 0.05~5In (A)

Time delay setting 0~20 (s)

Restraint slope setting 0.20~0.75

Tolerance of operating current ≤5% of operating current or 0.02×In, whichever is greater

Drop-off to pickup ratio ≥95%

Operating time (without time delay, without 50Hz: ≤30ms (3I0d>2 times current setting)
blocking criterion) 60Hz: ≤25ms (3I0d>2 times current setting)

Tolerance of time setting ≤1% of setting +30ms (3I0d>2 times current setting)

Drop-off time ≤30ms

2.10.3 Winding Differential Protection

Current setting of knee point 0.1~4In (A)

Pickup up setting 0.05~5In (A)

Restraint slope setting 0.20~0.75

Tolerance of operating current ≤5% or 0.02×In, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤30ms (Iwd>2 times current setting)


Operating time (without blocking criterion)
60Hz: ≤25ms (Iwd>2 times current setting)

Tolerance of time setting ≤1% of setting +30ms (Iwd>2 times current setting)

Drop-off time ≤30ms

2-10 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

2.10.4 Reactor Differential Protection


2.10.4.1 Biased Differential Protection

Pickup up setting 0.05~5p.u.

Slope setting 0.1~0.9

Tolerance of operating current ≤5% of operating current or 0.02p.u., whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤30ms( Id>2 times current setting)


Operating time (without blocking criterion)
60Hz: ≤25ms( Id>2 times current setting)

Drop-off time ≤30ms

2.10.4.2 Instantaneous Differential Protection

Current setting 0.05~20p.u.

Tolerance of current setting ≤2.5% of setting or 0.02p.u., whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤ 20ms( Id>1.5 times current setting)


Operating time
60Hz: ≤ 20ms( Id>1.5 times current setting)

Drop-off time ≤30ms

2.10.5 Inter-turn Fault Protection

Operating time without delay ≤60ms

2.10.6 Overexcitation Protection

Definite time U*/f* setting 1.0~1.7 p.u.

Definite time delay setting 0.1 s~9999 (s)

Inverse time U*/f* setting 1.0~1.7 p.u.

Inverse time delay setting 0.1 s~9999 (s)

Tolerance of U*/f* setting ≤2.5% of setting or 0.01 whichever is greater

Cooling time setting 0.1~9999 (s)

Drop-off to pickup ratio of definite-time


≥97%
overexcitation protection

Tolerance of operating time of definite-time


≤1% of setting +100ms (at 1.5 times U*/f* setting)
overexciation protection

Tolerance of operating time of inverse-time


≤2.5% of operating time or 30ms, whichever is greater
overexcitation protection

Drop-off time of definite-time overexcitation


≤30ms
protection

PCS-978 Transformer Relay 2-11


Date: 2016-06-22
2 Technical Data

2.10.7 Impedance Protection

Relay characeristic angle 1~89 (deg)

Impedance setting 0.05~200 (Ω)

Time setting 0.05~20 (s)

Tolerance of impedance setting ≤2.5%xSetting or 0.5Ω/In, whichever is greater

Drop-off to pickup ratio ≥95%

Tolerance of time setting ≤1%xsetting + 40ms (at 1.5 times impedance setting)

Drop-off time ≤30ms

Current setting of fault detector for PSBR 0.04~150 (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

2.10.8 Phase Overcurrent protection


2.10.8.1 Definte-time Characteristic

Current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤25 ms (at 2 times current setting)


Operating time
60Hz: ≤23 ms (at 2 times current setting)

Time delay setting 0.00~3600 (s)

Tolerance of time setting ≤1% of setting +30ms (at 2 times current setting)

Drop-off time ≤30ms

2.10.8.2 Inverse-time Characteristic

Pickup current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

Multiple of the maximum operating current to


10~40
pickup setting

Time multiplier setting 0.05~3.2

Minimum delay setting 0.0~20 (s)

Constant K 0.0~120

Constant C 0.0~20

Exponent alpha 0.02~5

≤2.5% of operating time or 30ms, whichever is greater (for


Operating time
current between 1.2 and 20 multiples of pickup)

Drop-off time ≤30ms

2-12 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

2.10.8.3 Control and Blocking Element

Phase-to-phase undervoltage setting 2~200 (V)

Negative-sequence voltage setting 2~200 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.01Un, whichever is greater

Drop-off to pickup ratio of voltage element ≥95%

Relay characteristic angle 0~360 (deg)

Tolerance of relay characteristic angle ≤3deg

Minimum polarizing voltage 2% of VT rated voltage


nd
2 harmonic for inrush 0.05~1.0

Current setting of releasing inrush blocking 0.04~30In (A)

Tolerance of current setting of releasing inrush


≤2.5% of setting or 0.02In, whichever is greater
blocking

2.10.9 Earth Fault Protection


2.10.9.1 Definte-time Characteristic

Current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤25ms (at 2 times current setting)


Operating time
60Hz: ≤23ms (at 2 times current setting)

Time delay setting 0.00~3600 (s)

Tolerance of time setting ≤1% of setting +30ms (at 2 times current setting)

Drop-off time ≤30ms

2.10.9.2 Inverse-time Characteristic

Pickup current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

Multiple of the maximum operating current to the


10~40
pickup setting

Time multiplier setting 0.05~3.2

Minimum delay setting 0.0~20 (s)

Constant K 0.0~120

Constant C 0.0~20

Exponent alpha 0.02~5

≤2.5% of operating time or 30ms, whichever is greater (for


Operating time
residual current between 1.2 and 20 multiples of pickup)

PCS-978 Transformer Relay 2-13


Date: 2016-06-22
2 Technical Data

Drop-off time ≤30ms

2.10.9.3 Control and Blocking Element

Relay characteristic angle 0~360 (deg)

Tolerance of relay characteristic angle ≤3deg

Minimum polarizing voltage 2% of VT rated voltage


nd
2 harmonic for inrush 0.05~1.0

Current setting of releasing inrush blocking 0.04~150 (A)

Tolerance of current setting of releasing inrush


≤2.5% of setting or 0.02In, whichever is greater
blocking

2.10.10 Negative-sequence Overcurrent Protection


2.10.10.1 Definte-time Characteristic

Current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤25 ms (at 2 times current setting)


Operating time
60Hz: ≤23 ms (at 2 times current setting)

Time delay setting 0.00~3600 (s)

Tolerance of time setting ≤1% of setting +30ms (at 2 times current setting)

Drop-off time ≤30ms

2.10.10.2 Inverse-time Characteristic

Pickup current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

Multiple of the maximum operating current to the


10~40
pickup setting

Time multiplier setting 0.05~3.2

Minimum delay setting 0.0~20 (s)

Constant K 0.0~120

Constant C 0.0~20

Exponent alpha 0.02~5

≤2.5% of operating time or 30ms, whichever is greater (for


Operating time of IDMT NegOC negative-sequence current between 1.2 and 20 multiples of
pickup)

Drop-off time ≤30ms

2-14 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

2.10.11 Phase Overvoltage Protection


2.10.11.1 Definte-time Characteristic

Voltage setting 2~200 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤35ms (at 1.2 times voltage setting)


Operating time
60Hz: ≤30ms (at 1.2 times voltage setting)

Time delay setting 0.00~3600 (s)

Tolerance of time setting ≤1% of setting +30ms (at 1.2 times voltage setting)

Drop-off time ≤30ms

2.10.11.2 Inverse-time Characteristic

Pickup voltage setting 2~200 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater

Drop-off to pickup ratio ≥95%

Multiple of the maximum operating voltage to the


10~40
pickup setting

Time multiplier setting 0.05~3.2

Minimum delay setting 0.0~20 (s)

Constant K 0.0~120

Constant C 0.0~20

Exponent alpha 0.02~5

≤2.5% of operating time or 30ms, whichever is greater (for


Operating time
voltage between 1.2 and 2 multiples of pickup)

Drop-off time ≤30ms

2.10.12 Residual Overvoltage Protection


2.10.12.1 Definte-time Characteristic

Voltage setting 2~200 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤35ms (at 1.2 times voltage setting)


Operating time
60Hz: ≤30ms (at 1.2 times voltage setting)

Time delay setting 0s~3600 (s)

Tolerance of time setting ≤1% of setting +30ms (at 1.2 times voltage setting)

Drop-off time ≤30ms

PCS-978 Transformer Relay 2-15


Date: 2016-06-22
2 Technical Data

2.10.12.2 Inverse-time Characteristic

Pickup voltage setting 2~200 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater

Drop-off to pickup ratio ≥95%

Multiple of the maximum operating current to the


10~40
pickup setting

Time multiplier setting 0.05~3.2

Minimum delay setting 0.0~20 (s)

Constant K 0.0~120

Constant C 0.0~20

Exponent alpha 0.02~5

≤2.5% of operating time or 30ms, whichever is greater (for


Operating time
residual voltage between 1.2 and 2 multiples of pickup)

Drop-off time ≤30ms

2.10.13 Undervoltage Protection

Voltage setting 10~100 (V)

Lowest voltage threshold of voltage recovery 10~100 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater

Drop-off to pickup ratio ≤102%

50Hz ≤20ms (at 0.8 times voltage setting)


Operating time
60Hz:≤20ms (at 0.8 times voltage setting)

Time setting 0.05~100 (s)

Time setting of fault recovery 0~100 (s)

Tolerance of time setting ≤1% of setting +30ms (at 0.8 times voltage setting)

du/dt setting 0~100 (V/s)

Drop-off time ≤30ms

2.10.14 Overfrequency Protection


Frequency setting 50~65 (Hz)
Tolerance of frequency setting ≤ 0.02Hz
Time setting 0~100 (s)
Tolerance of time setting ≤1%Setting+100ms (at 1.2 times frequency setting)

2.10.15 Underfrequency Protection


Frequency setting 45~60 (Hz)
Tolerance of frequency setting ≤ 0.02Hz
Time setting 0~100 (s)

2-16 PCS-978 Transformer Relay


Date: 2015-01-13
2 Technical Data

Time setting of fault recovery ≤1%Setting+100ms (at 0.8 times frequency setting)
df/dt setting 0.2~20 (Hz/s)
Tolerance of df/dt setting ≤ 0.02Hz/s

2.10.16 Thermal Overload Protection

Base current setting range 0.04In~30In (A)

Transformer thermal time constant 0~100 (s)

Thermal overload coefficient for trip 1~3

Thermal overload coefficient for alarm 1~3

≤2.5% of operating time or 30ms, whichever is greater (for


Operating time
current between 1.2 and 20 multiples of pickup)

Drop-off time ≤30ms

2.10.17 Breaker Failure Initiation

Range of phase current setting 0.04In~30In (A)

Range of residual current setting 0.04In~30In (A)

Range of negative sequence current setting 0.04In~30In (A)

Current setting tolerance ≤2.5% of setting or 0.02×In, whichever is greater

Drop-off to pickup ratio ≥95%

Time setting range 0~20 (s)

Time setting tolerance ≤1% of setting+30ms (at 2 times current setting)

Drop-off time ≤20ms

2.10.18 Pole Disagreement Protection

Range of residual current setting 0.04In~30In (A)

Range of negative sequence current setting 0.04In~30In (A)

Current setting tolerance ≤2.5% of setting or 0.02×In, whichever is greater

Drop-off to pickup ratio ≥95%

Range of time setting 0~20 (s)

Time setting tolerance ≤1% of setting+30ms (at 2 times current setting)

Drop-off time ≤30ms

2.10.19 Phase Overcurrent Alarm Element

Current setting 0.04In~30In (A)

Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater

Drop-off to pickup ratio ≥95%

50Hz: ≤25ms (at 2 times current setting)


Operating time without time delay
60Hz: ≤23ms (at 2 times current setting)

PCS-978 Transformer Relay 2-17


Date: 2016-06-22
2 Technical Data

Time setting 0~3600 (s)

Tolerance of time setting ≤1% of setting +30ms (at 2 times current setting)

Drop-off time ≤30ms

2.10.20 Residual Overvoltage Alarm Element

Voltage setting 2~200 (V)

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater

Drop-off to pickup ratio ≥95%

Time delay setting 0~3600 (s)

Tolerance of time setting ≤1% of setting+30ms (at 1.2 times voltage setting)

Drop-off time ≤30ms

2.10.21 Mechanical Protection

Delay pickup up time setting 0~3600 (s)

Pulse width setting 0~10 (s)

Time setting tolerance ≤1% of setting+30ms

2.10.22 Temperature Protection

Temperature setting 0~200 (°C)

Time setting 0.01~4800 (s)

Tolerance of temperature setting ≤0.5%x([26.Tmax]-[26.Tmin])

Drop-off to pickup ratio ≥99%x([26.T_Trp]-[26.Tmin])

Tolerance of time setting ≤1% of setting+40ms (at 1.5 times temperature setting)

Drop-off time ≤30ms

2-18 PCS-978 Transformer Relay


Date: 2015-01-13
3 Operation Theory

3 Operation Theory

Table of Contents
3 Operation Theory............................................................................... 3-a
3.1 Overview .......................................................................................................... 3-1
3.2 Three-phase Current Element (Curr3P) ......................................................... 3-1
3.2.1 Application ............................................................................................................................ 3-1
3.2.2 Function Description ............................................................................................................ 3-1
3.2.3 Function Block Diagram ....................................................................................................... 3-2
3.2.4 I/O Signals ............................................................................................................................ 3-2
3.2.5 Logic ..................................................................................................................................... 3-3
3.2.6 Settings................................................................................................................................. 3-3

3.3 Three-phase Voltage Element (Volt3P) .......................................................... 3-3


3.3.1 Application ............................................................................................................................ 3-3
3.3.2 Function Description ............................................................................................................ 3-3
3.3.3 Function Block Diagram ....................................................................................................... 3-4
3.3.4 I/O Signals ............................................................................................................................ 3-4
3.3.5 Logic ..................................................................................................................................... 3-5
3.3.6 Settings................................................................................................................................. 3-5

3.4 Residual Current Element (Curr1P) ............................................................... 3-5


3.4.1 Application ............................................................................................................................ 3-5
3.4.2 Function Description ............................................................................................................ 3-5
3.4.3 Function Block Diagram ....................................................................................................... 3-6
3.4.4 I/O Signals ............................................................................................................................ 3-6
3.4.5 Settings................................................................................................................................. 3-6

3.5 Residual Voltage Element (Volt1P) ................................................................. 3-6


3.5.1 Application ............................................................................................................................ 3-6
3.5.2 Function Description ............................................................................................................ 3-6
3.5.3 Function Block Diagram ....................................................................................................... 3-7
3.5.4 I/O Signals ............................................................................................................................ 3-7
3.5.5 Settings................................................................................................................................. 3-7
3.6 Transformer Current Differential Protection (87T) ........................................ 3-7

PCS-978 Transformer Relay 3-a


Date: 2016-06-22
3 Operation Theory

3.6.1 Application ............................................................................................................................ 3-7


3.6.2 Function Description ............................................................................................................ 3-8
3.6.3 Function Block Diagram ..................................................................................................... 3-30
3.6.4 I/O Signals .......................................................................................................................... 3-30
3.6.5 Logic ................................................................................................................................... 3-31
3.6.6 Settings............................................................................................................................... 3-34

3.7 Reactor Current Differential Protection (87R) ............................................. 3-35


3.7.1 Application .......................................................................................................................... 3-35
3.7.2 Function Description .......................................................................................................... 3-35
3.7.3 Function Block Diagram ..................................................................................................... 3-48
3.7.4 I/O Signals .......................................................................................................................... 3-48
3.7.5 Logic ................................................................................................................................... 3-49
3.7.6 Settings............................................................................................................................... 3-52

3.8 Restricted Earth Fault Protection (64REF) .................................................. 3-52


3.8.1 Application .......................................................................................................................... 3-52
3.8.2 Function Description .......................................................................................................... 3-53
3.8.3 Function Block Diagram ..................................................................................................... 3-59
3.8.4 I/O Signals .......................................................................................................................... 3-59
3.8.5 Logic ................................................................................................................................... 3-60
3.8.6 Settings............................................................................................................................... 3-61

3.9 Winding Differential Protection (87W) ......................................................... 3-61


3.9.1 Application .......................................................................................................................... 3-61
3.9.2 Function Description .......................................................................................................... 3-61
3.9.3 Function Block Diagram ..................................................................................................... 3-66
3.9.4 I/O Signals .......................................................................................................................... 3-66
3.9.5 Logic ................................................................................................................................... 3-68
3.9.6 Settings............................................................................................................................... 3-69
3.10 Inter-turn Fault Protection (21IT) ................................................................ 3-69
3.10.1 Application ........................................................................................................................ 3-69
3.10.2 Function Description ........................................................................................................ 3-69
3.10.3 I/O Signals ........................................................................................................................ 3-74
3.10.4 Logic ................................................................................................................................. 3-74
3.10.5 Settings ............................................................................................................................ 3-75
3.11 Overexcitation Protection (24) .................................................................... 3-75
3.11.1 Application ........................................................................................................................ 3-75

3-b PCS-978 Transformer Relay


Date: 2016-06-22
3 Operation Theory

3.11.2 Function Description ......................................................................................................... 3-75


3.11.3 Function Block Diagram ................................................................................................... 3-77
3.11.4 I/O Signals ........................................................................................................................ 3-77
3.11.5 Logic ................................................................................................................................. 3-78
3.11.6 Settings ............................................................................................................................. 3-79

3.12 Frequency Protection (81) .......................................................................... 3-81


3.12.1 Application ........................................................................................................................ 3-81
3.12.2 Function Description ........................................................................................................ 3-82
3.12.3 Function Block Diagram ................................................................................................... 3-83
3.12.4 I/O Signals ........................................................................................................................ 3-84
3.12.5 Logic ................................................................................................................................. 3-86
3.12.6 Settings ............................................................................................................................ 3-87

3.13 Impedance Protection (21) .......................................................................... 3-88


3.13.1 Application ........................................................................................................................ 3-88
3.13.2 Function Description ........................................................................................................ 3-89
3.13.3 Function Block Diagram ................................................................................................... 3-93
3.13.4 I/O Signals ........................................................................................................................ 3-93
3.13.5 Logic ................................................................................................................................. 3-94
3.13.6 Settings ............................................................................................................................ 3-95

3.14 Phase Overcurrent Protection (50/51P) ..................................................... 3-97


3.14.1 Application ........................................................................................................................ 3-97
3.14.2 Function Description ........................................................................................................ 3-97
3.14.3 Function Block Diagram ................................................................................................. 3-101
3.14.4 I/O Signals ...................................................................................................................... 3-101
3.14.5 Logic ............................................................................................................................... 3-102
3.14.6 Settings .......................................................................................................................... 3-104

3.15 Earth Fault Protection (50/51G) ................................................................ 3-107


3.15.1 Application ...................................................................................................................... 3-107
3.15.2 Function Description ...................................................................................................... 3-107
3.15.3 Function Block Diagram .................................................................................................. 3-111
3.15.4 I/O Signals ....................................................................................................................... 3-111
3.15.5 Logic ................................................................................................................................3-112
3.15.6 Settings ...........................................................................................................................3-113
3.16 Negative-Sequence Overcurrent Protection (50/51Q) ............................. 3-116
3.16.1 Application .......................................................................................................................3-116

PCS-978 Transformer Relay 3-c


Date: 2016-06-22
3 Operation Theory

3.16.2 Function Description .......................................................................................................3-116


3.16.3 Function Block Diagram ..................................................................................................3-117
3.16.4 I/O Signals .......................................................................................................................3-117
3.16.5 Logic ................................................................................................................................3-118
3.16.6 Settings ...........................................................................................................................3-119

3.17 Phase Overvoltage Protection (59P) ........................................................ 3-120


3.17.1 Application ...................................................................................................................... 3-120
3.17.2 Function Description ...................................................................................................... 3-120
3.17.3 Function Block Diagram ................................................................................................. 3-123
3.17.4 I/O Signals ...................................................................................................................... 3-123
3.17.5 Logic ............................................................................................................................... 3-124
3.17.6 Settings .......................................................................................................................... 3-124

3.18 Residual Overvoltage Protection (59G) ................................................... 3-126


3.18.1 Application ...................................................................................................................... 3-126
3.18.2 Function Description ...................................................................................................... 3-126
3.18.3 Function Block Diagram ................................................................................................. 3-128
3.18.4 I/O Signals ...................................................................................................................... 3-128
3.18.5 Logic ............................................................................................................................... 3-129
3.18.6 Settings .......................................................................................................................... 3-129

3.19 Undervoltage Protection (27P) ................................................................. 3-131


3.19.1 Application ...................................................................................................................... 3-131
3.19.2 Function Description ...................................................................................................... 3-131
3.19.3 Function Block Diagram ................................................................................................. 3-132
3.19.4 I/O Signals ...................................................................................................................... 3-132
3.19.5 Logic ............................................................................................................................... 3-133
3.19.6 Settings .......................................................................................................................... 3-134

3.20 Thermal Overload Protection (49) ............................................................ 3-135


3.20.1 Application ...................................................................................................................... 3-135
3.20.2 Function Description ...................................................................................................... 3-136
3.20.3 Function Block Diagram ................................................................................................. 3-138
3.20.4 I/O Signals ...................................................................................................................... 3-138
3.20.5 Logic ............................................................................................................................... 3-139
3.20.6 Settings .......................................................................................................................... 3-139
3.21 Breaker Failure Protection (50BF) ............................................................ 3-140
3.21.1 Application ...................................................................................................................... 3-140

3-d PCS-978 Transformer Relay


Date: 2016-06-22
3 Operation Theory

3.21.2 Function Description ...................................................................................................... 3-140


3.21.3 Function Block Diagram ................................................................................................. 3-141
3.21.4 I/O Signals ...................................................................................................................... 3-141
3.21.5 Logic ............................................................................................................................... 3-143
3.21.6 Settings .......................................................................................................................... 3-143

3.22 Pole Disagreement Protection (62PD) ..................................................... 3-144


3.22.1 Application ...................................................................................................................... 3-144
3.22.2 Function Description ...................................................................................................... 3-145
3.22.3 Function Block Diagram ................................................................................................. 3-145
3.22.4 I/O Signals ...................................................................................................................... 3-145
3.22.5 Logic ............................................................................................................................... 3-146
3.22.6 Settings .......................................................................................................................... 3-146

3.23 Phase Overcurrent Alarm (51PAlm) ......................................................... 3-147


3.23.1 Application ...................................................................................................................... 3-147
3.23.2 Function Description ...................................................................................................... 3-147
3.23.3 Function Block Diagram ................................................................................................. 3-148
3.23.4 I/O Signals ...................................................................................................................... 3-148
3.23.5 Logic ............................................................................................................................... 3-148
3.23.6 Settings .......................................................................................................................... 3-149

3.24 Residual Overvoltage Alarm (59GAlm) .................................................... 3-149


3.24.1 Application ...................................................................................................................... 3-149
3.24.2 Function Description ...................................................................................................... 3-149
3.24.3 Function Block Diagram ................................................................................................. 3-151
3.24.4 I/O Signals ...................................................................................................................... 3-151
3.24.5 Logic ............................................................................................................................... 3-151
3.24.6 Settings .......................................................................................................................... 3-152

3.25 Mechanical Protection (MR)...................................................................... 3-152


3.25.1 Application ...................................................................................................................... 3-152
3.25.2 Function Description ...................................................................................................... 3-153
3.25.3 Function Block Diagram ................................................................................................. 3-153
3.25.4 I/O Signals ...................................................................................................................... 3-154
3.25.5 Logic ............................................................................................................................... 3-154
3.25.6 Settings .......................................................................................................................... 3-155
3.26 Temperature Protection (26) ..................................................................... 3-156
3.26.1 Application ...................................................................................................................... 3-156

PCS-978 Transformer Relay 3-e


Date: 2016-06-22
3 Operation Theory

3.26.2 Function Description ...................................................................................................... 3-156


3.26.3 Function Block Diagram ................................................................................................. 3-157
3.26.4 I/O Signals ...................................................................................................................... 3-158
3.26.5 Logic ............................................................................................................................... 3-158
3.26.6 Settings .......................................................................................................................... 3-159

3.27 Output Map (OutMap) ................................................................................ 3-159


3.27.1 Application ...................................................................................................................... 3-159
3.27.2 Function Description ...................................................................................................... 3-159
3.27.3 I/O Signals ...................................................................................................................... 3-161
3.27.4 Settings .......................................................................................................................... 3-161

3.28 Intermediate Variable Element.................................................................. 3-162


3.28.1 Function Description ...................................................................................................... 3-162
3.28.2 I/O Signals ...................................................................................................................... 3-162

List of Figures
Figure 3.2-1 Logic diagram of current pre-processing ........................................................... 3-3

Figure 3.3-1 Logic diagram of voltage pre-processing ........................................................... 3-5

Figure 3.6-1 Current compensation calculation process...................................................... 3-13

Figure 3.6-2 Operation characteristic of sensitive biased differential element ................. 3-16

Figure 3.6-3 Operation characteristic of conventional biased differential element ........... 3-17

Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements ...... 3-18

Figure 3.6-5 Operation characteristic of DPFC biased differential protection ................... 3-21

Figure 3.6-6 Schematic of waveform symmetry principle .................................................... 3-23

Figure 3.6-7 Logic of inrush current blocking current differential protection.................... 3-26

Figure 3.6-8 Logic diagram of transformer differential protection start ............................. 3-31

Figure 3.6-9 Logic diagram of instantaneous differential element ...................................... 3-31

Figure 3.6-10 Logic diagram of biased differential element ................................................. 3-32

Figure 3.6-11 Logic diagram of DPFC biased differential element ...................................... 3-33

Figure 3.6-12 Logic diagram of CT circuit failure alarm........................................................ 3-33

Figure 3.7-1 Current compensation calculation process...................................................... 3-39

Figure 3.7-2 Operation characteristic of sensitive biased differential element ................. 3-41

Figure 3.7-3 Operation characteristic of conventional biased differential element ........... 3-42

3-f PCS-978 Transformer Relay


Date: 2016-06-22
3 Operation Theory

Figure 3.7-4 Operation characteristic of biased and Instantaneous differential element . 3-43

Figure 3.7-5 Operation characteristic of DPFC biased differential element ....................... 3-46

Figure 3.7-6 Operation characteristic of zero-sequence differential element .................... 3-47

Figure 3.7-6 Logic diagram of reactor differential protection start ..................................... 3-49

Figure 3.7-7 Logic diagram of instantaneous differential element ...................................... 3-50

Figure 3.7-8 Logic diagram of biased differential element ................................................... 3-50

Figure 3.7-9 Logic diagram of DPFC biased differential element ........................................ 3-50

Figure 3.7-11 Logic diagram of zero-sequence differential element ................................... 3-51

Figure 3.8-1 Application for two-windings transformer with one CB at one side .............. 3-53

Figure 3.8-2 Application for two-windings transformer with two CBs at one side ............ 3-54

Figure 3.8-3 Application for auto-transformer ....................................................................... 3-54

Figure 3.8-4 REF principle ........................................................................................................ 3-56

Figure 3.8-5 Operation characteristic of REF ......................................................................... 3-58

Figure 3.8-6 Logic diagram of restricted earth fault protection ........................................... 3-60

Figure 3.9-1 Winding differential protection applied to auto-transformer .......................... 3-62

Figure 3.9-2 Winding differential protection applied to stub differential protection ......... 3-62

Figure 3.9-3 Operating characteristic of winding differential protection ............................ 3-65

Figure 3.9-4 Logic diagram of winding differential protection ............................................. 3-68

Figure 3.10-1 Wiring diagram of shunt reactors in power system....................................... 3-70

Figure 3.10-2 Equivalent zero-sequence network for F1 ...................................................... 3-71

Figure 3.10-3 Vector relation for F1 ......................................................................................... 3-71

Figure 3.10-4 Equivalent zero-sequence network for F2 ...................................................... 3-72

Figure 3.10-5 Vector relation for F2 ......................................................................................... 3-72

Figure 3.10-6 Logic diagram of inter-turn fault protection ................................................... 3-74

Figure 3.11-1 Inverse-time characteristic of overexcitation protection .............................. 3-76

Figure 3.11-2 Logic diagram of definite-time overexcitation protection ............................. 3-78

Figure 3.11-3 Logic diagram of inverse-time overexcitation protection ............................. 3-79

Figure 3.12-1 Logic diagram of underfrequency protection ................................................. 3-86

Figure 3.12-2 Logic diagram of overfrequency protection ................................................... 3-87

Figure 3.13-1 Operating characteristic of phase-to-phase impedance element ................ 3-90

PCS-978 Transformer Relay 3-g


Date: 2016-06-22
3 Operation Theory

Figure 3.13-2 Operating characteristic of phase-to-ground impedance element .............. 3-90

Figure 3.13-3 Logic diagram of impedance protection (n=1, 2) ........................................... 3-94

Figure 3.14-1 VT and CT connection of direction element ................................................. 3-100

Figure 3.14-2 Directional characteristic ................................................................................ 3-100

Figure 3.14-3 Logic diagram of voltage control element (n=1, 2, 3, 4) .............................. 3-102

Figure 3.14-4 Logic diagram of direction element (n=1, 2, 3, 4) ......................................... 3-103

Figure 3.14-5 Logic Diagram of phase overcurrent protection (n=1, 2, 3) ..................... 3-103

Figure 3.14-6 Logic Diagram of phase overcurrent protection (stage 4) ....................... 3-104

Figure 3.15-1 VT and CT connection of direction element ................................................. 3-109

Figure 3.15-2 Directional characteristic ................................................................................ 3-110

Figure 3.15-3 Logic diagram of direction element (n=1, 2, 3, 4) ......................................... 3-112

Figure 3.15-4 Logic diagram of earth fault protection (n=1, 2, 3) ....................................... 3-112

Figure 3.15-5 Logic diagram of earth fault protection (stage 4) ......................................... 3-113

Figure 3.16-1 Logic diagram of negative-sequence overcurrent protection .................... 3-118

Figure 3.17-1 Logic diagram of residual overvoltage protection ....................................... 3-124

Figure 3.18-1 Logic diagram of residual overvoltage protection ....................................... 3-129

Figure 3.19-1 Logic diagram of undervoltage protection ................................................... 3-133

Figure 3.20-1 Characteristic curve of thermal overload protection ................................... 3-136

Figure 3.20-2 Logic diagram of thermal overload protection (method 1) ......................... 3-139

Figure 3.21-1 Logic diagram of breaker failure protection ................................................. 3-143

Figure 3.22-1 Logical diagram of pole disagreement protection ....................................... 3-146

Figure 3.23-1 Logic diagram of phase overcurrent alarm (n=1, 2) ..................................... 3-148

Figure 3.24-1 Logic diagram of residual overvoltage alarm ............................................... 3-151

Figure 3.25-1 Logic diagram of mechanical protection ...................................................... 3-155

Figure 3.26-1 Logic diagram of temperature protection ..................................................... 3-158

Figure 3.28-1 An example of programmable logic............................................................... 3-162

List of Tables
Table 3.2-1 I/O signals of three-phase currents element ........................................................ 3-2

Table 3.2-2 Settings of three-phase currents element ............................................................ 3-3

3-h PCS-978 Transformer Relay


Date: 2016-06-22
3 Operation Theory

Table 3.3-1 I/O signals of three-phase voltages element ........................................................ 3-4

Table 3.3-2 Settings of three-phase voltages element ............................................................ 3-5

Table 3.4-1 I/O signals of residual current element ................................................................. 3-6

Table 3.4-2 Settings of residual current element ..................................................................... 3-6

Table 3.5-1 I/O signals of residual voltage element ................................................................. 3-7

Table 3.5-2 Settings of residual voltage element ..................................................................... 3-7

Table 3.6-1 Matrix of phase compensation............................................................................. 3-11

Table 3.6-2 Comparison of different blocking modes ........................................................... 3-24

Table 3.6-3 I/O signals of transformer differential protection .............................................. 3-30

Table 3.6-4 Settings of transformer differential protection .................................................. 3-34

Table 3.7-1 I/O signals of reactor differential protection ...................................................... 3-48

Table 3.7-2 Settings of reactor current differential protection ............................................. 3-52

Table 3.8-1 I/O signals of restricted earth-fault protection ................................................... 3-59

Table 3.8-2 Settings of restricted earth fault protection ....................................................... 3-61

Table 3.9-1 I/O signals of winding differential protection ..................................................... 3-66

Table 3.9-2 Settings of winding differential protection ......................................................... 3-69

Table 3.10-1 I/O signals of inter-turn protection .................................................................... 3-74

Table 3.10-2 Settings of inter-turn fault protection ............................................................... 3-75

Table 3.11-1 I/O signals of overexcitation protection............................................................ 3-77

Table 3.11-2 Settings of overexcitation protection ................................................................ 3-79

Table 3.12-1 I/O signals of frequency protection ................................................................... 3-84

Table 3.12-2 Settings of frequency protection ....................................................................... 3-87

Table 3.13-1 I/O signals of impedance protection ................................................................. 3-93

Table 3.13-2 Settings of impedance protection ..................................................................... 3-95

Table 3.14-1 Inverse-time curve parameters .......................................................................... 3-98

Table 3.14-2 I/O signals of phase overcurrent protection................................................... 3-101

Table 3.14-3 Settings of phase overcurrent protection....................................................... 3-104

Table 3.15-1 Inverse-time curve parameters ........................................................................ 3-108

Table 3.15-2 I/O signals of earth fault protection ................................................................. 3-111

Table 3.15-3 Settings of earth fault protection ..................................................................... 3-113

PCS-978 Transformer Relay 3-i


Date: 2016-06-22
3 Operation Theory

Table 3.16-1 Inverse-time curve parameters ........................................................................ 3-117

Table 3.16-2 I/O signals of negative-sequence overcurrent protection ............................ 3-117

Table 3.16-3 Settings of negative-sequence overcurrent protection ................................ 3-119

Table 3.17-1 Inverse-time curve parameters ........................................................................ 3-122

Table 3.17-2 I/O signals of phase overvoltage protection .................................................. 3-123

Table 3.17-3 Settings of residual overvoltage protection ................................................... 3-124

Table 3.18-1 Inverse-time curve parameters ........................................................................ 3-127

Table 3.18-2 I/O signals of residual overvoltage protection ............................................... 3-128

Table 3.18-3 Settings of residual overvoltage protection ................................................... 3-129

Table 3.19-1 I/O signals of undervoltage protection ........................................................... 3-132

Table 3.19-2 Settings of undervoltage protection................................................................ 3-134

Table 3.20-1 I/O signals of thermal overload protection ..................................................... 3-138

Table 3.20-2 Settings of thermal overload protection ......................................................... 3-139

Table 3.21-1 I/O signals of breaker failure protection ......................................................... 3-141

Table 3.21-2 Settings of breaker failure protection ............................................................. 3-143

Table 3.22-1 I/O signals of pole disagreement protection .................................................. 3-145

Table 3.22-2 Settings of pole disagreement protection ...................................................... 3-146

Table 3.23-1 I/O signals of phase overcurrent alarm ........................................................... 3-148

Table 3.23-2 Settings of phase overcurrent alarm ............................................................... 3-149

Table 3.24-1 Inverse-time curve parameters ........................................................................ 3-150

Table 3.24-2 I/O signals of residual overvoltage alarm ....................................................... 3-151

Table 3.24-3 Settings of residual overvoltage alarm ........................................................... 3-152

Table 3.25-1 I/O signals of mechanical protection .............................................................. 3-154

Table 3.25-2 Settings of mechanical protection................................................................... 3-155

Table 3.26-1 I/O signals of temperature protection ............................................................. 3-158

Table 3.26-2 Settings of temperature protection ................................................................. 3-159

Table 3.27-1 I/O signals of programmable trip output......................................................... 3-161

Table 3.27-2 Settings of programmable trip output ............................................................. 3-161

Table 3.28-1 Signals of intermediate variable element ....................................................... 3-162

3-j PCS-978 Transformer Relay


Date: 2016-06-22
3 Operation Theory

3.1 Overview

The device consists of current differential protection, restricted earth fault protection,
overexcitation protection, winding differential protection, phase overcurrent protection, earth fault
protection, negative-sequence overcurrent protection, phase overcurrent alarm, phase
overvoltage protection, undervoltage protection, residual overvoltage protection, residual
overvoltage alarm, thermal overload protection, pole discrepancy protection, breaker failure
protection, impedance protection, inter-turn protection, mechanical protection and temperature
protection.

The device equips 2 DSP plug-in modules (i.e. protection DSP plug-in module and fault detector
DSP plug-in module). Protection DSP plug-in module is responsible for protection logic calculation,
and fault detector DSP plug-in module is responsible for fault detector. Fault detector element
operates to provide positive supply to output relays. The output relays can only operate when both
a protection element and the corresponding fault detector element operate simultaneously. An
alarm message will be issued with blocking output if a protection element operates while the
corresponding fault detector element does not operate.

3.2 Three-phase Current Element (Curr3P)

3.2.1 Application
Three-phase current element is responsible for pre-processing three phase currents and
calculates sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is used by the protection logic calculation.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.2.2 Function Description


Three-phase current element has following functions:

1. Pre-process three phase currents

2. Calculate information related to three-phase current

3. Monitor CT secondary circuit

3.2.2.1 CT Circuit Abnormality Supervision

If any of the following two criteria is met, the corresponding alarm signal [x.AlmL_CTS] will be
issued after 10s, and it will be reset after 10s if the device returns to normal condition.

1. Calculated residual current is greater than 0.06In or greater than 0.2 times maximum phase
current.

PCS-978 Transformer Relay 3-1


Date: 2016-06-22
3 Operation Theory

2. Negative-sequence current is greater than 0.1In or greater than 0.4 times maximum phase
current.

3.2.2.2 CT Circuit Failure Supervision

When three phase currents are engaged in the calculation of transformer differential protection,
restricted earth fault protection or winding differential protection, CT circuit failure supervision of
each protection is carried out in the corresponding protection element, which can refer to
corresponding sections for details.

3.2.2.3 Current Detection

When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.

3.2.3 Function Block Diagram

Curr3P

x.ia x.I3P

x.ib x.Ang(Ia)

x.ic x.Ang(Ib)

x.CTS.En_Alm x.Ang(Ic)

x.Ang(3I0_Cal)

x.AlmL_CTS

x.AlmH_CTS

x.Flg_OnLoad

3.2.4 I/O Signals


Table 3.2-1 I/O signals of three-phase currents element

No. Input Signal Description


1 x.ia Sampled value of phase-A current at x side of transformer
2 x.ib Sampled value of phase-B current at x side of transformer
3 x.ic Sampled value of phase-C current at x side of transformer
The enabling input of CT circuit abnormality alarm, it is triggered from binary input or
4 x.CTS.En_Alm
programmable logic etc.
No. Output Signal Description
1 x.I3P Three-phase currents at x side of transformer
2 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
3 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
4 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
5 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer
6 x.AlmL_CTS CT secondary circuit abnormality at x side of transformer

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7 x.AlmH_CTS CT secondary circuit failure at x side of transformer


8 x.Flg_OnLoad A flag indicating there is load current detected at x side of transformer

3.2.5 Logic

SIG x.3I0>0.06In >=1

SIG x.I2>0.1In
&
10s 10s x.AlmL_CTS
SIG x.CTS.En_Alm

SIG x.Ia>0.04In
>=1
SIG x.Ib>0.04In x.Flg_OnLoad

SIG x.Ic>0.04In

Figure 3.2-1 Logic diagram of current pre-processing

3.2.6 Settings
Table 3.2-2 Settings of three-phase currents element

No. Item Range Step Unit Description


Rated value of primary current at x side of
1 x.I1n 0~60000 1 A
transformer
Rated value of secondary current at x side of
2 x.I2n 1 or 5 A
transformer

3.3 Three-phase Voltage Element (Volt3P)

3.3.1 Application

Three-phase voltage element is responsible for pre-processing three phase voltages and
calculates sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.3.2 Function Description

Three-phase voltage element has following functions:

1. Pre-process three phase voltages

2. Calculate information related to three phase voltages

3. Monitor VT secondary circuit

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If any of two criteria is met and there is no operation of any fault detectors VT circuit abnormality
alarm will be issued after 10s. The abnormality alarm will be reset after 10s if the device returns to
normal condition.

1. Positive-sequence voltage is less than 0.3Unn and any phase current is greater than 0.04In.

2. Positive-sequence voltage is less than 0.3Unn and the circuit breaker is in closed position.

3. Negative-sequence voltage is greater than 0.08Unn.

4. The third harmonic magnitude of phase voltage is greater than 0.1Unn.

3.3.3 Function Block Diagram

Volt3P

x.ua x.U3P

x.ub x.Ang(Ua)

x.uc x.Ang(Ub)

x.52b x.Ang(Uc)

x.In_VT x.Ang(3U0_Cal)

x.Flg_OnLoad x.Alm_VTS

3.3.4 I/O Signals


Table 3.3-1 I/O signals of three-phase voltages element

No. Input signal Description


1 x.ua Sampled value of phase-A voltage at x side of transformer
2 x.ub Sampled value of phase-B voltage at x side of transformer
3 x.uc Sampled value of phase-C voltage at x side of transformer
Binary input of auxiliary normally closed contact of a circuit breaker at x side of
4 x.52b
transformer
5 x.In_VT Input signal of indicating VT in service at x side of transformer
6 x.Flg_OnLoad A flag indicating there is load current detected at x side of transformer
No. Output signal Description
1 x.U3P A voltage data set at x side of transformer
2 x.Ang(Ua) Phase angle of phase-A voltage at x side of transformer
3 x.Ang(Ub) Phase angle of phase-B voltage at x side of transformer
4 x.Ang(Uc) Phase angle of phase-C voltage at x side of transformer
5 x.Ang(3U0_Cal) Phase angle of calculated residual voltage at x side of transformer
6 x.Alm_VTS VT secondary circuit abnormality at x side of transformer

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3.3.5 Logic

SIG x.Up_3rd>10V
>=1
SIG x.U2>8V 10s 10s x.Alm_VTS

SIG x.U1<30V

SIG x.52bx. >=1 &

SIG x.Flg_OnLoad

SIG x.In_VT

Figure 3.3-1 Logic diagram of voltage pre-processing

Where:

Up_3rd is third harmonic of phase voltage

U2 is negative-sequence voltage

U1 is positive-sequence voltage

3.3.6 Settings
Table 3.3-2 Settings of three-phase voltages element

No. Item Range Step Unit Description


Rated value of primary voltage at x side of
1 x.U1n 1~2000 0.001 kV
transformer
Rated value of secondary voltage at x side of
2 x.U2n 100~130 0.001 V
transformer

3.4 Residual Current Element (Curr1P)

3.4.1 Application

Residual current element is responsible for pre-processing measured residual current and
calculates the magnitude and the phase angle of residual current, etc. All calculated information of
residual current element is used for the protection logic calculation.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.4.2 Function Description

Residual current element has following functions:

1. Pre-process measured residual current

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2. Calculate information related to residual current

3.4.3 Function Block Diagram

Curr1P

x.3i0 x.I1P

x.Ang(3I0_Ext)

3.4.4 I/O Signals


Table 3.4-1 I/O signals of residual current element

No. Input signal Description


1 x.3i0 Measured residual current at x side of transformer
No. Output signal Description
1 x.I1P A current data set at x side of transformer
2 x.Ang(3I0_Ext) Phase angle of measured residual current at x side of transformer

3.4.5 Settings
Table 3.4-2 Settings of residual current element

No. Item Range Step Unit Description


Primary rated current of neutral CT at x side of
1 x.I1n_NP 0~60000 1 A
transformer
Secondary rated current of neutral CT at x side of
2 x.I2n_NP 1 or 5 A
transformer

3.5 Residual Voltage Element (Volt1P)

3.5.1 Application

Residual voltage element is responsible for pre-processing residual voltage and calculates the
magnitude and the phase angle of residual voltage, etc. All calculated information of residual
voltage element is used for the protection logic calculation.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.5.2 Function Description

Residual voltage element has following functions:

1. Pre-process measured residual voltage

2. Calculate information related to residual voltage

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3.5.3 Function Block Diagram

Volt1P

x.3u0 x.U1P

x.Ang(3U0_Ext)

3.5.4 I/O Signals


Table 3.5-1 I/O signals of residual voltage element

No. Input signal Description


1 x.3u0 Measured residual voltage at x side of transformer
No. Output signal Description
1 x.U1P A voltage data set at x side of transformer
2 x.Ang(3U0_Ext) Phase angle of measured residual voltage at x side of transformer

NOTICE!

PCS-978 provides a phase calculation module (PhaseDif1P1) which is used to


calculate the phase of among residual current and residual voltage. Three input
quantities are available for this module x.AngRef, x.Ang(Ch01) and x.Ang(Ch02).
x.Ang(3I0_Cal), x.Ang(3U0_Cal), x.Ang(3I0_Ext) and x.Ang(3U0_Ext) can be
configured as input quantity of the module.

This module provides two outputs, x.Ang(Ch01-Ref) and x.Ang(Ch02-Ref), which mean
the phase between, x.Ang(Ch01) and x.AngRef and the phase between, x.Ang(Ch02)
and x.AngRef respectively.

3.5.5 Settings
Table 3.5-2 Settings of residual voltage element

No. Item Range Step Unit Description


Primary rated voltage of broken-delta VT at x side
1 x.U1n_Delt 1~2000 1000 kV
of transformer
Secondary rated voltage of broken-delta VT at x
2 x.U2n_Delt 10~200 100 V
side of transformer

3.6 Transformer Current Differential Protection (87T)

3.6.1 Application

In power system, the power transformer is one of most valuable and expensive equipment. If a
fault occurs in the protection zone of a transformer, current differential protection operates quickly
to clear the fault to avoid the transformer from damages or reduce the maintenance cost as low as
possible.

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3.6.2 Function Description


Transformer differential protection supports up to 6 group CT inputs, and can be used for
2-windings, 3-windings transformer and auto-transformer. There are 24 vector groups available for
two-winding transformer and 288 vector groups available for 3-winding transformer.

Transformer differential protection includes biased differential element, instantaneous differential


element, DPFC biased differential element. Biased differential element is biased characteristic
with three slopes Instantaneous differential element is without biased characteristic and blocking
logic and can accelerate to operate for transformer's severe internal faults. DPFC biased
differential element calculated by current variation has high sensitivity to inter-turn faults and
high-impedance fault under heavy load. Three differential elements mentioned above work
coordinately to form the high-speed current differential protection with high sensitivity.

3.6.2.1 Fault Detector

 Fault detector based on biased differential current

The fault detector can initiate biased differential element, and its operation equation is as follows.

Id>[87T.I_Biased] Equation 3.6-1

Where:

Id is the differential current of any phase.

 Fault detector based on instantaneous differential current

The fault detector can initiate instantaneous differential element, and its operation equation is as
follows.

Id>0.9x[87T.I_Inst] Equation 3.6-2

Where:

Id is the differential current of any phase.

 Fault Detector based on DPFC differential current

The fault detector can initiate DPFC biased differential element, and its operation equation is as
follows.

Equation 3.6-3

Where:

ΔIdt is the floating threshold varied with the change of load current from time to time. The change of
load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (ΔIdt) is higher than the change of current under these conditions and hence the

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element maintains stability.

Idth is fixed threshold in program. The sum value of ΔIdt and Idth is equal to 0.2p.u..

…… are DPFC current of each side of transformer representatively.

ΔId is DPFC differential current.

This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.

3.6.2.2 Amplitude Compensation

During the normal operation, the magnitudes of secondary current of each side of transformer are
different due to the mismatch between the CT ratios and the power transformer ratio. The current
value difference between each side shall be eliminated before calculation for current differential
protection by amplitude compensation.

 Calculate rated primary current at each side

Equation 3.6-4

Where:

Sn is the maximum rated capacity (i.e., the setting [Sn]).

U1n is rated primary voltage.

U1nBrm is rated primary voltage of side m (i.e., the settings [HVS.U1n_Tr], [MVS.U1n_Tr] or
[LVS.U1n_Tr]).

I1bBrm is rated primary current of side m.

 Calculate rated secondary current at each side

Equation 3.6-5

Where:

I2bBrm is rated secondary current of side m.

CTBrm is the CT ratio of side m.

 Limitation of secondary current

For all differential protections, the secondary currents of each side must follow below criterion.

Equation 3.6-6

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When selecting CT, the ratio between maximum value and minimum value should be considered.
It is recommended that the ratio is smaller than 16. Theoretically, the ratio is preferred to be as
small as it can be.

For DPFC biased differential element, the secondary currents of each side must follow Equation
3.6-7 in addition to Equation 3.6-6. Otherwise, alarm signals [ProtBrd.Fail_Settings] and
[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time unless DPFC
biased differential element is disabled.

Max(I2bBr1/I2nBr1, I2bBr2/I2nBr2, ……, I2bBrm/I2nBrm)>0.4


Equation 3.6-7
Min(I2bBr1/I2nBr1, I2bBr2/I2nBr2, ……, I2bBrm/I2nBrm)>0.1

Where:

I2bBr1, I2bBr2… I2bBrm are rated secondary current of branch 1, 2 … m of transformer.

I2nBr1, I2nBr2…I2nBrm are CT rated secondary current of branch 1, 2 … m of transformer.

NOTICE!

If Equation 3.6-6 is not met, alarm signals [ProtBrd.Fail_Settings] and


[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time.

When viewing settings and values of conventional current differential protection in the
device, p.u. (per unit value) is provided. The current in differential protection calculation
is not actual secondary value but per unit value which is got by actual secondary value
of each branch of transformer divided by transformer secondary rated current of each
side (i.e., I2bBrm).

3.6.2.3 Phase Compensation

 Phase compensation principle

False differential current is caused by phase shift between the power transformer primary current
and secondary current for delta/wye, so phases of each side secondary current must be
compensated by this phase compensation. △ →Y and Y→△ transfer methods by settings can be
selected to adjust phase angle of secondary current on each side of the transformer, and △ →Y
transfer method is recommended. Zero-sequence current is always eliminated both at Y and Δ
windings by adopting Δ→Y method.

The following transforming method is based on the assumptions listed here:

1. Each side three-phase CT of transformer shall be connected in star type.

2. The positive polarity of each side three-phase CT shall be at busbar side.

The wiring connection of HV, MV and LV sides may be different, so it is needed to compensate
phase of each side current of transformer for calculation of current differential protection. There
are two transforming methods for phase compensation: Δ→Y and Y→Δ, and different transforming
methods will result in the difference.

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Phase compensation is controlled by the following settings:

1. [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]: the wiring o’clock of MV/LV side with respect


to HV side, is the parameter shown on transformer nameplate with the range of 0~11, and
need no further calculation.

2. [Clk_PhComp]: the target o'clock each side current will be shifted to for phase compensation.

3. [HVS.En_I0Elim], [MVS.En_I0Elim] and [LVS.En_I0Elim]: logic settings to enable


zero-sequence current elimination for phase compensation of each side of transformer. The
setting is recommended to be set to “1” in general condition, and only if one side of
transformer, without earthing transformer being connected to, is not grounded, the setting of
corresponding side is recommended to be set to “0”.

For example:

The vector group of a transformer is Y0/Δ11 and the target o'clock ([Clk_PhComp]) is set to LV
side. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.

1. For HV side, with reference to the set target o'clock, the o'clock of HV side is 1 (i.e. wiring
o'clock 12-target o'clock 11) clock, so the matrix of relative o'clock 1 is adopted to compensate
HV side current.

2. For LV side, with reference to the set target o'clock, the o'clock of LV side is 0 (i.e. wiring
o'clock 11- target o'clock 11), so the matrix of relative o'clock 0 is adopted to compensate LV
side current.

If an earthing transformer is connected outside the protection zone of differential protection, the
setting [HVS.En_I0Elim] (or [LVS.En_I0Elim]) could be disabled, i.e. set to 0.

If an earthing transformer is connected within the protection zone of differential protection, then
zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the setting [HVS.En_I0Elim] (or [LVS.En_I0Elim])
must be enabled, i.e., set to 1.

Table 3.6-1 Matrix of phase compensation

Matrix (without zero-sequence current Matrix (with zero-sequence current


Relative o'clock
elimination) elimination)

0
(No phase shit)

1
(Shift 30°leading)

2
(shift 60°leading)

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3
(Shit 90°leading)

4
(Shit 120°leading)

5
(Shift 150°leading)

6
(Shift 180°leading)

7
(Shift 150°lagging)

8
(Shift 120°lagging)

S9
(Shift 90°lagging)

10
(Shift 60°lagging)

11
(Shift 30°lagging)

3.6.2.4 Calculate Differential and Restraint Currents

The equation of calculating differential current is:


 I dA   I A1  I A2   I A3  I A4 
         
 dB  M 1  I B1 2bBr1 M 2  I B 2  2bBr 2 M 3  I B3 2bBr3 M 4  I B 4  / I 2bBr 4 
I   / I   / I   / I  
 I dC   I C1  I C 2  I C 3 I C 4 
          
1 2 3 4
Equation 3.6-8
 I A5   I A6 
   
M 5   I B5  / I 2bBr5  M 6   I B6  / I 2bBr 6
I C5  I C6 
     
5 6

The above equation can be simplified to the following:

 I dA  I  A1  I  A2  I  A3  I A4  I A5  I A6



 I dB  I  B1  I  B 2  I  B3  I B 4  I B 5  I B 6 Equation 3.6-9

 I dC  I C1  I C 2  I C 3  I C 4  I C 5  I C 6

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The equation of calculating restraint current is:

 1
 
 I rA  2 I  A1  I  A2  I  A3  I  A4  I  A5  I  A6


 I rB 
1

I B1  I B 2  I B3  I B 4  I B5  I B 6  Equation 3.6-10
 2
 1

 I rC  2 I C1  I C 2  I C 3  I C 4  I C 5  I C 6 

Where:

IAm, IBm, ICm are the secondary current of branch m (m=1, 2, 3, 4, 5, 6).

I'Am, I'Bm, I'Cm are corrected secondary current of branch m (m=1, 2, 3, 4, 5, 6).

IdA, IdB, IdC are differential currents.

IrA, IrB, IrC are restraint currents.

M1, M2, M3, M4, M5, M6 are matrixes of phase shifting of each branch of transformer respectively.
Its value is decided according to the vector group of transformer and please refers to “section
3.6.2.2” for details.

I2bBr1, I2bBr2, I2bBr3, I2bBr4, I2bBr5, I2bBr6 are rated secondary values of each branch of transformer
respectively.

Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current (i.e.,
Id=I'_H+I'_L) should be zero during the normal operation of the transformer or an external fault
occurring.
*

HV side I_H I_L LV side


*

*
*

I'_H I'_L

PCS-978
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)

Magnitude compensation Magnitude compensation


(/I2bBr1) (/I2bBr2)

I''_H I''_L

Calculate differential current and restraint current

Figure 3.6-1 Current compensation calculation process

Where:

I_H, I_L are primary currents of HV and LV sides respectively.

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I'_H, I'_L are secondary currents of HV and LV sides respectively.

I''_H, I''_L are secondary corrected currents of HV and LV sides respectively.

M1, M2 are matrixes of phase shifting and zero-sequence current elimination of HV and LV sides
respectively.

I2bBr1, I2bBr2 are rated secondary currents at HV and LV sides respectively.

NOTICE!

The symbol “*” represents the polarity of CT. If current flowing into the polarity of CT, the
current direction is defined as forward direction.

To clarify the situation, three important operation conditions with ideal and matched measurement
quantities are considered.

1. Through-flowing current under undisturbed conditions or external fault:

I'_H flows into the protected zone, I'_L leaves the protected zone, according to the definition of
signs in above figure, therefore I'_H=–I'_L.

Moreover |I'_H|=|I'_L|

Id=|I'_H+I'_L|=|I'_H-I'_H|=0

Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|

Differential current (Id) is far less than restraint current (Ir), and current differential protection does
not operate.

2. Internal short-circuit fault, infeed with equal currents each side:

The following applies I'_L=I'_H, moreover |I'_L|=|I'_H|

Id=|I'_H+I'_L|=|I'_H+I'_H|=2|I'_H|

Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|

Differential current (Id) is two times of restraint current (Ir), and current differential protection
operates.

3. Internal short-circuit fault, infeed from one side only:

The following applies I'_L=0

Id=|I'_H+I'_L|=|I'_H+0|=|I'_H|

Ir=(|I'_H |+|I'_L|)/2=(|I'_H|+|0|)/2=|I'_H|/2

Differential current (Id) are two times of restraint current (Ir), and current differential protection
operates.

3.6.2.5 Biased Differential Element

1. Sensitive biased differential element

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The currents for following calculation are the products of the actual secondary current of each side
multiplying its own correction coefficient. The sensitive biased differential element with low pickup
setting and restraint slope is much more sensitive for a slight internal fault. Four blocking elements,
CT saturation, inrush current, overexcitation and CT circuit failure (optional) have also been
included for the protection in order to prevent it from the unwanted operation during an external
fault.

Equation 3.6-11

Where:

Id is the differential current.

Ir is the restraint current.

IPkp is the pickup setting of biased differential protection (i.e., [87T.I_Biased]).

Knee1 and Knee2 are respectively current settings of knee point 1 and knee point 2 (i.e.,
[87T.I_Knee1] and [87T.I_Knee2]).

K1, K2 and K3 are three slopes of biased differential protection. (i.e., [87T.Slope1], [87T.Slope2],
[87T.Slope3], recommended values: [87T.Slope1]=0.2, [87T.Slope2]=0.5 and [87T.Slope3]=0.75.)

Operation characteristic of sensitive biased differential element is shown below.

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Differential current
K=2

[87T.I_Inst]

t
en
m
le
le
ia
0.
6 nt
K= re
ffe
di
ed
as
bi
[87T.Slope1] ve [87T.Slope3]
iti
ns
se
of
ea
ar
n
a tio
er
op
1.2
[87T.Slope2]

[87T.I_Biased] Restraint current


0.8
[87T.I_Knee1] [87T.I_Knee2]

Figure 3.6-2 Operation characteristic of sensitive biased differential element

2. Conventional biased differential element

Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element is blocked only by an inrush current detection.
Conventional biased differential element provides faster operation for severe internal faults. Its
operation criterion is:

Equation 3.6-12

NOTICE!

The slope and the knee point are fixed in program, values of which eliminate the
influence of CT saturation during an external fault and ensures reliable operation even if
CT is saturated during an internal fault by means of its biased characteristic. Therefore,
the slope and the knee point with constant values do not need to be set by user.

Operation characteristic of conventional biased differential element is shown below.

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Differential current
K=2

[87T.I_Inst]

en al
lem on
t
l e nti
tia ve
ren con
iffe of
d d area
bia ation
K=0.6

se
er
op
1.2

Restraint current
0.8

Figure 3.6-3 Operation characteristic of conventional biased differential element

3.6.2.6 Instantaneous Differential Element

Instantaneous differential element for transformer is to accelerate the operation speed for
transformer's internal fault. The element has no blocking element but to guard that the setting must
be greater than the maximum inrush current. Instantaneous differential element shall operate to
clear the fault when any phase differential current is higher than its setting. Its operation criterion
is:

Id>[87T.I_Inst] Equation 3.6-13

Where:

Id is the maximum value of three phase differential currents.

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Differential current
F operation area of instantaneous
K=2 differential element

[87T.I_Inst]

of d
r ea ase t K=0.6
a i n
[87T.Slope1] n lb e
tio na elem
a o
e r ti a l ve
iti t
op ven nti e ns en
n r e s em
co iffe of l el [87T.Slope3]
d ea ia
ar ent
n r
io iffe
at
per ed d
E C o as
bi

D
1.2

[87T.Slope2]

[87T.I_Biased]
0.8 B Restraint current
A [87T.I_Knee2]
[87T.I_Knee1]

Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements

The characteristic of internal faults is a straight line with the slope 2 (63.4°) in the operation
diagram (dash-dotted line K=2)

Point A shows normal operation of transformer.

Point B shows CT saturation.

Point C, D, E, and F indicate internal faults or external fault of transformer.

1. Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure sensitivity and avoid
the unwanted operation when CT is saturated during an external fault. Its operation area is the tint
shadow area in the figure above.

When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.

When an external fault occurs, the short-circuit current rise strongly, causing a correspondingly
high restraint current (2 times through-flowing current) with little differential current. After CT
reaches saturation (point B), a differential quantity is produced and the restraint quantity is
reduced. In consequence, the operating point may moves into the tripping area of sensitive biased
differential protection. Because CT saturation criterion is equipped, sensitive biased differential
protection will not maloperate even the fault point moves into the operation area.

2. Conventional biased differential element will send tripping signal monitored by inrush current
only. It eliminates the influence of transient and steady saturations of CT during an external fault
and ensures reliable operation even if CT is in saturation condition during an internal fault by

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means of its biased characteristic. Its operation area is the deeper shadow area in the figure
above.

When an internal fault occurs, differential current rises greatly and the operating point moves to E
in the tripping area of conventional biased differential protection. (Only the second harmonic
criterion is adapted to distinguishing inrush current for blocking conventional biased differential
protection.)

3. Unrestrained instantaneous differential protection element will send tripping signal without
any blocking if differential current of any phase reaches its setting. Its operation area is over the
above two areas with the deepest dark shadow.

When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.

3.6.2.7 DPFC Biased Differential Element

DPFC biased differential protection is regardless of the load current and is sensitive to small
internal fault current within the transformer. Its performance against current transformer saturation
is also good. DPFC (Deviation of Power Frequency Component) is the power frequency
component of fault component, which is the differential value between the sampling value at this
time point and that at a cycle before.

DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to slight inter-turn fault is maintained during normal operation of transformer. The sensitivity
of transformer differential protection is improved greatly when DPFC biased differential element is
enabled, especially in the situation inter-turn fault during heavy load operation.

200

100

-100

-200
0 20 40 60 80 100 120
Original Current
100

50

-50

-100
0 20 40 60 80 100 120
DPFC current

I(k) is the sampling value at a point.

I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.

From above figures, it is concluded that DPFC can reflect the sudden change of fault current at the
initial stage of a fault and has a perfect performance of fault detection. DPFC biased differential

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3 Operation Theory

protection reflects variation of load condition to perform a sensitive protection for the transformer.
Lab tests show that it is more sensitive than the biased differential element under the heavy load
condition. DPFC restraint current and differential current are phase-segregated. DPFC biased
differential element can be blocked by inrush current, overexcitation and CT circuit failure. The
operation criterion is as follows:

Equation 3.6-14

Where:

ΔIdt is the floating threshold varied with the change of load current from time to time. The change of
load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (ΔIdt) is higher than the change of current under these conditions and hence the
element maintains stability.

Idth is fixed threshold and need not use to configure it. The sum value of ΔIdt and Idth is equal to
0.2p.u.

, , are DPFC current of branch k of the transformer.

ΔId is DPFC differential current.

ΔIr is DPFC restraint current, it is the maximum current among the restraint current of three
phases.

NOTICE!

Because the calculation of restraint current is different between DPFC biased


differential element and biased differential protection, it is difficult to test the
characteristic at site, so we recommend qualitative function test only at site.

Operation characteristic of DPFC biased differential element is shown below.

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Differential current
K=m

K=0.75

1.2p.u.

K=0.6
0.2p.u.
Restraint current
0.333p.u. 2p.u.

Figure 3.6-5 Operation characteristic of DPFC biased differential protection

The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.

DPFC biased differential element can detect a slight inter-turn fault of transformer more sensitively
than biased current differential element. During a slight inter-turn fault, fault current will flow
through transformer whether transformer is fed from one side or from both sides. Therefore,
following two typical situations (an external fault and a slight inter-turn fault) are given to show
differential and restraint current calculation.
During normal operation, Ia_HVS=1A∠0°, Ib_LVS=1A∠180°

1. A slight inter-turn fault: I'a_HVS=1.3A∠0°, I'b_LVS=1.1A∠180°, other phase are supposed


as zero

 Biased differential element:

Id=|I'a_HVS+I'b_LVS|

=|1.3A∠0°+1.1A∠180°|=0.2A

Ir=0.5x(|I'a_HVS|+|I'b_LVS|)

=0.5x(|1.3A∠0°|+|1.1A∠180°|)=1.2A

 DPFC biased differential element:

ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|

=|(1.3A∠0°-1A∠0°)+(1.1A∠180°-1A∠180°)|=0.2A

ΔIr=max(|I'a_HVS-Ia_HVS|,|I'b_LVS-Ib_LVS|)

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3 Operation Theory

=max(|1.3A∠0°-1A∠0°|,|1.1A∠180°-1A∠180°|)=0.3A

Conclusion: DPFC biased differential element is more sensitive than biased differential element
during an internal fault.

2. An external fault: I'a_HVS=2A∠0°, I'b_LVS=2A∠180°, other phase are supposed as zero

 Biased differential element:

Id=|I'a_HVS+I'b_LVS|

=|2A∠0°+2A∠180°|=0A

Ir=0.5x(|I'a_HVS|+|I'b_LVS|)

=0.5x(|2A∠0°|+|2A∠180°|)=2A

 DPFC biased differential element:

ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|

=|(2A∠0°-1A∠0°)+(2A∠180°-1A∠180°)|=0A

ΔIr=max(|I'a_HVS-Ia_HVS|, |I'b-_LVS-Ib_LVS|)

=max(|2A∠0°-1A∠0°|,|2A∠180°-1A∠180°|)=1A

Conclusion: DPFC biased differential element does not operate during an external fault.

3.6.2.8 Inrush Current Discrimination

The device provides optional inrush current distinguished principles: harmonic principle (second
harmonic and third harmonic) or waveform symmetry principle. The logic setting
[87T.Opt_Inrush_Ident] is used to select distinguished principle. The discrimination of inrush
current by third harmonics is independent criterion, and is not controlled by the setting
[87T.Opt_Inrush_Ident]. When an internal fault occurs and CT goes to stable saturation, there are
great third harmonic component in CT secondary current. Because sensitive biased differential
element has too high sensitivity, the third harmonic criterion is only used to block sensitive biased
differential element to prevent it from maloperation when both [87T.Opt_Inrush_Indent] and
[En_Hm3_Inrush] are set as “1”.

1. Inrush current discrimination based on harmonics

The second and third harmonics of differential current can be used to distinguish inrush current. Its
criteria are:

Equation 3.6-15

Where:

and are the second and third harmonics of phase differential current respectively.

is the fundamental component of corresponding phase differential current.

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It is recommended to set [87T.K_Hm2_Inrush]=0.15 and [87T.K_Hm3_Inrush]=0.2.

2. Inrush current discrimination based on waveform symmetry principle

The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized, plentiful harmonics will appear, and the waveform will be distorted,
interrupted and unsymmetrical. Wave symmetry principle is used to distinguish inrush current.

CT saturation characteristics make waveform unsymmetrical between the first half cycle and the
second half cycle. During internal faults, current waveform is sinusoidal wave, so two half cycles of
wave are almost symmetrical after aperiodic component is eliminated (calculate the differential of
differential current in fact).

As shown in Figure 3.6-6, arc ABC is a cycle of typical waveform of differential current with
aperiodic component. Flip the arc BC of second half cycle vertically to get the arc B'C', and then
move it forward half cycle to get the arc B''C''. The degree of symmetry of current wave is shown
as

Equation 3.6-16

Where:

X: arc AB

Y: arc B''C''

S+: are of X-Y

S-: are of X+Y

Figure 3.6-6 Schematic of waveform symmetry principle

For a differential current waveform, the area of X is almost equal to that of Y and the value of Ksym
is almost 0. For an unsymmetrical waveform, the area of X is not equal to that of Y, so the value of
Ksym is a great value. Therefore, waveform of inrush current can be distinguished from the
waveform of internal fault according to the value of K sym.

Both waveform symmetry principle and second harmonic principle are based on current distortion

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3 Operation Theory

due to inrush current, and the only difference is the mathematical method. The second harmonic
principle is to calculate the percentage of second harmonic in differential current, but the waveform
symmetry principle is to calculate the percentage of even harmonic to total differential current.

3.6.2.9 Inrush Blocking Mode

There are two optional blocking modes for inrush current, self-adaptive blocking mode and
phase-to-phase cross blocking mode, by the logic setting [87T.Opt_BlkMode_Inrush].
Self-adaptive blocking mode can enhance ability of differential protection to avoid maloperation
during transformer energization effectively and ensure high speed of differential protection for
faults under normal operation. The self-adaptive blocking mode is recommended to be selected in
the actual application.

1. Self-adaptive blocking mode

The device has an energizing detection element by current criterion (without additional breaker
position signal) to check whether the transformer is in the process of energization. Once the
transformer in the process of energization is detected, the following criterions are adopted to
improve the stability to avoid mal-operation caused by inrush current.

 Criterion 1

The device automatically decreases the restraint coefficient values of second harmonics and wave
distortion during the initial stage of transformer energization and with the passage of time
automatically increases those values which shall be not greater than corresponding values of
settings. This feature ensures biased differential element fast operation for transformer energized
on to a fault in addition to the inrush current blocking.

 Criterion 2

The device can be self-adaptive to enable the phase-to-phase crossing block mode according to
the comprehensive characteristics of three-phase differential current. If inrush current is
distinguished, the enables phase-to-phase crossing block mode for short time, and then switches
to phase-segregated blocking mode after a period.

 Criterion 3

If the second harmonic percent of differential current used as auxiliary criteria continues to rise,
then biased differential element is kept being blocked.

2. Phase-to-phase crossing blocking mode

Only if two phases current are distinguished not inrush current, then differential element of
corresponding two phases will be released to operate.

Conventional blocking mode is phase blocking mode, and a list is given below to compare the
difference among three blocking modes under different cases.

Table 3.6-2 Comparison of different blocking modes

Case Harmonic current Mode 1 Mode 2 Mode 3


1 Ida (large number of harmonic) Not operate Not operate Not operate

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Case Harmonic current Mode 1 Mode 2 Mode 3


Idb (large number of harmonic)
Idc (large number of harmonic)
Ida (normal)
2 Idb (normal) Operate Operate Operate
Idc (normal)
Ida (large number of harmonic) Operate or not operate
3 Idb (large number of harmonic) according to differential Not operate Not operate
Idc (normal) current waveform
Ida (large number of harmonic)
4 Idb (normal) Operate Operate Not operate
Idc (normal)

Mode 1: self-adaptive blocking mode

Mode 2: phase-to-phase crossing blocking mode

Mode 3: phase blocking mode (Not provided by PCS-978)

For mode 1 in case 3, when blocking criterion 1, 2 and 3 of inrush current discrimination are all
released to differential element, differential element can operate. Otherwise, differential element
will be blocked if any of three blocking criterions blocks.

Case 4 is usually an internal fault, and blocking mode 2 can ensure differential protection operate
correctly if there is an internal fault in case 4. Case 3 may be an internal fault or inrush current, and
blocking mode 1 can distinguish through its perfect criteria, hence, it is recommended to use
blocking mode 1.

NOTICE!

Only self-adaptive blocking mode (mode 1) and phase-to-phase crossing blocking


mode (mode 2) are provided by PCS-978.

The following figure shows the logic of inrush current blocking differential protection.

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3 Operation Theory

SIG Transformer energization >=1


&
SIG Blocking criterion 1 &

SIG Blocking criterion 3

SIG Flag_NoInrush_Harm &


>=1
SET [87T.Opt_Inrush_Ident]

&
No Inrush (Phase A)
&
SIG Flag_NoInrush_Wave No Inrush (Phase B)

SIG 87T.St No Inrush (Phase C)

SIG Flag_NoInrush_Hm3 >=1

Only valid for sensitive biased


EN [87T.En_Hm3_Blk]
differential element

SIG No Inrush (Phase A) &


& >=1

& >=1
SIG No Inrush (Phase B)
Not block 87T
&

&
SIG No Inrush (Phase C)
&

>=1
SET [87T.Opt_BlkMode_Inrush]
>=1
SIG Transformer energization 100ms 0ms &

SIG Blocking criterion 2

Figure 3.6-7 Logic of inrush current blocking current differential protection

Where:

“Flag_NoInrush_Harm” is the internal signal that means no inrush current is detected by the
harmonic principle.

“Flag_NoInrush_Wave” is the internal signal that means no inrush current is detected by the
waveform symmetry principle.

“Flg_NoInrush_Hm3” is the internal signal that means no inrush current is detected by the third
harmonic principle.

3.6.2.10 CT Saturation Detection

There are two kinds of CT saturation, i.e. transient CT saturation and stable CT saturation. If an

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external fault or an internal fault occurs, CT primary current increases greatly and CT secondary
current consists of fundamental component, DC component and harmonic component. The
decaying DC component results in remanent magnetism in magnetic core, and with the
accumulation of remanent magnetism, CT goes into saturation state which is called transient CT
saturation. With the time passed, the DC component decays to zero almost and CT is still
saturated caused by AC excitation, which is called stable CT saturation.

According to tests in lab, it is found that the second harmonic component is greater than the third
harmonic component at the stage of CT transient saturation and the third harmonic is greater than
the secondary harmonic at the stage of CT stable saturation. Therefore, the second and third
harmonics both can be used to detect CT saturation.

In order to prevent an unwanted operation of sensitive biased differential protection caused by


transient or steady state saturation of CT during an external fault, the second and third harmonics
of secondary current of individual CTs are used for the protection equipment to discriminate
saturation of three-phase CT. If CT saturation is detected, then sensitive biased differential
element will be blocked.

Equation 3.6-17

Where:

is the fundamental component of one phase current.

is the secondary harmonic of the same phase current.

is the third harmonic of the same phase current.

and are fixed coefficients of secondary and third harmonics respectively.

If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and sensitive biased differential element will be
blocked.

Internal faults can be distinguished from external faults by differential protection through the
asynchronous method of differential and restraint, and it is needed that the saturation free time of
CT is no less than 4ms for internal faults to ensure differential protection operate correctly with the
added CT saturation criterion.

3.6.2.11 Overexcitation Detection

When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The third or fifth harmonic of differential current can
be selected to determinate overexcitation.

Id_3rd/5th>[87T.K_Hm3/Hm5_OvExc]×Id_1st Equation 3.6-18

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3 Operation Theory

Where:

Id_1st is the fundamental component of differential current.

Id_3rd/5th is the third or fifth harmonic of differential current.

The fifth harmonic is recommended to be selected for overexcitation calculation.

The degree of overexcitation (overexcitation factor n) can is evaluated as follows:

Equation 3.6-19

Where:

and are per unit value of voltage and frequency respectively.

The base value for calculating per unit value of voltage is rated secondary voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.

If overexcitation factor is less than 1.4, biased differential element is blocked when the constant of
fifth or third harmonics is greater than [87T.K_Hm3/Hm5_OvExc] and this condition is judged as
overexcitation condition without damages to transformer. If overexcitation factor is greater than 1.4,
biased differential element is no longer being blocked by overexcitation because transformer is
damaged in this situation.

3.6.2.12 Differential CT Circuit Supervision

1. Differential CT circuit abnormality

If the differential current in any phase is continually greater than the alarm setting [87T.I_Alm] over
10s, the differential current abnormality alarm [87T.Alm_Diff] will be issued, but this alarm will not
block differential protection.

2. Differential CT circuit failure

The following two cases are considered as CT circuit failure, and the device can discriminate at
which side CT circuit is failure by unbalanced currents. Differential CT secondary circuit failure can
be judged more accurately and reliably by adopting combined method of voltage and current.

 First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential current
picks up, it will be judged as CT circuit failure and the alarm will be issued.

1) Negative-sequence voltage at any side is greater than 2%Upp (Upp is the secondary
phase-to-phase rated voltage).

2) Any phase current at any side increases after fault detector picks up.

3) The maximum phase current is greater than 1.1p.u. after the fault detector picks up.

4) DPFC element of any phase-to-phase voltage at any side picks up.

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 If the alarm of differential CT circuit abnormality (i.e. [87T.Alm_Diff]) is issued and


negative-sequence current at one side is greater than 0.04 times maximum phase current at
the same side or greater than 0.1In, and then CT circuit failure will be judged.

3. Influence of CT circuit failure on differential protection

The alarm of CT circuit failure can be settable to block transformer differential protection, reactor
differential protection, restricted earth-fault protection and winding differential protection. The
alarm of CT circuit failure is latched once issued, it can be reset only after the failure is cleared and
the device is reset.

 Transformer's conventional biased differential element and instantaneous differential element


are always not blocked during CT circuit failure.

 Transformer's DPFC biased differential element is always blocked during CT circuit failure.

 Transformer's sensitive biased differential element will be blocked during CT circuit failure
when the logic setting [87T.En_CTS_Blk] set as “1”.

 Reactor's sensitive biased differential element will be blocked during CT circuit failure when
the logic setting [87R.En_CTS_Blk] is set as “1”.

 Biased restricted earth-fault element will be blocked during CT circuit failure when the logic
setting [64REF.En_CTS_Blk] is set as “1”.

 Biased winding differential protection will be blocked during CT circuit failure when the logic
setting [87W.En_CTS_Blk] is set as “1”.

NOTICE!

The operation time of biased differential element controlled by CT circuit failure has
additional 50ms delay than that of biased differential protection not controlled by CT
circuit failure.

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3.6.3 Function Block Diagram

87T

87T.I3P1 87T.St

87T.I3P2 87T.On_Inst

87T.I3P3 87T.On_Biased

87T.I3P4 87T.On_DPFC

87T.I3P5 87T.Op

87T.I3P6 87T.Op_Inst

87T.En1 87T.Op_Biased

87T.En2 87T.Op_DPFC

87T.Blk 87T.Alm_Diff

87T.Alm_CTS

3.6.4 I/O Signals


Table 3.6-3 I/O signals of transformer differential protection

No. Input signal Description


1 87T.I3P1 Three-phase current data input 1 for transformer current differential protection.
2 87T.I3P2 Three-phase current data input 2 for transformer current differential protection.
3 87T.I3P3 Three-phase current data input 3 for transformer current differential protection.
4 87T.I3P4 Three-phase current data input 4 for transformer current differential protection.
5 87T.I3P5 Three-phase current data input 5 for transformer current differential protection.
6 87T.I3P6 Three-phase current data input 6 for transformer current differential protection.
Input signal 1 of enabling transformer current differential protection. It is triggered
7 87T.En1
from binary input or programmable logic etc.
Input signal 2 of enabling transformer current differential protection. It is triggered
8 87T.En2
from binary input or programmable logic etc.
Input signal of blocking transformer current differential protection. It is triggered
9 87T.Blk
from binary input or programmable logic etc.
No. Output signal Description
1 87T.St Transformer differential protection starts.
Instantaneous differential element of transformer differential protection is
2 87T.On_Inst
enabled.
3 87T.On_Biased Biased differential element of transformer differential protection is enabled.
4 87T.On_DPFC DPFC differential element of transformer differential protection is enabled.
5 87T.Op_Inst Instantaneous differential element of transformer differential protection operates.
6 87T.Op_Biased Biased differential element of transformer differential protection operates.
7 87T.Op_DPFC DPFC differential element of transformer differential protection operates.

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No. Input signal Description


8 87T.Op Transformer differential protection operates.
9 87T.Alm_Diff Differential current of transformer differential protection is abnormal.
10 87T.Alm_CTS CT secondary circuit of transformer differential protection is abnormal.
Instantaneous differential element of transformer differential protection picks up
11 87T.TrigDFR_Inst
to trigger DFR function.
Biased differential element of transformer differential protection picks up to trigger
12 87T.TrigDFR_Biased
DFR function.
DPFC differential element of transformer differential protection picks up to trigger
13 87T.TrigDFR_DPFC
DFR function.

3.6.5 Logic

SIG 87T.En1
&
SIG 87T.En2

SIG 87T.Blk

EN [87T.En_Inst] &

SET Idmax>[87T.I_Inst]
&
EN [87T.En_Biased] & >=1 87T.St

SET Idmax>[87T.I_Biased]

EN [87T.En_DPFC] &

SET ΔId>1.25ΔIdt+Idth

Figure 3.6-8 Logic diagram of transformer differential protection start

EN [87T.En_Inst]
&
SIG 87T.En1
& 87T.On_Inst
SIG 87T.En2

SIG 87T.Blk
&
SET Idmax>[87T.I_Inst]
87T.Op_Inst
SIG 87T.FD_Inst 0ms 500ms

Figure 3.6-9 Logic diagram of instantaneous differential element

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EN [87T.En_Biased]
&
SIG 87T.En1
& 87T.On_Biased
SIG 87T.En2

SIG 87T.Blk

SIG Conventional 87T & &

SIG Inrush current

SIG 87T.FD_Biased 0ms 500ms

EN [87T.En_Biased]
&
SIG 87T.En1
& &
SIG 87T.En2

SIG 87T.Blk
>=1
SIG Sensitive 87T 0ms 500ms & 87T.Op_Biased

SIG CT saturation >=1

SIG Inrush current

SIG CT circuit failure & &


&
EN [87T.En_CTS_Blk]

SIG Overexcitation &

SIG U*/f*>1.4

SIG 87T.FD_Biased 0ms 500ms

Figure 3.6-10 Logic diagram of biased differential element

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EN [87T.En_DPFC]
&
SIG 87T.En1
& 87T.On_DPFC
SIG 87T.En2

SIG 87T.Blk

SIG DPFC 87T

SIG Inrush current


& &
SIG CT circuit failure 87T.Op_DPFC

SIG Overexcitation &

SIG U*/f*>1.4

SIG 87T.FD_DPFC 0ms 500ms

Figure 3.6-11 Logic diagram of DPFC biased differential element

SIG U2>2%Upp >=1

>=1
SIG DPFC line voltage pickup
>=1 &
SIG Any phase current increase >=1 &
CT circuit failure
SIG Ipmax>1.1p.u.

SIG 87T.FD_Biased

SIG CT circuit failure &


T 0ms x.AlmH_CTS
SIG I2>0.04Ipmax or I2>0.1In

&
T 0ms 87T.Alm_CTS

Figure 3.6-12 Logic diagram of CT circuit failure alarm

Where:

Idmax is the maximum value of three phase differential currents.

“87T.FD_Inst” means that the fault detector of instantaneous differential element picks up.

“87T.FD_Biased” means that the fault detector of biased differential element picks up.

“87T.FD_DPFC” means that the fault detector of DPFC biased differential protection picks up.

“Upp” is phase-to-phase secondary rated voltage.

“T” is an internal time delay parameter, and it is floating and not open for user’s configuration.

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3.6.6 Settings
Table 3.6-4 Settings of transformer differential protection

No. Item Range Step Unit Description


Current setting of knee point 1 for
1 87T.I_Knee1 0.100~1.000 0.001 p.u.
transformer differential protection
Current setting of knee point 2 for
2 87T.I_Knee2 4.000~8.000 0.001 p.u.
transformer differential protection
3 87T.I_Biased 0.050~5.000 0.001 p.u. Pickup setting of biased differential element
Current setting of instantaneous differential
4 87T.I_Inst 0.050~20.000 0.001 p.u.
element
5 87T.Slope1 0.010~0.900 0.001 Slope 1 of biased differential element
6 87T.Slope2 0.100~0.900 0.001 Slope 2 of biased differential element
7 87T.Slope3 0.100~0.900 0.001 Slope 3 of biased differential element
Coefficient of second harmonics for inrush
8 87T.K_Hm2_Inrush 0.050~0.800 0.001
current detection
Coefficient of third harmonics for inrush
9 87T.K_Hm3_Inrush 0.050~0.800 0.001
current detection
Current setting of differential circuit
10 87T.I_Alm 0.050~1.500 0.001 p.u.
abnormality alarm
Coefficient of third or fifth harmonic for
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 0.001 overexcitation detection
The recommended value is 0.25.
Logic setting of enabling/disabling
instantaneous differential element
12 87T.En_Inst 0 or 1 1
0: disable
1: enable
Logic setting of enabling/disabling
conventional biased differential element
13 87T.En_Biased 0 or 1 1
0: disable
1: enable
Logic setting of enabling/disabling DPFC
biased differential element
14 87T.En_DPFC 0 or 1 1
0: disable
1: enable
Option of inrush current discrimination
principle:
15 87T.Opt_Inrush_Ident 0, 1 1
0: waveform symmetry
1: Harmonic principle
Option of inrush blocking mode
16 87T.Opt_BlkMode_Inrush 0, 1 1 0: self-adaptive blocking
1: phase-to-phase crossing
Logic setting of enabling/disabling third
17 87T.En_Hm3_Blk 0 or 1 1
harmonic blocking for inrush current

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No. Item Range Step Unit Description


0: disable
1: enable
Logic setting of enabling/disabling block
biased differential element during CT circuit
18 87T.En_CTS_Blk 0 or 1 1 failure
0: disable
1: enable
Option of third or fifth harmonic for
overexcitation criterion
19 87T.Opt_Hm3/Hm5_OvExc 0, 1 1
0: third harmonic
1: fifth harmonic
Tripping logic setting of transformer
differential protection
20 87T.OutMap 0000~FFFF
Refer to section 3.27 for detailed
description

3.7 Reactor Current Differential Protection (87R)

3.7.1 Application
If an earth fault or phase-to-phase fault of reactor occurs, current differential protection can
operate quickly to clear the fault to avoid the reactor from damages or reduce the maintenance
cost as low as possible. Different to transformer current differential protection based on
electromagnetic balance, reactor current differential protection is based on Kirchhoff's law, so it is
needed to develop current differential protection according to the actual application of reactor not
only to use transformer current differential protection to protect reactors.

3.7.2 Function Description


Reactor current differential protection consists of biased differential element, instantaneous
differential element, DPFC biased differential element and zero-sequence differential element.
Biased differential element is two-slope differential element with biased characteristic.
Unrestrained differential element is to accelerate the operating speed for reactor's severe internal
faults without biased characteristic and blocking elements. DPFC biased differential element
calculated by current variation has high sensitivity to earth faults at ground end of reactor.
Zero-sequence differential element based on calculated residual current of two sides of reactor
has high sensitivity to asymmetric fault. Above four differential protection elements work
coordinately to form the high-speed current differential protection with high sensitivity.

3.7.2.1 Fault Detector

1. Fault detector based on biased differential current

Its operation equation is as follows.

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Id>[87R.I_Biased] Equation 3.7-1

Where:

Id is the differential current of any phase.

2. Fault detector based on instantaneous differential current

Its operation equation is as follows.

Id>0.9x[87R.I_Inst] Equation 3.7-2

Where:

Id is the differential current of any phase.

3. Fault detector based on DPFC differential current

Its operation equation is as follows.

Equation 3.7-3

Where:

is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold ( ) is higher than the change of current under these conditions and
hence the element maintains stability.

and are DPFC current of two ends of reactor representatively.

is DPFC differential current.

is the fixed threshold and the value is 0.2p.u..

This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed and thus site setting is not required.

4. Fault detector of residual differential current

It includes biased characteristic and instantaneous characteristic, and its operation equation is as
follows.

I0d>[87R.I_Biased]
Equation 3.7-4
I0d>[87R.I_Inst]

Where:

I0d is residual differential current.

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3.7.2.2 Amplitude Compensation

Under normal condition, the magnitudes of secondary current of both ends of reactor are different
due to the mismatch between CT ratios. The current value difference shall be eliminated before
calculation for current differential protection by amplitude compensation.

1. Calculate rated primary current at each side

Sn
I1b  Equation 3.7-5
3U n

Where:

S n is the rated capacity of reactor (i.e., the setting [Sn] in “System Settings” menu).

U n is rated voltage of reactor. (i.e., the setting [Un] in “System Settings” menu).

I1b is rated primary current of reactor.

2. Calculate rated secondary current at each side

Equation 3.7-6

Where:

I2b1, I2b2 are rated secondary current of two ends of reactor.

CTLine is CT ratio at the line side of reactor (also called CT1 hereinafter).

CTNP is CT ratio at the neutral point of reactor (also called CT2 hereinafter).

3. Correction coefficients

Kph1=1

Kph2=(I1n_CT2)/(I1n_CT1) Equation 3.7-7

Kph2≤4

Where:

I1n_CT1 is the primary current of CT at the line side of reactor.

I1n_CT2 is the primary current of CT at the neutral point of reactor.

Kph1 is the correction coefficient of CT at the line side of reactor.

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Kph2 is the correction coefficient of CT at the neutral point of reactor.

Line side of reactor is taken as reference side, so the correction coefficient of line side is 1 and that
of neutral point is equal to the ratio of primary current of CT2 to primary current of CT1. The
maximum ratio of two sides is 4. If the ratio is out of the limit, the device will be blocked and
corresponding alarm messages are issued.

When viewing settings and values of current differential protection in the device, the unit “p.u.” (per
unit value) can be found. The current in differential protection calculation is not actual secondary
value but per unit value which is got by actual secondary value of each side of reactor divided by
reactor secondary rated current of each branch (i.e., I2b1, I2b2).

3.7.2.3 Calculations of Differential and Restraint Currents

 I dA   I A1  I A2 
     
I
 dB   K  /
ph1  I B1 2b1I  K 
ph2  I B 2  / I 2b 2
Equation 3.7-8
 I dC   I C1  I C 2
    
1 2

The above equation can be simplified to the following:

I dA  I  A1  I  A2

I dB  I  B1  I  B 2 Equation 3.7-9

I dC  I C1  I C 2

Where:

IA1, IB1, IC1 are the equation vectors, the secondary current of line side of reactor.

IA2, IB2, IC2 are the equation vectors, the secondary current of neutral side of reactor.

IA1, IB1, IC1 are the corrected secondary current of line side of reactor.

IA2, IB2, IC2 are the corrected secondary current of neutral side of reactor.

IdA, IdB, IdC are differential currents.

Kph1, Kph2 are corrected coefficients of line and neutral sides of reactor respectively.

I2b1, I2b2 are CT rated secondary values at line side and at neutral point of reactor respectively.

The equation of calculating restraint current is:

 I rA  I  A2

 I rB  I B 2 Equation 3.7-10

 I rC  I C 2

Where:

IrA, IrB, IrC are restraint currents.

Current compensation process is shown in the flowing figure. In an ideal situation, the differential

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current (i.e., Id=I'_Line+I'_NP) should be zero during normal operation of reactor or an external
fault.

*
*
I_Line I_NP
Line side CT1 CT2 Neutral point

*
*
*

*
I'_Line I'_NP

PCS-978

Magnitude compensation (*Kph1/I2b1) Magnitude compensation (*Kph2/I2b2)

I''_Line I''_NP

Calculate differential current and restraint current

Figure 3.7-1 Current compensation calculation process

NOTICE!

The symbol “*” represents the polarity of CT. If current flowing into the polarity of CT, the
current direction is defined as positive direction.

Where:

I_Line, I_NP are primary currents of line side and neutral point of reactor respectively.

I'_Line, I'_NP are secondary currents of line side and neutral point of reactor respectively.

I''_Line, I''_NP are corrected secondary currents of line side and neutral point of reactor
respectively.

CT1, CT2 are current transformer at line side and neutral point of reactor respectively.

Kph1, Kph2 are corrected coefficients of line side and neutral point of reactor respectively.

I2b1, I2b2 are rated secondary values of CT at line side and neutral point of reactor respectively.

To clarify the situation, two important operation conditions with ideal and matched measurement
quantities are considered.

1. Through-flowing current under undisturbed conditions or external fault:

I'_Line flows into the protected zone, I'_NP leaves the protected zone, i.e. is negative
according to the definition of signs in above figure, therefore I'_Line=–I'_NP.

Moreover |I'_Line|=|I'_NP|

Id=|I'_Line+I'_NP|=0

Ir=|I'_NP|=|I'_Line|

No differential current (Id=0), restraint current (Ir) corresponds to double the through-flowing

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current, and current differential protection does not operate.

2. Internal short-circuit,|I'_Line|>|I'_NP|

The following applies I'_NP=0.5xI'_Line

Id=|I'_Line+I'_NP|=|I'_Line+0.5xI'_Line|=1.5x|I'_Line|

Ir=|I'_NP|=0.5x|I'_Line|

Differential current (Id) are three times of restraint current (Ir) and corresponding to the total
fault, and current differential protection operates.

3.7.2.4 Biased Differential Element

Biased differential element with initial restraint slope consists of sensitive and conventional
differential elements as well as independent CT saturation criterion and harmonic blocking.

1. Sensitive biased differential element

The currents used in this section analysis and the following analysis have been corrected, that
means the currents for following calculation are the products of the actual secondary current of
each side multiplying its own correction coefficient.

The sensitive biased differential element with low pickup setting and restraint slope is much more
sensitive for a slight internal fault. Three blocking elements, CT saturation, inrush current, CT
circuit failure (optional) have also been included in order to prevent it from unwanted operation
during an external fault.

Equation 3.7-11

Where:

and are phase currents of line side and neutral point of reactor respectively.

is the differential current.

is the restraint current.

KP is knee point, and its value is determined by the settings [87R.I_Biased] and [87R.Slope].

In order to improve the sensitivity of differential protection, the current of neutral point is taken as
restraint current. When an internal fault occurs, current partly flows into ground through the short
circuit point, so the current of neutral point will decrease and therefore the sensitivity of differential
protection is improved. Operation characteristic of sensitive biased differential element is shown

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below.

Differential current

K
[87R.I_Inst]

ia l
nt
re
ffe
di
ed
as
K=0.6 bi
it ive t
s n
en e
f s elem
e ao
ar
n
a tio
er [87R.Slope]
Op

1.2p.u.

[87R.I_Biased]
Restraint current

0 KP 0.8p.u.

Figure 3.7-2 Operation characteristic of sensitive biased differential element

2. Conventional biased differential element

Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element, which is blocked only by an inrush current detection.
Conventional biased differential element provides fast operation for severe internal faults.
Operation criterion is:

Equation 3.7-12

NOTICE!

Parameters of this protection have been fixed in the program and do not need to be
configured by user.

Operation characteristic of conventional biased differential element is shown below.

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Differential current
[87R.I_Inst]

t l
en na
m io
le nt
l e ve
ia n
nt co
re of
ffe a
di are
K=0.6

ed n
as i o
bi rat
pe
O

1.2p.u.

Restraint current

0 0.8p.u.

Figure 3.7-3 Operation characteristic of conventional biased differential element

3.7.2.5 Instantaneous Differential Element

Instantaneous differential element for reactor is to accelerate the operation speed for reactor's
internal fault. The element has no blocking element but to guard that the setting must be greater
than the maximum unbalanced current caused by inrush current. Instantaneous differential
element shall operate to clear the fault when any phase differential current is higher than its setting.
Operation criterion is:

Id>[87R.I_Inst] Equation 3.7-13

Where:

Id is the maximum value of three phase differential currents.

Operation characteristic of instantaneous differential element is shown below.

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Differential current
K

Operating area of
F instantaneous differential element

[87R.I_Inst]

t l
en na
K=0.6 l
ia

m io
nt

le nt
re

le e
ffe

ia nv
di

nt co
ed

re of
ias
eb

ffe a
di are
iv
it t
ns en

ed g
as in
se m

bi rat
of ele

pe
ea
O ar
E g
in
at
er
Op
[87R.Slope]
D

1.2p.u.

[87R.I_Biased]
A Restraint current

0 KP 0.8p.u.

Figure 3.7-4 Operation characteristic of biased and Instantaneous differential element

Where:

The value of K is not more than 1.

A is the point shows normal operation of reactor.

D, E, and F are points show internal faults of reactor.

1. Sensitive biased differential element will send tripping signal monitored by criteria of CT
transient characteristic difference, and CT circuit failure (optional). It can ensure sensitivity
and avoid the unwanted operation when CT is saturated during an external fault or caused by
inrush current. Its operation area is the tint shadow area in the figure above.

When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the operation area of sensitive biased differential element.

2. Conventional biased differential element will send tripping signal without blocking criteria. It
eliminates the influence of transient and steady CT saturations during an external fault and
ensures reliable operation even if CT is in saturation condition during an internal fault by
means of its biased characteristic. Its operation area is the deeper shadow area in the figure
above.

When an internal fault occurs, differential current rises greatly and the operating point moves
to E in the operation area of conventional biased differential element.

3. Instantaneous differential element will send tripping signal without any blocking if differential
current of any phase reaches its setting. Its operation area is over the above two areas with

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the deepest dark shadow.

When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.

3.7.2.6 DPFC Biased Differential Element

DPFC biased differential element is regardless of load current and is sensitive to small internal
fault current within the reactor. Its performance against CT saturation is also good. Lab tests show
that it is more sensitive than biased differential element under the heavy load condition.

DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to faults with fault resistance and faults close to neutral side is maintained during normal
operation of reactor. Floating threshold patent technology is adopted to prevent maloperation of
DPFC differential protection due to system frequency deviation, external faults and CB tripping
process.

The sensitivity of reactor current differential protection is improved greatly when DPFC differential
protection enabled, especially in the situation faults with fault resistance and faults close to neutral
point. Operation criteria are:

Equation 3.7-14

Where:

is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold ( ) is higher than the change of current under these conditions and hence the
element maintains stability.

is fixed threshold and need not use to configure it. The sum value of and is equal to
0.2p.u.

, , are the DPFC current of line side of reactor.

, , are the DPFC current of neutral point of reactor.

is the DPFC differential current.

is the DPFC restraint current, it is the maximum current among the restraint current of three

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phases.

NOTICE!

Calculation of restraint current of DPFC biased differential element is different to the


biased differential element, it is difficult to test the characteristic at site, so we
recommend qualitative function test only at site.

The calculation of DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element is blocked by inrush current and CT circuit failure. DPFC biased
differential element has the higher anti-CT saturation characteristic, the sensitivity of which to
slight inter-turn fault is maintained during normal operation of reactor.

An example of fault calculation is given.

During normal operation, Ia_Line=0.5A∠180°, Ib_NP=0.5A∠180°

1. An external fault: I'a_Line’=2A∠180°, I'b_NP=2A∠180°, other phase supposed zero

 Biased differential protection for the fault:

Id=|I'a_Line+I'b_NP|=|2A∠180°+2A∠180°|=0A

Ir=|I'b_NP|=|2A∠180°|=2A

 DPFC differential protection for the fault:

ΔId=|(I'a_Line-Ia_Line)+(I'b_NP-Ib_NP)|

=|(2A∠0°-0.5A∠0°)+(2A∠180°-0.5A∠180°)|=0A

ΔIr=Max(|I'a_Line-Ia_Line|, |I'b_NP-Ib_NP|)

=Max(|2A∠0°-0.5A∠0°|,| 2A∠180°-0.5A∠180°|)=1.5A

Conclusion: DPFC differential protection does not operate during an external fault.

2. A sight turn-to-ground fault: I'a_Line=1.1A∠0°, I'b_NP=0.7A∠180°, other phase supposed


zero

 Biased differential protection for the fault:

Id=|I'a_Line+I'b_NP|=|1.1A∠0°+0.7A∠180°|=0.3A

Ir=|I'b_NP|=0.7A

 DPFC differential protection for the fault:

ΔId=|(I'a_Line-Ia_Line)+(I'b_NP-Ib_NP)|

=|(1.1A∠0°-0.5A∠0°)+(0.7A∠180°-0.5A∠180°)|=0.4A

ΔIr= Max(|I'a_Line-Ia_Line|, |I'b_NP-Ib_NP|)

=Max(|1.1A(∠0°-0.5A∠0°|,|0.7A∠180°-0.5A∠180°|)=0.6A

Conclusion: DPFC differential protection is more sensitive than biased differential protection

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during an internal fault.

Differential current
Operation area of DPFC
K=m
biased differential element

K=0.75

1.2p.u.

0.2p.u. K=0.6 Restraint current

0.333p.u. 2p.u.

Figure 3.7-5 Operation characteristic of DPFC biased differential element

The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.

3.7.2.7 Zero-sequence Differential Element

Operation criteria are:

Equation 3.7-15

Equation 3.7-16

Equation 3.7-17

Where:

are calculated residual current of two ends of reactor respectively

is residual differential current.

is residual restraint current

In order to prevent zero-sequence differential element from being affected by non-identical CT


transient characteristic and CT saturation, positive-sequence current restraint blocking criterion is
adopted and its criterion is showed below.

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I0>β0×I1 Equation 3.7-18

Where:

I0 is the zero-sequence current at a side.

I1 is its corresponding positive-sequence current.

β0 is a proportional constant.

Operation characteristic of zero-sequence differential element is shown below.


Differential current

Operating area of
instantaneous zero-sequence
F
differential element

[87R.I_Inst]
l l
tia na

K=0.6
en tio

ce
t fe r e n

en
en dif nv

qu
o

e
el nc of c

- s
ro
ze t
ue a
em e
eq re

iv e e n
-s a

sit m
ro ing

en ele
f s tial
ze r a t

o
ea eren
pe

ar
O

g diff
a tin
er
Op
[87R.Slope]

1.2p.u.

[87R.I_Biased]
Restraint current

0 KP 0.8p.u.

Figure 3.7-6 Operation characteristic of zero-sequence differential element

3.7.2.8 Inrush Current Discrimination

Please refer to Section 3.6.2.8 for details.

3.7.2.9 CT Saturation Detection

Please refer to Section 3.6.2.10 for details.

3.7.2.10 Differential CT Circuit Supervision

Please refer to Section 3.6.2.12 for details.

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3.7.3 Function Block Diagram

87R

87R.I3P1 87R.St

87R.I3P2 87R.Op

87R.En1 87R.Op_Inst

87R.En2 87R.Op_InstREF

87R.Blk 87R.Op_Biased

87R.Op_DPFC

87R.Op_REF

87R.On_Inst

87R.On_InstREF

87R.On_Biased

87R.On_DPFC

87R.On_DPFC

87R.Alm_Diff

87R.Alm_CTS

3.7.4 I/O Signals


Table 3.7-1 I/O signals of reactor differential protection

No. Input signal Description


1 87R.I3P1 Three-phase current data input 1 for reactor differential protection.
2 87R.I3P2 Three-phase current data input 2 for reactor differential protection.
Input signal 1 of enabling reactor differential protection. It is triggered from binary
3 87R.En1
input or programmable logic etc.
Input signal 2 of enabling reactor differential protection. It is triggered from binary
4 87R.En2
input or programmable logic etc.
Input signal of blocking reactor differential protection. It is triggered from binary
5 87R.Blk
input or programmable logic etc.
No. Output signal Description
1 87R.St Reactor differential protection starts.
2 87R Op_Inst Instantaneous differential element of reactor differential protection operates.
Instantaneous zero-sequence differential element of reactor differential
3 87R Op_InstREF
protection operates.
4 87R Op_Biased Biased differential element of reactor differential protection operates.
5 87R Op_DPFC DPFC differential element of reactor differential protection operates.

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No. Input signal Description


6 87R Op_REF Zero-sequence differential element of reactor differential protection operates.
7 87R.Op Reactor differential protection operates.
8 87R On_Inst Instantaneous differential element of reactor differential protection is enabled.
Instantaneous zero-sequence differential element of reactor differential
9 87R On_InstREF
protection is enabled.
10 87R On_Biased Biased differential element of reactor differential protection is enabled.
11 87R On_DPFC DPFC differential element of reactor differential protection is enabled.
12 87R On_REF Zero-sequence differential element of reactor differential protection is enabled.
13 87R Alm_Diff Differential current of reactor differential protection is abnormal.
14 87R Alm_CTS CT secondary circuit of reactor differential protection is abnormal.
Instantaneous differential element reactor differential protection picks up to
15 87R.TrigDFR_Inst
trigger DFR function.
Biased differential element of reactor differential protection picks up to trigger
16 87R.TrigDFR_Biased
DFR function.
DPFC differential element of reactor differential protection picks up to trigger
17 87R.TrigDFR_DPFC
DFR function.

3.7.5 Logic

SIG 87R.En1
&
SIG 87R.En2

SIG 87R.Blk

EN [87R.En_Inst] &

SIG Idmax>[87R.I_Inst]
>=1
EN [87R.En_Biased] &

SIG Idmax>[87R.I_Biased]

&
EN [87R.En_REF]
&
SIG I0d>[87R.I_Inst]
>=1 >=1 87R.St
EN [87R.En_REF] &

SIG I0d>[87R.I_Biased]

EN [87R.En_DPFC] &

SIG ΔId>1.25ΔIdt+ΔIdh

Figure 3.7-7 Logic diagram of reactor differential protection start

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EN [87R.En_Inst]
&
SIG 87R.En1
& 87R.On_Inst
SIG 87R.En2

SIG 87R.Blk
&
SET Idmax>[87R.I_Inst] 87R.Op_Inst

SIG 87R.FD_Inst 0ms 500ms

Figure 3.7-8 Logic diagram of instantaneous differential element

SIG Conventional 87R


&
SIG 87R.FD_Biased 0ms 500ms

EN [87R.En_Biased]
&
SIG 87R.En1
& 87R.On_Biased
SIG 87R.En2
&
SIG 87R.Blk
>=1
SIG Sensitive 87R & 87R.Op_Biased

SIG CT saturation
&
SIG CT circuit failure & &

EN [87R.En_CTS_Blk]

SIG 87R.FD_Biased 0ms 500ms

Figure 3.7-9 Logic diagram of biased differential element

EN [87R.En_DPFC]
&
SIG 87R.En1
& 87R.On_DPFC
SIG 87R.En2

SIG 87R.Blk

SIG DPFC 87R & &


87R.Op_DPFC
SIG CT saturation
&
SIG CT circuit failure

SIG Inrush current

SIG 87R.FD_DPFC 0ms 500ms

Figure 3.7-10 Logic diagram of DPFC biased differential element

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EN [87R.En_REF]
&
EN [87R.En_Inst] 87R.On_InstREF

SIG 87R.En1
&
SIG 87R.En2

SIG 87R.Blk
&
SET I0d>[87R.I_Inst]
87R.Op_InstREF
SIG 87R.FD_InstREF 0ms 500ms

SIG Conventional 87R REF


&
SIG 87R.FD_REF 0ms 500ms

EN [87R.En_REF]
&
SIG 87R.En1
& 87R.On_REF
SIG 87R.En2
&
SIG 87R.Blk
>=1
SIG Sensitive 87R REF & 87R.Op_REF

SIG CT saturation
&
SIG CT circuit failure & &

EN [87R.En_CTS_Blk]

SIG 87R.FD_REF 0ms 500ms

Figure 3.7-11 Logic diagram of zero-sequence differential element

Where:

Idmax is the maximum value of three phase differential currents.

“87R.FD_Inst” means that the fault detector of instantaneous differential element picks up.

“87R.FD_Biased” means that the fault detector of biased differential element picks up.

“87R.FD_DPFC” means that the fault detector of DPFC biased differential protection picks up.

“87R.FD_InstREF” means that the fault detector of instantaneous zero-sequence differential


protection picks up.

“87R.FD_REF” means that the fault detector of DPFC zero-sequence differential protection picks
up.

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3.7.6 Settings
Table 3.7-2 Settings of reactor current differential protection

No. Item Range Step Unit Description


1 87R.I_Biased 0.05~5 0.001 p.u. Pickup setting of biased differential element
2 87R.I_Inst 0.05~20 0.001 p.u. Current setting of instantaneous differential element
3 87R.Slope 0.1~0.9 0.001 Slope of biased differential element
Coefficient of second harmonics for inrush
4 87R.K_Hm2_Inrush 0.05~0.3 0.001
current detection
Coefficient of third harmonics for inrush current
5 87R.K_Hm3_Inrush 0.05~0.3 0.001
detection
Current setting of differential current abnormality
6 87R.I_Alm 0.1~1.5 0.001 p.u.
alarm
Logic setting of enabling/disabling instantaneous
differential element
7 87R.En_Inst 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling conventional
biased differential element
8 87R.En_Biased 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling DPFC biased
differential element
9 87R.En_DPFC 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling zero-sequence
differential element
10 87R.En_REF 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling block biased
differential element during CT circuit failure
11 87R.En_CTS_Blk 0 or 1
0: disable
1: enable
Tripping logic setting of reactor current differential
protection.
12 87R.OutMap 0000~FFFF The logic setting is shared by the instantaneous
differential element, biased differential element
and DPFC biased differential element.

3.8 Restricted Earth Fault Protection (64REF)

3.8.1 Application

Restricted earth fault protection (REF) is meant to protect a single winding of a power transformer,

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and the protected winding must be earthed. In the case of delta windings, the winding must be
earthed by an earthing transformer, which must be electrically placed between the winding and the
current transformers. REF can be applied to protection of two-winding transformer, three-winding
transformer or auto-transformer.

REF is a kind of differential protection, so it calculates differential current and restrained current.
The differential current is a vector difference of the neutral current (i.e., current flowing in the
neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF operates on the fault current only, and is not dependent
on eventual load currents. This makes REF a very sensitive protection.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.8.2 Function Description


3.8.2.1 Overview

The difference between current differential protection and REF is that the first one is based on
adjusted phase current balance and the latter is based on balance of calculated residual current
and residual current from neutral CT.

Three groups of REF are for each side of a three-winding transformer at most. REF is not affected
by inrush current and the tap of transformer. CT Transient detection function based on the ratio of
residual current to positive current is adopted to eliminate the influence of difference of transient
characteristic to REF.
*

HV side I_H LV side


*
*

3I0Cal'_H

Magnitude compensation

I'_HNP *
REF at HV side I_HNP

Figure 3.8-1 Application for two-windings transformer with one CB at one side

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HV side 1

* * *

I_H1
LV side

I_H2
3I0Cal'_H1 3I0Cal'_H2 * * *

HV side 2

Magnitude
*
compensation
REF at HV side I_HNP
Magnitude
compensation

Magnitude
compensation
I'_HNP

Figure 3.8-2 Application for two-windings transformer with two CBs at one side

HV side

* * *
I_H

3I0Cal'_H I_M
*

MV side CW side
*
*

3I0Cal'_M
*
I_CW
Magnitude
LV side

compensation
REF at HV side
Magnitude
compensation

I'_CW
Magnitude
compensation

Figure 3.8-3 Application for auto-transformer

Maximum 4 group of CTs and 1 neutral point CT inputs for REF, and the maximum current inputs
applied for an auto-transformer with two circuit breakers at HV and MV sides respectively.

NOTICE!

The symbol “*” represents the polarity of CT. If current flowing into the polarity of CT, the
current direction is defined as positive direction. Three phase currents and neutral point
current of a three-phase winding are used to calculate REF. Polarity of three-phase CT

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is at busbar side, and the default polarity of neutral point CT is at transformer side as
shown in Figure 3.8-1, Figure 3.8-2 and Figure 3.8-3. It is should be noted that the
definition of CT polarity is different with other differential protection of transformer.

DANGER!

Before REF of a side is put into service on site, polarity of neutral point CT must have
been checked by a primary injection test. Otherwise an undesired operation may occur
during an external earth fault.

3.8.2.2 Fault Detector

REF's pickup criterion is:

I0d>[x.64REF.I_Biased] Equation 3.8-1

Where:

I0d is the residual differential current of some side.

3.8.2.3 Amplitude Compensation

If CTs used for REF have different primary rated values, the device will automatically adjust the
currents with respective correction ratio shown as below.

I1n I1n _ max


K lph   K lb and K  min( ,4) Equation 3.8-2
I1n _ max lb
I1n _ min

Where:

K1ph is the correction coefficient of the calculated side.

I1n is CT primary rated value at calculated side.

I1n_min is minimum primary rated value among all CTs for REF.

I1n_max is maximum primary rated value among all CTs for REF.

This calculation method is to take the minimum CT primary rated value of all calculated sides as
the reference side. If the multiple of maximum CT primary rated value to minimum CT primary
rated value is greater than 4, then reference side shall be taken as 4 and other sides shall be
calculated proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be
calculated proportionally.

The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (K1ph).

3.8.2.4 Calculate Differential and Restraint Current

The equation of calculating residual differential current is:

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I0d  K lph1  I01 / I 2n _ CT1  K lph2  I02 / I 2n _ CT 2  K lph3  I03 / I 2n _ CT 3  K lph4  I04 / I 2n _ CT 4  K lphNP I NP / I 2n _ CTNP
          
1 2 3 4 5

The above equation can be simplified to the following:

  I 02
I 0d  I 01   I 03
  I 04
  I NP Equation 3.8-3

Where:

I0d is the residual differential current.

I01, I02, I03, I04 are secondary values of calculated residual current at each side.

INP is secondary current at neutral point.

I'01, I'02, I'03, I'04 are secondary values of corrected calculated residual current at each side.

I'NP is the secondary corrected current at neutral point.

K1ph1, K1ph2, K1ph3, K1ph4 are corrected coefficients of amplitude compensation at each side.

K1phNP is corrected coefficient of amplitude compensation at neutral point.

I2n_CT1, I2n_CT2, I2n_CT3, I2n_CT4 are CT rated secondary values at each side.

I2n_CTNP is CT rated secondary value at neutral point.

The equation of calculating residual restraint current is:

 , I02
I0r  max{ I01  , I03
 , I04
 , I0 NP } Equation 3.8-4

Where:

I0r is the residual restraint current.

Ia
*

A
Ib
*

B
Ic
*

C
*

I_NP

3I0Cal' =I'c+I'b+I'a

I'_NP REF

Figure 3.8-4 REF principle

1. Through-flowing current under undisturbed conditions or external fault:

I_NP' flows into the protected zone from ground, 3I0Cal' leaves the protected zone, i.e. is

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positive according to the definition of signs in above figure, therefore I_NP'= 3I0Cal'.

I0d=|3I0Cal'–I_NP'|=|3I0Cal'–3I0Cal'|=0

I0r=Max(|3I0Cal'|, |I_NP'|)=|3I0Cal'|

No differential current, but restraint current corresponds to the through-flowing current, hence,
REF does not operate.

2. Internal short-circuit:

The following applies I_NP'=–3I0Cal', moreover |I_NP'|=|3I0Cal'|

3I0d=|3I0Cal'–I_NP'|=|3I0Cal'–(–3I0Cal')|=2x|3I0Cal'|

3I0r=Max(|3I0Cal'|, |I_HNP)=Max(|3I0Cal'|, |3I0Cal'|)=|3I0Cal'|

Differential current are two times of restraint current and corresponding to the total fault, hence,
REF operates.

3.8.2.5 Operation Criterion

The operation criteria of REF protection are as follows:

Equation 3.8-5

Where:

is the differential current at side x of transformer.

is the restraint current at side x of transformer.

, , , are the calculated residual currents at side x of transformer.

is the residual current from neutral point CT at side x of transformer.

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3.8.2.6 Operation Characteristic

Differential current
K=m

[x.64REF.Slope]

[x.64REF.I_Biased]
Restraint current

[x.64REF.I_Knee]

Figure 3.8-5 Operation characteristic of REF

The value of m is defined by the branch number for REF calculation. For example, there are two
branches at HV side (wye winding with neutral point earthed), so there are three branches
constitute REF of HV side and m is equal to 3.

3.8.2.7 CT Transient Characteristic Difference Detection

Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and
three-phase faults, the unbalance of three-phase CTs results in residual current which may lead to
maloperation of RFE. Therefore, positive-sequence current restraint blocking criterion is adopted
to prevent REF from maloperation in above mentioned conditions.

When the residual current of REF at each side is greater than 0 times positive-sequence current,
it is decided that zero-sequence current is caused by a fault and release REF. Positive-sequence
current restraint blocking criterion is showed below.

I0>β0×I1 Equation 3.8-6

Where:

I0 is the zero-sequence current at a side.

I1 is its corresponding positive-sequence current.

β0 is a proportional constant and the value is 0.6

3.8.2.8 CT Saturation Detection

CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid
maloperation of REF during an external fault. Please refer to Section 3.6.2.10 for details.

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3.8.2.9 CT Circuit Supervision

CT circuit supervision for REF is divided into two kinds: differential CT circuit abnormality without
the pickup of the fault detector and differential CT circuit failure with the pickup of the fault detector.

3.8.2.9.1 CT Circuit Abnormality

If the following operation formula is met for 10s, CT circuit abnormality alarm of REF will be issued
without blocking the protection.

The operation formula is as follows:

I0d>Max(0.2×[x.64REF.I_Biased], 0.1In) Equation 3.8-7

3.8.2.9.2 CT Circuit Failure

Please refer to Section 3.6.2.12 for details.

3.8.3 Function Block Diagram

64REF

x.64REF.I3P1 x.64REF.St

x.64REF.I3P2 x.64REF.On

x.64REF.I3P3 x.64REF.Op

x.64REF.I3P4 x.64REF.Alm_Diff

x.64REF.I1P x.64REF.Alm_CTS

x.64REF.En1

x.64REF.En2

x.64REF.Blk

3.8.4 I/O Signals


Table 3.8-1 I/O signals of restricted earth-fault protection

No. Input signal Description


Three-phase current data input 1 for restricted earth fault protection at side x of of
1 x.64REF.I3P1
transformer.
Three-phase current data input 2 for restricted earth fault protection at side x of of
2 x.64REF.I3P2
transformer.
Three-phase current data input 3 for restricted earth fault protection at side x of of
3 x.64REF.I3P3
transformer.
Three-phase current data input 4 for restricted earth fault protection at side x of of
4 x.64REF.I3P4
transformer.
Residual current data input for restricted earth fault protection at side x of of
5 x.64REF.I1P
transformer.

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No. Input signal Description


Input signal 1 of enabling restricted earth fault protection at side x of of transformer.
6 x.64REF.En1
It is triggered from binary input or programmable logic etc.
Input signal 2 of enabling restricted earth fault protection at side x of of transformer.
7 x.64REF.En2
It is triggered from binary input or programmable logic etc.
Input signal of blocking restricted earth fault protection at side x of of transformer. It
8 x.64REF.Blk
is triggered from binary input or programmable logic etc.
No. Output signal Description
1 x.64REF.St Restricted earth-fault protection at side x of transformer starts.
2 x.64REF.On Restricted earth-fault protection at side x of transformer is enabled.
3 x.64REF.Op Restricted earth-fault protection at side x of transformer operates.
Differential current of restricted earth-fault protection at side x of transformer is
4 x.64REF.Alm_Diff
abnormal.
CT secondary circuit of restricted earth-fault protection at side x of transformer is
5 x.64REF.Alm_CTS
abnormal.
Restricted earth-fault protection at side x of transformer picks up to trigger DFR
6 x.64REF.TrigDFR
function.

3.8.5 Logic

SIG I0d>[x.64REF.I_Biased] &


x.64REF.St
EN [x.64REF.En] &
x.64REF.On
SIG x.64REF.En1
&
SIG x.64REF.En2

SIG x.64REF.Blk

SIG Flag_x.64REF &

SIG I0>β0×I1
&
SIG CT saturation

SIG CT circuit failure &

EN [x.64REF.En_CTS_Blk]
&
SIG x.3I0Ext>0.04In >=1 & [x.64REF.t_Op] 0ms x.64REF.Op

EN [x.64REF.En_NPCurr]

SIG x.64REF.FD 0ms 500ms

Figure 3.8-6 Logic diagram of restricted earth fault protection

Where:

“Flag_x.64REF” means that operation criterion of REF at side x is satisfied.

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x.3I0Ext is the measured residual current at side x.

“x.64REF.FD” means that the fault detector of REF at side x picks up.

3.8.6 Settings
Table 3.8-2 Settings of restricted earth fault protection

No. Item Range Step Unit Description


Knee point setting of REF
1 x.64REF.I_Knee 0.1~4 0.001 In
0.5In is recommended.
2 x.64REF.I_Biased 0.05~5 0.001 In Pickup setting of REF
Percentage restraint coefficient of REF
3 x.64REF.Slope 0.2~0.75 0.001
0.5 is recommended.
Time delay for REF
4 x.64REF.t_Op 0~20 0.001 s
Recommended value is zero.
Logic setting of enabling/disabling block REF
during CT circuit failure
5 x.64REF.En_CTS_Blk 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling neutral
current criterion
6 x.64REF.En_NPCurr 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling REF
7 x.64REF.En 0 or 1 0: disable
1: enable
8 x.64REF.OutMap 0000~FFFF Tripping logic setting of REF

3.9 Winding Differential Protection (87W)

3.9.1 Application
When each side and common winding of auto-transformer are installed with three phase CTs,
winding differential protection can be equipped. Winding differential protection is based on
Kirchhoff's law, so inrush current has no effect on it. Winding differential protection consists of
phase winding differential protection and residual winding differential protection. Residual winding
differential protection adopts the calculated residual current of each side and common winding for
the protection calculation and three-phase CT polarity is easy to be checked. The operation
principle of which is similar to that of REF, but compared to REF, winding differential protection can
operate not only during internal earth faults but also during phase-to-phase faults.

3.9.2 Function Description


3.9.2.1 Overview

Winding differential protection is based on Kirchhoff's first law and calculates differential currents

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of electrical connection circuits including phase A, phase B phase C and residual differential
currents. Inrush current and tap change of the transformer have no effect on winding differential
protection. Winding differential protection has high sensitivity to internal earth faults because there
is no load current in the restraint current. Normally, winding differential protection is applied in
following two situations.

HV side
* * *
I_H

I_M
I'_H

*
MV side
*
CW side
*

I'_M
I_CW
Magnitude
LV side
compensation Winding
* * *
differential
Magnitude protection
compensation

Magnitude I'_CW
compensation

Figure 3.9-1 Winding differential protection applied to auto-transformer

HV side 1
* * * I_Bush
*

I_H1
LV side
*

HV side
*

I_H2
* * *
I'_H1
I'_H2 HV side 2

Magnitude
compensation Winding differential
protection
Magnitude
compensation

Magnitude
compensation
I'_HBush

Figure 3.9-2 Winding differential protection applied to stub differential protection

Where:

I_HBush is primary current value of bushing CT at HV side

I'_HBush is secondary current value of bushing CT at HV side

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DANGER!

When winding differential protection is used as stub differential protection, CT polarity


must be checked. If CT polarity at CB side and bushing CT polarity at some side of a
transformer are both at busbar side, either of them must be reversed by PCS-Explorer.

3.9.2.2 Fault Detector

The criterion of fault detector of winding differential protection is as follows.

Iwd>[87W.I_Biased] Equation 3.9-1

Where:

Iwd is winding differential current.

3.9.2.3 Amplitude Compensation

If CTs used by winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically with parameters input. Following gives
the criteria of calculating correction coefficient.

I1n
K wph   K wb
I1n _ max
Equation 3.9-2
I1n _ max
K wb  min( ,4)
I1n _ min

Where:

Kwph is the correction coefficient of the calculated CT input.

I1n is the primary value of CT at calculated CT input.

I1n_min is the minimum value among primary values of all CTs for winding differential protection.

I1n_max is the maximum value among primary values of all CTs for winding differential protection.

This calculation method is to take the minimum CT primary rating of all calculated CT inputs as the
reference. If the multiple of the maximum CT primary ratio to the minimum CT primary rating is
greater than 2.95, then reference shall be taken as 2.95 and others shall be calculated
proportionally. Otherwise, the reference shall be taken as 1, and others will be calculated
proportionally.

The currents used in the following analysis have been corrected, which means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (Kwph).

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3.9.2.4 Calculate Differential and Restraint Current

The differential current is as follows.

 I wdA   I A1   I A2   I A3 
       
I
 wdB   K I I I
  B1  / I 2n _ CT1  K wph2   B 2  / I 2n _ CT 2  K wph3   B3  / I 2n _ CT 3 
 I wdC  wph1  IC1  IC 2   IC 3 
       
 I wd 0   I 01  I 02   I 
  03 
1 2 3
Equation 3.9-3
 I A4   I A5 
   
I B4  I
K wph4   / I 2n _ CT 4  K wph5   B5  / I 2n _ CT 5
IC 4   IC 5 
   
 I   I 
04  05 
4 5

The above equation can be simplified to the following:

Equation 3.9-4

The restraint current is:

Equation 3.9-5

Where:

IwdA, IwdB, IwdC, Iwd0 are respectively three phase and residual winding differential currents.

IAn, IBn, ICn, I0n are respectively secondary values of three phase currents and calculated neutral
current of branch m (m=1, 2, 3, 4, 5).

I'An, I'Bn, I'Cn, I'0n are respectively secondary values of corrected three phase currents and
calculated residual current of branch m (m=1, 2, 3, 4, 5).

Kwph1, Kwph2, Kwph3, Kwph4, Kwph5 are corrected coefficients of each side for magnitude compensation
respectively.

I2n_CT1, I2n_CT2, I2n_CT3, I2n_CT4, I2n_CT5 are respectively rated secondary values of CTs of each
branch.

IwrA, IwrB, IwrC, Iwr0 are secondary values of three phase restraint currents and neutral restraint
current respectively.

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3.9.2.5 Operation Criterion

The operation criteria of winding differential protection is as follows, and maximum 5 branches are
supported for the calculation.

Equation 3.9-6

Where:

Iw1, Iw2, Iw3, Iw4, Iw5 are currents of five branches respectively.

Iwd is winding differential current.

Iwr is winding restraint current.

NOTICE!

For protecting an autotransformer, a winding differential protection is composed of


three-phase currents of HV side, LV side and common winding. When calculated
residual currents of each branch are used for the calculation, the winding differential
protection (87W) becomes neutral differential protection (87N) also called residual
differential protection in the following description.

3.9.2.6 Operation Characteristic


Differential current

K=m

[87W.Slope]

[87W.I_Biased]
Restraint current
[87W.I_Knee]

Figure 3.9-3 Operating characteristic of winding differential protection

The value of m is defined by the branch number for winding differential protection. For example,

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winding differential protection is applied for protecting an autotransformer including HV side, MV


side and common winding and m is equal to 3.

3.9.2.7 CT Saturation Detection

CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid
maloperation of winding differential protection during an external fault. Please refer to Section
3.6.2.10 for details.

3.9.2.8 CT Circuit Supervision

3.9.2.8.1 CT Circuit Abnormality

If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.

The operation criterion is as follows:

Iwd>max(0.2×[87W.I_Biased], 0.1In) Equation 3.9-7

Where:

In is CT rated secondary voltage.

3.9.2.8.2 CT Circuit Failure

Please refer to Section 3.6.2.12 for details.

3.9.3 Function Block Diagram

87W

87W.I3P1 87W.St

87W.I3P2 87W.On_PhSeg

87W.I3P3 87W.On_REF

87W.I3P4 87W.Op_PhSeg

87W.I3P5 87W.Op_REF

87W.En1 87W.Alm_Diff

87W.En2 87W.Alm_CTS

87W.Blk

3.9.4 I/O Signals


Table 3.9-1 I/O signals of winding differential protection

No. Input signal Description


1 87W.I3P1 Three-phase current data input 1 for winding differential protection.
2 87W.I3P2 Three-phase current data input 2 for winding differential protection.

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No. Input signal Description


3 87W.I3P3 Three-phase current data input 3 for winding differential protection.
4 87W.I3P4 Three-phase current data input 4 for winding differential protection.
5 87W.I3P5 Three-phase current data input 5 for winding differential protection.
Input signal 1 of enabling winding differential protection. It is triggered from binary
6 87W.En1
input or programmable logic etc.
Input signal 2 of enabling winding differential protection. It is triggered from binary
7 87W.En2
input or programmable logic etc.
Input signal of blocking winding differential protection. It is triggered from binary input
8 87W.Blk
or programmable logic etc.
No. Output signal Description
1 87W.St Winding differential protection starts.
2 87W.On_PhSeg Phase-segregated winding differential protection is enabled.
3 87W.On_REF Restricted earth-fault element of winding differential protection is enabled.
4 87W.Op_PhSeg Phase-segregated winding differential protection operates.
5 87W.Op_REF Restricted earth-fault element of winding differential protection operates.
6 87W.Alm_Diff Differential current of winding differential protection is abnormal.
7 87W.Alm_CTS CT secondary circuit of winding differential protection is abnormal.
8 87W.TrigDFR Winding differential protection picks up to trigger DFR function.

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3.9.5 Logic

SIG 87W.En1
&
SIG 87W.En2

SIG 87W.Blk
&
SIG Iwd>[87W.I_Biased] 87W.St

EN [87W.En]

SIG 87W.En1
&
SIG 87W.En2
&
SIG 87W.Blk
87W.On_PhSeg
EN [87W.En_PhSeg]

SIG 87W.Flag_DIFF
& &
SIG CT Staturation 87W.Op_PhSeg

SIG CT circuit failure &

EN [87W.En_CTS_Blk]

SIG 87W.FD 0ms 500ms

SIG 87W.En1
&
SIG 87W.En2
&
SIG 87W.Blk
87W.On_REF
EN [87W.En_REF]

SIG Flag_PSBlk &

SIG 87W.Flag_DIFF
& &
SIG CT Staturation 87W.Op_REF

SIG CT circuit failure &

EN [87W.En_CTS_Blk]

SIG 87W.FD 0ms 500ms

Figure 3.9-4 Logic diagram of winding differential protection

Where:

“87W.Flag_DIFF” means that the operation criterion of winding differential protection is satisfied.

“87W.FD” means that the fault detector of winding differential protection picks up.

“Flag_PSBlk” means that the operation criterion of positive-sequence blocking is satisfied.

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3.9.6 Settings
Table 3.9-2 Settings of winding differential protection

No. Item Range Step Unit Description


Knee point setting of biased winding differential
1 87W.I_Knee 0.1~4 0.001 In
protection.
Pickup setting of biased winding differential
2 87W.I_Biased 0.05~5 0.001 In
protection
Percentage restraint coefficient of biased
3 87W.Slope 0.1~0.9 0.001
winding differential protection
Logic setting of enabling/disabling blocking
winding differential protection during CT circuit
4 87W.En_CTS_Blk 0 or 1 failure
0: disable
1: enable
Logic setting of enabling/disabling phase winding
differential protection.
5 87W.En_PhSeg 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling winding
differential protection.
6 87W.En_REF 0 or 1
0: disable
1: enable
Tripping logic setting of winding differential
7 87W.OutMap 0000~FFFF
protection

3.10 Inter-turn Fault Protection (21IT)

3.10.1 Application

Shunt reactors as the key equipment are widely applied in extra-high voltage and ultra-high
voltage level power system, which has a dominate effect on safe operation of the power system.
The inter-turn fault is a common internal fault occurred in reactor, but current differential protection
cannot operate during inter-turn faults. Considering earth fault protection cannot be taken as the
fast protection for inter-turn faults, a dedicated protection for inter-turn protection of reactor is
needed to be equipped.

Inter-turn faults in reactors present a formidable challenge to the protection engineer. The current
and voltage changes encountered during an inter-turn fault can be of similar magnitude as load
variation, and therefore, sensitive, reliable protection schemes should be considered.

3.10.2 Function Description


Inter-turn fault protection consists of zero-sequence power direction element and zero-sequence
impedance element. They can improve sensitivity and ensure the device against maloperation

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during external faults, transient process (such as series compensated lines, LC resonance, power
swing etc.) or abnormal conditions (such as pole disagreement, CT secondary circuit failure, etc.)

Inter-turn fault protection adopts the current from CT at line side of reactor. The amplitude of
residual voltage is compensated to ensure zero-sequence power direction element can distinguish
direction correctly when system impedance is too low. Inter-turn fault protection will be blocked
during CT and VT circuit failure.

3.10.2.1 Fault Detector

DPFC inter-turn fault detector will enable inter-turn fault protection, and its operation equation is as
follows.

Equation 3.10-1

Where:

is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold ( ) is higher than the change of current under these conditions and
hence the element maintains stability.

and are DPFC current of two ends of reactor representatively.

is DPFC differential current.

is the fixed threshold and the value is 0.2p.u..

3.10.2.2 Residual Power Direction Element

The wiring diagram of shunt reactors in power system is shown as Figure 3.10-1.

F1
AC1 Zs1 ZL Zs2 AC2

* Relay 1 Relay 2 *

Zr1 Zr2 F2

Shunt reactor 1 Shunt reactor 2

Figure 3.10-1 Wiring diagram of shunt reactors in power system

Where:

AC1, AC2: equivalent voltage source

Zs1, Zs2: equivalent system impedance

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Zr1, Zr2: impedance of shunt reactor

ZL: line impedance

F1: fault point 1

F2: fault point 2

1. F1: External single-phase earth fault of line (close-up external earth fault)

The fault point is zero-sequence power source, the equivalent zero-sequence network is shown
below.

Zs' U0 Zr2

I0
Fault PS

Figure 3.10-2 Equivalent zero-sequence network for F1

Where:

Zs': equivalent system impedance, Zs'=(Zr1//Zs1+ ZL)//Zs2

U0: relay detected zero sequence voltage

I0: relay detected zero sequence current

FaultPS: fault power source

It is an external earth fault, so viewing from the device location, zero-sequence current flows to
reactor from reactor grounding point and via transmission line back to the ground at the earth fault
point. Therefore, the equation between U0 and I0 at the relay location is: U0=I0xZr2.

Vector relation between U0 and I0 is:

U0

I0

Figure 3.10-3 Vector relation for F1

2. F2: Internal inter-turn fault

Because of the fault point in reactor, the equivalent zero-sequence network is shown below.

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Z's Zr2-1 Zr2-2


U0

I0 Fault PS

Figure 3.10-4 Equivalent zero-sequence network for F2

Where:

Z's: equivalent system impedance, Z's=(Zr2//Zs2+ ZL)//Zs2

Zr2-1: impedance of Zr2 part 1

Zr2-2: impedance of Zr2 part 2

U0: detected zero-sequence voltage by the device

I0: detected zero-sequence current by the device

Fault PS: fault power source

It is an internal inter-turn fault, so viewing from reactor relay location, zero-sequence current flows
from reactor to ground through system reactance. Therefore, the equation between U0 and I0 at
the device location is: U0=-I0xZ's.

Vector relation between U0 and I0 is

I0

U0

Figure 3.10-5 Vector relation for F2

The phase angle of residual current leading residual voltage is nearly 90°if an inter-turn fault of
reactor winding occurs. The residual current phase leads the residual voltage phase if an internal
single-phase earth fault occurs, and the residual current phase lags the residual voltage phase if
an external single-phase earth fault occurs. Therefore, the phase angle between residual current
and residual voltage can be used to distinguish internal faults from external faults. The
zero-sequence impedance of system very small compared to reactor impedance, so the residual
voltage detected by the device will not be sensitive to operate and need to be compensated.

The operation criterion of residual power direction element is:

Equation 3.10-2

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Where:

and are respectively calculated residual voltage and calculated residual current from VT
and CT at the line side of reactor.

is the zero-sequence impedance of reactor including neutral earthing reactor, i.e.,


[21I.Zn_Reac_NP].

k is the floating coefficient adaptive to variation of zero-sequence voltage and current from 0 to
0.8.

3.10.2.3 Zero-sequence Impedance Element

Zero-sequence impedance of reactor is usually thousands of ohms which is greater than system
impedance. When an inter-turn fault or internal single-phase earth fault of reactor occurs, the
impedance detected by the device is exactly the zero-sequence impedance of system. If an
external single-phase fault of reactor occurs, the impedance detected by the device is the
zero-sequence impedance of reactor. According to different values of measured impedances,
inter-turn faults (or internal fault) and external earth faults can be distinguished.

Operation criterion:

Zm<0.25xZ0 Equation 3.10-3

Where:

Zm is measured zero-sequence impedance.

Z0 is zero-sequence impedance of reactor.

NOTICE!

When VT abnormality (including star line of VT is not connected) is detected, the


operation criteria of residual power direction element and zero-sequence impedance
element are not satisfied, which implies that inter-turn fault protection is out of service.

When CT abnormality at line side is detected, the operation criteria of residual power
direction element and zero-sequence impedance element are not satisfied, which
implies that inter-turn fault protection is out of service.

21IT

21IT.I3P 21IT.St

21IT.U3P 21IT.On

21IT.En1 21IT.Op

21IT.En2

21IT.Blk

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3.10.3 I/O Signals


Table 3.10-1 I/O signals of inter-turn protection

No. Input signal Description


1 21IT.I3P Three-phase current data input for inter-turn fault protection.
2 21IT.U3P Three-phase voltage data input for inter-turn fault protection.
Input signal 1 of enabling inter-turn fault protection. It is triggered from binary input or
3 21IT.En1
programmable logic etc.
Input signal 2 of enabling inter-turn fault protection. It is triggered from binary input or
4 21IT.En2
programmable logic etc.
Input signal of blocking inter-turn fault protection. It is triggered from binary input or
5 21IT.Blk
programmable logic etc.
No. Output signal Description
1 21IT.St Inter-turn fault protection starts.
2 21IT.On Inter-turn fault protection is enabled.
3 21IT.Op Inter-turn fault protection operates.
4 21IT.TrigDFR Inter-turn fault protection picks up to trigger DFR function.

3.10.4 Logic

EN [21IT.En]
&
SIG 21IT.En1
&
SIG 21IT.En2
21IT.On
SIG 21IT.Blk

SIG Flag_ZSImpedance &


& &
SIG FwdDir_ROC 21IT.Op

SIG Alm_VTS &

&
SIG AlmL_CTS
21IT.St
SIG 21IT.FD_DPFC 0ms 500ms

Figure 3.10-6 Logic diagram of inter-turn fault protection

Where:

“Flag_ZSImpedance” means that zero-sequence impedance element operates.

“FwdDir_ROC” means that zero-sequence power direction element operates.

21IT.FD_DPFC means that DPFC inter-turn fault detector operates.

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3.10.5 Settings
Table 3.10-2 Settings of inter-turn fault protection

No. Item Range Step Unit Description


Logic setting of enabling/disabling
inter-turn fault protection
1 21IT.En 0 or 1
0: disable
1: enable
Tripping logic setting of inter-turn
2 21IT.OutMap 0000~FFFF
fault protection

3.11 Overexcitation Protection (24)

3.11.1 Application
Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such condition may occur when a unit is on load, but are more likely to arise when it is
on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are
in particular danger to experience overexcitation condition.

During overexcitation, field current of transformer rises greatly to cause excessive heating and
severe damage. The transformer, working magnetic flux density near the knee point, is subject to
overexcitation. Frequency range for normal operation is 45~55Hz for 50Hz working frequency of
power system and 55~65Hz for 60Hz working frequency of power system.

Overexcitation protection can be configured at any side of transformer through PCS-Explorer, and
it is recommended to be equipped at the side without OLTC.

3.11.2 Function Description


Overexcitation protection consists of two stages definite-time overexcitation protection and one
stage inverse-time overexcitation protection for trip purpose or alarm purpose. The voltage for
protection calculation is RMS of three phase voltages and not affected by frequency fluctuation.
Overexcitation inverse-time curve is sectional linear curve, which has high adaptability.

The overexcitation degree can be reflected by overexcitation multiple which is calculated by


voltage and frequency, according to the following equation.

n=U*/f* Equation 3.11-1

Where:

U* and f* are per unit value of voltage and frequency respectively.

The base value for calculating per unit value of voltage is secondary voltage corresponding to
primary voltage of one side of transformer, and the base value for calculating per unit value of
frequency is rated frequency. Hence, under normal operation, n should be equal to 1.

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For example, overexcitation protection is equipped at HV side, primary voltage of HV side is


525kV (i.e., [HVS.U1n_Tr]=525kV) and voltage transformer ratio is 500kV/100V. The base value
for calculating per unit value of voltage is equal to:

This base voltage calculation is carried out in the device and users need not calculate VT ratio
when configure settings.

1. Definite-time operation criterion:

U*/f*>[24DTn.K_Set] Equation 3.11-2

Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on


given inverse-time operation characteristic, obtaining overexcitation multiple by calculation, and
getting the corresponding time delay by sectional linear insertion. It reflects the heat accumulation
and radiation.

Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of various transformers.

Following figure shows inverse-time characteristic of overexcitation protection.

U*/f*

n0

n1
n2
n3
n4
n5
n6
n7
n8
n9

t (s)
0 t0 t1t2 t3 t4 t5 t6 t7 t8 t9

Figure 3.11-1 Inverse-time characteristic of overexcitation protection

The main harm of overexcitation to transformer is overheat, so accumulation method is adopted


and accumulate the time delay according to curve time corresponding to calculated overexcitation
multiple. When accumulated time delay is greater than the operating time delay, inverse-time
overexcitation protection operates. Dissipating process is also simulated, when overexcitation
multiple is less than the minimum overexcitation multiple setting, the accumulated value
decreases to 0 gradually. If overexcitation protection operates and overexcitation condition
disappears, thermal accumulation value decreases to 0 in 10s.

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Overexcitation multiple comprises overexcitation information at current instant and also


overexcitation information integrated over various time intervals from its beginning.

Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation among various settings of n and t are:

3.11.3 Function Block Diagram

24DT1

24DT1.OvExc 24DT1.St

24DT1.En1 24DT1.On

24DT1.En2 24DT1.Op

24DT1.Blk

24DT2

24DT2.OvExc 24DT2.St

24DT2.En1 24DT2.On

24DT2.En2 24DT2.Alm

24DT2.Blk

24IDMT

24IDMT.OvExc 24IDMT.St

24IDMT.En1 24IDMT.On

24IDMT.En2 24IDMT.Op

24IDMT.Blk 24IDMT.Alm

3.11.4 I/O Signals


Table 3.11-1 I/O signals of overexcitation protection

No. Input signal Description


Measurement data (including frequency and voltage) required by stage n of
1 24DTn.OvExc
definite-time overexcitation protection. (n=1, 2)
Input signal 1 of enabling stage n of definite-time overexcitation protection. It is
2 24DTn.En1
triggered from binary input or programmable logic etc. (n=1, 2)
Input signal 2 of enabling stage n of definite-time overexcitation protection. It is
3 24DTn.En2
triggered from binary input or programmable logic etc. (n=1, 2)

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No. Input signal Description


Input signal of blocking stage n of definite-time overexcitation protection. It is
4 24DTn.Blk
triggered from binary input or programmable logic etc. (n=1, 2)
Measurement data (including frequency and voltage) required by inverse-time
5 24IDMT.OvExc
overexcitation protection.
Input signal 1 of enabling inverse-time overexcitation protection. It is triggered from
6 24IDMT.En1
binary input or programmable logic etc.
Input signal 2 of enabling inverse-time overexcitation protection. It is triggered from
7 24IDMT.En2
binary input or programmable logic etc.
Input signal of blocking inverse-time overexcitation protection. It is triggered from
8 24IDMT.Blk
binary input or programmable logic etc.
No. Output signal Description
1 24DT1.St Stage 1 of definite-time overexcitation protection starts.
2 24DT1.On Stage 1 of definite-time overexcitation protection is enabled.
3 24DT1.Op Stage 1 of definite-time overexcitation protection operates to trip.
4 24DT2.St Stage 2 of definite-time overexcitation protection starts.
5 24DT2.On Stage 2 of definite-time overexcitation protection is enabled.
6 24DT2.Alm Stage 2 of definite-time overexcitation protection operates to alarm.
7 24IDMT.St Inverse-time overexcitation protection starts
8 24IDMT.On Inverse-time overexcitation protection is enabled.
9 24IDMT.Op Inverse-time overexcitation protection operates to trip.
10 24IDMT.Alm Inverse-time overexcitation protection operates to alarm.
11 24DT1.TrigDFR Stage 1 of definite-time overexcitation protection picks up to trigger DFR function.
12 24DT2.TrigDFR Stage 2 of definite-time overexcitation protection picks up to trigger DFR function.
13 24DTIDMT.TrigDFR Inverse-time overexcitation protection picks up to trigger DFR function.

3.11.5 Logic

SIG 24DT1.En1
&
SIG 24DT1.En2 &
24DT1.On
SIG 24DT1.Blk
&
EN [24DT1.En]
[24DT1.t_Op] 0ms 24DT1.Op
SIG U*/f*>[24DT1.K_Set]
24DT1.St
SIG 24DT2.En1
&
SIG 24DT2.En2 &
24DT2.On
SIG 24DT2.Blk
&
EN [24DT2.En]
[24DT2.t_Op] 0ms 24DT2.Alm
SIG U*/f*>[24DT2.K_Set]
24DT2.St

Figure 3.11-2 Logic diagram of definite-time overexcitation protection

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SIG 24IDMT.En1
&
SIG 24IDMT.En2 &
24IDMT.On
SIG 24IDMT.Blk
24IDMT.St
EN [24IDMT.En]
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT 24IDMT.Op

EN [24IDMT.En_Trp]
&
SIG U*/f*>[24IDMT.K_Alm] & IDMT 24IDMT.Alm

EN [24IDMT.En_Alm]

Figure 3.11-3 Logic diagram of inverse-time overexcitation protection

3.11.6 Settings
Table 3.11-2 Settings of overexcitation protection

No. Item Range Step Unit Description


It is used to set reference voltage of
overexcitation calculation, and it is
1 24.Un 0~2000 0.001 kV
usually set as primary rated voltage
at calculated side of transformer
Voltage option between phase
voltage and phase-to-phase voltage
for calculation of overexcitation
2 24.Opt_Up/Upp 0, 1 1
protection
0: phase voltage
1: phase-to-phase voltage
Multiple setting of stage 1 of
3 24DT1.K_Set 1.0~1.7 0.001 definite-time overexcitation
protection for trip purpose
Time delay setting of stage 1 of
4 24DT1.t_Op 0.1~9999 0.001 s definite-time overexcitation
protection for trip purpose
Logic settings of enabling/disabling
stage 1 of definite-time
overexcitation protection for trip
5 24DT1.En 0 or 1
purpose
0: disable
1: enable
Tripping logic settings of stage 1 of
6 24DT1.OutMap 0000~FFFF definite-time overexcitation
protection for trip purpose
7 24DT2.K_Set 1.0~1.7 0.001 Multiple setting of stage 2 of

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No. Item Range Step Unit Description


definite-time overexcitation
protection for alarm purpose
Time delay setting of stage 2 of
8 24DT2.t_Op 0.1~9999 0.001 s definite-time overexcitation
protection for alarm purpose
Logic settings of enabling/disabling
stage 2 of definite-time
overexcitation protection for alarm
9 24DT2.En 0 or 1
purpose
0: disable
1: enable
Highest-limit multiple setting of
10 24IDMT.K0_Set 1.0~1.7 0.001 inverse-time overexcitation
protection: n0
Time delay setting corresponding to
11 24IDMT.t0_Op 0.1~9999 0.001 s
highest-limit setting: t0
Multiple setting 1 of inverse-time
12 24IDMT.K1_Set 1.0~1.7 0.001
overexcitation protection: n1
Time delay setting corresponding to
13 24IDMT.t1_Op 0.1~9999 0.001 s
multiple setting 1: t1
Multiple setting 2 of inverse-time
14 24IDMT.K2_Set 1.0~1.7 0.001
overexcitation protection: n2
Time delay setting corresponding to
15 24IDMT.t2_Op 0.1-9999 0.001 s
multiple setting 2: t2
Multiple setting 3 of inverse-time
16 24IDMT.K3_Set 1.0~1.7 0.001
overexcitation protection: n3
Time delay setting corresponding to
17 24IDMT.t3_Op 0.1~9999 0.001 s
multiple setting 3: t3
Multiple setting 4 of inverse-time
18 24IDMT.K4_Set 1.0~1.7 0.001
overexcitation protection: n4
Time delay setting corresponding to
19 24IDMT.t4_Op 0.1~9999 0.001 s
multiple setting 4: t4
Multiple setting 5 of inverse-time
20 24IDMT.K5_Set 1.0~1.7 0.001
overexcitation protection: n5
Time delay setting corresponding to
21 24IDMT.t5_Op 0.1~9999 0.001 s
multiple setting 5: t5
Multiple setting 6 of inverse-time
22 24IDMT.K6_Set 1.0~1.7 0.001
overexcitation protection: n6
Time delay setting corresponding to
23 24IDMT.t6_Op 0.1~9999 0.001 s
multiple setting 6: t6
Multiple setting 7 of inverse-time
24 24IDMT.K7_Set 1.0~1.7 0.001
overexcitation protection: n7
25 24IDMT.t7_Op 0.1~9999 0.001 s Time delay setting corresponding to

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No. Item Range Step Unit Description


multiple setting 7: t7
Multiple setting 8 of inverse-time
26 24IDMT.K8_Set 1.0~1.7 0.001
overexcitation protection: n8
Time delay setting corresponding to
27 24IDMT.t8_Op 0.1~9999 0.001 s
multiple setting 8: t8
Lowest-limit multiple setting of
28 24IDMT.K9_Set 1.0~1.7 0.001
inverse-time overexcitation: n9
Time delay setting corresponding to
29 24IDMT.t9_Op 0.1~9999 0.001 s
lowest-limit multiple setting: t9
Multiple setting of inverse-time
30 24IDMT.K_Alm 0.5~0.99 0.001 overexcitation protection for alarm
purpose
Logic setting of enabling/disabling
inverse-time overexcitation
31 24IDMT.En_Alm 0 or 1 protection for alarm purpose
0: disable
1: enable
Cooling time of inverse-time
32 24IDMT.t_Cooling 0.1~9999 0.001 s
overexcitation protection
Logic setting of enabling/disabling
inverse-time overexcitation
33 24IDMT.En_Trp 0 or 1 protection for trip purpose
0: disable
1: enable
Tripping logic setting of inverse-time
34 24IDMT.OutMap 0000~FFFF 1
overexcitation protection

NOTICE!

Please input the corresponding values of selected 10 points of overexcitation curve of


transformer to the device and the values of 10 points are distributed averagely.

Inverse-time overexcitation protection is set with reference to the curve given by the
transformer manufactory. The relation among all settings of inverse-time overexcitation
protection is:

[24IDMT.K9_Set]<[24IDMT.K8_ Set]<…<[24IDMT.K1_Set]<[24IDMT.K0_ Set]

[24IDMT.t0_Op]<[ 24IDMT.t1_ Op]<…<[24IDMT.k8_ Op] <[24IDMT.t9_ Op]

3.12 Frequency Protection (81)

3.12.1 Application
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to

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re-balance between power supply and the load. On the contrary, if the power frequency of regional
rises due to the active power excess demand, overfrequency protection operates to perform
generator rejection to shed part of the generators automatically according to the rising frequency
so that power supply and the load are re-balanced.

3.12.2 Function Description


3.12.2.1 Fault Detector

1. Underfrequency protection

The operation criterion is:

f<[81U.f_Pkp] Equation 3.12-1

2. Overfrequency protection

The operation criterion is:

f>[81O.f_Pkp] Equation 3.12-2

Where:

f is the measured system frequency.

3.12.2.2 Blocking Element

1. Underfrequency Protection

In order to prevent possible maloperation of underfrequency protection in conditions of high


harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:

1) undervoltage blocking

If the positive voltage U<0.15Un, underfrequency will be blocked.

2) df/dt blocking

If -df/dt≥[81U.df/dt_Blk], underfrequency protection will be blocked. The blocking will not be


released automatically until the system frequency recovers to be less than the setting [81U.f_Pkp].

3) frequency over-range blocking

If the system frequency is less than the setting [f_low_FreqAlm] or greater than the setting
[f_High_FreqAlm], underfrequency protection will be blocked.

2. Overfrequency Protection

In order to prevent possible maloperation of overfrequency protection in conditions of high


harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:

1) Blocking in undervoltage condition

If the positive voltage U<0.15Un, overfrequency protection will be blocked.

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2) frequency over-range blocking element

If the system frequency is less than the setting [f_low_FreqAlm] or greater than the setting
[f_High_FreqAlm], overfrequency protection will be blocked.

3.12.2.3 Protection Principle

The operation criteria of underfrequency protection and overfrequency protection are shown as
following respectively, and the corresponding protection operates when any criterion is met.

f<[81U.UFx.f_Set] Equation 3.12-3

f>[81O.OFx.f_Set] Equation 3.12-4

Where:

f is the measured system frequency.

3.12.3 Function Block Diagram

81O

81O.U3P 81O.St

81O.Freq 81O.OF1.On

81O.En1 81O.OF2.On

81O.En2 81O.OF3.On

81O.Blk 81O.OF4.On

81O.OF1.Op

81O.OF2.Op

81O.OF3.Op

81O.OF4.Op

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81U

81U.U3P 81U.St

81U.Freq 81U.UF1.On

81U.En1 81U.UF2.On

81U.En2 81U.UF3.On

81U.Blk 81U.UF4.On

81U.UF1.Op

81U.UF2.Op

81U.UF3.Op

81U.UF4.Op

3.12.4 I/O Signals


Table 3.12-1 I/O signals of frequency protection

No. Input signal Description


1 81O.U3P Three-phase voltage data input for overfrequency protection.
2 81O.Freq Measured frequency data input for overfrequency protection.
Input signal 1 of enabling overfrequency protection. It is triggered from binary input
3 81O.En1
or programmable logic etc.
Input signal 2 of enabling overfrequency protection. It is triggered from binary input
4 81O.En2
or programmable logic etc.
Input signal of blocking overfrequency protection. It is triggered from binary input or
5 81O.Blk
programmable logic etc.
6 81U.U3P Three-phase voltage data input for underfrequency protection.
7 81U.Freq Measured frequency data input for underfrequency protection.
Input signal 1 of enabling underfrequency protection. It is triggered from binary
8 81U.En1
input or programmable logic etc.
Input signal 2 of enabling underfrequency protection. It is triggered from binary
9 81U.En2
input or programmable logic etc.
Input signal of blocking underfrequency protection. It is triggered from binary input
10 81U.Blk
or programmable logic etc.
No. Output signal Description
1 81O.St Overfrequency protection starts.
2 81O.OF1.On Stage 1 of overfrequency protection is enabled.
3 81O.OF2.On Stage 2 of overfrequency protection is enabled.
4 81O.OF3.On Stage 3 of overfrequency protection is enabled.
5 81O.OF4.On Stage 4 of overfrequency protection is enabled.
6 81O.OF1.Op Stage 1 of overfrequency protection operates.
7 81O.OF2.Op Stage 2 of overfrequency protection operates.

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No. Input signal Description


8 81O.OF3.Op Stage 3 of overfrequency protection operates.
9 81O.OF4.Op Stage 4 of overfrequency protection operates.
10 81O.TrigDFR Overfrequency protection picks up to trigger DFR function.
11 81U.St Underfrequency protection starts.
12 81U.UF1.On Stage 1 of underfrequency protection is enabled.
13 81U.UF2.On Stage 2 of underfrequency protection is enabled.
14 81U.UF3.On Stage 3 of underfrequency protection is enabled.
15 81U.UF4.On Stage 4 of underfrequency protection is enabled.
16 81U.UF1.Op Stage 1 of underfrequency protection operates.
17 81U.UF2.Op Stage 2 of underfrequency protection operates.
18 81U.UF3.Op Stage 3 of underfrequency protection operates.
19 81U.UF4.Op Stage 4 of underfrequency protection operates.
20 81U.TrigDFR Underfrequency protection picks up to trigger DFR function.

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3.12.5 Logic

SIG 81U.En1
&
SIG 81U.En2 Enable 81U

SIG 81U.Blk

SIG U1<0.15Un >=1

SET -df/dt>[81U.df/dt_Blk]

SET f<[f_low_FreqAlm] >=1 >=1


Block 81U
SET f>[f_High_FreqAlm]

SIG x.In_VT

SET f<[81U.f_Pkp] 50ms 0ms &

SIG Block 81U &

SIG Enable 81U


&
SIG f<[81U.UF1.f_Set] [81U.UF1.t_Op] 0ms 81U.UF1.Op

EN [81U.UF1.En]
&
81U.UF1.On

&
SIG f<[81U.UF2.f_Set] [81U.UF2.t_Op] 0ms 81U.UF2.Op

SIG [81U.UF2.En]
&
81U.UF2.On

&
SIG f<[81U.UF3.f_Set] [81U.UF3.t_Op] 0ms 81U.UF3.Op

EN [81U.UF3.En]
&
81U.UF3.On

&
SIG f<[81U.UF4.f_Set] [81U.UF4.t_Op] 0ms 81U.UF4.Op

EN [81U.UF4.En]
&
81U.UF4.On

Figure 3.12-1 Logic diagram of underfrequency protection

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SIG 81O.En1
&
SIG 81O.En2 Enable 81O

SIG 81O.Blk

OTH U1<0.15Un

SET f<[f_low_FreqAlm] >=1 >=1


Block 81O
SET f>[f_High_FreqAlm]

SIG x.In_VT

SET f>[81O.f_Pkp] 50ms 0ms &

SIG Block 81O &

SIG Enable 81O


&
SET f>[81O.OF1.f_Set] [81O.OF1.t_Op] 0ms 81O.OF1.Op

EN [81O.OF1.En]
&
81O.OF1.On

&
SET f>[81O.OF2.f_Set] [81O.OF2.t_Op] 0ms 81O.OF2.Op

EN [81O.OF2.En]
&
81O.OF2.On

&
SET f>[81O.OF3.f_Set] [81O.OF3.t_Op] 0ms 81O.OF3.Op

EN [81O.OF3.En]
&
81O.OF3.On

&
SET f>[81O.OF4.f_Set] [81O.OF4.t_Op] 0ms 81O.OF4.Op

EN [81O.OF4.En]
&
81O.OF4.On

Figure 3.12-2 Logic diagram of overfrequency protection

3.12.6 Settings
Table 3.12-2 Settings of frequency protection

No. Item Range Step Unit Description


Pickup setting of overfrequency
1 81O.f_Pkp 50~65 0.01 Hz
protection
2 81O.OFn.f_Set 50~65 0.01 Hz Frequency setting of stage n of

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No. Item Range Step Unit Description


overfrequency protection (n=1, 2, 3,
4)
Time delay of stage n of
3 81O.OFn.t_Op 0~6000 0.001 s overfrequency protection (n=1, 2, 3,
4)
Logic setting of enabling/disabling
stage n of overfrequency protection
4 81O.OFn.En 0 or 1 (n=1, 2, 3, 4)
0:disable
1:enable
Tripping logic setting of stage n of
5 81O.OFn.OutMap. 0000~FFFF overfrequency protection (n=1, 2, 3,
4)
Pickup setting of underfrequency
6 81U.f_Pkp 45~60 0.01 Hz
protection
df/dt setting of blocking
7 81U.df/dt_Blk 0.05~20 0.01 Hz/s
underfrequency protection
Frequency setting of stage n of
8 81U.UFn.f_Set 45~60 0.01 Hz underfrequency protection (n=1, 2,
3, 4)
Time delay of stage n of
9 81U.UFn.t_Op 0~6000 0.001 s underfrequency protection (n=1, 2,
3, 4)
Logic setting of enabling/disabling
stage n of underfrequency
10 81U.UFn.En 0 or 1 protection (n=1, 2, 3, 4)
0:disable
1:enable
Logic setting of enabling/disabling
df/dt blocking function for stage n of
underfrequency protection (n=1, 2,
11 81U.UFn.En_df/dt_Blk 0 or 1
3, 4)
0:disable
1:enable
Tripping logic setting of stage n of
12 81U.UFn.OutMap 0000~FFFF underfrequency protection (n=1, 2,
3, 4)

3.13 Impedance Protection (21)

3.13.1 Application
When phase overcurrent protection and earth fault protection cannot meet the sensitivity

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requirement of transformer backup protection, impedance protection may be configured. The


operation mode of power system has little effect on impedance protection, so impedance
protection cooperates with protections of adjacent equipment more easily.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.13.2 Function Description

Impedance protection consists of two stages phase-to-phase impedance elements and two stages
phase-to-ground elements, and power swing blocking releasing function. CT polarity of each side
is at busbar side, and directions settings are based on this polarity.

3.13.2.1 Fault Detector

The fault detector of impedance protection includes the fault detector based on DPFC
phase-to-phase current and the fault detector based on negative-sequence current. Impendence
protection will be enabled for 500ms if any fault detector picks up, and will keep being enabled if
phase-to-phase or phase-to-ground impedance element operates.

1. Fault detector based on DPFC phase-to-phase current

ΔI>1.25ΔIt+Ith Equation 3.13-1

Where:

ΔIt is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold current is slightly
greater than the unbalance current, multiple 1.25 of the deviation component is reasonable.

ΔI is the deviation value of phase-to-phase current.

Ith is the fixed threshold (0.2In).

 Fault detector based on negative-sequence current

I2>0.2In Equation 3.13-2

Where:

I2 is the negative-sequence current.

In is the CT secondary rated current.

3.13.2.2 Phase-to-phase Impedance Element

Figure 3.13-1 shows operating characteristic of phase-to-phase impedance element with relay
characteristic angle [x.21.RCA] (φm).

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jx
Zp

m
R

Zn

Figure 3.13-1 Operating characteristic of phase-to-phase impedance element

Where:

Zn is the reverse impedance setting [x.21.ZP1.Z_Rev] or [x.21.ZP2.Z_Rev] (pointing to system)

Zp is the forward impedance setting [x.21.ZP1.Z_Fwd] or [x.21.ZP2.Z_Fwd] (pointing to


transformer)

The operation criterion of phase-to-phase impedance element is:

Equation 3.13-3

NOTICE!

If VT circuit abnormal message [x.Alm_VTS] is issued or VT is out of service,


impedance protection will be blocked.

3.13.2.3 Phase-to-ground Impedance Element

Figure 3.13-2 shows operating characteristic of phase-to-ground impedance element with relay
characteristic angle [x.21.RCA].

jx
Zp

m
R

Zn

Figure 3.13-2 Operating characteristic of phase-to-ground impedance element

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Where:

Zn is the reverse impedance setting [x.21.ZG1.Z_Rev] or [x.21.ZG2.Z_Rev] (pointing to system)

Zp is the forward impedance setting [x.21.ZG1.Z_Fwd] or [x.21.ZG2.Z_Fwd] (pointing to


transformer)

The operation criterion of phase-to-phase impedance relay is as follows.

Equation 3.13-4

Where:

K=(Z0-Z1)/3Z1 is the zero-sequence compensation coefficient ([x.21.K0]) and recommended value


is 0~2. “k” is generally 0.6 if protection direction points to local busbar, and “k” is 0~0.1, if
protection direction points to transformer.

3.13.2.4 Power Swing Blocking Releasing (PSBR)

PCS-978 adopts releasing power swing blocking to avoid maloperation of impedance protection
resulting from power swing. In another word, in order to avoid unwanted operation of impedance
relay during system oscillation, the protection is blocked all along under the normal condition and
power swing. Only if fault (internal fault or power swing with internal fault) is detected, power swing
blocking for impedance protection is released by PSBR element.

Power swing blocking for impedance element will be released if any of the following PSBR
elements operate.

1. Fault detector PSBR element (FD PSBR)

2. Unsymmetrical fault PSBR element (UF PSBR)

3. Symmetrical fault PSBR element (SF PSBR)

1. Fault detector PSBR element

If any of the following condition is matched, FD PSBR will operate for 160ms.

1) Positive-sequence overcurrent element does not operate (i.e. Equation 3.13-5 is met) at the
moment that one of the fault detectors of impedance protection picks up.

I1<[x.21.I_PSBR] Equation 3.13-5

I1 is positive-sequence current.

2) Positive-sequence overcurrent element operates (i.e. Equation 3.13-6 is met) at the moment
that one of the fault detectors of impedance protection picks up, but the duration of keeping
operating is less than 10ms.

I1>[x.21.I_PSBR] Equation 3.13-6

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2. Unsymmetrical fault PSBR element

The operation criterion:

I 0  I 2  m  I1 Equation 3.13-7

Where:

“m” is the internal fixed coefficient which can ensure UF PSBR operate during power swing with an
internal unsymmetrical fault, while not operate during power swing or power swing with an external
fault.

I1, I2, I0 are positive-sequence current, negative-sequence current and zero-sequence current
respectively.

3. Symmetrical fault PSBR element

If a three-phase fault occurs and FD PSBR is invalid (160ms after fault detector operates), neither
FD PSBR nor UF PSBR will be able to operate to release the distance protection. Thus, SF PSBR
is provided for this case specially. This detection is based on measuring the voltage at power
swing center:

UOS=U1×COSΦ Equation 3.13-8

Where:

Φ: the angle between positive-sequence voltage and positive-sequence current

U1: the positive-sequence voltage

The criterion of SF PSBR element comprises the following two parts:

1) when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.

2) when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.

NOTICE!

If the time delay of impedance protection is more than 1.5s, PSBR function is not
required for impedance protection.

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3.13.3 Function Block Diagram

21

x.21.I3P x.21.St

x.21.U3P x.21.ZP1.On

x.21.En1 x.21.ZP2.On

x.21.En2 x.21.ZG1.On

x.21.Blk x.21.ZG2.On

x.21.ZP1.Op

x.21.ZP2.Op

x.21.ZG1.Op

x.21.ZG2.Op

3.13.4 I/O Signals


Table 3.13-1 I/O signals of impedance protection

No. Input signal Description


1 x.21.I3P Three-phase current data input for impedance protection at side x of transformer.
2 x.21.U3P Three-phase voltage data input for impedance protection at side x of transformer.
Input signal 1 of enabling impedance protection at side x of transformer. It is
3 x.21.En1
triggered from binary input or programmable logic etc.
Input signal 2 of enabling impedance protection at side x of transformer. It is
4 x.21.En2
triggered from binary input or programmable logic etc.
Input signal of blocking impedance protection at side x of transformer. It is triggered
5 x.21.Blk
from binary input or programmable logic etc.
No. Output signal Description
1 x.21.St Impedance protection at side x of transformer starts.
Stage n of phase-to-phase impedance protection at side x of transformer is
2 x.21.ZPn.On
enabled. (n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer is
3 x.21.ZGn.On
enabled. (n=1, 2)
Stage n of phase-to-phase impedance protection at side x of transformer operates.
4 x.21.ZPn.Op
(n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer
5 x.21.ZGn.Op
operates. (n=1, 2)
Stage n of phase-to-phase impedance protection at side x of transformer picks up
6 x.21.ZPn.TrigDFR
to trigger DFR function. (n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer picks up
7 x.21.ZGn.TrigDFR
to trigger DFR function. (n=1, 2)

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3.13.5 Logic

SIG UF PSBR >=1

SIG SF PSBR
>=1
SET I1>[x.21.I_PSBR] 10ms 0 &
0 160ms
SIG x.21.FD

>=1

EN [x.21.En_PSBR]
&
SIG Flag_ZPn x.21.ZPn.On

EN [x.21.ZPn.En]
&
SIG x.21.En1
&
SIG x.21.En2

SIG x.21.Blk
& x.21.St
SIG x.Alm_VTS >=1 &
[x.21.ZPn.t_Op] 0s x.21.ZPn.Op
SIG x.In_VT

SIG x.21.FD 0 500ms

SIG UF PSBR >=1

SIG SF PSBR
>=1
SET I1>[x.21.I_PSBR] 10ms 0 &
0 160ms
SIG x.21.FD

>=1

EN [x.21.En_PSBR]
&
SIG Flag_ZGn x.21.ZGn.On

EN [x.21.ZGn.En]
&
SIG x.21.En1
&
SIG x.21.En2

SIG x.21.Blk
&
x.21.St
SIG x.Alm_VTS >=1 &
[x.21.ZGn.t_Op] 0s x.21.ZGn.Op
SIG x.In_VT

SIG x.21.FD 0 500ms

Figure 3.13-3 Logic diagram of impedance protection (n=1, 2)

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Where:

“x.21.FD” means that the fault detector based on DPFC phase-to-phase current or
negative-sequence current at x side of transformer operates.

“Flag_ZPn” means that phase-to-phase operation equation of stage n of impedance protection is


met.

“Flag_ZGn” means that phase-to-ground operation equation of stage n of impedance protection is


met.

3.13.6 Settings
Table 3.13-2 Settings of impedance protection

No. Item Range Step Unit Description


Relay characteristic angle (also called
1 x.21.RCA 1~89 0.01 deg
reach angle)
Current setting of PSBR element
2 x.21.I_PSBR 0.04~150 0.001 A It should be greater than maximum
load current.
Logic setting of enabling/disabling
power swing blocking releasing
function to control impedance
3 x.21.En_PSBR 0 or 1
protection
0: disable
1: enable
Forward impedance setting of stage
4 x.21.ZP1.Z_Fwd 0.01~200 0.001 Ω 1 of phase-to-phase impedance
protection
Reverse impedance setting of stage
5 x.21.ZP1.Z_Rev 0.01~200 0.001 Ω 1 of phase-to-phase impedance
protection
Time delay of stage 1 of
6 x.21.ZP1.t_Op 0.05~20 0.001 s phase-to-phase impedance
protection
Logic setting of enabling/disabling
stage 1 of phase-to-phase
7 x.21.ZP1.En 0 or 1 impedance protection
0: disable
1: enable
Tripping logic setting of stage 1 of
8 x.21.ZP1.OutMap 0000~FFFF phase-to-phase impedance
protection
Forward impedance setting of stage
9 x.21.ZP2.Z_Fwd 0.01~200 0.001 Ω 2 of phase-to-phase impedance
protection

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No. Item Range Step Unit Description


Reverse impedance setting of stage
10 x.21.ZP2.Z_Rev 0.01~200 0.001 Ω 2 of phase-to-phase impedance
protection
Time delay of stage 2 of
11 x.21.ZP2.t_Op 0.05~20 0.001 s phase-to-phase impedance
protection
Logic setting of enabling/disabling
stage 2 of phase-to-phase
12 x.21.ZP2.En 0 or 1 impedance protection
0: disable
1: enable
Tripping logic setting of stage 2 of
13 x.21.ZP2.OutMap 0000~FFFF phase-to-phase impedance
protection
Zero-sequence compensation
14 x.21.K0 0~2 0.001
coefficient
Forward impedance setting of stage
15 x.21.ZG1.Z_Fwd 0.01~200 0.001 Ω 1 of phase-to-ground impedance
protection
Reverse impedance setting of stage
16 x.21.ZG1.Z_Rev 0.01~200 0.001 Ω 1 of phase-to-ground impedance
protection
Time delay of stage 1 of
17 x.21.ZG1.t_Op 0.05~20 0.001 s phase-to-ground impedance
protection
Logic setting of enabling/disabling
stage 1 of phase-to-ground
18 x.21.ZG1.En 0 or 1 impedance protection
0: disable
1: enable
Tripping logic setting of stage 1 of
19 x.21.ZG1.OutMap 0000~FFFF phase-to-ground impedance
protection
Forward impedance setting of stage
20 x.21.ZG2.Z_Fwd 0.01~200 0.001 Ω 2 of phase-to-ground impedance
protection
Reverse impedance setting of stage
21 x.21.ZG2.Z_Rev 0.01~200 0.001 Ω 2 of phase-to-ground impedance
protection
Time delay of stage 2 of
22 x.21.ZG2.t_Op 0.05~20 0.001 s phase-to-ground impedance
protection
23 x.21.ZG2.En 0 or 1 Logic setting of enabling/disabling

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No. Item Range Step Unit Description


stage 2 of phase-to-ground
impedance protection
0: disable
1: enable
Tripping logic setting of stage 2 of
24 x.21.ZG2.OutMap 0000~FFFF phase-to-ground impedance
protection

3.14 Phase Overcurrent Protection (50/51P)

3.14.1 Application
When a fault occurs in power system, the current increases and phase overcurrent protection
operates to avoid damages to protected equipment. Voltage control element can be selected to
improve the sensitivity of phase overcurrent protection and directional element can be selected to
improve the selectivity of the protection. In case that phase overcurrent protection operates
unexpectedly, harmonic blocking element can be selected to block the protection.

An external fault will result in transformer overload, and phase overcurrent protection operates to
trip circuit breakers of transformer to avoid physical damage. To small transformers, phase
overcurrent protection can protect transformer from internal faults as main protection, to
large-scale transformers, no-directional protection is applied as the backup protection of
transformer differential protection.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.14.2 Function Description

Phase overcurrent protection includes four stages phase overcurrent protection with independent
logic, current and time delay settings. Stage 1, 2, 3 are definite-time characteristic, and stage 4
can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is
selectable, among IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined
inverse-time curve. Each stage of phase overcurrent protection can select voltage control element,
direction element, and harmonic blocking element.

3.14.2.1 Operation Criterion

The operation criterion is:

IP>[x.50/51Pn.I_Set] Equation 3.14-1

Where:

IP is measured phase current.

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3 Operation Theory

3.14.2.2 Time Curve

Stage 4 can be selected as definite-time or inverse-time characteristic, and the inverse-time


characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics and
a user-defined inverse-time curve. The inverse-time operating time curve is as follows.

Equation 3.14-2

Where:

Iset is current setting [x.50/51P4.I_Set].

TP is time multiplier setting [x.50/51P4.TMS].

K, C is constants.

α is a constant.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.50/51P4.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.

Table 3.14-1 Inverse-time curve parameters

x.51P4.Opt_Curve Description K α C
DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined

If all available curves do not comply with user application, the user may configure setting
[x.50/51P4.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.

3.14.2.3 Voltage Control Element

Phase overcurrent protection is equipped as the backup protection of transformer and adjacent

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power equipment, and voltage is usually used to control phase overcurrent protection to improve
sensitivity of the protection. Unsymmetrical faults result in unsymmetrical sequence voltages and
symmetrical faults lead to low three phase voltages at relay location, so phase overcurrent
protection can operate if the sequence voltage greater than a setting or phase voltage lower than
a setting. Therefore, current settings of phase overcurrent protection can be set lower with high
sensitivity.

The voltage control element picks up if phase-to-phase voltage is lower than its setting or
negative-sequence voltage is greater than its setting. The operation criterion is:

UΦΦ<[x.50/51P.VCE.UPP_VCE] Equation 3.14-3

or

U2>[ x.50/51P.VCE.U2_VCE] Equation 3.14-4

Where:

UΦΦ is the phase-to-phase voltage.

U2 is the negative-sequence voltage.

The voltage at any side can be used as the input of voltage control element, and there is a logic
settings used to select at which side voltage control element is used to control phase overcurrent
protection of some side.

Overcurrent element Voltage control


Ia> Uab< or Uca< or U2>
Ib> Ubc< or Uab< or U2>
Ic> Uca< or Ubc< or U2>

3.14.2.4 Direction Element

Phase overcurrent protection can select to be controlled by direction element to fulfill coordinating
with other protections of power grid

Positive-sequence voltage (U1) is adopted as polarizing voltage, and memory voltage is used
during close-up faults to ensure the direction element working properly. Phase current (IP) is
adopted for calculation of direction element, and if phase current is less than current threshold,
neither of forward and reverse directions is met.

When a fault occurs at forward direction, the angle between polarizing voltage and fault current is:

Equation 3.14-5

When a fault occurs at reverse direction, the angle is:

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3 Operation Theory

Equation 3.14-6

Relay characteristic angle [ x.50/51P.DIR.RCA], i.e., the angle polarizing voltage leading fault
current, is given as the directional setting, and the forward operating range is:

Equation 3.14-7

If VT and CT are connected as shown in Figure 3.14-1, i.e. polarity of CT is at busbar side, and
forward direction points to protected object, then forward and reverse operating regions are shown
in Figure 3.14-2.

VT
Dir
Reverse
Direction
Element

CT
Forward

Protected
Object

Figure 3.14-1 VT and CT connection of direction element

Reverse

URef (U1)
Φsen
Φsen+180°
IDir (Ip) Forward

Figure 3.14-2 Directional characteristic

3.14.2.5 Harmonic Blocking Element

When phase overcurrent protection is used to protect transformer during transformer energization,
in order to prevent inrush current leading to maloperation of phase overcurrent protection,
harmonic blocking function can be selected.

Blocking mode is selectable between phase segregated blocking mode or phase crossing

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blocking mode through the setting [x.50/51P.HMB.Opt_HmBlk]. If any phase harmonic meets the
following criterion, harmonic blocking condition is satisfied. However, when any phase current is
greater than the setting [x.50/51P.HMB.I_Rls_HmBlk], phase overcurrent protection does not be
blocked by harmonic even if blocking condition is satisfied.

Operation criterion:

IP_2nd>[x.50/51P.HMB.K_Hm2]×IP Equation 3.14-8

Where:

IP_2nd is second harmonic of phase current

IP is fundamental component of phase current.

If fundamental component of any phase current is lower than the minimum operating current
(0.04In), then harmonic calculation is not carried out and harmonic blocking element does not
work.

3.14.3 Function Block Diagram

50/51P

x.50/51Pn.I3P x.50/51Pn.St

x.50/51Pn.U3P x.50/51Pn.On

x.50/51Pn.En1 x.50/51Pn.Op

x.50/51Pn.En2

x.50/51Pn.Blk

3.14.4 I/O Signals


Table 3.14-2 I/O signals of phase overcurrent protection

No. Input signal Description


Three-phase current data input for stage n of phase overcurrent protection at side
1 x.50/51Pn.I3P
x of transformer or reactor. (n=1, 2, 3, 4)
Three-phase voltage data input for stage n of phase overcurrent protection at side
2 x.50/51Pn.U3P
x of transformer or reactor. (n=1, 2, 3, 4)
Input signal 1 of enabling stage n of phase overcurrent protection at side x of
3 x.50/51Pn.En1 transformer or reactor. It is triggered from binary input or programmable logic etc.
(n=1, 2, 3, 4)
Input signal 2 of enabling stage n of phase overcurrent protection at side x of
4 x.50/51Pn.En2 transformer or reactor. It is triggered from binary input or programmable logic etc.
(n=1, 2, 3, 4)
Input signal of blocking stage n of phase overcurrent protection at side x of
5 x.50/51Pn.Blk
transformer or reactor. It is triggered from binary input or programmable logic etc.

PCS-978 Transformer Relay 3-101


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3 Operation Theory

No. Input signal Description


(n=1, 2, 3, 4)
No. Output signal Description
Stage n of phase overcurrent protection at side x of transformer or reactor starts.
1 x.50/51Pn.St
(n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor is
2 x.50/51Pn.On
enabled. (n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor
3 x.50/51Pn.Op
operates. (n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor picks up
4 x.50/51Pn.TrigDFR
to trigger DFR function. (n=1, 2, 3, 4)

3.14.5 Logic

SIG x.50/51Pn.VCE.En &


&
SIG x.50/51Pn.VCE.Blk UPP VCE Release

SET UΦΦ<[x.50/51P.VCE.Upp_VCE] &

SIG x.Alm_VTS >=1


>=1
SIG x.In_VT &

EN [x.50/51P.En_VTS_Blk]

SIG x.50/51Pn.VCE.En &


&
SIG x.50/51Pn.VCE.Blk U2 VCE Release

SET U2<[x.50/51P.VCE.U2_VCE] &

SIG x.Alm_VTS >=1


>=1
SIG x.In_VT &

EN [x.50/51P.En_VTS_Blk]

Figure 3.14-3 Logic diagram of voltage control element (n=1, 2, 3, 4)

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SET [x.50/51Pn.Opt_Dir]=Forward &

SIG Direction element (Forward)


>=1
SIG Direction element (Reverse) & &
>=1
SET [x.50/51Pn.Opt_Dir]=Reverse DIR Release

SIG x.Alm_VTS >=1


&
SIG x.In_VT

&

>=1
EN [x.50/51P.DIR.En_VTS_Blk]

SET [x.50/51Pn.Opt_Dir]=Non_Directional

Figure 3.14-4 Logic diagram of direction element (n=1, 2, 3, 4)

SIG [x.50/51Pn.En]
&
SIG x.50/51Pn.En1
& x.50/51Pn.On
SIG x.50/51Pn.En2

SIG x.50/51Pn.Blk

SET IP>[x.50/51Pn.I_Set]

SIG UPP VCE Release >=1


& x.50/51Pn.St
SIG U2 VCE Release >=1 & &
[x.50/51Pn.t_Op] 0ms x.50/51Pn.Op
EN [x.50/51Pn.En_VCE]

SIG DIR Release

SIG Second harmonic &

EN [50/51Pn.En_Hm2_Blk]

Figure 3.14-5 Logic Diagram of phase overcurrent protection (n=1, 2, 3)

PCS-978 Transformer Relay 3-103


Date: 2016-06-22
3 Operation Theory

SIG [x.50/51P4.En]
&
SIG x.50/51P4.En1
& x.50/51P4.On
SIG x.50/51P4.En2

SIG x.50/51P4.Blk

SET IP>[x.50/51P4.I_Set]

SIG UPP VCE Release >=1


x.50/51P4.St
&
SIG U2 VCE Release >=1 & & Timer
t
x.50/51P4.Op
EN [x.50/51P4.En_VCE] t

SIG DIR Release

SIG Second harmonic &

EN [50/51P4.En_Hm2_Blk]

Figure 3.14-6 Logic Diagram of phase overcurrent protection (stage 4)

Where:

UΦΦ is the phase-to-phase voltage

U2 is the negative-sequence voltage

3.14.6 Settings
Table 3.14-3 Settings of phase overcurrent protection

No. Item Range Step Unit Description


Phase-to-phase voltage setting of
1 x.50/51P.VCE.Upp_VCE 2~200 0.001 V
voltage control element
Negative-sequence voltage setting
2 x.50/51P.VCE.U2_VCE 2~200 0.001 V
of voltage control element
Relay characteristic angle of phase
3 x.50/51P.DIR.RCA 0~360 1 deg
overcurrent protection
Harmonic blocking coefficient of
4 x.50/51P.HMB.K_Hm2 0.05~1.0 0.001
phase overcurrent protection
Current setting of releasing harmonic
blocking function of phase
5 x.50/51P.HMB.I_Rls_HmBlk 0.04~150 0.001 A
overcurrent protection.
It is recommended to set as 0.15.
Option of harmonic blocking mode
6 x.50/51P.HMB.Opt_HmBlk 0, 1 1 0: phase-segregated blocking mode
1: phase crossing blocking mode
Logic setting of enabling/disabling
7 x.50/51P.En_VTS_Blk 0 or 1 block for phase overcurrent
protection during VT circuit abnormal

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No. Item Range Step Unit Description


0: disable
1: enable
When VT circuit fails or VT is not in
service, phase overcurrent
protection will be blocked if the
setting is set as “1”, and phase
overcurrent protection is not
controlled by direction element and
voltage control element if the setting
is set as ”0”.
Current setting of stage n of phase
8 x.50/51Pn.I_Set 0.04~30In 0.001 A
overcurrent protection (n=1, 2, 3)
Time delay of stage n of phase
9 x.50/51Pn.t_Op 0~3600 0.001 s
overcurrent protection (n=1, 2, 3)
Logic setting of enabling/disabling
voltage control element for phase
10 x.50/51Pn.En_VCE 0 or 1 overcurrent protection (n=1, 2, 3)
0: disable
1: enable
Non_Directional
Direction option of stage n of phase
11 x.50/51Pn.Opt_Dir Forward
overcurrent protection (n=1, 2, 3)
Reverse
Logic setting of enabling/disabling
harmonic blocking for stage n of
phase overcurrent protection (n=1, 2,
12 x.50/51Pn.En_Hm2_Blk 0 or 1
3)
0: disable
1: enable
Logic setting of enabling/disabling
stage n of phase overcurrent
13 x.50/51Pn.En 0 or 1 protection (n=1, 2, 3)
0: disable
1: enable
Tripping logic setting of stage n of
14 x.50/51Pn.OutMap 0000~FFFF phase overcurrent protection (n=1, 2,
3)
Pickup setting of stage 4 of phase
15 x.50/51P4.I_Set 0.04~30In 0.001 A
overcurrent protection
Multiple of the maximum operating
16 x.50/51P4.K_I_Max 10~40 0.001 current to the pickup setting of stage
4 of phase overcurrent protection
Time delay of stage 4 of phase
17 x.50/51P4.t_Op 0~3600 0.001 s
overcurrent protection

PCS-978 Transformer Relay 3-105


Date: 2016-06-22
3 Operation Theory

No. Item Range Step Unit Description


Time multiplier setting of stage 4 of
18 x.50/51P4.TMS 0.05~3.2 0.001
phase overcurrent protection
Minimum delay of stage 4 of phase
19 x.50/51P4.tmin 0~20 0.001 s
overcurrent protection
The constant K of stage 4 of phase
20 x.50/51P4.K 0~120 0.001
overcurrent protection
The constant C of stage 4 of phase
21 x.50/51P4.C 0~20 0.001
overcurrent protection
The exponent alpha of stage 4 of
22 x.50/51P4.Alpha 0.02~5 0.001
phase overcurrent protection
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for
ANSIE
23 x.50/51P4.Opt_Curve stage 4 of phase overcurrent
ANSIV
protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Logic setting of enabling/disabling
voltage control element for stage 4 of
24 x.50/51P4.En_VCE 0 or 1 phase overcurrent protection
0: disable
1: enable
Non_Directional
Direction option of stage 4 of phase
25 x.50/51P4.Opt_Dir Forward
overcurrent protection
Reverse
Logic setting of enabling/disabling
harmonic blocking for stage 4 of
26 x.50/51P4.En_Hm2_Blk 0 or 1 phase overcurrent protection
0: disable
1: enable
Logic setting of enabling/disabling
stage 4 of phase overcurrent
27 x.50/51P4.En 0 or 1 protection
0: disable
1: enable
28 x.51P4.OutMap 0000~FFFF Tripping logic setting of stage 4 of

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Date: 2016-06-22
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No. Item Range Step Unit Description


phase overcurrent protection

NOTICE!

If the minimum operating time [x.50/51P4.tmin] is set to “0”, the maximum operating
current is valid, and the setting [x.50/51P4.K_I_Max] can be set according to
requirements. If the current is greater than [x.50/51P4.K_I_Max] multiplying
[x.50/51P4.I_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point current equal to [x.50/51P4.K_I_Max]
multiplying [x.50/51P4.I_Set]. If [x.50/51P4.tmin] is not set to “0”, then maximum
operating current is not valid and users only can set the setting [x.50/51P4.tmin].

3.15 Earth Fault Protection (50/51G)

3.15.1 Application
During normal operation of power system, there is trace residual current whereas a fault current
flows to earth will result in greater residual current. Therefore residual current is adopted for the
calculation of earth fault protection.

In order to improve the selectivity of earth fault protection in power grid with multiple power
sources, directional element can be selected to control earth fault protection. For application on
transformer circuits, second harmonic also can be selected to block earth fault protection to avoid
the effect of sympathetic current on the protection.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.15.2 Function Description

Earth fault protection includes four stages earth fault element with independent logic, current and
time delay settings. Stage 1, 2, 3 are definite-time characteristic, and stage 4 can be selected as
definite-time or inverse-time characteristic. The inverse-time characteristic is selectable, among
IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.

Measured neutral current or calculated residual current can be selected for the calculation of earth
fault protection. Earth fault protection is controlled by direction element and second harmonic
Directional element can select among no direction, forward direction and reverse direction.

3.15.2.1 Operation Criterion

The operation criterion is:

3I0>[x.50/51Gn.3I0_Set] Equation 3.15-1

Where:

PCS-978 Transformer Relay 3-107


Date: 2016-06-22
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3I0 is measured neutral current or calculated residual current, which is selected by user through
the setting [x.50/51Gn.Opt_3I0], n (n=1, 2, 3 or 4).

3.15.2.2 Time Curve

Stage 4 can be selected as definite-time or inverse-time characteristic, and inverse-time operation


time curve is as follows.

Equation 3.15-2

Where:

Iset is residual current setting [x.50/51G4.3I0_Set].

TP is time multiplier setting [x.50/51G4.TMS].

K and C are constants.

α is a constant.

I is actual value of measured current from the neutral CT or calculated residual current.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.50/51G4.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.

Table 3.15-1 Inverse-time curve parameters

x.50/51G4.Opt_Curve Time Characteristic K α C


DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable User-defined

If all available curves do not comply with user application, the user may configure setting
[x.50/51G4.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.

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3.15.2.3 Direction Element

Calculated residual voltage (3U0) is adopted as polarizing quantity (i.e. polarizing voltage) of
directional element. The current quantity can select the measured neutral current (IN) or the
calculated residual current (3I0).

When a fault occurs at forward direction, the angle polarizing voltage leading fault current is:

Equation 3.15-3

When a fault occurs at reverse direction, the angle is:

Equation 3.15-4

Relay characteristic angle [x.50/51G.DIR.RCA], i.e., the angle of polarizing voltage leading fault
current, is given as the directional setting, and the forward operating region is:

Equation 3.15-5

If VT and CT are connected as shown in Figure 3.15-1, i.e. polarity of CT is at busbar side, and
forward direction points to protected object, then forward and reverse operating regions are shown
in Figure 3.15-2.

VT
Dir
Reverse
Direction
Element

CT
Forward

Protected
Object

Figure 3.15-1 VT and CT connection of direction element

PCS-978 Transformer Relay 3-109


Date: 2016-06-22
3 Operation Theory

Forward

IDir (3I0 or IN)

Uref(3U0)
Φsen

Reverse

Figure 3.15-2 Directional characteristic

3.15.2.4 Harmonic Blocking Element

In order to prevent effects of sympathetic inrush current on earth fault protection, harmonics
blocking function can be selected for each stage.

When the percent of second harmonic to fundamental component of zero-sequence current is


greater than setting [x.50/51G.HMB.K_Hm2], harmonic blocking element operates to block earth
fault protection if logic setting [x.50/51Gn.En_Hm2_Blk] (n=1, 2, 3 or 4) is set as “1”. Operation
criterion:

Equation 3.15-6

Where:

I0_2nd is second harmonic of zero sequence current/

I0 is fundamental component of zero sequence current.

When residual current is greater than the setting [x.50/51G.HMB.3I0_Rls_HmBlk], earth fault
protection does not be blocked by harmonic even if the operation criterion is satisfied.

If fundamental component of zero-sequence current is lower than the minimum operating current
(0.4In), harmonic calculation is not carried out and harmonic blocking element does not work.

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3.15.3 Function Block Diagram

50/51G

x.50/51Gn.I3P x.50/51Gn.St

x.50/51Gn.U3P x.50/51Gn.On

x.50/51Gn.I1P x.50/51Gn.Op

x.50/51Gn.En1

x.50/51Gn.En2

x.50/51Gn.Blk

3.15.4 I/O Signals


Table 3.15-2 I/O signals of earth fault protection

No. Input signal Description


Three-phase voltage data input for stage n of earth fault protection at side x of
1 x.50/51Gn.U3P
transformer or reactor. (n=1, 2, 3, 4)
Three-phase current data input for stage n of earth fault protection at side x of
2 x.50/51Gn.I3P
transformer or reactor. (n=1, 2, 3, 4)
Measured neutral current data input for stage n of earth fault protection at side x of
3 x.50/51Gn.I1P
transformer or reactor. (n=1, 2, 3, 4)
Input signal 1 of enabling stage n of earth fault protection at side x of transformer or
4 x.50/51Gn.En1
reactor. It is triggered from binary input or programmable logic etc. (n=1, 2, 3, 4)
Input signal 2 of enabling stage n of earth fault protection at side x of transformer or
5 x.50/51Gn.En2
reactor. It is triggered from binary input or programmable logic etc. (n=1, 2, 3, 4)
Input signal of blocking stage n of earth fault protection at side x of transformer or
6 x.50/51Gn.Blk
reactor. It is triggered from binary input or programmable logic etc. (n=1, 2, 3, 4)
No. Output signal Description
Stage n of earth fault protection at side x of transformer or reactor starts. (n=1, 2, 3,
1 x.50/51Gn.St
4)
Stage n of earth fault protection at side x of transformer or reactor is enabled. (n=1,
2 x.50/51Gn.On
2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor operates. (n=1,
3 x.50/51Gn.Op
2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor picks up to
4 x.50/51Gn.TrigDFR
trigger DFR function. (n=1, 2, 3, 4)

PCS-978 Transformer Relay 3-111


Date: 2016-06-22
3 Operation Theory

3.15.5 Logic

SET [x.50/51Gn.Opt_Dir]=Forward &


>=1
SIG Direction element (Forward) &

SIG Direction element (Reverse) &

SET [x.50/51Gn.Opt_Dir]=Reverse

SIG x.Alm_VTS >=1


&
SIG x.In_VT

&
>=1
>=1 DIR Release
EN [x.50/51G.DIR.En_VTS_Blk]

SET [x.50/51Gn.Opt_Dir]=Non_Directional

Figure 3.15-3 Logic diagram of direction element (n=1, 2, 3, 4)

EN [x.50/51Gn.En]
&
SIG x.50/51Gn.En1
& x.50/51Gn.On
SIG x.50/51Gn.En2

SIG x.50/51Gn.Blk

SET [x.50/51Gn.Opt_3I0] &

SET 3I0>[x.50/51Gn.3I0_Set]
>=1 &
x.50/51Gn.St
& &
[x.50/51Gn.t_Op] 0ms x.50/51Gn.Op
SET IN>[x.50/51Gn.3I0_Set]

SIG DIR Release

SIG Second harmonic &

EN [x.50/51Gn.En_Hm2_Blk]

Figure 3.15-4 Logic diagram of earth fault protection (n=1, 2, 3)

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EN [x.50/51G4.En]
&
SIG x.50/51G4.En1
& x.50/51G4.On
SIG x.50/51G4.En2

SIG x.50/51G4.Blk

SET [x.50/51G4.Opt_3I0] &

SET 3I0>[x.50/51G4.3I0_Set]
>=1 &
&

SET IN>[x.50/51G4.3I0_Set]
x.50/51G4.St
SIG DIR Release
& Timer
t
SIG Second harmonic & x.50/51G4.Op
t

EN [x.50/51G4.En_Hm2_Blk]

Figure 3.15-5 Logic diagram of earth fault protection (stage 4)

Where:

3I0 is calculated residual current.

IN is measured neutral current.

3.15.6 Settings
Table 3.15-3 Settings of earth fault protection

No. Item Range Step Unit Description


Relay characteristic angle of earth
1 x.50/51G.DIR.RCA 0~360 1 deg
fault protection
Harmonic blocking coefficient of
2 x.50/51G.HMB.K_Hm2 0.05~1.0 0.001
earth fault protection
Current setting of releasing
3 x.50/51G.HMB.3I0_Rls_HmBlk 0.04~150 0.001 A harmonic blocking function of earth
fault protection
Logic setting of enabling/disabling
earth fault protection be blocked
during VT circuit abnormality
0: disable
4 x.50/51G.DIR.En_VTS_Blk 0 or 1 1: enable
When VT circuit fails or VT is not in
service, directional earth fault is
blocked if the setting is set as “1”.
Directional earth fault protection

PCS-978 Transformer Relay 3-113


Date: 2016-06-22
3 Operation Theory

No. Item Range Step Unit Description


switches to non-directional earth
fault protection if the setting is set as
“0”.
Current setting of stage n of earth
5 x.50/51Gn.3I0_Set 0.04~30In 0.001 A
fault protection (n=1, 2, 3)
Time delay of stage n of earth fault
6 x.50/51Gn.t_Op 0~3600 0.001 s
protection (n=1, 2, 3)
Non_Directional
Direction option of stage n of earth
7 x.50/51Gn.Opt_Dir Forward
fault protection (n=1, 2, 3)
Reverse
Option of residual current for the
calculation of stage n of earth fault
8 x.50/51Gn.Opt_3I0 0, 1 1 protection (n=1, 2, 3)
0: Measured residual current
1: Calculated residual current
Logic setting of enabling/disabling
harmonic blocking for stage n of
9 x.50/51Gn.En_Hm2_Blk 0 or 1 earth fault protection (n=1, 2, 3)
0: disable
1: enable
Logic setting of enabling/disabling
stage n of earth fault protection (n=1,
10 x.50/51Gn.En 0 or 1 2, 3)
0: disable
1: enable
Tripping logic setting of stage n of
11 x.50/51Gn.OutMap 0000~FFFF
earth fault protection (n=1, 2, 3)
Pickup setting of stage 4 of earth
12 x.50/51G4.3I0_Set 0.04~30In 0.001 A
fault protection
Multiplier of the maximum operating
13 x.50/51G4.K_3I0_Max 10~40 0.001 residual current to the pickup setting
of stage 4 of earth fault protection
Time delay of stage 4 of earth fault
14 x.50/51G4.t_Op 0~3600 0.001 s
protection
Time multiplier setting of stage 4 of
15 x.50/51G4.TMS 0.05~3.2 0.001
earth fault protection
Minimum delay of stage 4 of earth
16 x.50/51G4.tmin 0~20 0.001 s
fault protection
The constant K of stage 4 of earth
17 x.50/51G4.K 0~120 0.001
fault protection
The constant C of stage 4 of earth
18 x.50/51G4.C 0~20 0.001
fault protection
19 x.50/51G4.Alpha 0.02~5 0.001 The exponent alpha of stage 4 of

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No. Item Range Step Unit Description


earth fault protection
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for
20 x.50/51G4.Opt_Curve
ANSIV stage 4 of earth fault protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Non_Directional
Direction option of stage 4 of earth
21 x.50/51G4.Opt_Dir Forward
fault protection
Reverse
Option of residual current for the
calculation of stage 4 of earth fault
22 x.50/51G4.Opt_3I0 0, 1 1 protection
0: Measured residual current
1: Calculated residual current
Logic setting of enabling/disabling
harmonic blocking for stage 4 of
23 x.50/51G4.En_Hm2_Blk 0 or 1 earth fault protection
0: disable
1: enable
Logic setting of enabling/disabling
stage 4 of earth fault protection
24 x.50/51G4.En 0 or 1
0: disable
1: enable
Tripping logic setting of stage 4 of
25 x.50/51G4.OutMap 0000~FFFF
earth fault protection

NOTICE!

If the minimum operating time [x.50/51G4.tmin] is set to “0”, the maximum operating
current is valid, and the setting [x.50/51G4.K_3I0_Max] can be set according to
requirements. If the current is greater than [x.50/51G4.K_3I0_Max] multiplying
[x.50/51G4.3I0_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point residual current equal to
[x.50/51G4.K_3I0_Max] multiplying [x.50/51G4.3I0_Set]. If [x.50/51G4.tmin] is not set
to “0”, then maximum operating current is not valid and users only can set the setting

PCS-978 Transformer Relay 3-115


Date: 2016-06-22
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[x.50/51G4.tmin].

3.16 Negative-Sequence Overcurrent Protection (50/51Q)

3.16.1 Application

Negative-sequence overcurrent protection is applied as the backup protection for generator.


When an unsymmetrical short-circuit fault or a three-phase fault occurs in power system, there is
negative-sequence current generated in stator winding of generator, and negative-sequence
current will produce an opposite rotating magnetic field in gap. Therefore, harmonic currents occur
in rotor, which make some parts with great current density be locally burned and even result in the
retaining ring loosing due to heat to lead to great damage of generator. Negative-sequence
overcurrent protection is equipped to prevent generator from such damage.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.16.2 Function Description

Negative-sequence overcurrent protection includes two stages negative-sequence overcurrent


protection with independent logic, current and time delay settings. Stage 1 is definite-time
characteristic, and stage 2 can be selected as definite-time or inverse-time characteristic. The
inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics and a user-defined inverse-time curve.

3.16.2.1 Operation Criterion

The operation criterion of stage 1 negative-sequence overcurrent protection is:

I2>[x.50/51Q1.I2_Set] Equation 3.16-1

Where:

I2 is negative-sequence current.

3.16.2.2 Time Curve

Stage 2 can be selected as definite-time or inverse-time characteristic, and inverse-time operating


time curve is as follows.

Equation 3.16-2

Where:

Iset is negative-sequence current setting [x.50/51Q2.I2_Set].

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Tp is time multiplier setting [x.50/51Q2.TMS].

K and C are constants.

α is a constant.

I is actual value of measured negative-sequence current.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.50/51Q2.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.

Table 3.16-1 Inverse-time curve parameters

x.50/51Q2.Opt_Curve Time Characteristic K α C


DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable User-defined

If all available curves do not comply with user application, user may configure setting
[x.50/51Q2.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.

3.16.3 Function Block Diagram

50/51Q

x.50/51Qn.I3P x.50/51Qn.St

x.50/51Qn.En1 x.50/51Qn.On

x.50/51Qn.En2 x.50/51Qn.Op

x.50/51Qn.Blk

3.16.4 I/O Signals


Table 3.16-2 I/O signals of negative-sequence overcurrent protection

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No. Input signal Description


Three-phase current data input for stage n of negative-sequence overcurrent
1 x.50/51Qn.I3P
protection at side x of transformer. (n=1, 2)
Input signal 1 of enabling stage n of negative-sequence overcurrent protection at
2 x.50/51Qn.En1 side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
Input signal 2 of enabling stage n of negative-sequence overcurrent protection at
3 x.50/51Qn.En2 side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
Input signal of blocking stage n of negative-sequence overcurrent protection at
4 x.50/51Qn.Blk side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
No. Output signal Description
Stage n of negative-sequence overcurrent protection at side x of transformer
1 x.50/51Qn.St
starts. (n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer is
2 x.50/51Qn.On
enabled. (n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer
3 x.50/51Qn.Op
operates. (n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer picks
4 x.50/51Qn.TrigDFR
up to trigger DFR function. (n=1, 2)

3.16.5 Logic

EN [x.50/51Q1.En]
&
SIG x.50/51Q1.En1
& x.50/51Q1.On
SIG x.50/51Q1.En2

SIG x.50/51Q1.Blk
&
SIG x.50/51Q1.I3P x.50/51Q1.St

[x.50/51Q1.t_Op] 0ms x.50/51Q1.Op


SET [x.50/51Q1.I2_Set]

EN [x.50/51Q2.En]
&
SIG x.50/51Q2.En1
& x.50/51Q2.On
SIG x.50/51Q2.En2 Timer
t
x.50/51Q2.Op
SIG x.50/51Q2.Blk t
&
SIG x.50/51Q2.I3P x.50/51Q2.St

SET [x.50/51Q2.I2_Set]

Figure 3.16-1 Logic diagram of negative-sequence overcurrent protection

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3.16.6 Settings
Table 3.16-3 Settings of negative-sequence overcurrent protection

No. Item Range Step Unit Description


Current setting of stage 1 of negative-sequence
1 x.50/51Q1.I2_Set 0.04~30In 0.001 A
overcurrent protection
Time delay of stage 1 of negative-sequence
2 x.50/51Q1.t_Op 0~3600 0.001 s
overcurrent protection
Logic setting of enabling/disabling stage 1 of
negative-sequence overcurrent protection
3 x.50/51Q1.En 0 or 1
0: disable
1: enable
Tripping logic setting of stage 1 of
4 x.50/51Q1.OutMap 0000~FFFF
negative-sequence overcurrent protection
Pickup setting of stage 2 of negative-sequence
5 x.50/51Q2.I2_Set 0.04~30In 0.001 A
overcurrent protection
Multiplier of the maximum operating
negative-sequence current to the pickup setting
6 x.50/51Q2.K_I2_Max 10~40 0.001
of stage 2 of negative-sequence overcurrent
protection
Time delay of stage 2 of negative-sequence
7 x.50/51Q2.t_Op 0~3600 0.001 s
overcurrent protection
Time multiplier setting of stage 2 of ground
8 x.50/51Q2.TMS 0.05~3.2 0.001
overcurrent protection
Minimum delay of stage 2 of negative-sequence
9 x.50/51Q2.tmin 0~20 0.001 s
overcurrent protection
The constant K of stage 2 of negative-sequence
10 x.50/51Q2.K 0~120 0.001
-sequence overcurrent protection
The constant C of stage 2 of negative-sequence
11 x.50/51Q2.C 0~20 0.001
overcurrent protection
The exponent alpha of stage 2 of
12 x.50/51Q2.Alpha 0.02~5 0.001
negative-sequence overcurrent protection
DefTime
IECN
IECV
IECE
IECST
IECLT Option of characteristic curve for stage 2 of
13 x.50/51Q2.Opt_Curve
ANSIE negative-sequence overcurrent protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV

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No. Item Range Step Unit Description


ANSILT
UserDefine
Logic setting of enabling/disabling stage 2 of
negative-sequence overcurrent protection
14 x.50/51Q2.En 0 or 1
0: disable
1: enable
Tripping logic setting of stage 2 of
15 x.50/51Q2.OutMap 0000~FFFF
negative-sequence overcurrent protection

NOTICE!

If the minimum operating time [x.50/51Q2.tmin] is set to “0”, the maximum operating
current is valid, and the setting [x.50/51Q2.K_I2_Max] can be set according to
requirements. If the current is greater than [x.50/51Q2.K_I2_Max] multiplying
[x.50/51Q2.I_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point negative-sequence current equal to
[x.50/51Q2.K_I2_Max] multiplying [x.50/51Q2.I2_Set]. If [x.51Q2.tmin] is not set to “0”,
then maximum operating current is not valid and users only can set the setting
[x.50/51Q2.tmin].

3.17 Phase Overvoltage Protection (59P)

3.17.1 Application
In the power system, when users operating circuit breakers or a fault occurring, system
parameters will change, which can cause the power system electromagnetic energy converting
and transferring and overvoltage will appears in the system. Overvoltage protection is equipped
for the protection of electric equipment and its insulation.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.17.2 Function Description


Phase overvoltage protection includes two stages phase overvoltage element with independent
logic, voltage and time delay settings. Stage 1 is definite-time characteristic, and stage 2 can be
selected as definite-time or inverse-time characteristic. The inverse-time characteristic is
selectable among IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined
inverse-time curve.

3.17.2.1 Operation Criterion

Phase overvoltage protection can select phase voltage or phase-to-phase voltage for protection
calculation.

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 Phase voltage criterion

Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected determined by the logic setting [x.59Pn.Opt_1P/3P].

Equation 3.17-1

Equation 3.17-2

Where:

UΦ_max is the maximum value of three phase voltages.

When [x.59Pn.Opt_1P/3P] is set as “0”, “1-out-of-3” logic (i.e., Equation 3.17-1) is selected as
operation criterion

When [x.59Pn.Opt_1P/3P] is set as “1”, “3-out-of-3” logic (i.e., Equation 3.7-13) is selected as
operation criterion.

 Phase-to-phase voltage criterion

Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected determined by the logic setting [x.59Pn.Opt_1P/3P].

Equation 3.17-3

Equation 3.17-4

Where:

UΦΦ_max is the maximum value of phase-to-phase value of one side.

When [x.59Pn.Opt_1P/3P] is set as “0”, “1-out-of-3” logic (i.e., Equation 3.17-3) is selected as
operation criterion.

When [x.59Pn.Opt_1P/3P] is set as “1”, “3-out-of-3” logic (i.e., Equation 3.17-4) is selected as
operation criterion.

3.17.2.2 Time Curve

Stage 2 of phase overvoltage protection can be selected as definite-time or inverse-time


characteristic, and inverse-time operating time curve is as follows.

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Equation 3.17-5

Where:

Uset is voltage setting [x.59P2.U_Set].

Tp is time multiplier setting [x.59P2.TMS].

K and C are constants.

α is a constant.

U is actual measured phase voltage (or phase-to-phase voltage) value.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.59P2.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.

Table 3.17-1 Inverse-time curve parameters

x.59P2.Opt_Curve Time Characteristic K α C


DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined

If all available curves do not comply with user application, user may configure setting
[x.59P2.Opt_Curve] at “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.

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3.17.3 Function Block Diagram

59P

x.59Pn.U3P x.59Pn.St

x.59Pn.En1 x.59Pn.On

x.59Pn.En2 x.59Pn.Op

x.59Pn.Blk

3.17.4 I/O Signals


Table 3.17-2 I/O signals of phase overvoltage protection

No. Input signal Description


Three-phase voltage data input for stage n of phase overvoltage protection at side
1 x.59Pn.U3P
x of transformer. (n=1, 2)
Input signal 1 of enabling stage n of phase overvoltage protection at side x of
2 x.59Pn.En1
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
Input signal 2 of enabling stage n of phase overvoltage protection at side x of
3 x.59Pn.En2
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
Input signal of blocking stage n of phase overvoltage protection at side x of
4 x.59Pn.Blk
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
No. Output signal Description
1 x.59Pn.St Stage n of phase overvoltage protection at side x of transformer starts. (n=1, 2)
Stage n of phase overvoltage protection at side x of transformer is enabled. (n=1,
2 x.59Pn.On
2)
3 x.59Pn.Op Stage n of phase overvoltage protection at side x of transformer operates. (n=1, 2)
Stage n of phase overvoltage protection at side x of transformer picks up to trigger
4 x.59Pn.TrigDFR
DFR function. (n=1, 2)

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3.17.5 Logic

EN [x.59P1.En]
&
SIG x.59P1.En1
& x.59P1.On
SIG x.59P1.En2

SIG x.59P1.Blk
&
SIG x.59P1.U3P x.59P1.St

[x.59P1.t_Op] 0ms x.59P1.Op


SET [x.59P1.U_Set]

EN [x.59P2.En]
&
SIG x.59P2.En1
& x.59P2.On
SIG x.59P2.En2 Timer
t
x.59P2.Op
SIG x.59P2.Blk t
&
SIG x.59P2.U3P x.59P2.St

SET [x.59P2.U_Set]

Figure 3.17-1 Logic diagram of phase overvoltage protection

3.17.6 Settings
Table 3.17-3 Settings of phase overvoltage protection

No. Item Range Step Unit Description


Voltage setting of stage 1 of phase overvoltage
1 x.59P1.U_Set 2~200 0.001 V
protection
Time delay of stage 1 of phase overvoltage
2 x.59P1.t_Op 0~3600 0.001 s
protection
Option of phase voltage or phase-to-phase
voltage used for protection calculation of stage 1
3 x.59P1.Opt_Up/Upp 0, 1 1 of phase overvoltage protection
0: phase voltage
1: phase-to-phase voltage
Option of “1-out-of-3” logic or “3-out-of-3” logic
used for operation criterion of stage 1 of phase
4 x.59P1.Opt_1P/3P 0, 1 1 overvoltage protection
0: 1-out-of-3
1: 3-out-of-3
Logic setting of enabling/disabling stage 1 of
phase overvoltage protection
5 x.59P1.En 0 or 1 1
0: disable
1: enable

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No. Item Range Step Unit Description


Tripping logic setting of stage 1 of phase
6 x.59P1.OutMap 0000~FFFF
overvoltage protection
Pickup setting of stage 2 of phase overvoltage
7 x.59P2.U_Set 2~200 0.001 V
protection
Multiplier of the maximum operating voltage to
8 x.59P2.K_U_Max 1~10 0.001 the pickup setting of stage 2 of phase
overvoltage protection
Time delay of stage 2 of phase overvoltage
9 x.59P2.t_Op 0~3600 0.001 s
protection
Option of phase voltage or phase-to-phase
voltage used for protection calculation of stage 2
10 x.59P2.Opt_Up/Upp 0~1 1 of phase overvoltage protection
0: phase voltage
1: phase-to-phase voltage
Option of “1-out-of-3” logic or “3-out-of-3” logic
used for operation criterion of stage 2 of phase
11 x.59P2.Opt_1P/3P 0~1 1 overvoltage protection
0: 1-out-of-3
1: 3-out-of-3
Time multiplier setting of stage 2 of phase
12 x.59P2.TMS 0.05~3.2 0.001
overvoltage protection
Minimum delay of stage 2 of phase overvoltage
13 x.59P2.tmin 0~20s 0.001 s
protection
The constant K of stage 2 of phase overvoltage
14 x.59P2.K 0~120 0.001
protection
The constant C stage 2 of phase overvoltage
15 x.59P2.C 0~20 0.001
protection
The exponent alpha stage 2 of phase
16 x.59P2.Alpha 0.02~5 0.001
overvoltage protection
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for stage 2 of
17 x.59P2.Opt_Curve
ANSIV overvoltage protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine

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No. Item Range Step Unit Description


Logic setting of enabling/disabling stage 2 of
phase overvoltage protection
18 x.59P2.En 0 or 1
0: disable
1: enable
Tripping logic setting of stage 2 of phase
19 x.59P2.OutMap 0000~FFFF
overvoltage protection

NOTICE!

If the minimum operating time [x.59P2.tmin] is set to “0”, the maximum operating
voltage is valid, and the setting [x.59P2.K_U_Max] can be set according to
requirements. If the voltage is greater than [x.59P2.K_U_Max] multiplying
[x.59P2.U_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point voltage equal to [x.59P2.K_U_Max]
multiplying [x.59P2.U_Set]. If [x.59P2.tmin] is not set to “0”, then maximum operating
voltage is not valid and users only can set the setting [x.59P2.tmin].

3.18 Residual Overvoltage Protection (59G)

3.18.1 Application
A single phase earth fault happening to ungrounded system or Peterson coil grounded system will
result in residual overvoltage, so residual overvoltage protection is equipped to prevent protected
equipment being damaged by residual overvoltage in this condition.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.18.2 Function Description


Residual overvoltage protection includes two stages residual overvoltage element with
independent logic, voltage and time delay settings. Stage 1 is definite-time characteristic, and
stage 2 can be selected as definite-time or inverse-time characteristic. The inverse-time
characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics and a
user-defined inverse-time curve.

3.18.2.1 Operation Criterion

3U0>[x.59Gn.3U0_Set] Equation 3.18-1

Where:

3U0 is measured residual voltage.

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3.18.2.2 Time Curve

Stage 2 of residual overvoltage protection can be selected as definite-time or inverse-time


characteristic, and inverse-time operating time curve is as follows.

Equation 3.18-2

Where:

Uset is residual voltage setting [x.59G2.3U0_Set].

Tp is time setting [x.59G2.TMS].

K and C are constants.

α is a constant.

U is actual measured residual voltage.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.59G2.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.

Table 3.18-1 Inverse-time curve parameters

x.59G2.Opt_Curve Time Characteristic K α C


DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined

If all available curves do not comply with user application, user may configure setting
[x.59G2.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.

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3.18.3 Function Block Diagram

59G

x.59Gn.U3P x.59Gn.St

x.59Gn.U1P x.59Gn.On

x.59Gn.En1 x.59Gn.Op

x.59Gn.En2

x.59Gn.Blk

3.18.4 I/O Signals


Table 3.18-2 I/O signals of residual overvoltage protection

No. Input signal Description


Three-phase voltage data input for stage n of residual overvoltage protection at
1 x.59Gn.U3P
side x of transformer. (n=1, 2)
Measured residual voltage data input for stage n of residual overvoltage protection
2 x.59Gn.U1P
at side x of transformer. (n=1, 2)
Input signal 1 of enabling stage n of residual overvoltage protection at side x of
3 x.59Gn.En1
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
Input signal 2 of enabling stage n of residual overvoltage protection at side x of
4 x.59Gn.En2
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
Input signal of blocking stage n of residual overvoltage protection at side x of
5 x.59Gn.Blk
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
No. Output signal Description
1 x.59Gn.St Stage 1 of residual overvoltage protection at side x of transformer starts. (n=1, 2)
Stage 1 of residual overvoltage protection at side x of transformer is enabled. (n=1,
2 x.59Gn.On
2)
Stage 1 of residual overvoltage protection at side x of transformer operates. (n=1,
3 x.59Gn.Op
2)
Stage 1 of residual overvoltage protection at side x of transformer picks up to
4 x.59Gn.TrigDFR
trigger DFR function. (n=1, 2)

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3.18.5 Logic

EN [x.59G1.En]
&
SIG x.59G1.En1
& x.59G1.On
SIG x.59G1.En2

SIG x.59G1.Blk

SIG x.59G1.U3P >=1 &


x.59Gn.St
SIG x.59G1.U1P
[x.59G1.t_Op] 0ms x.59G1.Op
SET [x.59G1.U_Set]

EN [x.59G2.En]
&
SIG x.59G2.En1
& x.59G2.On
SIG x.59G2.En2
Timer
SIG x.59G2.Blk t
x.59G2.Op
t
SIG x.59G2.U3P >=1 &
x.59G2.St
SIG x.59G2.U1P

SET [x.59G2.U_Set]

Figure 3.18-1 Logic diagram of residual overvoltage protection

3.18.6 Settings
Table 3.18-3 Settings of residual overvoltage protection

No. Item Range Step Unit Description


Voltage setting of stage 1 of residual
1 x.59G1.3U0_Set 2~200 0.001 V
overvoltage protection
Time delay of stage 1 of residual overvoltage
2 x.59G1.t_Op 0~3600 0.001 s
protection
Logic setting of enabling/disabling stage 1 of
residual overvoltage protection
3 x.59G1.En 0 or 1
0: disable
1: enable
Residual voltage option for the calculation of
stage 1 of residual overvoltage protection
4 x.59G1.Opt_3U0 0, 1 1
0: Measured residual voltage
1: Calculated residual voltage
Tripping logic setting of stage 1 of residual
5 x.59G1.OutMap 0000~FFFF
overvoltage protection
Voltage setting of stage 2 of residual
6 x.59G2.3U0_Set 2~200 0.001 V
overvoltage protection

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No. Item Range Step Unit Description


Multiplier of the maximum operating residual
7 x.59G2.K_3U0_Max 1~2 0.001 voltage to the pickup setting of stage 2 of
residual overvoltage protection
Time delay of stage 2 of residual overvoltage
8 x.59G2.t_Op 0~3600 0.001 s
protection
Minimum delay of stage 2 of residual
9 x.59G2.tmin 0~20s 0.001 s
overvoltage protection
Time multiplier setting of stage 2 of residual
10 x.59G2.TMS 0.05~3.2 0.001
overvoltage protection
The constant K of stage 2 of residual
11 x.59G2.K 0.0~120 0.001
overvoltage protection
The constant C stage 2 of residual overvoltage
12 x.59G2.C 0.0~20 0.001
protection
The exponent alpha stage 2 of residual
13 x.59G2.Alpha 0.02~5 0.001
overvoltage protection
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for stage 2 of
14 x.59G2.Opt_Curve
ANSIV residual overvoltage protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Logic setting of enabling/disabling stage 2 of
residual overvoltage protection
15 x.59G2.En 0 or 1
0: disable
1: enable
Residual voltage option for the calculation of
stage 2 of residual overvoltage protection
16 x.59G2.Opt_3U0 0, 1 1
0: Measured residual voltage
1: Calculated residual voltage
Tripping logic setting of stage 2 of residual
17 x.59G2.OutMap 0000~FFFF
overvoltage protection

NOTICE!

If the minimum operating time [x.59G2.tmin] is set to “0”, the maximum operating
voltage is valid, and the setting [x.59G2.K_3U0_Max] can be set according to

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requirements. If the residual voltage is greater than [x.59G2.K_3U0_Max] multiplying


[x.59G2.3U0_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point residual voltage equal to
[x.59G2.K_3U0_Max] multiplying [x.59G2.3U0_Set]. If [x.59G2.tmin] is not set to “0”,
then maximum operating voltage is not valid and users only can set the setting
[x.59G2.tmin].

3.19 Undervoltage Protection (27P)

3.19.1 Application

The increase of reactive power load leads to voltage decreasing, and voltage quality cannot be
satisfied only through AVR and OLTC. In this situation, undervoltage protection should operate to
shed part of loads to make voltage recovery to the normal level. Undervoltage protection includes
four stages definite-time undervoltage element with independent voltage and time delay settings,
and they can be blocked by the change rate of voltage.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.19.2 Function Description

Three-phase undervoltage caused by the lack of system reactive power is almost symmetrical and
does not change suddenly, so the undervoltage protection adopts the positive-sequence voltage
for the protection calculation. If negative-sequence voltage is greater than 0.15Un or
positive-sequence voltage changes suddenly, the undervoltage protection is blocked.

Undervoltage load shedding protection has the unique capability of fault distinguishing, and its
operating time does not need to coordinate with that of other protections, so undervoltage
protection can operate quickly when system voltage is low.

When a short circuit occurs in the power system, bus voltage will decreases suddenly and
therefore undervoltage protection should be blocked simultaneously. After other protections
operate to clear the fault, the voltage at the relay location recovers quickly. If the voltage cannot
recover to the normal operation value, but greater than the value of setting [x.27P.U_Recov],
blocking of undervoltage protection should be released at once, and the protection can operate to
shed corresponding loads to make voltage recovery. (When system voltage collapses, disappears
or decreases, voltage recovery is the progress that the system voltage recovers to rated voltage.)

In order to prevent undesired operation of undervoltage protection caused by abnormality


contestations such as load back feed, higher harmonics, voltage circuit failure etc., following
blocking criteria are equipped.

1. Undervoltage blocking

If positive-sequence voltage is lower than 0.15Un, undervoltage protection is blocked.

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2. Negative-sequence blocking

If negative-sequence voltage is greater than 0.15Un, undervoltage protection is blocked.

3. Change rate of voltage blocking

If the change rate of voltage (du/dt) is greater than the setting [x.27P.du/dt_Blk], undervoltage
protection is blocked and the blocking is not released until the system voltage greater than the
recovery voltage and above (setting [x.27P.U_Recov])

When any one criterion is met, undervoltage protection is blocked.

3.19.3 Function Block Diagram

27P

x.27P.U3P x.27P.UVn.St

x.27P.En1 x.27P.UVn.On

x.27P.En2 x.27P.UVn.Op

x.27P.Blk x.27P.Alm_Unrecov

3.19.4 I/O Signals


Table 3.19-1 I/O signals of undervoltage protection

No. Input signal Description


Three-phase voltage data input for undervoltage protection at side x of
1 x.27P.U3P
transformer.
Input signal 1 of enabling undervoltage protection at side x of transformer. It is
2 x.27P.En1
triggered from binary input or programmable logic etc.
Input signal 2 of enabling undervoltage protection at side x of transformer. It is
3 x.27P.En2
triggered from binary input or programmable logic etc.
Input signal of blocking undervoltage protection at side x of transformer. It is
4 x.27P.Blk
triggered from binary input or programmable logic etc.
No. Output signal Description
1 x.27P.UVn.St Stage n of undervoltage protection at side x of transformer starts. (n=1, 2, 3, 4)
Stage n of undervoltage protection at side x of transformer is enabled. (n=1, 2, 3,
2 x.27P.UVn.On
4)
3 x.27P.UVn.Op Stage n of undervoltage protection at side x of transformer operates. (n=1, 2, 3, 4)
The voltage at side x of transformer does not recover to normal level.
4 x.27P.Alm_Unrecov (If the voltage does not recover to the value greater than the setting
[x.27.U_Recov] after the time delay [x.27.t_Recov], alarm signal will be issued.)
Stage n of undervoltage protection at side x of transformer picks up to trigger DFR
5 x.27P.UVn.TrigDFR
function. (n=1, 2, 3, 4)

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3.19.5 Logic

SIG x.27P.En1
&
SIG x.27P.En2 Enable 27P

SIG x.27P.Blk

SIG x.Alm_VTS
>=1
SIG U1<0.15Un

SIG U2>0.15Un

SET -du/dt>[x.27P.du/dt_Blk] & >=1


Block 27P
EN [x.27P.En_du/dt_Blk]

SIG x.In_VT

SIG Enable 27P &

SIG Block 27P


&
SET U1<[x.27P.UV1.U_Set] x.27P.UV1.St

EN [x.27P.UV1.En] [x.27P.UV1.t_Op] 0ms x.27P.UV1.Op


&
x.27P.UV1.On

&
SET U1<[x.27P.UV2.U_Set] x.27P.UV2.St

EN [x.27P.UV2.En] [x.27P.UV2.t_Op] 0ms x.27P.UV2.Op


&
x.27P.UV2.On

&
SET U1<[x.27P.UV3.U_Set] x.27P.UV3.St

EN [x.27P.UV3.En] [x.27P.UV3.t_Op] 0ms x.27P.UV3.Op


&
x.27P.UV3.On

&
SET U1<[x.27P.UV4.U_Set] x.27P.UV4.St

EN [x.27P.UV4.En] [x.27P.UV4.t_Op] 0ms x.27P.UV4.Op


&
x.27P.UV4.On

Figure 3.19-1 Logic diagram of undervoltage protection

Where:

U1 is the positive sequence voltage.

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“x.In_VT” is the input signal indicating that VT at x side of transformer is in service. The signal can
be configured as a binary input according to user requirements, and if the binary input is not
configured, its default value is 1.

3.19.6 Settings
Table 3.19-2 Settings of undervoltage protection

No. Item Range Step Unit Description


du/dt blocking setting of undervoltage
1 x.27P.du/dt_Blk 0~100 0.001 V/s
protection
2 x.27P.U_Recov 10~100 0.001 V Lowest voltage threshold of fault recovery
Time setting of fault recovery
It should be greater than the operating time of
3 x.27P.t_Recov 0~20 0.001 s backup protection generally. For example, if the
longest operating time of backup protection is 4s,
the setting [x.27.t_Recov] can be set to “4.5s~5s”.
Voltage setting of stage 1 of undervoltage
4 x.27P.UV1.U_Set 10~100 0.001 V
protection
Time delay of stage 1 of undervoltage
5 x.27P.UV1.t_Op 0.05~100 0.001 s
protection
Logic setting of enabling/disabling du/dt
blocking function for stage 1 of undervoltage
6 x.27P.UV1.En_du/dt_Blk 0 or 1 protection
0: disable
1: enable
Logic setting of enabling/disabling stage 1 of
undervoltage protection
7 x.27P.UV1.En 0 or 1
0: disable
1: enable
Tripping logic setting of stage 1 of undervoltage
8 x.27P.UV1.OutMap 0000~FFFF
protection
Voltage setting of stage 2 of undervoltage
9 x.27P.UV2.U_Set 0~100 0.001 V
protection
Time delay of stage 2 of undervoltage
10 x.27P.UV2.t_Op 0.05~100 0.001 s
protection
Logic setting of enabling/disabling du/dt
blocking function for stage 2 of undervoltage
11 x.27P.UV2.En_du/dt_Blk 0 or 1 protection.
0: disable
1: enable
Logic setting of enabling/disabling stage 2 of
undervoltage protection.
12 x.27P.UV2.En 0 or 1
0: disable
1: enable

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No. Item Range Step Unit Description


Tripping logic setting of stage 2 of undervoltage
13 x.27P.UV2.OutMap 0000~FFFF
protection
Voltage setting of stage 3 of undervoltage
14 x.27P.UV3.U_Set 0~100 0.001 V
protection
Time delay of stage 3 of undervoltage
15 x.27P.UV3.t_Op 0.05~100 0.001 s
protection
Logic setting of enabling/disabling du/dt
blocking function for stage 3 of undervoltage
16 x.27P.UV3.En_du/dt_Blk 0 or 1 1 protection
0: disable
1: enable
Logic setting of enabling stage 3 of
undervoltage protection
17 x.27P.UV3.En 0 or 1 1
0: disable
1: enable
Tripping logic setting of stage 3 of undervoltage
18 x.27P.UV3.OutMap 0000~FFFF
protection
Voltage setting of stage 4 of undervoltage
19 x.27P.UV4.U_Set 0~100 0.001 V
protection
Time delay of stage 4 of undervoltage
20 x.27P.UV4.t_Op 0.05~100 0.001 s
protection
Logic setting of enabling/disabling stage 4 of
undervoltage protection
21 x.27P.UV4.En 0 or 1 1
0: disable
1: enable
Logic setting of enabling/disabling du/dt
blocking function for stage 4 of undervoltage
22 x.27P.UV4.En_du/dt_Blk 0 or 1 1 protection
0: disable
1: enable
Tripping logic setting of stage 4 of undervoltage
23 x.27P.UV4.OutMap 0000~FFFF
protection

3.20 Thermal Overload Protection (49)

3.20.1 Application

During overload operation of a power transformer, great current results in greater heat to lead
temperature of transformer increase and if the temperature reaches too high values, the
equipment might be damaged. The insulation within the transformer will have forced ageing. As a
consequence of this, the risk of internal phase-to-phase or phase-to-ground faults will increase.
High temperature will degrade the quality of the transformer oil.

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Thermal overload protection estimates the internal heat content of the transformer (temperature)
continuously. This estimation is made by using a thermal model of the transformer with two time
constants, which is based on current measurement.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.20.2 Function Description

The device provide two methods to fulfill thermal overload protection, one is to calculate thermal
accumulation according the actual measured current, and the other is to calculate temperature
difference between windings temperature and oil temperature to gain winding temperature by oil
temperature acquired by external transducer (PT100).

1. Method 1

Two stages overload protection are available, one stage for alarm purpose and the other stage for
trip purpose. When the temperature increases to the alarm value, thermal overload protection
issues alarm signal to remind the operator for attention, and if the temperature continues to
increase to the trip value, thermal overload protection issues trip command.

There are maximum three thermal overload protection elements equipped at each side of
transformer, and it is recommended to be equipped at the side without OLTC. Thermal overload
protection adopts IEC 60255-8 as thermal time characteristic, and fundamental current or 1st to 7th
harmonic current is used for protection calculation.

The device provides a thermal overload model which is based on the IEC60255-8 standard.

t Refer to IEC60255-8

Ip
P=—
IB

P = 0.0
P = 0.6
P = 0.8
P = 0.9

kIB I

Figure 3.20-1 Characteristic curve of thermal overload protection

There are two types of thermal time characteristic, cold start characteristic and hot start
characteristic. The thermal overload formulas are shown as below.

1. Cold start characteristic

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2
I eq
t    ln Equation 3.20-1
2
I eq  (k  I B ) 2

2. Hot start characteristic

2
I eq  I 2p
t    ln Equation 3.20-2
2
I eq  (k  I B ) 2

Where:

t is the theoretical operate time, following application of the overload current.

τ is the heating thermal time constant of the protected device, i.e. [x.49.Tau].

Ieq is the equivalent heating current, i.e. actual measured current.

IP is the steady-state load current prior to the overload for a duration which would result in
constant thermal level (duration is greater than several time constant τ), which is memory current.
For cold start characteristic, it is zero.

ln is natural logarithm

IB is the base current, i.e. [x.49.Ib_Set].

k is thermal overload coefficient, i.e. [x.49.K_Alm] or [x.49.K_Trp].

The hot start characteristic is adopted in the device. The calculation is carried out at zero of IP, so
users need not to set the value of IP.

Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.

2. Method 2

The actual windings temperature can be gained by oil temperature, which is measured by external
transducer (PT100), plus temperature difference between windings temperature and oil
temperature, i.e.,

T_windings (windings temperature) = T_oil (oil temperature) + T_Diff (temperature difference


between windings and oil)

The temperature difference can be calculated according to the current, and is changed with the
current. When the current is increased from 0 to I, the temperature accumulation complies with the
following equation.

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Finally, stable temperature difference:

Where:

I is the measured current

α is cooling factor, taking 1.6 or 2

t is time

Tau is time constant

According to the calculated windings temperature, the user can compare it with user-defined
temperature value, and can set stage and time delay to trip or alarm by user-defined logic.

3.20.3 Function Block Diagram

49

x.49.I3P x.49.St

x.49.En1 x.49.On

x.49.En2 x.49.Op

x.49.Blk x.49.Alm

3.20.4 I/O Signals


Table 3.20-1 I/O signals of thermal overload protection

No. Input signal Description


Three-phase current data input for thermal overload protection at side x of
1 x.49.I3P
transformer or reactor.
Clear command of thermal accumulation value for thermal overload protection at
2 x.49.Clr
side x of transformer or reactor.
Input signal 1 of enabling thermal overload protection at side x of transformer or
3 x.49.En1
reactor. It is triggered from binary input or programmable logic etc.
Input signal 2 of enabling thermal overload protection at side x of transformer or
4 x.49.En2
reactor. It is triggered from binary input or programmable logic etc.
Input signal of blocking thermal overload protection at side x of transformer or
5 x.49.Blk
reactor. It is triggered from binary input or programmable logic etc.
No. Output signal Description
1 x.49.St Thermal overload protection at side x of transformer or reactor starts.
2 x.49.On Thermal overload protection at side x of transformer or reactor is enabled.
3 x.49.Op Thermal overload protection at side x of transformer or reactor operates to trip.

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No. Input signal Description


4 x.49.Alm Thermal overload protection at side x of transformer or reactor operates to alarm.
Thermal overload protection at side x of transformer or reactor picks up to trigger
5 x.49.TrigDFR
DFR function.
The calculated temperature difference of phase-A between winding temperature
6 x.49.T_Diff_A
and oil temperature.
The calculated temperature difference of phase-B between winding temperature
7 x.49.T_Diff_B
and oil temperature.
The calculated temperature difference of phase-C between winding temperature
8 x.49.T_Diff_C
and oil temperature.

3.20.5 Logic

>=1
&
SIG x.49.En1
& x.49.On
SIG x.49.En2

SIG x.49.Blk
&
SIG x.49.I3P x.49.St

& Timer
SET [x.49.Ib_Set] t
x.49.Alm
t
EN [x.49.En_Alm]

& Timer
t
x.49.Op
t
EN [x.49.En_Trp]

SIG x.49.Clr

Figure 3.20-2 Logic diagram of thermal overload protection (method 1)

3.20.6 Settings
Table 3.20-2 Settings of thermal overload protection

No. Item Range Step Unit Description


Tripping setting of thermal capacity for thermal
1 x.49.K_Trp 1~3 0.001
overload protection
Alarm setting of thermal capacity for thermal
2 x.49.K_Alm 1~3 0.001
overload protection
Base current setting of thermal overload
3 x.49.Ib_Set 0.04~30In 0.001 A
protection
4 x.49.Tau 0.1~100 0.001 min Thermal time constant
The convertor coefficient from the current to the
5 x.49.K_T_Diff 0~200 0.001
temperature
6 x.49.Alpha_Cold 1~2 0.001 The cooling mode of transformer, usually,

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No. Item Range Step Unit Description


natural cooling: 1.6
forced cooling: 2
Logic setting of enabling/disabling thermal
overload protection operate to trip
7 x.49.En_Trp 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling thermal
overload protection operate to alarm
8 x.49.En_Alm 0 or 1
0: disable
1: enable
Tripping logic setting of thermal overload
9 x.49.OutMap 0000~FFFF
protection

3.21 Breaker Failure Protection (50BF)

3.21.1 Application

Breaker failure protection is applied to inter-trip each side of transformer when initiation signals of
breaker failure protection from busbar protection or other device are received. When the binary
input of external tripping is energized and current element picks up, a trip command will be issued
with a time delay to trip circuit breakers at each side of transformer. PCS-978 can provide two the
same breaker failure protection modules for two branches application at each side. However, the
second breaker failure protection module is disabled by default, which can be enabled by
PCS-Explorer.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.21.2 Function Description

The device provides four kinds of current criteria including phase current criterion, zero-sequence
current criterion, negative-sequence current criterion and DPFC current criterion. If any current
criterion is satisfied, current element of breaker failure protection picks up.

1. Phase current criterion

IΦ_max>[x.50BF.I_Set] Equation 3.21-1

Where:

IΦ_max is the maximum value of three phase-current of some side.

2. Zero-sequence current criterion

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3I0>[x.50BF.3I0_Set] Equation 3.21-2

Where:

3I0 is three times calculated zero-sequence current of some side.

3. Negative-sequence current criterion

I2>[x.50BF.I2_Set] Equation 3.21-3

Where:

I2 is negative-sequence current of some side.

4. DPFC current criteria

ΔI>1.25×ΔIt+Ith Equation 3.21-4

Where:

ΔIt is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold current is slightly
greater than the unbalance current, multiple 1.25 of the deviation component is reasonable.

ΔI is the half-wave calculated of phase-to-phase current.

Ith is the fixed threshold of 0.1p.u. and does not need to be set on site.

3.21.3 Function Block Diagram

50BF

x.50BF.I3P x.50BF.St

x.50BF.Init x.50BF.On_t1

x.50BF.En1 x.50BF.On_t2

x.50BF.En2 x.50BF.Op_t1

x.50BF.Blk x.50BF.Op_t2

x.50BF.Alm_Init

x.50BF.Alm_Curr

3.21.4 I/O Signals


Table 3.21-1 I/O signals of breaker failure protection

No. Input signal Description


1 x.50BF.I3P Three-phase current data input for breaker failure protection at side x of

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No. Input signal Description


transformer.
2 x.50BF.Init Input signal of initiating breaker failure protection at side x of transformer.
Input signal of normally open auxiliary contact of circuit breaker at side x of
3 x.52b
transformer.
Input signal 1 of enabling breaker failure protection at side x of transformer. It is
4 x.50BF.En1
triggered from binary input or programmable logic etc.
Input signal 2 of enabling breaker failure protection at side x of transformer. It is
5 x.50BF.En2
triggered from binary input or programmable logic etc.
Input signal of blocking breaker failure protection at side x of transformer. It is
6 x.50BF.Blk
triggered from binary input or programmable logic etc.
No. Output signal Description
1 x.50BF.St Breaker failure protection at side x of transformer starts.
2 x.50BF.On_t1 Breaker failure protection with the time delay 1 at side x of transformer is enabled.
3 x.50BF.On_t2 Breaker failure protection with the time delay 2 at side x of transformer is enabled.
4 x.50BF.Op_t1 Breaker failure protection at side x of transformer operates with the time delay 1.
5 x.50BF.Op_t2 Breaker failure protection at side x of transformer operates with the time delay 2.
The duration of input signal of initiating breaker failure protection at side x of
6 x.50BF.Alm_Init
transformer is over 3s.
The current criterion of breaker failure protection at side x of transformer is
7 x.50BF.Alm_Curr
satisfied for over 3s.
8 x.50BF.TrigDFR Breaker failure protection at side x of transformer picks up to trigger DFR function.

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3.21.5 Logic

SIG x.50BF.Init
&
EN [x.50BF.En_CB_Ctrl] &

SIG x.50BF.FD

SIG x.52b

SIG IΦ_max>0.06In

SET [x.50BF.En_Ip] & >=1


>=1 &
SET IΦ_max>[x.50BF.Ip_Set] >=1

EN [x.50BF.En_3I0] &

SET 3I0>[x.50BF.3I0_Set]

EN [x.50BF.En_I2] &
>=1
SET I2>[x.50BF.I2_Set]

EN [x.50BF.En_DPFC] &

SIG ΔI>1.25ΔIt+Ith

SIG x.50BF.Blk [x.50BF.t1_Op] 0ms x.50BF.Op_t1


& &
SIG x.50BF.En1 x.50BF.St
&
SIG x.50BF.En2
x.50BF.On_t1
&
EN [x.50BF.En_t1]
x.50BF.St
&
[x.50BF.t2_Op] 0ms x.50BF.Op_t2
x.50BF.On_t2
EN [x.50BF.En_t2]

Figure 3.21-1 Logic diagram of breaker failure protection

Where:

In is rated secondary current of CT.

IΦ_max is the maximum value of three phase-current of x side.

3I0 is calculated residual current.

I2 is negative-sequence current.

“x.50BF.FD” means that the fault detector of breaker failure protection of x side picks up.

3.21.6 Settings
Table 3.21-2 Settings of breaker failure protection

No. Item Range Step Unit Description


1 x.50BF.Ip_Set 0.04~30In 0.001 A Current setting of phase current criterion.
2 x.50BF.3I0_Set 0.04~30In 0.001 A Current setting of residual current criterion.
3 x.50BF.I2_Set 0.04~30In 0.001 A Current setting of negative-sequence current

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No. Item Range Step Unit Description


criterion.
Logic setting of enabling/disabling phase current
criterion to control breaker failure protection
4 x.50BF.En_Ip 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling
negative-sequence current criterion to control
5 x.50BF.En_I2 0 or 1 breaker failure protection.
0: disable
1: enable
Logic setting of enabling/disabling DPFC current
criterion to control breaker failure protection.
6 x.50BF.En_DPFC 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling
residual-sequence current criterion to control
7 x.50BF.En_3I0 0 or 1 breaker failure protection.
0: disable
1: enable
8 x.50BF.t1_Op 0~20 0.001 s Time delay 1 of breaker failure protection.
To enable the criterion of CB position for breaker
failure protection.
9 x. 50BF.En_CB_Ctrl 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling time delay 1
of breaker failure protection.
10 x.50BF.En_t1 0 or 1
0: disable
1: enable
Tripping logic setting of time delay 1 of breaker
11 x.50BF.OutMap_t1 0000~FFFF
failure protection.
12 x.50BF.t2_Op 0~20 0.001 s Time delay 2 of breaker failure protection.
Logic setting of enabling/disabling time delay 2
of breaker failure protection.
13 x.50BF.En_t2 0 or 1
0: disable
1: enable
Tripping logic setting of time delay 2 of breaker
14 x.50BF.OutMap_t2 0000~FFFF
failure protection

3.22 Pole Disagreement Protection (62PD)

3.22.1 Application
With voltage level involved, the switching equipment usually consists of single pole devices that

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are not mechanically linked, with each pole having an independent operating mechanism. With
such an arrangement, the possibility exists that one pole may not operate coincidentally with the
other poles, thus creating an undesirable imbalance in system voltages or, in case the switching
equipment were called upon to clear a fault, might fail to remove the faulted source from service.
So that if a pole disagreement fault is detected, after a certain delay, the device will initiate a trip
command to trip all poles of the switching equipment.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.22.2 Function Description

There are two current control elements for pole disagreement protection: residual current element
and negative-sequence current element which are configurable by logic settings and are “OR”
relation to release pole disagreement protection. The input signal of pole disagreement position,
“62PD.In_PD_CB”, is used to initiate pole disagreement protection.

3.22.3 Function Block Diagram

62PD

x.62PD.I3P x.62PD.St

x.62PD.In_PD_CB x.62PD.On

x.62PD.En1 x.62PD.Op

x.62PD.En2 x.62PD.Alm

x.62PD.Blk

3.22.4 I/O Signals


Table 3.22-1 I/O signals of pole disagreement protection

No. Input signal Description


Three-phase current data input for pole disagreement protection at side x of
1 x.62PD.I3P
transformer.
2 x.62PD.In_PD_CB Input signal of indicating pole disagreement state at side x of transformer.
Input signal 1 of enabling pole disagreement protection at side x of transformer. It
3 x.62PD.En1
is triggered from binary input or programmable logic etc.
Input signal 2 of enabling pole disagreement protection at side x of transformer. It
4 x.62PD.En2
is triggered from binary input or programmable logic etc.
Input signal of blocking pole disagreement protection at side x of transformer. It is
5 x.62PD.Blk
triggered from binary input or programmable logic etc.
No. Output signal Description
1 x.62PD.St Pole disagreement protection at side x of transformer starts.
2 x.62PD.On Pole disagreement protection at side x of transformer is enabled.

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No. Input signal Description


3 x.62PD.Op Pole disagreement protection at side x of transformer operates to trip.
4 x.62PD.Alm Pole disagreement protection at side x of transformer operates to alarm.
Pole disagreement protection at side x of transformer picks up to trigger DFR
5 x.62PD.TrigDFR
function.

3.22.5 Logic

SIG 62PD.In_PD_CB

SET 3I0>[x.62PD.3I0_Set] &

EN [x.62PD.En_3I0]
>=1 >=1 &
x.62PD.St

[x.62PD.t_Op] 0ms x.62PD.Op


SET I2>[x.62PD.I2_Set] &

EN [x.62PD.En_I2]

SIG x.62PD.Blk
&
SIG x.62PD.En1 &
x.62PD.On
SIG x.62PD.En2

EN [x.62PD.En]

SIG x.62PD.In_PD_CB [x.62PD.t_Alm] 0ms x.62PD.Alm

Figure 3.22-1 Logical diagram of pole disagreement protection

Where:

3I0 is calculated residual current.

I2 is negative-sequence current.

3.22.6 Settings
Table 3.22-2 Settings of pole disagreement protection

No. Item Range Step Unit Description


Residual current setting of pole disagreement
1 x.62PD.3I0_Set 0.04~30In 0.001 A
protection
Negative-sequence current setting of pole
2 x.62PD.I2_Set 0.04~30In 0.001 A
disagreement protection
Time delay of pole disagreement protection for
3 x.62PD.t_Op 0~20 0.001 s
trip purpose
Time delay of pole disagreement protection for
4 x.62PD.t_Alm 0~20 0.001 s
alarm purpose
5 x.62PD.En_3I0 0 or 1 1 Logic setting of enabling/disabling residual

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No. Item Range Step Unit Description


current criterion to control pole disagreement
protection
0: disable
1: enable
Logic setting of enabling/disabling
negative-sequence current criterion to control
6 x.62PD.En_I2 0 or 1 1 breaker failure protection
0: disable
1: enable
Logic setting of enabling/disabling pole
disagreement protection
7 x.62PD.En_PD 0 or 1 1
0: disable
1: enable
Tripping logic setting of pole disagreement
8 x.62PD.OutMap 0000~FFFF
protection

3.23 Phase Overcurrent Alarm (51PAlm)

3.23.1 Application
During overload operation of a power transformer, great current results in greater heat to lead
temperature of transformer increase and if the temperature reaches certain values, the
transformer might be damaged. The insulation within the transformer will have forced ageing.

Phase overcurrent alarm is equipped to monitor the load of transformer winding, and when load
current exceeds the transformer limit load current, phase overcurrent alarm can be applied to
issue alarm signal to remind field operators. Besides, during overload of transformer, it is needed
to initiate cooling system (such as cooling fan) and blocking OLTC. Therefore phase overcurrent
alarm can also be applied to initiate cooling system and block OLTC.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.23.2 Function Description

Phase overcurrent alarm provides two-stage definite-time phase overcurrent alarm elements with
independent logic, current and time delay settings. Phase overcurrent alarm is only applied for
alarm signals. Fundamental current or 1st to 7th harmonic current is used for protection
calculation.

The operation criterion:

IP>[51PAlmn.I_Set] Equation 3.23-1

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Where:

IP is phase current.

3.23.3 Function Block Diagram

51PAlm

x.51PAlmn.I3P x.51PAlmn.St

x.51PAlmn.En1 x.51PAlmn.On

x.51PAlmn.En2 x.51PAlmn.Alm

x.51PAlmn.Blk

3.23.4 I/O Signals


Table 3.23-1 I/O signals of phase overcurrent alarm

No. Input signal Description


Three-phase current data input for stage n of phase overcurrent alarm at side x of
1 x.51PAlmn.I3P
transformer. (n=1, 2)
Input signal 1 of enabling stage n of phase overcurrent alarm at side x of
2 x.51PAlmn.En1
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
Input signal 2 of enabling stage n of phase overcurrent alarm at side x of
3 x.51PAlmn.En2
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
Input signal of blocking stage n of phase overcurrent alarm at side x of transformer.
4 x.51PAlmn.Blk
It is triggered from binary input or programmable logic etc. (n=1, 2)
No. Output signal Description
1 x.51PAlmn.St Stage n of phase overcurrent alarm at side x of transformer starts. (n=1, 2)
2 x.51PAlmn.On Stage n of phase overcurrent alarm at side x of transformer is enabled. (n=1, 2)
Stage n of phase overcurrent alarm at side x of transformer operates to alarm.
3 x.51PAlmn.Alm
(n=1, 2)

3.23.5 Logic

EN [x.51PAlmn.En]
&
SIG x.51PAlmn.En1
& x.51PAlmn.On
SIG x.51PAlmn.En2

SIG x.51PAlmn.Blk
&
SIG x.51PAlmn.I3P x.51PAlmn.St

[x.51PAlmn.t_Op] 0ms x.51PAlmn.Alm


SET [x.51PAlmn.I_Set]

Figure 3.23-1 Logic diagram of phase overcurrent alarm (n=1, 2)

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3.23.6 Settings
Table 3.23-2 Settings of phase overcurrent alarm

No. Item Range Step Unit Description


Current setting of stage n of phase overcurrent
1 x.51PAlmn.I_Set 0.04A~30In 0.001 A
alarm (n=1, 2)
Time delay of stage n of phase overcurrent
2 x.51PAlmn.t_Op 0~3600 0.001 s
alarm (n=1, 2)
Drop off ratio of stage n of phase overcurrent
3 x.51PAlmn.K_DropOut 0.7~1.0 0.001
alarm (n=1, 2)
Logic setting of enabling/disabling stage n of
phase overcurrent alarm (n=1, 2)
4 x.51PAlmn.En 0 or 1
0: disable
1: enable

3.24 Residual Overvoltage Alarm (59GAlm)

3.24.1 Application
A single phase earth fault occurrence in ungrounded system will result in high residual overvoltage,
so residual overvoltage alarm is equipped to issue alarm signal to remind the operators in this
condition.

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

3.24.2 Function Description


Only one-stage residual overvoltage alarm is equipped, it can be selected as definite-time or
inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.

3.24.2.1 Operation Criterion

3U0>[x.59GAlm.3U0_Set] Equation 3.24-1

Where:

3U0 is measured residual voltage.

3.24.2.2 Time Curve

Residual overvoltage alarm can be selected as definite-time or inverse-time characteristic, and


inverse-time operating time curve is as follows.

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Equation 3.24-2

Where:

Uset is residual voltage setting [x.59GAlm.3U0_Set].

Tp is time setting [x.59GAlm.TMS].

K and C are constants.

α is a constant

U is actual measured residual voltage.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.59GAlm.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.

Table 3.24-1 Inverse-time curve parameters

x.59GAlm.Opt_Curve Time Characteristic K α C


DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined

If all available curves do not comply with user application, user may configure setting [x.
59GAlm.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.

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3.24.3 Function Block Diagram

59GAlm

x.59GAlm.U3P x.59GAlm.St

x.59GAlm.U1P x.59GAlm.On

x.59GAlm.En1 x.59GAlm.Alm

x.59GAlm.En2

x.59GAlm.Blk

3.24.4 I/O Signals


Table 3.24-2 I/O signals of residual overvoltage alarm

No. Input signal Description


Three-phase voltage data input for residual overvoltage alarm at side x of
1 x.59GAlm.U3P
transformer.
Measured residual voltage data input for residual overvoltage alarm at side x of
2 x.59GAlm.U1P
transformer.
Input signal 1 of enabling residual overvoltage alarm at side x of transformer. It is
3 x.59GAlm.En1
triggered from binary input or programmable logic etc.
Input signal 2 of enabling residual overvoltage alarm at side x of transformer. It is
4 x.59GAlm.En2
triggered from binary input or programmable logic etc.
Input signal of blocking residual overvoltage alarm at side x of transformer. It is
5 x.59GAlm.Blk
triggered from binary input or programmable logic etc.
No. Output signal Description
1 x.59GAlm.St Residual overvoltage alarm at side x of transformer starts.
2 x.59GAlm.On Residual overvoltage alarm at side x of transformer is enabled.
3 x.59GAlm.Alm Residual overvoltage alarm at side x of transformer operates to alarm.

3.24.5 Logic

EN [x.59GAlm.En]
&
SIG x.59GAlm.En1
& x.59GAlm.On
SIG x.59GAlm.En2

SIG x.59GAlm.Blk

SIG x.59GAlm.U3P >=1 &


x.59GAlm.St
SIG x.59GAlm.U1P Timer
t x.59GAlm.Alm
t
SET [x.59GAlm.3U0_Set]

Figure 3.24-1 Logic diagram of residual overvoltage alarm

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3 Operation Theory

3.24.6 Settings
Table 3.24-3 Settings of residual overvoltage alarm

No. Item Range Step Unit Description


1 x.59GAlm.3U0_Set 2~200 0.001 V Voltage setting of residual overvoltage alarm
2 x.59GAlm.t_Alm 0~3600 0.001 s Time delay of residual overvoltage alarm
Multiplier of the maximum operating residual
3 x.59GAlm.K_3U0_Max 1~2 0.001 voltage to the pickup setting of residual
overvoltage alarm
4 x. 59GAlm.tmin 0~20 0.001 s Minimum delay of residual overvoltage alarm
Time multiplier setting of residual overvoltage
5 x. 59GAlm.TMS 0.05~3.2 0.001
alarm
6 x. 59GAlm.K 0.0~120 0.001 The constant K of residual overvoltage alarm
7 x. 59GAlm.C 0.0~20 0.001 s The constant C of residual overvoltage alarm
The exponent alpha of residual overvoltage
8 x. 59GAlm.Alpha 0.02~5 0.001
alarm
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for residual
9 x. 59GAlm.Opt_Curve
ANSIV overvoltage alarm
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Logic setting of enabling/disabling residual
overvoltage alarm
10 x.59GAlm.En 0 or 1
0: disable
1: enable
Option of residual voltage for residual
overvoltage alarm
11 x.59GAlm.Opt_3U0 0, 1 1
0: Measured residual voltage
1: Calculated residual voltage

3.25 Mechanical Protection (MR)

3.25.1 Application

If there is a fault in transformer body, winding temperature relay, oil temperature relay and

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Buchholz relay (or called gas relay) integrated in transformer will operate to send signals to
PCS-978. Mechanical protection will repeat these signals to send alarm signals, or send tripping
command directly or send tripping command with time delay to prevent transformer from damage.
Inputs of mechanical protection are operation signals of transformer's integrated relay, and it is
generally required to repeat those signals through high-power relays to improve the anti-inference
ability of the protection.

3.25.2 Function Description

Mechanical protection provides 4 mechanical signal input channels for tripping directly or with time
delay. It adopts high-power relays d to improve the anti-interference ability of mechanical
protection. If 110Vac (or 220Vac) voltage is connected to the signal input terminal of mechanical
relay, mechanical protection does not maloperate by mistake.

Mechanical relay repeats external signal through high-power relays and send them to CPU
through opto-coupler circuits. After CPU receives those signals, the device will record them as
events and send tripping command with settable time delays. Because the dropoff time of
mechanical input signals is usually too long, the setting [MR.t_PW_n] (n=1, 2, 3, and 4) can be set
to avoid mechanical relay sending long-time tripping command.

3.25.3 Function Block Diagram

MR

MR.Input1 MR.Sig1

MR.Input2 MR.Sig2

MR.Input3 MR.Sig3

MR.Input4 MR.Sig4

MR.En1 MR.On1

MR.En2 MR.On2

MR.Blk MR.On3

MR.On4

MR.Op1

MR.Op2

MR.Op3

MR.Op4

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3.25.4 I/O Signals


Table 3.25-1 I/O signals of mechanical protection

No. Input signal Description


1 MR.Input1 Input signal 1 of mechanical relay.
2 MR.Input2 Input signal 2 of mechanical relay.
3 MR.Input3 Input signal 3 of mechanical relay.
4 MR.Input4 Input signal 4 of mechanical relay.
Input signal 1 of enabling mechanical protection. It is triggered from binary input or
5 MR.En1
programmable logic etc.
Input signal 2 of enabling mechanical protection. It is triggered from binary input or
6 MR.En2
programmable logic etc.
Input signal of blocking mechanical protection. It is triggered from binary input or
7 MR.Blk
programmable logic etc.
No. Output signal Description
1 MR.Sig1 Repeating output signal 1 of mechanical relay.
2 MR.Sig2 Repeating output signal 2 of mechanical relay.
3 MR.Sig3 Repeating output signal 3 of mechanical relay.
4 MR.Sig4 Repeating output signal 4 of mechanical relay.
5 MR.On1 Input signal 1 of mechanical relay is enabled.
6 MR.On2 Input signal 2 of mechanical relay is enabled.
7 MR.On3 Input signal 3 of mechanical relay is enabled.
8 MR.On4 Input signal 4 of mechanical relay is enabled.
9 MR.Op1 Input signal 1 of mechanical relay operates.
10 MR.Op2 Input signal 2 of mechanical relay operates.
11 MR.Op3 Input signal 3 of mechanical relay operates.
12 MR.Op4 Input signal 4 of mechanical relay operates.

3.25.5 Logic

EN [MR.En_1]
&
SIG MR.En1
& MR.On1
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_1] MR.Op1
SIG MR.Input1

EN [MR.En_2]
&
SIG MR.En1
& MR.On2
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_2] MR.Op2
SIG MR.Input2

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EN [MR.En_3]
&
SIG MR.En1
& MR.On3
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_3] MR.Op3
SIG MR.Input3

EN [MR.En_4]
&
SIG MR.En1
& MR.On4
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_4] MR.Op4
SIG MR.Input4

Figure 3.25-1 Logic diagram of mechanical protection

3.25.6 Settings
Table 3.25-2 Settings of mechanical protection

No. Item Range Step Unit Description


Delay pickup time of tripping command of
1 MR.t_DPU_1 0~3600 0.001 s
mechanical relay 1
Pulse width of tripping command of mechanical
2 MR.t_PW_1 0~10 0.001 s
relay 1
Logic setting of enabling/disabling mechanical
relay 1
3 MR.En_1 0 or 1
0: disable
1: enable
4 MR.OutMap_1 0000~FFFF Tripping logic setting of mechanical relay 1
Delay pickup time of tripping command of
5 MR.t_DPU_2 0~3600 0.001 s
mechanical relay 2
Pulse width of tripping command of mechanical
6 MR.t_PW_2 0~10 0.001 s
relay 2
Logic setting of enabling/disabling mechanical
relay 2
7 MR.En_2 0 or 1
0: disable
1: enable
8 MR.OutMap_2 0000~FFFF Tripping logic setting of mechanical relay 2
Delay pickup time of tripping command of
9 MR.t_DPU_3 0~3600 0.001 s
mechanical relay 3
Pulse width of tripping command of mechanical
10 MR.t_PW_3 0~10 0.001 s
relay 3
11 MR.En_3 0 or 1 Logic setting of enabling/disabling mechanical

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No. Item Range Step Unit Description


relay 3
0: disable
1: enable
12 MR.OutMap_3 0000~FFFF Tripping logic setting of mechanical relay 3
Delay pickup time of tripping command of
13 MR.t_DPU_4 0~3600 0.001 s
mechanical relay 4
Pulse width of tripping command of mechanical
14 MR.t_PW_4 0~10 0.001 s
relay 4
Logic setting of enabling/disabling mechanical
relay 4
15 MR.En_4 0 or 1
0: disable
1: enable
16 MR.OutMap_4 0000~FFFF Tripping logic setting of mechanical relay 4

3.26 Temperature Protection (26)

3.26.1 Application
Temperature protection is applied for protecting transformer or reactor from being damaged by
over temperature due to overloads or other reasons.

3.26.2 Function Description


It can receive 6 DC signals (0~20mA or 0~5V) from external temperature transducers to convert to
temperature values.

NOTICE!

Analog inputs between 0~4mA DC can also be processed, and all the analog inputs
between 0~4mA DC will be processed as 4mA. Therefore, 0~20mA analog DC input
can be processed.

The device can receive signals from external temperature transducers and convert these signals
into digital data as required via DC plug-in module NR1410B. The actual operation temperature of
a transformer can be calculated with the following equation after setting the range of temperature
measurement (minimum temperature setting corresponds to 4mA or 0V, and maximum
temperature setting corresponds to 20mA or 5V).

Equation 3.26-1

Where:

Cmin is the minimum measured value.

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Tmin is the temperature corresponding to minimum measured value.

CC is actual measured value.

Cmax and Tmax are maximum measured value and the temperature corresponding to it respectively.

K is the slope of temperature converting

T is the actual temperature after converting.

When the maximum value, among three phase temperature values of transformer corresponding
to three transducer inputs, is greater than the setting for trip purpose, temperature protection
operate to trip circuit breakers. The operation criterion is as follows.

T>[26.T_Trp] Equation 3.26-2

Where:

T is maximum value among three phase temperature values of transformer corresponding to three
transducer inputs.

[26.T_Trp] is the temperature setting for tripping of temperature protection.

When the maximum value, among three phase temperature values of transformer corresponding
to three transducer inputs, is greater than the setting for alarm purpose, temperature protection
operates to issue the related alarm signal. The operation criterion is as follows.

T>[26.T_Alm] Equation 3.26-3

Where:

T is maximum value among three phase temperature values of transformer corresponding to three
transducer inputs.

[26.T_Alm] is the temperature setting for alarming of temperature alarm element.

3.26.3 Function Block Diagram

26

26.Input_PhA 26.T_PhA

26.Input_PhB 26.T_PhB

26.Input_PhC 26.T_PhC

26.En1 26.St

26.En2 26.On

26.Blk 26.Op

26.Alm

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3.26.4 I/O Signals


Table 3.26-1 I/O signals of temperature protection

No. Input signal Description


1 26.Input_PhA DC input signal of phase A from external transducer.
2 26.Input_PhB DC input signal of phase B from external transducer.
3 26.Input_PhC DC input signal of phase C from external transducer.
Input signal 1 of enabling temperature protection. It is triggered from binary input or
4 26.En1
programmable logic etc.
Input signal 2 of enabling temperature protection. It is triggered from binary input or
5 26.En2
programmable logic etc.
Input signal of blocking temperature protection. It is triggered from binary input or
6 26.Blk
programmable logic etc.
No. Output signal Description
1 26.T_PhA Calculated temperature of phase-A signal from external transducer.
2 26.T_PhB Calculated temperature of phase-B signal from external transducer.
3 26.T_PhC Calculated temperature of phase-C signal from external transducer.
4 26.St Temperature protection starts.
5 26.On Temperature protection is enabled.
6 26.Op Temperature protection operates to trip.
7 26.Alm Temperature protection operates to alarm.
8 26.TrigDFR Temperature protection picks up to trigger DFR function.

3.26.5 Logic

SIG T_PhA>[26.T_Trp]
>=1
SIG T_PhB>[26.T_Trp] &
[26.t_Trp] 0s 26.Op
SIG T_PhC>[26.T_Trp]
26.St
EN [26.En_Trp]
&
SIG 26.En1
& 26.On
SIG 26.En2

SIG 26.Blk &


26.On
EN [26.En_Alm]

SIG 26.Blk
&
SIG T_PhA>[26.T_Alm]
>=1 [26.t_Alm] 0s 26.Alm
SIG T_PhB>[26.T_Alm]

SIG T_PhC>[26.T_Alm]

Figure 3.26-1 Logic diagram of temperature protection

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3.26.6 Settings
Table 3.26-2 Settings of temperature protection

No. Item Range Step Unit Description


Temperature setting corresponding to the
1 26.Tmax 0~200 0.01 °C
maximum input
Temperature setting corresponding to the
2 26.Tmin 0~200 0.01 °C
minimum input
Temperature setting for trip purpose of
3 26.T_Trp 0~200 0.01 °C
temperature protection
Temperature setting for alarm purpose of
4 26.T_Alm 0~200 0.01 °C
temperature alarm element
Time delay for trip purpose of temperature
5 26.t_Trp 0.01~4800 0.001 s
protection
Time delay for alarm purpose of temperature
6 26.t_Alm 0.01~4800 0.001 s
protection
Logic setting of enabling/disabling temperature
protection for trip purpose
7 26.En_Trp 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling temperature
protection for alarm purpose
8 26.En_Alm 0 or 1
0: disable
1: enable
9 26.OutMap 0000~FFFF Tripping logic setting of temperature protection
Input option of temperature transducer
0~5V Input signal from Pt100 sensors, i.e., the nominal
10 26.Opt_Input_T 0~20mA 1 resistance of 100 ohms at 0 °C (Pt is the symbol
Pt100 for platinum, 100 for the resistance in ohm at
0 °C).

3.27 Output Map (OutMap)

3.27.1 Application
Output map controls tripping outputs of protection elements and programmable logics. Each
protection element has its corresponding tripping logic setting used to configure tripping output
contacts, and 10 tripping outputs of programmable logics are equipped for visual logic
programming.

3.27.2 Function Description


All tripping output contacts are with a dwell time of 120ms (fixed in program) to ensure sufficient
time of tripping command to open the circuit breaker.

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3.27.2.1 Protection Element Trip Output

For default configuration, each protection element can control total 10 groups of tripping output
contacts by tripping logic settings. Therefore, the user can configure the tripping output contacts of
each protection element individually though the corresponding tripping logic setting. 10 groups of
independent tripping output contacts can be defined to trip HV side, MV side, and LVS side etc.
Each group of tripping contacts can correspond to certain amount of contacts on binary output
plug-in modules.

Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 16 binary bits as follows and is expressed by a
hexadecimal number of 4 digits from 0000H to FFFFH. The tripping logic setting is specified as
follows:

Bit Definition Bit Definition


0 TrpOutput01 8 TrpOutput09
1 TrpOutput02 9 TrpOutput10
2 TrpOutput03 10 TrpOutput11
3 TrpOutput04 11 TrpOutput12
4 TrpOutput05 12 TrpOutput13
5 TrpOutput06 13 TrpOutput14
6 TrpOutput07 14 TrpOutput15
7 TrpOutput08 15 TrpOutput16

“TrpOutput01” just means to drive 1st group of tripping output contacts and please refer to Chapter
“Hardware”. The tripping outputs are recorded as “T01~T16” by the device when they operate, and
“Txx” (xx=01, 02…16) represents “trip output xx” (xx=01, 02…16). The circuit breaker
corresponding with bit which is set as “1” will be tripped. Tripping output logic settings should be
set on basis of application-specific drawings.

For example, if transformer differential protection operates to make “TrpOutput01”, “TrpOutput02”,


“TrpOutput03” contacts pickup, bit “0”, bit “1” and bit “2” shall be filled with “1” and other bits shall
be filled with “0”. Then a hexadecimal number 0007H is formed as the tripping output logic setting,
i.e. [87T.OutMap] shall be set as “0007H”.

3.27.2.2 Programmable Trip Output

The device provides 10 programmable trip output with I/O signals and settings for users used by
visualization programming. Users can set trip output of programming logic if trip output of
protection element provided by the device cannot meet application requirements completely.

For example, if it is required to set stage 1 of phase overcurrent protection at HV side of the
transformer operate to issue trip command after its operation criterion is satisfied “AND” receiving
a binary input which can be a blocking signal from other device, programmable trip output can
complete the function configuration as following steps.

1. Set tripping logic setting of stage 1 of phase overcurrent protection at HV side of the
transformer as “0000H”, i.e., [HVS.50/51P.OutMap]=0000H.

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2. Finish required programming logic by PCS-Explorer.

3. Connect final output of programming logic to input signal of programmable trip output.

4. Set corresponding tripping logic setting of programmable trip output to complete the function
configuration.

3.27.3 I/O Signals


Table 3.27-1 I/O signals of programmable trip output

No. Input signal Description


1 Sig_ProgTrp01 Input signal of programmable tripping output element 1.
2 Sig_ProgTrp02 Input signal of programmable tripping output element 2.
3 Sig_ProgTrp03 Input signal of programmable tripping output element 3.
4 Sig_ProgTrp04 Input signal of programmable tripping output element 4.
5 Sig_ProgTrp05 Input signal of programmable tripping output element 5.
6 Sig_ProgTrp06 Input signal of programmable tripping output element 6.
7 Sig_ProgTrp07 Input signal of programmable tripping output element 7.
8 Sig_ProgTrp08 Input signal of programmable tripping output element 8.
9 Sig_ProgTrp09 Input signal of programmable tripping output element 9.
10 Sig_ProgTrp10 Input signal of programmable tripping output element 10.

3.27.4 Settings
Table 3.27-2 Settings of programmable trip output

No. Item Range Step Unit Description


Tripping logic setting of programmable trip output
1 OutMap_ProgTrp01 0000~FFFF
01
Tripping logic setting of programmable trip output
2 OutMap_ProgTrp02 0000~FFFF
02
Tripping logic setting of programmable trip output
3 OutMap_ProgTrp03 0000~FFFF
03
Tripping logic setting of programmable trip output
4 OutMap_ProgTrp04 0000~FFFF
04
Tripping logic setting of programmable trip output
5 OutMap_ProgTrp05 0000~FFFF
05
Tripping logic setting of programmable trip output
6 OutMap_ProgTrp06 0000~FFFF
06
Tripping logic setting of programmable trip output
7 OutMap_ProgTrp07 0000~FFFF
07
Tripping logic setting of programmable trip output
8 OutMap_ProgTrp08 0000~FFFF
08
Tripping logic setting of programmable trip output
9 OutMap_ProgTrp09 0000~FFFF
09
10 OutMap_ProgTrp10 0000~FFFF Tripping logic setting of programmable trip output

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3 Operation Theory

No. Item Range Step Unit Description


10

3.28 Intermediate Variable Element

3.28.1 Function Description

In order to better support logic programming function, 20 intermediate variables are provided. The
user can distribute the middle results of logic programming to intermediate variables, and use the
intermediate variables to carry out other logic programming. Not only intermediate variable display
is supported by the device, but also its state change report is recorded by the device.

For example, if LED 10 is needed to be lit when stage 1 of phase overcurrent protection at HV side
of transformer or stage 1 of phase overcurrent protection at LV side of transformer operates, then
the following logic can be programmed through PCS-Explorer.

SIG HVS.50/51P1.Op >=1


Sig_Spare01
SIG LVS.50/51P1.Op

SIG Sig_Spare01 LED 10

Figure 3.28-1 An example of programmable logic

3.28.2 I/O Signals

The following signals of intermediate variable are used to transfer signals, so they are input
signals and the corresponding output signals at the same time.

Table 3.28-1 Signals of intermediate variable element

No. Item Description

1 Sig_Spare01 Signal of intermediate variable 1 for logic programming

2 Sig_Spare02 Signal of intermediate variable 2 for logic programming

3 Sig_Spare03 Signal of intermediate variable 3 for logic programming

4 Sig_Spare04 Signal of intermediate variable 4 for logic programming

5 Sig_Spare05 Signal of intermediate variable 5 for logic programming

6 Sig_Spare06 Signal of intermediate variable 6 for logic programming

7 Sig_Spare07 Signal of intermediate variable 7 for logic programming

8 Sig_Spare08 Signal of intermediate variable 8 for logic programming

9 Sig_Spare09 Signal of intermediate variable 9 for logic programming

10 Sig_Spare10 Signal of intermediate variable 10 for logic programming

11 Sig_Spare11 Signal of intermediate variable 11 for logic programming

12 Sig_Spare12 Signal of intermediate variable 12 for logic programming

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No. Item Description

13 Sig_Spare13 Signal of intermediate variable 13 for logic programming

14 Sig_Spare14 Signal of intermediate variable 14 for logic programming

15 Sig_Spare15 Signal of intermediate variable 15 for logic programming

16 Sig_Spare16 Signal of intermediate variable 16 for logic programming

17 Sig_Spare17 Signal of intermediate variable 17 for logic programming

18 Sig_Spare18 Signal of intermediate variable 18 for logic programming

19 Sig_Spare19 Signal of intermediate variable 19 for logic programming

20 Sig_Spare20 Signal of intermediate variable 20 for logic programming

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3 Operation Theory

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4 Supervision

4 Supervision

Table of Contents
4.1 Overview ........................................................................................................... 4-1
4.2 Relay Self-supervision .................................................................................... 4-1
4.2.1 Relay Hardware Supervision ................................................................................................ 4-1

4.2.2 Output Tripping Circuit Supervision...................................................................................... 4-1

4.2.3 Setting Checking .................................................................................................................. 4-1

4.2.4 Memory Checking ................................................................................................................ 4-1

4.2.5 Opto-coupler Power Supervision ......................................................................................... 4-2

4.2.6 Fault Detector Element Supervision .................................................................................... 4-2

4.2.7 Test Mode Supervision ......................................................................................................... 4-2

4.2.8 Hardware Configuration Supervision ................................................................................... 4-2

4.3 CT Circuit Supervision (CTS).......................................................................... 4-2


4.4 Voltage Circuit Supervision (VTS) .................................................................. 4-2
4.5 Frequency Supervision ................................................................................... 4-2
4.6 Failure and Abnormality Alarms ..................................................................... 4-3
4.6.1 Hardware Self-supervision Alarms ....................................................................................... 4-3

4.6.2 Protection Function Alarms .................................................................................................. 4-6

List of Tables
Table 4.6-1 Alarm message description ...................................................................................... 4-3

Table 4.6-2 Troubleshooting ...................................................................................................... 4-4

Table 4.6-3 Alarm message description ................................................................................... 4-7

Table 4.6-4 Troubleshooting ...................................................................................................... 4-7

PCS-978 Transformer Relay 4-a


Date: 2015-06-26
4 Supervision

4-b PCS-978 Transformer Relay


Date: 2015-06-26
4 Supervision

4.1 Overview

Though the protection system is in non-operating state under normal conditions, it is waiting for a
power system fault to occur at any time and must operate for the fault without fail. When
equipment is in energizing process before the LED “HEALTHY” is on, the equipment needs to be
checked to ensure no errors. Therefore, the automatic supervision function, which checks the
health of the protection system when startup and during normal operation, plays an important role.

The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.

In case a fatal fault is detected during automatic supervision, the equipment will be blocked. It
means that relay is out of service. Before you must re-energize the relays to make relay back into
service, please find out the cause and inform the manufacturer.

When a failure is detected by the automatic supervision, it is followed with an LCD message, LED
indication and alarm contact outputs. At the same time event recording will record the failure alarm
which can be viewed in event recording report and be printed.

4.2 Relay Self-supervision

4.2.1 Relay Hardware Supervision

All chips on each module are monitored to ensure whether they are damaged or have errors. If
any one of them is detected damaged or having error, the corresponding alarm signal
[ProtBrd.Fail_DSP] or [FDBrd.Fail_DSP] is issued with equipment being blocked.

AC current and voltage samplings of protection DSP module and fault detector DSP module are
monitored and if the samples are detected to be wrong or inconsistent, an alarm
[ProtBrd.Fail_Sample] or [FDBrd.Fail_Sample] will be issued and the relay will be blocked.

4.2.2 Output Tripping Circuit Supervision


States of binary outputs are continuously monitored. If any abnormality of the BO module at slot
Bxx (Bxx is the slot number) is detected, the alarm signal [Bxx.Alm_Output] will be issued.

4.2.3 Setting Checking


This relay has 30 setting groups, while only one is active at the same time. The settings of active
setting group are checked to ensure they are reasonable. If settings are checked to be
unreasonable or out of setting scopes, a corresponding alarm signal will be issued, and the
protective device will also be blocked.

4.2.4 Memory Checking


Data in non-volatile memory, which are not changed after device energized, are always checked
during device normal operation, such as settings, pointers, etc. If these data changed abnormally,
the corresponding alarm [ProtBrd.Memory] or [FDBrd.Memory] will be issued.

PCS-978 Transformer Relay 4-1


Date: 2015-06-26
4 Supervision

4.2.5 Opto-coupler Power Supervision


Positive power supply of opto-coupler on each BI module at slot xx (Bxx is the slot number) is
continuously monitored, and if a failure or damage on the module is detected, then the alarm
signal [Bxx.Alm_OptoDC] will be issued.

4.2.6 Fault Detector Element Supervision


If any fault detector picks up to trigger oscillography function, the corresponding binary input
changing report will be recorded in “IO Events” menu with tripping report [TrigDFR] being issued.

If a fault detector on protection or fault detector DSP module keeps picking up for 500s, the
corresponding alarm signal [ProtBrd.Alm_Pkp] or [FDBrd.Alm_Pkp] will be issued without
equipment being blocked.

4.2.7 Test Mode Supervision

When protection equipment is in communication test mode the alarm signal [Alm_CommTest] is
issued without blocking equipment.

4.2.8 Hardware Configuration Supervision

Module configuration is checked automatically during equipment initialization, if plug-in module


configuration is not consistent to the design drawing of an applied-specific, the alarm signal
[Fail_BoardConfig] is issued with the equipment being blocked.

4.3 CT Circuit Supervision (CTS)

CTS is designed to detect the CT secondary circuit to ensure that current measurement is the
actual value of power system. The main purpose of the function is to ensure the integrity of CT
circuits maintaining the performance of the device.

4.4 Voltage Circuit Supervision (VTS)

VTS is designed to detect the VT secondary circuit to ensure that voltage measurement is the
actual value of power system. When VT failure is detected, the device can automatically adjust the
configuration of protection elements of which the stability would be affected and might lead to
mal-operation.

4.5 Frequency Supervision

If system frequency detected is too high or low, the device will issue an alarm signal [Alm_Freq]
instantly to reminding operators for attention. The device provides two settings [f_High_FreqAlm]
and [f_Low_FreqAlm] to set the threshold of frequency alarm.

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Date: 2015-06-26
4 Supervision

4.6 Failure and Abnormality Alarms

NOTICE!

Following alarm messages and corresponding LED indicators are fixed in device.
Besides, there are other programmable LED indicators configured according to different
project requirement.

4.6.1 Hardware Self-supervision Alarms

Equipment hardware circuits and software working conditions are always monitored by the relay. If
any abnormality occurs, the corresponding alarm message will be issued on the LCD of the
equipment.

When some light failures are detected, part of protection functions probably be disabled and
others can still work. Some severe failures of hardware or software will result in the equipment
being blocked and the contacts of equipment failure will operate at same time. During that
condition, the protection relay has to be out of service for maintenance.

NOTICE!

If alarm signal is issued with equipment being blocked, please try to make a fault
diagnosis by referring the issued alarm messages but not simply reboot or re-power the
relay. If user cannot find the failure reason on site, please inform the manufacturer or
the agent for maintenance.

Table 4.6-1 Alarm message description

No. Item Description


Failure Signals: Blocke device, “HEALTHY” LED off, “ALARM” LED on
1 Fail_Device The device fails.
2 Fail_Setting_OvRange Setting values are out of range.
Mismatch between the configuration of plug-in modules and the designing
3 Fail_BoardConfig
drawing of an applied-specific project.
After configuration file is updated, settings of the file and settings saved on
4 Fail_SettingItem_Chgd
the device are not matched.
5 ProtBrd.Fail_Settings Error is found during checking settings on protection module.
6 FDBrd.Fail_Settings Error is found during checking settings on fault detector module.
7 ProtBrd.Fail_Memory Error is found during checking the memory data on protection module.
8 FDBrd.Fail_Memory Error is found during checking the memory data on fault detector module.
9 ProtBrd.Fail_Sample Sample values on protection module are abnormal.
10 FDBrd.Fail_Sample Sample values on fault detector module are abnormal.
11 ProtBrd.Fail_Config Software configuration error on protection module is found.
12 FDBrd.Fail_Config Software configuration error on fault detector module is found.
13 ProtBrd.Fail_DSP DSP chip on protection module is damaged.
14 FDBrd.Fail_DSP DSP chip on fault detector module is damaged.
15 ProtBrd.Fail_QF_SV The quality factor of sample values on protection module is abnormal.

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Date: 2015-06-26
4 Supervision

No. Item Description


16 FDBrd.Fail_QF_SV The quality factor of sample values on fault detector module is abnormal.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
17 Alm_Device The device is abnormal.
18 Alm_CommTest The device is in the communication test mode.
19 Alm_TimeSyn Time synchronization abnormality alarm.
The error is found during checking the version of software downloaded to
20 Alm_Version
the device.
21 Alm_Settings_MON The error is found during MON module checking settings of device.
22 BI_Maintenance The device is in maintenance state.
The active setting group configured by settings in device and that configured
23 Alm_BI_SettingGrp
by binary input are not matched.
24 Bxx.Alm_OptoDC The power supply of Bxx binary input module is abnormal.
The duration of pickup of any fault detector on protection module is in
25 ProtBrd.Alm_Pkp
excess of 10s.
The duration of pickup of any fault detector on fault detector module is in
26 FDBrd.Alm_Pkp
excess of 10s.
27 Alm_Insuf_Memory The memory of MON module is insufficient.
28 Bxx.Alm_Output BO module at slot xx (Bxx is the slot number) is abnormal.
29 Bxx.Alm_Board The board at slot xx (Bxx is the slot number) is abnormal.

Table 4.6-2 Troubleshooting

No. Item Handling suggestion


Failure Signals: Blocke device, “HEALTHY” LED off, “ALARM” LED on
The signal is always issued with other specific failure signals.
1 Fail_Device
Please refer to the handling suggestion of other specific fail signals.
Please reset setting values according to the range described in the
instruction manual, then re-power or reboot the equipment and the alarm
2 Fail_Setting_OvRange
message will disappear and the equipment will restore to normal operation
state.
Step 1: Go to the menu “Information”->”Board Info”, check the abnormality
information.
Step 2: For the module with abnormality, if the module is not used, then
3 Fail_BoardConfig remove, and if the module is used, then check whether the module is
installed properly and work normally.
After the abnormality is removed, re-power or reboot the equipment and the
equipment will restore to normal operation state.
Please check the settings mentioned in the prompt message on the LCD,
4 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm Settings” item to
confirm settings. Then the equipment will restore to normal operation stage.
Step 1: Check CT ratio settings of each side of transformer to be set in
5 ProtBrd.Fail_Settings
proper range, and if needed, please reset those settings and reboot or
6 FDBrd.Fail_Settings re-power the equipment.

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Date: 2015-06-26
4 Supervision

No. Item Handling suggestion


Step 2: Check overexcitation settings to be set reasonable, and if needed,
please reset those settings and reboot or re-power the equipment.
Step 3: After above two steps, abnormality may disappear. Otherwise, a
hardware failure probably occurs and please inform the manufacturer or the
agent
7 ProtBrd.Fail_Memory
Please inform the manufacturer or the agent for maintenance.
8 FDBrd.Fail_Memory
Step 1: Please make the equipment out of service.
9 ProtBrd.Fail_Sample Step 2: Then check if the analog input modules and wiring connectors
connected to those modules are installed at the position.
Step 3: Re-power the equipment and the equipment will restore to normal
10 FDBrd.Fail_Sample
operation state.
11 ProtBrd.Fail_Config Please inform configuration engineers to check and confirm visualization
12 FDBrd.Fail_Config functions of the device.
13 ProtBrd.Fail_DSP Chips are damaged and please inform the manufacturer or the agent to
14 FDBrd.Fail_DSP replace the module.

15 ProtBrd.Fail_QF_SV These alarms may be issued for electric transformer applied projects. If
alarms are issued, please check working state of merging units and the
16 FDBrd.Fail_QF_SV
connection between merging units and the protection device.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
The signal is always issued with other specific alarm signals.
17 Alm_Device
Please refer to the handling suggestion of other specific alarm signals.
No special treatment is needed. Just wait the completion of communication
18 Alm_CommTest
test or exit the test.
Step1: Check whether the selected clock synchronization mode matches
the clock synchronization source.
Step 2: Check whether the wiring connection between the equipment and
the clock synchronization source is correct.
Step 3: Check whether the setting for selecting clock synchronization (i.e.
19 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSyn] as “No TimeSyn”.
After the abnormality is removed, the “ALARM” LED will be extinguished
and the corresponding alarm message will disappear and the equipment will
restore to normal operation state.
Users may pay no attention to the alarm signal in the project commissioning
stage, but it is needed to download the latest package file (including correct
20 Alm_Version version checksum file) provided by R&D engineer to make the alarm signal
disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service.
21 Alm_Settings_MON Please inform the manufacturer or the agent for maintenance.
After maintenance is finished, please de-energized the binary input
22 BI_Maintenance [BI_Maintenance] and then the alarm will disappear and the equipment
restore to normal operation state.

PCS-978 Transformer Relay 4-5


Date: 2015-06-26
4 Supervision

No. Item Handling suggestion


Please check the value of setting [Active_Grp] and binary input of indicating
active group, and make them matched. Then the “ALARM” LED will be
23 Alm_BI_SettingGrp
extinguished and the corresponding alarm message will disappear and the
equipment will restore to normal operation state.
Step 1: Check whether the binary input module is connected to the power
supply.
Step 2: check whether the voltage of power supply is in the required range.
24 Bxx.Alm_OptoDC
After the voltage for binary input module restores to normal range, the
“ALARM” LED will be extinguished and the corresponding alarm message
will disappear and the equipment will restore to normal operation state.
Please check secondary values and protection settings. If settings are not
set reasonable to make fault detectors pick up, please reset settings, and
then the alarm message will disappear and the equipment will restore to
25 ProtBrd.Alm_Pkp normal operation state.

NOTICE!

Tripping out contacts will be blocked in 1s after the device is


energized with “HEALTHY” LED indicator being lit. This situation
is decided as a relay fault, and the alarm signal [ProtBrd.Alm_Pkp]
26 FDBrd.Alm_Pkp
and [FDBrd.Alm_Pkp] will be issued after tripping output contacts
keeps on picking up over 10s.

Please replace the MON module on device with another one with greater
27 Alm_Insuf_Memory
memory.
Please re-insert corresponding binary output module and re-power or reboot
28 Bxx.Alm_Output the equipment after the completion of insertion, and then the equipment will
restore to normal operation state.
29 Bxx.Alm_Board Please check the module located in slot xx.

NOTICE!

If the equipment still cannot restore to normal operation state after suggested
procedures, please inform the manufacturer or the agent for maintenance.

4.6.2 Protection Function Alarms


During the device's normal operation, VT and CT circuit and some binary input circuits are always
monitored by the device. If any abnormality of them occurs or any alarm element operates, the
corresponding alarm message will be issued on the LCD without blocking the device and
“ALARM” LED is lit at the same time.

When this kind of alarm messages are issued, the operators need to find the abnormality reason,
and then take corresponding measures to eliminate the alarm message to make the device return
to the normal operation state.

4-6 PCS-978 Transformer Relay


Date: 2015-06-26
4 Supervision

Table 4.6-3 Alarm message description

No. Item Description


Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
Whether the corresponding biased differential protection is blocked is decided by the corresponding
logic setting.
1 87T.Alm_CTS CT secondary circuit for transformer differential protection fails.
2 87R Alm_CTS CT secondary circuit of reactor differential protection is abnormal.
3 x.64REF.Alm_CTS CT secondary circuit for restricted earth fault protection of side x fails.
4 87W.Alm_CTS CT secondary circuit of winding differential protection is abnormal.
5 x.AlmH_CTS CT secondary circuit at side x fails.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
6 87T.Alm_Diff Differential current of transformer differential protection is abnormal.
7 87R Alm_Diff Differential current of reactor differential protection is abnormal.
Differential current of restricted earth-fault protection at side x of transformer
8 x.64REF.Alm_Diff
is abnormal.
9 87W.Alm_Diff Differential current of winding differential protection is abnormal.
10 x.Alm_VTS VT secondary circuit at x side is abnormal.
11 x.AlmL_CTS CT secondary circuit at x side is abnormal.
12 x.49.Alm Thermal overload protection operates to issue alarm signal.
13 24DT2.Alm Definite-time overexcitation alarm element operates.
14 24IDMT.Alm Inverse-time overexcitation alarm element operates.
15 x.62PD.Alm Pole disagreement protection of x side operates to issue alarm signal.
16 Alm_Freq System frequency abnormality alarm signals.
17 26.Alm Alarm element of temperature protection operates.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED off
18 x.51PAlm1.Alm Stage 1 overload alarm element of x side operates.
19 x.51PAlm2.Alm Stage 2 overload alarm element of x side operates.
20 x.59GAlm.Alm Residual overvoltage alarm element of x side operates.

Table 4.6-4 Troubleshooting

No. Item Description


Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
Whether the corresponding biased differential protection is blocked is decided by the corresponding
logic setting.
1 87T.Alm_CTS
2 87R Alm_CTS Please check the corresponding CT secondary circuit. After the abnormality
3 x.64REF.Alm_CTS is eliminated, equipment can return to normal operation state by energizing
4 87W.Alm_CTS the binary input [BI_RstTarg]
5 x.AlmH_CTS
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
6 87T.Alm_Diff Please check the corresponding sampling values and CT secondary circuit
7 87R Alm_Diff to find out the reason resulting in the abnormality. If sample values of the
8 x.64REF.Alm_Diff equipment are not correct, please inform the manufacturer or agent for

PCS-978 Transformer Relay 4-7


Date: 2015-06-26
4 Supervision

No. Item Description


maintenance, and if it is caused by the failure of the CT secondary circuit or
9 87W.Alm_Diff primary system, please finish troubleshooting according to the operating
instructions of protection relay.
Please check the corresponding CT secondary circuit. After the abnormality
10 x.Alm_VTS
is eliminated, “ALARM” LED will go off automatically and equipment returns
11 x.AlmL_CTS to normal operation state.
12 x.49.Alm
13 24DT2.Alm
14 24IDMT.Alm
15 x.62PD.Alm Please treat according to the specific application requirements
16 x.51PAlm1.Alm
17 x.51PAlm2.Alm
18 26.Alm
Please check device measured frequency with system actual frequency. If
19 Alm_Freq device measured frequency is inconsistent with the system actual
frequency, please check the device.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED off
20 x.51PAlm1.Alm
21 x.51PAlm2.Alm Please treat according to the specific application requirements
22 x.59GAlm.Alm

NOTICE!

The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.

4-8 PCS-978 Transformer Relay


Date: 2015-06-26
5 Management

5 Management

Table of Contents
5 Management ...................................................................................... 5-a
5.1 Measurement ................................................................................................... 5-1
5.1.1 Measurements1 & Measurements2..................................................................................... 5-1

5.1.2 Power Value ......................................................................................................................... 5-8

5.1.3 Temperature Value ............................................................................................................... 5-8

5.2 Recording ........................................................................................................ 5-8


5.2.1 Overview .............................................................................................................................. 5-8

5.2.2 Event Recording .................................................................................................................. 5-9

5.2.3 Disturbance Recording ........................................................................................................ 5-9

5.2.4 Present Recording ............................................................................................................. 5-10

PCS-978 Transformer Relay 5-a


Date: 2015-06-26
5 Management

5-b PCS-978 Transformer Relay


Date: 2015-06-26
5 Management

5.1 Measurement
This device performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.

NOTICE!

This device can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer.

5.1.1 Measurements1 & Measurements2


Access path:

MainMenu  “Measurements”  “Measurements1” or  “Measurements2”

The contents of “Measurements1” are as same as that of “Measurements2”. “Measurements1”


is used to display measured values from protection calculation DSP (displayed in secondary
value), while “Measurements2” is used to display measured values from fault detector DSP
(displayed in secondary value).

5.1.1.1 HVS/MVS/LVS Measurements

Access path:

MainMenu  “Measurements”  “Measurements1”  “HVS Measurements”

MainMenu  “Measurements”  “Measurements1”  “MVS Measurements”

MainMenu  “Measurements”  “Measurements1”  “LVS Measurements”

“HVS Measurements” is used to display measured values and corresponding phase angles of HV
side.

“MVS Measurements” is used to display measured values and corresponding phase angles of
MV side.

“LVS Measurements” is used to display measured values and corresponding phase angles of LV
side.

Secondary voltages/currents are displayed in this device by default. If the setting


[Opt_Display_Status] of the submenu “Settings”  “Device Setup”  “Comm Settings” is
modified to “PriValue”, primary voltages/currents will be displayed in this device.

No. Symbol Definition Resolution Unit

1 x.Ua Phase-A voltage of x side. 0.000 V/kV

2 x.Ub Phase-B voltage of x side. 0.000 V/kV

PCS-978 Transformer Relay 5-1


Date: 2015-06-26
5 Management

3 x.Uc Phase-C voltage of x side. 0.000 V/kV

4 x.3U0Cal Calculated residual voltage of x side. 0.000 V/kV

5 x.U1 Positive-sequence voltage of x side. 0.000 V/kV

6 x.U2 Negative-sequence voltage of x side. 0.000 V/kV

7 x.Uab Phase-AB voltage of x side. 0.000 V/kV

8 x.Ubc Phase-BC voltage of x side. 0.000 V/kV

9 x.Uca Phase-CA voltage of x side. 0.000 V/kV

10 x.Ang(Ua-Ub) Angle between phase-A and phase-B voltages of x side. 0 deg

11 x.Ang(Ub-Uc) Angle between phase-B and phase-C voltages of x side. 0 deg

12 x.Ang(Uc-Ua) Angle between phase-C and phase-A voltages of x side. 0 deg

13 x.3U0Ext Measured external residual voltage of x side. 0.000 V/kV

14 x.Ia Phase-A current of x side. 0.000 A

15 x.Ib Phase-B current of x side. 0.000 A

16 x.Ic Phase-C current of x side. 0.000 A

17 x.3I0Cal Calculated residual current of x side. 0.000 A

18 x.I1 Positive-sequence current of x side. 0.000 A

19 x.I2 Negative-sequence current of x side. 0.000 A

20 x.Ang(Ia-Ib) Angle between phase-A and phase-B currents of x side. 0 deg

21 x.Ang(Ia-Ic) Angle between phase-B and phase-C currents of x side. 0 deg

22 x.Ang(Ic-Ia) Angle between phase-C and phase-A currents of x side. 0 deg

23 x.3I0Ext Measured external residual current of x side. 0.000 A

24 x.Ang(Ua-Ia) Angle between phase A voltage and current of x side. 0 deg

25 x.Ang(Ub-Ib) Angle between phase B voltage and current of x side. 0 deg

26 x.Ang(Uc-Ic) Angle between phase C voltage and current of x side. 0 deg

Phase A thermal state of thermal overload protection.


27 x.49.Accu_A When the value is “1”, thermal overload protection 0.000 %
operates.

Phase B thermal state of thermal overload protection.


28 x.49.Accu_B When the value is “1”, thermal overload protection 0.000 %
operates.

Phase C thermal state of thermal overload protection.


29 x.49.Accu_C When the value is “1”, thermal overload protection 0.000 %
operates.

NOTICE!

The symbol ”x” represents some side of transformer defined by the user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS”, etc. If only one
protection element is equipped, the prefix “x.” may disappear.

5-2 PCS-978 Transformer Relay


Date: 2015-06-26
5 Management

5.1.1.2 CWS Measurements

Access path:

MainMenu  “Measurements”  “Measurements1”  “CWS Measurements”

“CWS Measurements” is used to display measured values of common winding side.

Secondary currents are displayed in this device by default. If the setting [Opt_Display_Status] of
the submenu “Settings”  “Device Setup”  “Comm Settings” is modified to “PriValue”,
primary currents will be displayed in this device.

No. Symbol Definition Resolution Unit

1 CWS.Ia Phase-A current of common winding side. 0.000 A

2 CWS.Ib Phase-B current of common winding side. 0.000 A

3 CWS.Ic Phase-C current of common winding side. 0.000 A

4 CWS.3I0Cal Calculated residual voltage of common winding side. 0.000 A

5 CWS.I1 Positive-sequence current of common winding side. 0.000 A

6 CWS.I2 Negative-sequence current of common winding side. 0.000 A

Angle between phase-A and phase-B currents of


7 CWS.Ang(Ia-Ib) 0 deg
common winding side.

Angle between phase-B and phase-C currents of


8 CWS.Ang(Ia-Ic) 0 deg
common winding side

Angle between phase-C and phase-A currents of


9 CWS.Ang(Ic-Ia) 0 deg
common winding side

Measured external residual current of common winding


10 CWS.3I0Ext 0.000 A
side.

5.1.1.3 OvExc Measurements

Access path:

MainMenu  “Measurements”  “Measurements1”  “OvExc Measurements”

“OvExc Measurements” is used to display measured values of overexcitation protection.

No. Symbol Definition Resolution Unit

1 f Measured system frequency 0.000 Hz

Overexcitation multiple of definite-time overexcitation


2 24.U/f 0.000 /
protection.

Thermal state of inverse-time overexcitation protection.


3 24IDMT.ThermAccu When the value is “100%”, inverse-time overexcitation 0.000 %
protection operates.

5.1.1.4 Diff Measurements

Access path:

PCS-978 Transformer Relay 5-3


Date: 2015-06-26
5 Management

MainMenu  “Measurements”  “Measurements1”  “Diff Measurements”

“Diff Measurements” is used to display currents for current differential protection and
corresponding phase angles.

No. Symbol Definition Resolution Unit

1 87T.Ida Phase-A differential current. 0.000 p.u.

2 87T.Idb Phase-B differential current. 0.000 p.u.

3 87T.Idc Phase-C differential current. 0.000 p.u.

4 87T.Ira Phase-A restraint current. 0.000 p.u.

5 87T.Irb Phase-B restraint current. 0.000 p.u.

6 87T.Irc Phase-C restraint current. 0.000 p.u.

7 87T.Ia_Th Threshold value of phase-A restraint current. 0.000 p.u.

8 87T.Ib_Th Threshold value of phase-B restraint current. 0.000 p.u.

9 87T.Ic_Th Threshold value of phase-C restraint current. 0.000 p.u.

Phase-A 2nd harmonic percentage of total differential


10 87T.Ida_Hm2_Pcnt 0.000 %
current.

Phase-B 2nd harmonic percentage of total differential


11 87T.Idb_Hm2_Pcnt 0.000 %
current.

Phase-C 2nd harmonic percentage of total differential


12 87T.Idc_Hm2_Pcnt 0.000 %
current.

Phase-A 3rd harmonic percentage of total differential


13 87T.Ida_Hm3_Pcnt 0.000 %
current.

Phase-B 3rd harmonic percentage of total differential


14 87T.Idb_Hm3_Pcnt 0.000 %
current.

Phase-C 3rd harmonic percentage of total differential


15 87T.Idc_Hm3_Pcnt 0.000 %
current.

Phase-A 5th harmonic percentage of total differential


16 87T.Ida_Hm5_Pcnt 0.000 %
current.

Phase-B 5th harmonic percentage of total differential


17 87T.Idb_Hm5_Pcnt 0.000 %
current.

Phase-C 5th harmonic percentage of total differential


18 87T.Idc_Hm5_Pcnt 0.000 %
current.

Phase-A corrected current of branch m (m= 1,2, 3, 4,


19 87T.Ia_Cr_Brm 0.000 p.u.
5, 6) for differential protection.

Phase-B corrected current of branch m (m= 1,2, 3, 4,


20 87T.Ib_Cr_Brm 0.000 p.u.
5, 6) for differential protection.

Phase-C corrected current of branch m (m= 1,2, 3, 4,


21 87T.Ic_Cr_Brm 0.000 p.u.
5, 6) for differential protection.

22 87T.Ang(Ia)_Br1-Brm Angle between phase-A currents of branch 1 and 0 deg

5-4 PCS-978 Transformer Relay


Date: 2015-06-26
5 Management

branch m (m= 2, 3, 4, 5, 6).

Angle between phase-B currents of branch 1 and


23 87T.Ang(Ib)_Br1-Brm 0 deg
branch m (m= 2, 3, 4, 5, 6).

Angle between phase-C currents of branch 1 and


24 87T.Ang(Ic)_Br1-Brm 0 deg
branch m (m= 2, 3, 4, 5, 6).

Reference current of branch m (m=1, 2, 3, 4, 5, 6) of


25 87T.Ib_Brm 0.000 A
power transformer for differential protection.

26 87R.Ia_Cr_Br1 Corrected values of phase-A current of branch 1. 0.000 p.u.

27 87R.Ib_Cr_Br1 Corrected values of phase-B current of branch 1. 0.000 p.u.

28 87R.Ic_Cr_Br1 Corrected values of phase-C current of branch 1. 0.000 p.u.

Corrected values of calculated residual current of


29 87R.3I0_Cr_Br1 0.000 p.u.
branch 1.

30 87R.Ia_Cr_Br2 Corrected values of phase-A current of branch 2. 0.000 p.u.

31 87R.Ib_Cr_Br2 Corrected values of phase-B current of branch 2. 0.000 p.u.

32 87R.Ic_Cr_Br2 Corrected values of phase-C current of branch 2. 0.000 p.u.

Corrected values of calculated residual current of


33 87R.3I0_Cr_Br2 0.000 p.u.
branch 2.

Phase angles of phase-A current between branch 1


34 87R.Ang(Ia)_Br1-Br2 0 deg
and branch 2.

Phase angles of phase-B current between branch 1


35 87R.Ang(Ib)_Br1-Br2 0 deg
and branch 2.

Phase angles of phase-C current between branch 1


36 87R.Ang(Ic)_Br1-Br2 0 deg
and branch 2.

Phase angles of calculated residual between branch 1


37 87R.Ang(3I0)_Br1-Br2 0 deg
and branch 2.

38 87R.Ida Phase-A differential current 0.000 p.u.

39 87R.Idb Phase-B differential current 0.000 p.u.

40 87R.Idc Phase-C differential current 0.000 p.u.

41 87R.3I0d Zero-sequence differential current 0.000 p.u.

42 87R.Ira Phase-A restraint current 0.000 p.u.

43 87R.Irb Phase-B restraint current 0.000 p.u.

44 87R.Irc Phase-C restraint current 0.000 p.u.

45 87R.3I0r Zero-sequence restraint current 0.000 p.u.

46 87R.Ia_Th Threshold value of phase-A restraint current. 0.000 p.u.

47 87R.Ib_Th Threshold value of phase-B restraint current. 0.000 p.u.

48 87R.Ic_Th Threshold value of phase-C restraint current. 0.000 p.u.

Threshold value of calculated residual restraint


49 87R.3I0_Th 0.000 p.u.
current.

PCS-978 Transformer Relay 5-5


Date: 2015-06-26
5 Management

Second harmonic percentage of phase-A differential


50 87R.Ida_Hm2_Pcnt 0.000 %
current.

Second harmonic percentage of phase-B differential


51 87R.Idb_Hm2_Pcnt 0.000 %
current.

Second harmonic percentage of phase-C differential


52 87R.Idc_Hm2_Pcnt 0.000 %
current.

Third harmonic percentage of phase-A differential


53 87R.Ida_Hm3_Pcnt 0.000 %
current.

Third harmonic percentage of phase-B differential


54 87R.Idb_Hm3_Pcnt 0.000 %
current.

Third harmonic percentage of phase-C differential


55 87R.Idc_Hm3_Pcnt 0.000 %
current.

5.1.1.5 REF Measurements

Access path:

MainMenu  “Measurements”  “Measurements1”  “REF Measurements”

“REF Measurements” is used to display corrected currents for restricted earth fault protection and
corresponding phase angles.

No. Symbol Definition Resolution Unit

Residual differential current of x side REF


1 x.64REF.3I0d 0.000 In
protection.

Residual restraint current of x side REF


2 x.64REF.3I0r 0.000 In
protection.

Threshold of residual restraint current of x side


3 x.64REF.3I0_Th 0.000 In
REF protection.

Corrected calculated residual current for branch


4 x.64REF.3I0_Cr_Brm 0.000 In
m of x side REF protection (m=1, 2, 3, 4).

Corrected residual current from neutral CT of x


5 x.64REF.3I0_Cr_NP 0.000 In
side REF protection.

Angle of calculated residual current between


6 x.64REF.Ang(3I0)_Br1-Brm branch 1 and branch m of x side REF protection 0 deg
(m=2, 3, 4).

Angle between calculated residual current of


7 x.64REF.Ang(3I0)_Br1-NP branch 1 and current from neutral CT of x side 0 deg
REF protection.

Corrected coefficient of current for branch m of


8 x.64REF.K_Brm 0.000 /
x side REF protection (m=1, 2, 3, 4).

Corrected coefficient of current from neutral CT


9 x. 64REF.K_NP 0.000 /
of x side REF protection

5-6 PCS-978 Transformer Relay


Date: 2015-06-26
5 Management

5.1.1.6 WDIF Measurements

Access path:

MainMenu  “Measurements”  “Measurements1”  “WDIF Measurements”

“WDIF Measurements” is used to display measured values and corresponding phase angles of
winding differential protection.

No. Symbol Definition Resolution Unit

Phase-A differential current of winding differential


1 87W.Ida 0.000 In
protection.

Phase-B differential current of winding differential


2 87W.Idb 0.000 In
protection.

Phase-C differential current of winding differential


3 87W.Idc 0.000 In
protection.

Residual differential current of winding differential


4 87W.3I0d 0.000 In
protection.

Phase-A restraint current of winding differential


5 87W.Ira 0.000 In
protection.

Phase-B restraint current of winding differential


6 87W.Irb 0.000 In
protection.

Phase-C restraint current of winding differential


7 87W.Irc 0.000 In
protection.

Residual restraint current of winding differential


8 87W.3I0r 0.000 In
protection.

Threshold of phase-A restraint current of winding


9 87W.Ia_Th 0.000 In
differential protection.

Threshold of phase-B restraint current of winding


10 87W.Ib_Th 0.000 In
differential protection.

Threshold of phase-C restraint current of winding


11 87W.Ic_Th 0.000 In
differential protection.

Threshold of residual restraint current of winding


12 87W.3I0_Th 0.000 In
differential protection.

Phase-A corrected current of branch m (m= 1,2, 3,


13 87W.Ia_Cr_Brm 0.000 In
4, 5) for differential protection.

Phase-B corrected current of branch m (m= 1,2, 3,


14 87W.Ib_Cr_Brm 0.000 In
4, 5) for differential protection.

Phase-C corrected current of branch m (m= 1,2, 3,


15 87W.Ic_Cr_Brm 0.000 In
4, 5) for differential protection.

Corrected calculated residual current for branch m


16 87W.3I0_Cr_Brm 0.000 In
(m=1, 2, 3, 4, 5) of winding differential protection.

PCS-978 Transformer Relay 5-7


Date: 2015-06-26
5 Management

Angle between phase-A currents of branch 1 and


17 87W.Ang(Ia)_Br1-Brm branch m (m= 2, 3, 4, 5) of winding differential 0 deg
protection.

Angle between phase-B currents of branch 1 and


18 87W.Ang(Ib)_Br1-Brm branch m (m= 2, 3, 4, 5) of winding differential 0 deg
protection.

Angle between phase-C currents of branch 1 and


19 87W.Ang(Ic)_Br1-Brm branch m (m= 2, 3, 4, 5) of winding differential 0 deg
protection.

Angle between calculated residual current of


20 87W.Ang(3I0)_Br1-Brm branch 1 and branch m (m= 2, 3, 4, 5) of winding 0 deg
differential protection.

Corrected coefficient of current for branch m of


21 87W.K_Brm 0.000 /
winding differential protection. (m=1, 2, 3, 4, 5).

5.1.2 Power Value


Access path:

MainMenu  “Measurements”  “Measurements3”  “Power Measurements”

“Power Measurements” is used to display power values.

No. Symbol Definition Unit

1 x.P The primary value of active power (P) MW

2 x.Q The primary value of reactive power (Q) MVAr

3 x.S The primary value of apparent power (S) MVA

4 x.Cos The value of power factor (Cos) -

5.1.3 Temperature Value


Access path:

MainMenu  “Measurements”  “Measurements3”  “Temp Measurements”

“Temp Measurements” is used to display temperature values.

No. Symbol Definition Unit

1 26.T_PhA Calculated temperature of phase A. deg

2 26.T_PhB Calculated temperature of phase B. deg

3 26.T_PhC Calculated temperature of phase C. deg

5.2 Recording
5.2.1 Overview
This device provides the following recording functions:

5-8 PCS-978 Transformer Relay


Date: 2015-06-26
5 Management

1. Event recording

2. Disturbance recording

3. Present recording

All the recording information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform
analysis software.

5.2.2 Event Recording


5.2.2.1 Overview

The device can store the latest 1024 disturbance records, 1024 binary events, 1024 supervision
events and 1024 device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.

5.2.2.2 Disturbance Records

When any protection element operates or drops off, such as fault detector, distance protection etc.,
they will be logged in event records.

5.2.2.3 Supervision Events

The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records.

5.2.2.4 Binary Events

When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records.

5.2.2.5 Device Logs

If an operator implements some operations on the device, such as reboot protective device,
modify setting, etc., they will be logged in event records.

5.2.3 Disturbance Recording


5.2.3.1 Application

Disturbance records can be used to have a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. Analysis of
the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.

5.2.3.2 Design

A disturbance record consists of fault record and fault waveform. The disturbance record can be
initiated by fault detector element, tripping element or configurable signal [BI_TrigDFR].

PCS-978 Transformer Relay 5-9


Date: 2015-06-26
5 Management

5.2.3.3 Capacity and Information of Disturbance Records

The device can store up to 32 disturbance records with waveform in non-volatile memory. It is
based on first in first out queue that the oldest disturbance record will be overwritten by the latest
one.

For each disturbance record, the following items are included:

1. Sequence number

Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.

2. Date and time of fault occurrence

The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.

3. Relative operating time

An operating time (not including the operating time of output relays) is recorded in the record.

4. Faulty phase

5. Protection elements

5.2.3.4 Capacity and Information of Fault Waveform

MON module can store 32 pieces of fault waveform oscillogram in non-volatile memory. If a new
fault occurs when 32 fault waveform have been stored, the oldest will be overwritten by the latest
one.

Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.

Each waveform recording includes pre-fault waveform that is determined by the setting
[Num_Cyc_PreTrigDFR] and post-fault waveform that is 250 cycles at least, and a completed
waveform recording can record 400 cycles at most. Each cycle waveform is high-frequency
recording at a rate of 1200Hz or 1440Hz (24 points per cycle).

5.2.4 Present Recording


Present recording is a waveform triggered manually on on the device′s LCD or remotely through
PCS-Explorer software. Recording content of present recording is same to that of disturbance
recording.

Each waveform recording includes pre-fault waveform that is determined by the setting
[Num_Cyc_PreTrigDFR] and 250-cycles post-fault waveform. Each cycle waveform is
high-frequency recording at a rate of 1200Hz or 1440Hz (24 points per cycle).

5-10 PCS-978 Transformer Relay


Date: 2015-06-26
6 Hardware Description

6 Hardware Description

Table of Contents
6.1 Overview ........................................................................................................... 6-1
6.2 Typical Wiring .................................................................................................. 6-3
6.2.1 Conventional CT/VT Wiring (For Reference Only)............................................................... 6-3

6.2.2 ECT/EVT Wiring (For Reference Only) ................................................................................ 6-5

6.2.3 CT Requirement ................................................................................................................... 6-7

6.3 Plug-in Module Description ............................................................................ 6-8


6.3.1 PWR Plug-in Module (Power Supply) .................................................................................. 6-9

6.3.2 MON Plug-in Module (Monitor & Management) ................................................................. 6-11

6.3.3 AI Plug-in Module (AC Analog Input) ................................................................................. 6-14

6.3.4 DSP Plug-in Module (Protection Calculation) .................................................................... 6-59

6.3.5 DSP Plug-in Module (Fault Detector) ................................................................................. 6-60

6.3.6 BI Plug-in Module (Binary Input) ........................................................................................ 6-60

6.3.7 BO Plug-in Module (Binary Output).................................................................................... 6-67

6.3.8 DI Plug-in Module (DC Analog Input) ................................................................................. 6-71

6.3.9 MR Plug-in Module (Mechanical Relay Input/Output)........................................................ 6-74

6.3.10 NET-DSP module (Optional) ............................................................................................ 6-75

6.3.11 HMI Module ...................................................................................................................... 6-79

6.4 Tripping Output Group .................................................................................. 6-79

List of Figures
Figure 6.1-1 Hardware diagram .................................................................................................. 6-1

Figure 6.1-2 Front view of PCS-978 ........................................................................................... 6-3

Figure 6.1-3 Typical rear view of PCS-978 ................................................................................ 6-3

Figure 6.2-1 Typical wiring of PCS-978 (conventional CT/VT) ............................................... 6-4

Figure 6.2-2 Typical wiring of PCS-978 (ECT/EVT) .................................................................. 6-6

PCS-978 Transformer Relay 6-a


Date: 2016-06-22
6 Hardware Description

Figure 6.3-1 View of PWR plug-in module ................................................................................ 6-9

Figure 6.3-2 Output contacts of PWR plug-in module .......................................................... 6-10

Figure 6.3-3 View of MON plug-in module .............................................................................. 6-11

Figure 6.3-4 Connection of communication terminal ............................................................ 6-13

Figure 6.3-5 Jumpers of clock synchronization port ............................................................ 6-13

Figure 6.3-6 Schematic diagram of CT circuit automatically closed ....................................... 6-14

Figure 6.3-7 View of AI plug-in module (NR1401) .................................................................. 6-15

Figure 6.3-8 Typical CT/VT connection 1 for two-windings transformer ............................ 6-16

Figure 6.3-9 Typical CT/VT connection 2 for two-windings transformer ............................ 6-18

Figure 6.3-10 Typical CT/VT connection 3 for two-windings transformer .......................... 6-20

Figure 6.3-11 Typical CT/VT connection 4 for two-windings transformer .......................... 6-22

Figure 6.3-12 Typical CT/VT connection 5 for two-windings transformer .......................... 6-24

Figure 6.3-13 Typical CT/VT connection 1 for three-windings transformer........................ 6-27

Figure 6.3-14 Typical CT/VT connection 2 for three-windings transformer........................ 6-30

Figure 6.3-15 Typical CT/VT connection 3 for three-windings transformer........................ 6-33

Figure 6.3-16 Typical CT/VT connection 1 for auto-transformer.......................................... 6-36

Figure 6.3-17 Typical CT/VT connection 2 for auto-transformer.......................................... 6-40

Figure 6.3-18 View of AI plug-in module (NR1408) ................................................................ 6-43

Figure 6.3-19 Typical CT/VT connection 1 for two-windings transformer .......................... 6-44

Figure 6.3-20 Typical CT/VT connection 2 for two-windings transformer .......................... 6-46

Figure 6.3-21 Typical CT/VT connection for three-windings transformer........................... 6-49

Figure 6.3-22 View of AI plug-in module (NR1409) ................................................................ 6-52

Figure 6.3-23 Typical CT/VT connection for two-windings transformer ............................. 6-53

Figure 6.3-24 Typical CT/VT connection for three-windings transformer........................... 6-56

Figure 6.3-25 View of DSP plug-in module ............................................................................. 6-59

Figure 6.3-26 View of DSP plug-in module ............................................................................. 6-60

Figure 6.3-27 Voltage dependence for binary inputs ............................................................ 6-61

Figure 6.3-28 Debouncing technique ...................................................................................... 6-61

Figure 6.3-29 View of BI plug-in module (NR1503) ................................................................ 6-62

Figure 6.3-30 View of BI plug-in module (NR1504) ................................................................ 6-63

6-b PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Figure 6.3-31 View of BI plug-in module (NR1508A) ............................................................. 6-65

Figure 6.3-32 View of BO plug-in module (NR1521A) ............................................................ 6-68

Figure 6.3-33 View of BO plug-in module (NR1521H) ............................................................ 6-68

Figure 6.3-34 View of BO plug-in module (NR1580A) ............................................................ 6-69

Figure 6.3-35 View of BO plug-in module (NR1523B) ............................................................ 6-70

Figure 6.3-36 View of BO plug-in module (NR1521C) ............................................................ 6-71

Figure 6.3-37 View of DI plug-in module (NR1410A) ............................................................. 6-72

Figure 6.3-38 View of DI plug-in module (NR1410B) ............................................................. 6-73

Figure 6.3-39 View of MR plug-in module (NR1536A/NR1536B) .......................................... 6-74

Figure 6.3-40 View of the NET-DSP module ........................................................................... 6-75

List of Tables
Table 6.1-1 module configuration .............................................................................................. 6-2

Table 6.3-1 Terminal definition and description of PWR plug-in module ........................... 6-10

Table 6.3-2 Encoding of IEC 61850-7-3 quality....................................................................... 6-76

PCS-978 Transformer Relay 6-c


Date: 2016-06-22
6 Hardware Description

6-d PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

6.1 Overview

The PCS-978 adopts 32-bit microchip processor CPU as control core for logic calculation and
management function, meanwhile, adopts high-speed digital signal processor DSP to be in charge
of all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultra-high reliability and safety of
the device.

Output Relay
Binary Input
External
Protection
Conventional CT/VT A/D Calculation
DSP

ECVT

Fault
A/D Detector Pickup
DSP Relay

ECVT
ETHERNET
LCD +E
GPS
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT

Figure 6.1-1 Hardware diagram

The working process of the device is as follows: firstly, the current and voltage is converted into
small voltage signal and sent to DSP module after being filtered and converted by AD for
protection calculation and fault detector respectively. When DSP module completes all the
protection calculation, the result will be sent to 32-bit CPU on MON module to be recorded.
Protection DSP module carries out protection logic calculation, tripping output, and MON module
completes SOE (sequence of event) record, waveform recording, printing, communication
between protection and SAS and communication between HMI and CPU. The work process of
fault detector DSP module is similar to that of protection DSP module, and the only difference is,
when fault detector DSP module decides a fault detector picks up, only positive power supply of
output relay will be switched on.

The PCS-978 is comprised of intelligent modules, except that few particular modules’ (MON
module DSP module, and PWR module) position cannot be changed in the whole device, the
others like AI (analog input) module such as AC current, AC voltage, DC current, and etc., and IO
(input and output) module such as binary input, tripping output, signal output, and etc can be
flexibly configured according to the remained slot positions.

PCS-978 Transformer Relay 6-1


Date: 2016-06-22
6 Hardware Description

Table 6.1-1 module configuration

No. ID Module description Remark


1 NR1101/NR1102 Management module (MON module) standard
2 NR1156 Protection calculation module (DSP module) standard
3 NR1156 Fault detector calculation module (DSP module) standard
4 NR1401 Analog input module (AI module) standard
5 NR1410 DC analog input module (DI module) option
6 NR1503/NR1504/NR1508 Binary input module (BI module) standard
7 NR1536 Mechanical relay module (MR module) option
8 NR1521/NR1523/NR1580 Binary output module (BO module) standard
9 NR1301 Power supply module (PWR module) standard
GOOSE and SV from merging unit by IEC61850-9-2
10 NR1136 option
(NET-DSP module)
11 Human machine interface module (HMI module) standard

 MON module provides functions like management function, completed event record, setting
management, and etc.

 DSP modules are totally the same, to carry out filtering, sampling and protection calculation
and fault detector calculation respectively.

 AI module converts AC current and voltage to low voltage signals with current transformers
and voltage transformers respectively.

 BI module provides binary input via opto-couplers with rating voltage among
24V/48V/110V/125V/220V/250V opto-coupler (configurable).

 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.

 PWR module converts DC 250/220/125/110V into different DC voltage levels for various
modules of the equipment

 HMI module is comprised of LCD, keypad, LED indicator and test serial ports, and it is
convenient for user to perform human-machine interaction with equipment.

 NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.

PCS-978 is made of a 4U height 19” chassis for flush mounting. Components mounted on its front
include a 320×240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex RJ45
port. A monolithic micro controller is installed in the equipment for these functions.

Following figures show front and rear views of PCS-978 respectively.

6-2 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

1
HEALTHY
11
PCS-978
2 12
ALARM TRANSFORMER RELAY
3 13

4 14

C GRP
5 15

6 16
ENT

ES
7 17

8 18

9 19

10 20

Figure 6.1-2 Front view of PCS-978

20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable. For the 9-button keypad, “ENT” is “enter”, “GRP” is “group number” and
“ESC” is “escape”.

NR1102M NR1156 NR1156 NR1401 NR1401 NR1504 NR1521 NR1521 NR1523B NR1301
1 2 3 1 2 3 5V OK ALM
ETHERNET

4 5 6 4 5 6 BO_ALM BO_FAIL

ON

OFF

DANGER DANGER
1 BO_COM1
2 BO_FAIL

3 BO_ALM

4 BO_COM2

5 BO_FAIL

6 BO_ALM

7 OPTO+

8 OPTO-

9
10 PWR+

11 PWR-

12 GND

Figure 6.1-3 Typical rear view of PCS-978

6.2 Typical Wiring

6.2.1 Conventional CT/VT Wiring (For Reference Only)

NR1102 NR1156 NR1156 NR1401 NR1401 NR1504 NR1521 NR1521 NR1523 NR1301
MON module

PWR module
DSP module

DSP Module

BO module

BO module

BO module
AI module

AI module

BI module

Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

PCS-978 Transformer Relay 6-3


Date: 2016-06-22
6 Hardware Description

The following typical wiring is given based on above hardware configuration

0401

0402
0403

0404
0405

0406
0407

0408
0409

0410
0411

0412
0413

0414
0415

0416
0417

0418
0419

0420
0421

0422
0423

0424
Ua

Ub

Uc
Ia

Ib

Ia

Ib

Ia

Ib
Ic

Ic

Ic
AI plug-in module

1201 Power supply supervision 1301


BO_01
1302

1202 + BI_01 1303


BO_02
1304

*BI plug-in module can be independent common terminal


1305

BO_03
1306
1207 + BI_06 ……

1208 1317
Not used BO_09
1318
1209 + BI_07 1319
BO_10

BO plug-in module for trip


1320

1321
BO_11
1214 + BI_12 1322

1215 1401
Not used BO_01
1402
1216 + BI_13 1403
BO_02
1404

1405
BO_03
1221 + BI_18 1406
……
1222 - 1417
BO_09
1418
PWR+ P110 1419
External DC power Power BO_10
supply P111 Supply 1420
PWR-
P107 1421
OPTO+ BO_11
Power supply for 1422
opto-coupler (24V) P108
OPTO-
P102 BO_FAIL
P103 1501
BO_ALM BO_01
P101 1502
COM
P105 1503
BO_FAIL BO_02
BO plug-in module for signal

P106 1504
BO_ALM
P104 1505
COM BO_03
P112 1506
Transducer_24V_Return

……
To_Transducer_24V

Grounding Screw 1517


Grounding Bus BO_09
1518
1519
Optional optical or electrical Ethernet to SCADA
COM(optonal)

485-1A 0101 BO_10


1520
cable with single point earthing
To the screen of other coaxial

485-1B 0102
1521
SGND 0103 BO_11
1522
0104

SYN+ 0101 S3
Clock SYN

Input_-
Jumper

SYN- 0102 0-20mA


SGND 0103 Input_+ or 0-5V
S1
0104
Current input+
RTS 0105
PRINT

PT100

Current input-
TXD 0106
Measurement input+
SGND 0107 Multiplex RJ45 (Front) Measurement input-

AI plug-in module
3I0

3I0

3I0
Ub

Ua
Uc

Reserved voltage input


Ib

Ia
Ic
0624

0623
0622

0621
0620

0619
0618

0617
0616

0615
0614

0613
0612

0611
0610

0609
0608

0607
0606

0605
0604

0603
0602

0601

Figure 6.2-1 Typical wiring of PCS-978 (conventional CT/VT)

6-4 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

PCS-978 (conventional CT/VT and conventional binary output)

Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

Module ID NR1102 NR1156 NR1156 NR1401 NR1401 NR1504 NR1521 NR1521 NR1523B NR1301

MON DSP DSP AI AI BI BO BO BO PWR

PCS-978 (conventional CT/VT and GOOSE binary output)

Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

Module ID NR1102 NR1156 NR1156 NR1401 NR1401 NR1136 NR1504 NR1521 NR1521 NR1523B NR1301
NET-
MON DSP DSP AI AI BI BO BO BO PWR
DSP

6.2.2 ECT/EVT Wiring (For Reference Only)

Typical configuration of PCS-978 connected to ECT/EVT configuration is given as below for


reference.

NR1102 NR1156 NR1156 NR1136 NR1136 NR1504 NR1521 NR1521 NR1523 NR1301
NET-DSP Module

NET-DSP Module
MON module

PWR module
DSP module

DSP Module

BO module

BO module

BO module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

The following typical wiring is given based on above hardware configuration

PCS-978 Transformer Relay 6-5


Date: 2016-06-22
6 Hardware Description

MU

RX TX …… RX TX RX TX RX TX …… RX TX RX TX
Channel 8 Channel 2 Channel 1 Channel 8 Channel 2 Channel 1
RX
NET-DSP plug-in module (optional IRIG-B)

1201 Power supply supervision 1301


BO_01
1302

1202 + BI_01 1303


BO_02
1304

*BI plug-in module can be independent common terminal


1305
… BO_03
1306
1207 + BI_06 ……

1208 1317
Not used BO_09
1318
1209 + BI_07 1319
BO_10

BO plug-in module for trip


1320

1321
BO_11
1214 + BI_12 1322

1215 1401
Not used BO_01
1402
1216 + BI_13 1403
BO_02
1404

1405
BO_03
1221 + BI_18 1406
……
1222 - 1417
BO_09
1418
PWR+ P110 1419
External DC power Power BO_10
supply P111 Supply 1420
PWR-
P107 1421
OPTO+ BO_11
Power supply for 1422
opto-coupler (24V) P108
OPTO-
P102 BO_FAIL
P103 1501
BO_ALM BO_01
P101 1502
COM
P105 1503
BO_FAIL BO_02
BO plug-in module for signal

P106 1504
BO_ALM
P104 1505
COM BO_03
P112 1506
…… Transducer_24V_Return

To_Transducer_24V
Grounding Screw 1517
Grounding Bus BO_09
1518
1519
Optional optical or electrical Ethernet to SCADA
COM(optonal)

485-1A 0101 BO_10


1520
cable with single point earthing
To the screen of other coaxial

485-1B 0102
1521
SGND 0103 BO_11
1522
0104

SYN+ 0101 S3
Clock SYN

Input_-
Jumper

SYN- 0102 0-20mA


SGND 0103 Input_+ or 0-5V
S1
0104
Current input+
RTS 0105
PRINT

PT100

Current input-
TXD 0106
Measurement input+
SGND 0107 Multiplex RJ45 (Front) Measurement input-

Figure 6.2-2 Typical wiring of PCS-978 (ECT/EVT)

6-6 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

PCS-978 ECT/EVT, GOSSE, with conventional BI and BO

Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

Module ID NR1102 NR1151 NR1151 NR1136 NR1136 NR1504 NR1521 NR1521 NR1523B NR1301
NET- NET-
MON DSP DSP BI BO BO BO PWR
DSP DSP

PCS-978 ECT/EVT, GOSSE, without conventional BI and BO

Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

Module ID NR1102 NR1151 NR1151 NR1136 NR1136 NR1504 NR1301


NET- NET-
MON DSP DSP BI PWR
DSP DSP

In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. Two DSP modules respectively receive the data from merging unit
through the optical-fibre interface to complete the protection calculation and fault detector.

The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.

6.2.3 CT Requirement
-Rated primary current Ipn:

According to the rated current or maximum load current of primary apparatus.

-Rated continuous thermal current Icth:

According to the maximum load current

-Rated short-time thermal current Ith and rated dynamic current Idyn:

According to the maximum fault current

-Rated secondary current Isn

-Accuracy limit factor Kalf:

Ipn Rated primary current (amps)


Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor Kalf=Ipal/Ipn
IPal Rated accuracy limit primary current (amps)

Performance verification

Esl > Esl′

Rated secondary limiting e.m.f (volts)


Esl
Esl = kalf×Isn×(Rct+Rbn)

PCS-978 Transformer Relay 6-7


Date: 2016-06-22
6 Hardware Description

Kalf Accuracy limit factor (Kalf=Ipal/Ipn)


IPal Rated accuracy limit primary current (amps)
Ipn Rated primary current (amps)
Isn Rated secondary current (amps)
Rct Current transformer secondary winding resistance. (ohms)
Rated resistance burden (ohms)
Rbn
Rbn=Sbn/Isn2
Sbn Rated burden (VAs)

Required secondary limiting e.m.f (volts)


Esl′
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k stability factor = 2
Protective checking factor current (amps)
Ipcf
Same as the maximum prospective fault current
Isn Rated secondary current (amps)
Rct Current transformer secondary winding resistance. (ohms)
Real resistance burden (ohms)
Rb
Rb=Rr+2×RL+Rc
Rc Contact resistance, 0.05-0.1 ohm (ohms)
RL Resistance of a single lead from relay to current transformer (ohms)
Rr Impedance of relay phase current input (ohms)
Ipn Rated primary current (amps)

For example:

1. Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA

Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn2)

= 30×5×(1+60/25)=510V

2. Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A

Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn

= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn

= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V

Thus, Esl > Esl′

6.3 Plug-in Module Description

The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module, MR plug-in module, DI plug-in module and
NET-DSP plug-in module. Terminal definitions and application of each plug-in module are
introduced as follows.

6-8 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

6.3.1 PWR Plug-in Module (Power Supply)


PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2 “Technical Data”. The standardized output voltages
are +5V and +24V DC. The tolerances of the output voltages are continuously monitored.

The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device.

The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.

A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
as below.

NR1301

5V OK ALM

BO_ALM BO_FAIL

ON

OFF

1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND

Figure 6.3-1 View of PWR plug-in module

The power switch in the dotted box of above figure maybe is not existed.

PCS-978 Transformer Relay 6-9


Date: 2016-06-22
6 Hardware Description

01
BO_FAIL
02
BO_ALM
03

04
BO_FAIL
05
BO_ALM
06

Figure 6.3-2 Output contacts of PWR plug-in module

Terminal definition and description is shown as follows:

Table 6.3-1 Terminal definition and description of PWR plug-in module

Terminal No. Symbol Description

01 BO_COM1 Common terminal 1

02 BO_FAIL Device failure output 1 (01-02, NC)

03 BO_ALM Device abnormality alarm output 1 (01-03, NO)

04 BO_COM2 Common terminal 2

05 BO_FAIL Device failure output 2 (04-05, NC)

06 BO_ALM Device abnormality alarm output 2 (04-06, NO)

07 OPTO+ Positive power supply for BI module (24V)

08 OPTO- Negative power supply for BI module (24V)

09 Blank Not used

10 PWR+ Positive input of power supply for the device (250V/220V/125V/110V)

11 PWR- Negative input of power supply for the device (250V/220V/125V/110V)

12 GND Grounded connection of the power supply

NOTICE!

The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input
voltage is out of range, an alarm signal (Fail_Device) will be issued. For non-standard
rated voltage power supply module please specify when place order, and check if the
rated voltage of power supply module is the same as the voltage of power source
before the device being put into service.

PWR module provides terminal 12 and grounding screw for device grounding. Terminal
12 shall be connected to grounding screw and then connected to the earth copper bar
of panel via dedicated grounding wire.

Effective grounding is the most important measure for a device to prevent EMI, so
effective grounding must be ensured before the device is put into service.

PCS-978, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not

6-10 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

applied periodically. Deterioration can be avoided by powering the relays up once a


year.

6.3.2 MON Plug-in Module (Monitor & Management)

MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.

MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces that exchange information with above system by
using IEC 61850, PPS/IRIG-B differential time synchronization interface and RS-232 printing
interface.

Modules with various combinations of memory and interface are available as shown in the table
below.

CAUTION!

Do NOT look into the end of an optical fiber connected to an optical port.

Do NOT look into an optical port/connector.

A direct sight to laser light may cause temporary or permanent blindness.

NR1102M NR1102N NR1101D NR1101F

TX
ETHERNET
ETHERNET ETHERNET
RX

TX

RX

ETHERNET

Figure 6.3-3 View of MON plug-in module

PCS-978 Transformer Relay 6-11


Date: 2016-06-22
6 Hardware Description

Module ID Memory Interface Terminal No. Usage Physical Layer


4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN- To clock Twisted pair wire
RS-485/TTL
03 SGND synchronization
NR1102M 256M DDR
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
2 FO Ethernet To SCADA Optical fiber ST
01 SYN+
02 SYN- To clock
RS-485/TTL Twisted pair wire
NR1102N 256M DDR 03 SGND synchronization
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
2 RJ45 Ethernet To SCADA
01 A
02 B
RS-485 To SCADA
03 SGND
04
05 A
Twisted pair wire
06 B
RS-485 To SCADA Cable
07 SGND
NR1101D 256M DDR 08
09 SYN+
10 SYN- To clock
RS-485/TTL
11 SGND synchronization
12
13 RTS
14 TXD
RS-232 To printer Cable
15 SGND
16
3 RJ45 Ethernet To SCADA
01 A
NR1101F 02 B
RS-485 To SCADA
(Support 03 SGND Twisted pair wire
256M DDR
independent 04 Cable
MAC) 05 A
RS-485 06 B To SCADA
07 SGND

6-12 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

08
09 SYN+
10 SYN- To clock
RS-485/TTL
11 SGND synchronization
12
13 RTS
14 TXD
RS-232 To printer Cable
15 SGND
16

The correct method of connection is shown in Figure 6.3-4. Generally, the shielded cables with two
pairs of twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to
connect the “+” and “–” terminals of differential signal; the other pair of twisted pairs are used to
connect the signal ground of the interface, i.e. connect the signal groundings of all the devices
connected with the bus to the twisted pair. The module reserves a free terminal for all the
communication ports; the blank terminal does not need to be connected.

Twisted pair wire


A 01

B 02

COM
SGND 03
cable with single point earthing
To the screen of other coaxial

04

Twisted pair wire


SYN+ 01 Clock SYN

SYN- 02

SGND 03

04

Cable
RTS 05
PRINT

TXD 06

SGND 07

Figure 6.3-4 Connection of communication terminal

Pin1

Pin2

Pin3

Figure 6.3-5 Jumpers of clock synchronization port

PCS-978 Transformer Relay 6-13


Date: 2016-06-22
6 Hardware Description

NOTICE!

As shown in Figure 6.3-5, the external receiving mode of IRIG-B differential time
synchronization interface can be set by the jumper J8&J9.

Jumper RS-485 TTL


J8 Pin-1 and Pin-2 are connected. (RS-485+) Pin-2 and Pin-3 are connected. (TTL+)
J9 Pin-1 and Pin-2 are connected. (RS-485-) Pin-2 and Pin-3 are connected. (TTL-)

6.3.3 AI Plug-in Module (AC Analog Input)


AI module can transform these high AC input values to relevant low AC output value for the DSP
module. The transformers are used both to step-down the currents and voltages to levels
appropriate to the electronic circuitry of this device and to provide effective isolation between this
device and the power system. A low pass filter circuit is connected to each transformer (CT or VT)
secondary circuit for reducing the noise of each analog AC input signal. However, the module is
not required if the device is used with ECT/EVT.

For AI module, if the plug is not put in the socket, external CT circuit is closed itself. Just shown as
below:

Plug
Socket

In

Out

plug is not put in the socket

In

Out

Put the plug in the socket

Figure 6.3-6 Schematic diagram of CT circuit automatically closed

There are four types of AI module with rating 1A (NR1401), 5A (NR1401), 1A/5A (NR1408) or
1A/5A (NR1409). Please declare which kind of AI module is needed before ordering. Maximum

6-14 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

linear range of the current converter is 40In.

NOTICE!

Because the rated value of the input current transformer is optional, it is necessary to
check whether the rated values of the current transformer inputs are accordant to the
demand of the engineering before putting the device into operation.

 NR1401

It has 12 input transformers, and each channel can be configured as a specified current or voltage
channel by PCS-Explorer software according to user requirements. There are four kinds of typical
application module as following shows.

1. Type A: 6I and 6U, 6 current channels and 6 voltage channels

2. Type B: 9I and 3U, 9 current channels and 3 voltage channels

3. Type C: 12I, 12 current channels

4. Type D: 12U, 12 voltage channels

A 24-pin connector is fixed on the front of this module, and its pin definition is described as below.

01 I1 02 I1n 01 I1 02 I1n 01 I1 02 I1n 01 U1 02 U1n


NR1401
03 I2 04 I2n 03 I2 04 I2n 03 I2 04 I2n 03 U2 04 U2n

05 I3 06 I3n 05 I3 06 I3n 05 I3 06 I3n 05 U3 06 U3n

07 I4 08 I4n 07 I4 08 I4n 07 I4 08 I4n 07 U4 08 U4n

09 I5 10 I5n 09 I5 10 I5n 09 I5 10 I5n 09 U5 10 U5n

11 I6 12 I6n 11 I6 12 I6n 11 I6 12 I6n 11 U6 12 U6n

13 U1 14 U1n 13 I7 14 I7n 13 I7 14 I7n 13 U7 14 U7n

15 U2 16 U2n 15 I8 16 I8n 15 I8 16 I8n 15 U8 16 U8n

17 U3 18 U3n 17 I9 18 I9n 17 I9 18 I9n 17 U9 18 U9n

19 U4 20 U4n 19 U1 20 U1n 19 I10 20 I10n 19 U10 20 U10n

21 U5 22 U5n 21 U2 22 U2n 21 I11 22 I11n 21 U11 22 U11n

23 U6 24 U6n 23 U3 24 U3n 23 I12 24 I12n 23 U12 24 U12n

Figure 6.3-7 View of AI plug-in module (NR1401)

NOTICE!

In above figure, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12 and U1, U2, U3, U4, U5, U6,
U7, U8, U9, U10, U11, U12 are polarity terminals of corresponding relevant voltage and
current inputs respectively.

1. Typical application 1 for two-windings transformer

PCS-978 Transformer Relay 6-15


Date: 2016-06-22
6 Hardware Description

In this application, there are one branch at HV side and two branches at LV side without voltage
input.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 12 current channels

The CT/VT wiring diagram for the application is shown below.

LV side 2

*
A

*
B

*
C

HV side LV side 1
*

*
A A
*

*
B B
*

*
C C
*

0420 0422
0419 0421
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0413
0414
0415
0416
0417
PCS-978 0418

Figure 6.3-8 Typical CT/VT connection 1 for two-windings transformer

The following table lists the pin definition of AI module.

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

0403 I2 Ib_H The phase B current input of HV side (polarity).

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

6-16 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0407 I4 Ia_L1 The phase A current input of LV side 1 (polarity).

0408 I4n Ian_L1 The phase A current input of LV side 1.

0409 I5 Ib_L1 The phase B current input of LV side 1 (polarity).

0410 I5n Ibn_L1 The phase B current input of LV side 1.

0411 I6 Ic_L1 The phase C current input of LV side 1 (polarity).

0412 I6n Icn_L1 The phase C current input of LV side 1.

0413 I7 Ia_L2 The phase A current input of LV side 2 (polarity).

0414 I7n Ian_L2 The phase A current input of LV side 2.

0415 I8 Ib_L2 The phase B current input of LV side 2 (polarity).

0416 I8n Ibn_L2 The phase B current input of LV side 2.

0417 I9 Ic_L2 The phase C current input of LV side 2 (polarity).

0418 I9n Icn_L2 The phase C current input of LV side 2.

0419 I10 3I0_H The neutral current input of HV side (polarity).

0420 I10n 3I0n_H The neutral current input of HV side.

0421 I11 3I0_L The neutral current input of LV side (polarity).

0422 I11n 3I0n_L The neutral current input of LV side.

0423 I12 Reserved

0424 I12n Reserved

2. Typical application 2 for two-windings transformer

In this application, there is one branch at HV side and LV side respectively with voltage input at HV
side.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 9 current channels and 3 voltage channels

The CT/VT wiring diagram for the application is shown below.

PCS-978 Transformer Relay 6-17


Date: 2016-06-22
6 Hardware Description

HV side LV side

*
A A

*
B B

*
C C

*
0414 0416
0413 0415
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0419
0420
0421
0422
0423
0424 PCS-978

Figure 6.3-9 Typical CT/VT connection 2 for two-windings transformer

The following table lists the pin definition of AI module.

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

0403 I2 Ib_H The phase B current input of HV side (polarity).

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

0407 I4 Ia_L The phase A current input of LV side (polarity).

0408 I4n Ian_L The phase A current input of LV side.

0409 I5 Ib_L The phase B current input of LV side (polarity).

0410 I5n Ibn_L The phase B current input of LV side.

0411 I6 Ic_L The phase C current input of LV side (polarity).

0412 I6n Icn_L The phase C current input of LV side.

0413 I7 3I0_H The neutral current input of HV side (polarity).

0414 I7n 3I0n_H The neutral current input of HV side.

0415 I8 3I0_L The neutral current input of LV side (polarity).

6-18 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0416 I8n 3I0n_L The neutral current input of LV side.

0417 I9 Reserved

0418 I9n Reserved

0419 U1 Ua_H The phase A voltage input of HV side (polarity).

0420 U1n Uan_H The phase A voltage input of HV side.

0421 U2 Ub_H The phase B voltage input of HV side (polarity).

0422 U2n Ubn_H The phase B voltage input of HV side.

0423 U3 Uc_H The phase C voltage input of HV side (polarity).

0424 U3n Ucn_H The phase C voltage input of HV side.

3. Typical application 3 for two-windings transformer

In this application, there is one branch at HV side and LV side respectively with voltage input at HV
side.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 9 current inputs and 3 voltage inputs

The CT/VT wiring diagram for the application is shown below.

PCS-978 Transformer Relay 6-19


Date: 2016-06-22
6 Hardware Description

HV side LV side

*
A A

*
B B

*
C C

0416 0415

0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0419
0420
0421
0422
0423
0424 PCS-978

Figure 6.3-10 Typical CT/VT connection 3 for two-windings transformer

The following table lists the pin definition of AI module.

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

0403 I2 Ib_H The phase B current input of HV side (polarity).

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

0407 I4 Ia_L The phase A current input of LV side (polarity).

0408 I4n Ian_L The phase A current input of LV side.

0409 I5 Ib_L The phase B current input of LV side (polarity).

0410 I5n Ibn_L The phase B current input of LV side.

0411 I6 Ic_L The phase C current input of LV side (polarity).

0412 I6n Icn_L The phase C current input of LV side.

6-20 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0413 I7 Reserved

0414 I7n Reserved

0415 I8 3I0_L The neutral current input of LV side (polarity).

0416 I8n 3I0n_L The neutral current input of LV side.

0417 I9 Reserved

0418 I9n Reserved

0419 U1 Ua_H The phase A voltage input of HV side (polarity).

0420 U1n Uan_H The phase A voltage input of HV side.

0421 U2 Ub_H The phase B voltage input of HV side (polarity).

0422 U2n Ubn_H The phase B voltage input of HV side.

0423 U3 Uc_H The phase C voltage input of HV side (polarity).

0424 U3n Ucn_H The phase C voltage input of HV side.

4. Typical application 4 for two-windings transformer

In this application, there is one branch at HV side and LV side respectively with voltage input at HV
and LV sides.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 6 current inputs and 6 voltage inputs
06 NR1401 6 current inputs and 6 voltage inputs

The CT/VT wiring diagram for the application is shown below.

PCS-978 Transformer Relay 6-21


Date: 2016-06-22
6 Hardware Description

HV side LV side

*
A A

*
B B

*
C C

*
0608 0612
0607 0611
0401 0601
0402 0602
0403 0603
0404 0604
0405 0605
0406 0606
0619 0623
0620 0624
0413 0613
0414 0614
0415 0615
0416 0616
0417 0617
0418 PCS-978 0618

Figure 6.3-11 Typical CT/VT connection 4 for two-windings transformer

The following table lists the pin definition of AI module.

Slot 04&05

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

0403 I2 Ib_H The phase B current input of HV side (polarity).

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

0407 I4 Reserved

0408 I4n Reserved

0409 I5 Reserved

0410 I5n Reserved

0411 I6 Reserved

0412 I6n Reserved

0413 U1 Ua_H The phase A voltage input of HV side (polarity).

0414 U1n Uan_H The phase A voltage input of HV side.

0415 U2 Ub_H The phase B voltage input of HV side (polarity).

0416 U2n Ubn_H The phase B voltage input of HV side.

6-22 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0417 U3 Uc_H The phase C voltage input of HV side (polarity).

0418 U3n Ucn_H The phase C voltage input of HV side.

0419 U4 Reserved

0420 U4n Reserved

0421 U5 Reserved

0422 U5n Reserved

0423 U6 Reserved

0424 U6n Reserved

Slot 06&07

Pin No. Original definition New definition Description

0601 I1 Ia_L The phase A current input of LV side (polarity).

0602 I1n Ian_L The phase A current input of LV side.

0603 I2 Ib_L The phase B current input of LV side (polarity).

0604 I2n Ibn_L The phase B current input of LV side.

0605 I3 Ic_L The phase C current input of LV side (polarity).

0606 I3n Icn_L The phase C current input of LV side.

0607 I4 3I0_H The neutral current input of HV side (polarity).

0608 I4n 3I0n_H The neutral current input of HV side.

0609 I5 Reserved

0610 I5n Reserved

0611 I6 3I0_L The neutral current input of LV side (polarity).

0612 I6n 3I0n_L The neutral current input of LV side.

0613 U1 Ua_L The phase A voltage input of LV side (polarity).

0614 U1n Uan_L The phase A voltage input of LV side.

0615 U2 Ub_L The phase B voltage input of LV side (polarity).

0616 U2n Ubn_L The phase B voltage input of LV side.

0617 U3 Uc_L The phase C voltage input of LV side (polarity).

0618 U3n Ucn_L The phase C voltage input of LV side.

0619 U4 3U0_H The residual voltage input of HV side (polarity).

0620 U4n 3U0n_H The residual voltage input of HV side.

0621 U5 Reserved

0622 U5n Reserved

PCS-978 Transformer Relay 6-23


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0623 U6 3U0_L The residual voltage input of LV side (polarity).

0624 U6n 3U0n_L The residual voltage input of LV side.

5. Typical application 5 for two-windings transformer

In this application, there is one branch at HV side and LV side respectively with voltage input at HV
and LV sides.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 6 current inputs and 6 voltage inputs
06 NR1401 6 current inputs and 6 voltage inputs

The CT/VT wiring diagram for the application is shown below.

HV side LV side
*

*
A A
*

*
B B
*

*
C C

0612 0611

0401 0601
0402 0602
0403 0603
0404 0604
0405 0605
0406 0606
0619 0623
0620 0624
0413 0613
0414 0614
0415 0615
0416 0616
0417 0617
0418 PCS-978 0618

Figure 6.3-12 Typical CT/VT connection 5 for two-windings transformer

The following table lists the pin definition of AI module.

Slot 04&05

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

6-24 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0403 I2 Ib_H The phase B current input of HV side (polarity).

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

0407 I4 Reserved

0408 I4n Reserved

0409 I5 Reserved

0410 I5n Reserved

0411 I6 Reserved

0412 I6n Reserved

0413 U1 Ua_H The phase A voltage input of HV side (polarity).

0414 U1n Uan_H The phase A voltage input of HV side.

0415 U2 Ub_H The phase B voltage input of HV side (polarity).

0416 U2n Ubn_H The phase B voltage input of HV side.

0417 U3 Uc_H The phase C voltage input of HV side (polarity).

0418 U3n Ucn_H The phase C voltage input of HV side.

0419 U4 Reserved

0420 U4n Reserved

0421 U5 Reserved

0422 U5n Reserved

0423 U6 Reserved

0424 U6n Reserved

Slot 06&07

Pin No. Original definition New definition Description

0601 I1 Ia_L The phase A current input of LV side (polarity).

0602 I1n Ian_L The phase A current input of LV side.

0603 I2 Ib_L The phase B current input of LV side (polarity).

0604 I2n Ibn_L The phase B current input of LV side.

0605 I3 Ic_L The phase C current input of LV side (polarity).

0606 I3n Icn_L The phase C current input of LV side.

0607 I4 Reserved

0608 I4n Reserved

PCS-978 Transformer Relay 6-25


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0609 I5 Reserved

0610 I5n Reserved

0611 I6 3I0_L The neutral current input of LV side (polarity).

0612 I6n 3I0n_L The neutral current input of LV side.

0613 U1 Ua_L The phase A voltage input of LV side (polarity).

0614 U1n Uan_L The phase A voltage input of LV side.

0615 U2 Ub_L The phase B voltage input of LV side (polarity).

0616 U2n Ubn_L The phase B voltage input of LV side.

0617 U3 Uc_L The phase C voltage input of LV side (polarity).

0618 U3n Ucn_L The phase C voltage input of LV side.

0619 U4 3U0_H The residual current input of HV side (polarity).

0620 U4n 3U0n_H The residual current input of HV side.

0621 U5 Reserved

0622 U5n Reserved

0623 U6 3U0_L The residual current input of LV side (polarity).

0624 U6n 3U0n_L The residual current input of LV side.

6. Typical application 1 for three-windings transformer

In this application, there is one branch at HV side, MV side and LV side respectively with voltage
input at HV side, MV side and LV side.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 6 current inputs and 6 voltage inputs
06 NR1401 6 current inputs and 6 voltage inputs

The CT/VT wiring diagram for the application is shown below.

6-26 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

C
A

B
LV side
* * *

HV side MV side
*

*
A A
*

*
B B
*

*
C C
*

0610
0608
0607 0609
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0619 0621
0620 0622
0413 0419
0414 0420
0415 0421
0416 0422
0417 0423
0418 0424
0601
0602
0603
0604
0605
0606
0623
0624
0613
0614
0615
0616
0617
PCS-978 0618

Figure 6.3-13 Typical CT/VT connection 1 for three-windings transformer

The following tables list the pin definition of AI module.

Slot 04&05

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

0403 I2 Ib_H The phase B current input of HV side (polarity).

PCS-978 Transformer Relay 6-27


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

0407 I4 Ia_M The phase A current input of MV side (polarity).

0408 I4n Ian_M The phase A current input of MV side.

0409 I5 Ib_M The phase B current input of MV side (polarity).

0410 I5n Ibn_M The phase B current input of MV side.

0411 I6 Ic_M The phase C current input of MV side (polarity).

0412 I6n Icn_M The phase C current input of MV side.

0413 U1 Ua_H The phase A voltage input of HV side (polarity).

0414 U1n Uan_H The phase A voltage input of HV side.

0415 U2 Ub_H The phase B voltage input of HV side (polarity).

0416 U2n Ubn_H The phase B voltage input of HV side.

0417 U3 Uc_H The phase C voltage input of HV side (polarity).

0418 U3n Ucn_H The phase C voltage input of HV side.

0419 U4 Ua_M The phase A voltage input of MV side (polarity).

0420 U4n Uan_M The phase A voltage input of MV side.

0421 U5 Ub_M The phase B voltage input of MV side (polarity).

0422 U5n Ubn_M The phase B voltage input of MV side.

0423 U6 Uc_M The phase C voltage input of MV side (polarity).

0424 U6n Ucn_M The phase C voltage input of MV side.

Slot 06&07

Pin No. Original definition New definition Description

0601 I1 Ia_L The phase A current input of LV side (polarity).

0602 I1n Ian_L The phase A current input of LV side.

0603 I2 Ib_L The phase B current input of LV side (polarity).

0604 I2n Ibn_L The phase B current input of LV side.

0605 I3 Ic_L The phase C current input of LV side (polarity).

0606 I3n Icn_L The phase C current input of LV side.

0607 I4 3I0_H The neutral current input of HV side (polarity).

0608 I4n 3I0n_H The neutral current input of HV side.

0609 I5 3I0_M The neutral current input of MV side (polarity).

6-28 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0610 I5n 3I0n_M The neutral current input of MV side.

0611 I6 Reserved

0612 I6n Reserved

0613 U1 Ua_L The phase A voltage input of LV side (polarity).

0614 U1n Uan_L The phase A voltage input of LV side.

0615 U2 Ub_L The phase B voltage input of LV side (polarity).

0616 U2n Ubn_L The phase B voltage input of LV side.

0617 U3 Uc_L The phase C voltage input of LV side (polarity).

0618 U3n Ucn_L The phase C voltage input of LV side.

0619 U4 3U0_H The residual voltage input of HV side (polarity).

0620 U4n 3U0n_H The residual voltage input of HV side.

0621 U5 3U0_M The residual voltage input of MV side (polarity).

0622 U5n 3U0n_M The residual voltage input of MV side.

0623 U6 3U0_L The residual voltage input of LV side (polarity).

0624 U6n 3U0n_L The residual voltage input of LV side.

7. Typical application 2 for three-windings transformer

In this application, there is one branch at HV side, MV side and LV side respectively with voltage
input at HV side, MV side and LV side.

AI Module configuration:

Slot No. Module ID Type


04 NR1401 12 current inputs
06 NR1401 12 voltage inputs

The CT/VT wiring diagram for the application is shown below.

PCS-978 Transformer Relay 6-29


Date: 2016-06-22
6 Hardware Description

C
A

B
LV side
* * *

HV side MV side
*

*
A A
*

*
B B
*

*
C C
*

0422
0419
0420 0421
0401 0413
0402 0414
0403 0415
0404 0416
0405 0417
0406 0418
0619 0621
0620 0622
0601 0613
0602 0614
0603 0615
0604 0616
0605 0617
0606 0618
0407
0408
0409
0410
0411
0412
0623
0624
0607
0608
0609
0610
0611
PCS-978 0612

Figure 6.3-14 Typical CT/VT connection 2 for three-windings transformer

The following tables list the pin definition of AI module.

Slot 04&05

Pin No. Original definition New definition Description

0401 I1 Ia_H The phase A current input of HV side (polarity).

0402 I1n Ian_H The phase A current input of HV side.

0403 I2 Ib_H The phase B current input of HV side (polarity).

6-30 PCS-978 Transformer Relay


Date: 2016-06-22
6 Hardware Description

Pin No. Original definition New definition Description

0404 I2n Ibn_H The phase B current input of HV side.

0405 I3 Ic_H The phase C current input of HV side (polarity).

0406 I3n Icn_H The phase C current input of HV side.

0407 I4 Ia_M The phase A current input of MV side (polarity).

0408 I4n Ian_M The phase A current input of MV side.

0409 I5 Ib_M The phase B current input of MV side (polarity).

0410 I5n Ibn_M The phase B current input of MV side.

0411 I6 Ic_M The phase C current input of MV side (polarity).

0412 I6n Icn_M The phase C current input of MV side.

0413 I7 Ia_L The phase A current input of LV side (polarity).

0414 I7n Ian_L The phase A current input of LV side.

0415 I8 Ib_L The phase B current input of LV side (polarity).

0416 I8n Ibn_L The phase B current input of LV side.

0417 I9 Ic_L The phase C current input of LV side (polarity).

0418 I9n Icn_L The phase C current input of LV side.

0419 I10 3I0_H The neutral current input of HV side (polarity).

0420 I10n 3I0n_H The neutral current input of HV side.

0421 I11 3I0_M The neutral current input of MV side (polarity).

0422 I11n 3I0n_M The neutral current input of MV side.

0423 I12 Reserved

0424 I12n Reserved

Slot 06&07

Pin No. Original definition New definition Description

0601 U1 Ua_H The phase A voltage input of HV side (polarity).

0602 U1n Uan_H The phase A voltage input of HV side.

0603 U2 Ub_H The phase B voltage input of HV side (polarity).

0604 U2n Ubn_H The phase B voltage input of HV side.

0605