0 views

Uploaded by thitana

© All Rights Reserved

- DSP Practical File Programs
- reportFigaro
- Analog to Digital
- 7 Digital
- PCI 6023E
- Measurement of Body Temperature and Heart Rate
- IRJET-Low Frequency CMOS Sigma-Delta Analog to Digital Converter for Medical Application
- 5. Kitchen Timer and Room Thermometer
- TestMSST2010
- Diagnosis of continuous rotor–stator rubbing in large scale turbine units using acoustic emission
- Data Aquisition Fundamental
- Mitra-Ch9 (1) Ch 5 Adsp
- AD7708_7718.pdf
- T2 Analog I-O Modules
- Oemax Nx70 Um002a en p
- slyt640
- Simulation Questions[1]
- job 5
- aa
- Placa Del Receptor

You are on page 1of 102

MS/s SAR-Assisted Pipeline ADC

Iniyavan Elumalai

Master of Science Thesis

A Capacitance-Based Reference

Scheme for a 14b-Linear, 100 MS/s

SAR-Assisted Pipeline ADC

University of Technology

Iniyavan Elumalai

Technology

Copyright © Broadcom Corporation

All rights reserved.

All rights reserved.

Delft University of Technology

Department of

Electrical Engineering

The undersigned hereby certify that they have read and recommend to the Faculty of

Electrical Engineering, Mathematics and Computer Science for acceptance a thesis

entitled

A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s

SAR-Assisted Pipeline ADC

by

Iniyavan Elumalai

in partial fulfillment of the requirements for the degree of

Master of Science Microelectronics

Supervisor(s):

Prof. Dr. John R. Long

Christopher Ward

Reader(s):

Prof. Dr. Kofi Makinwa

Abstract

Voltage reference buffers have always been the most power-hungry blocks in switched-capacitor

SAR ADCs. High frequency dynamic loading of the buffer by the capacitive DAC causes

glitches on the reference voltage, and the buffer has to be fast enough to recover such tran-

sients to 1/2 LSB precision in every bit cycle. Such stringent requirements entail an immensely

capable buffer for high-speed, high-resolution converters. One obvious solution circumventing

the active buffer is to use a stand-alone capacitor that holds the reference voltage during SAR

evaluation. This solution accompanies, besides good power efficiency, excellent DAC settling

speed and noise properties, thereby greatly helping the ADC FoM. Reducing the capacitance

of the stand-alone capacitor for chip area concerns brings in code-dependent errors on the

reference, leading to heavy distortion.

This project implements an area-conscious, capacitance-based reference buffer scheme for

a 14b-linear, 100 MS/s SAR-assisted pipeline ADC in 28 nm CMOS. With moderately-valued

capacitances, two elaborate calibration techniques are proposed that help to suppress the

reference-induced distortion to less than 84 dB, effectively not degrading the SNDR. Designed

for 12-bit SNR, the prototype ADC with the implemented reference scheme consumes

1.81 mW and achieves a Schreier FoM of 175.5 dB.

ii Abstract

Acknowledgments

It feels good to finish a thesis. It feels better to reminisce the times, and thank everyone who

had been of help.

I would like to begin by thanking Dr. Klaas Bult, who, besides introducing me into

the world of circuits with colourful, entertaining slides, provided me with this wonderful

opportunity to work at Broadcom. His support throughout this project is invaluable, and his

knowledge and experience in circuit design will continue to motivate my aspirations.

My supervisors at Broadcom, Christopher Ward and Dr. Frank Van der Goes, had been

of excellent guidance during this project. Chris, with his knack for animated explanations

that clarify even the most obscure of concepts, and Frank, with his never-ending stream of

innovative ideas will remain great sources of inspiration to me.

I would also like to thank my promoter, Prof. John Long for his extensive support. If

the reader finds this thesis uncluttered, if this writing has been at all effective, it is because

of his elaborate and meticulous feedback.

I want to thank Prof. Kofi Makniwa and Dr. Wouter A. Serdijn for teaching me more

of circuits, and am glad that they are serving on my thesis committee.

I am grateful to all the engineers at Broadcom Bunnik for the good times in the office,

and Els Van Zijl for taking good care of me and most of my administrative tasks. I would

like to acknowledge Rohan Sehgal and Nitz Saputra for providing guidance in improving my

thesis.

I owe the best times of my graduate life to my friends, in particular, Vamshi, Sangan,

Mandi, Anna and Jort, who have respectively got me through an arduous year of mount-

ing assignments, minor financial troubles, winter, summer and a precocious post-graduate

delirium.

To my family - amma, appa and akka, thank you for your love and other happy things

in my life.

Table of Contents v

Table of Contents

Abstract i

Acknowledgments iii

1 Introduction 1

1-1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1-2 Limitations of SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1-2-1 SAR Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1-2-2 Requirements on the Reference Buffer . . . . . . . . . . . . . . . . . . 6

1-3 Research Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1-4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2-1 Basic Nonidealities in Charge Redistribution SAR A/D Converters . . . . . . 9

2-1-1 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2-1-2 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2-1-3 Static Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2-1-4 Dynamic Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2-2 Dynamic Performance Measures . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2-3 Speed Limitations of a SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . 15

2-4 Popular Techniques in Relevant Literature . . . . . . . . . . . . . . . . . . . . 15

2-4-1 Asynchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2-4-2 Overranging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2-4-3 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2-5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

vi Table of Contents

3-1 Conventional Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 21

3-2 A Stand-alone Capacitor as the Reference Buffer . . . . . . . . . . . . . . . . 25

3-3 Deterministic Errors on the Reference Voltage . . . . . . . . . . . . . . . . . . 26

3-4 Benefits of the Proposed Reference Scheme . . . . . . . . . . . . . . . . . . . 31

3-5 Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3-6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4-1 Reference-induced Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4-2 Error Compensation in Charge Domain . . . . . . . . . . . . . . . . . . . . . 38

4-3 Implementation Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4-3-1 Systematically Decreasing Vref . . . . . . . . . . . . . . . . . . . . . . 42

4-3-2 Cancelling Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4-3-3 Compensating for a Fewer Cycles . . . . . . . . . . . . . . . . . . . . . 45

4-4 Sources of Inaccuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4-4-1 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4-4-2 Switch Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4-5 Reference Scheme Implementation in the Fine SAR ADC . . . . . . . . . . . 47

4-6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4-7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5-1 Need for Digital Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5-2 Calibration Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5-2-1 Residue Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5-2-2 Calibration Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5-2-3 Deterministic Calibration Procedure . . . . . . . . . . . . . . . . . . . 57

5-3 Reference Scheme Implementation in Coarse SAR ADC . . . . . . . . . . . . 58

5-3-1 System-level Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5-3-2 Circuit-level Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5-4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5-5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6 Conclusion 71

6-1 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6-2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

A-1 Set-and-down Switching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 76

A-2 Split-capacitor Switching Algorithm . . . . . . . . . . . . . . . . . . . . . . . 77

Bibliography 79

List of Figures vii

List of Figures

1-2 State-of-the-art ADCs with their Schreier FoM . . . . . . . . . . . . . . . . . . . 3

1-3 Simplified schematic of a charge redistribution SAR ADC . . . . . . . . . . . . . 4

1-4 Capacitive DAC configurations during different phases of operation for the 4-bit

digital code: 0110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1-5 DAC voltage during the conversion phase for the 4-bit digital code: 0110 . . . . 6

2-2 Thermal noise in a charge redistribution SAR ADC . . . . . . . . . . . . . . . . 11

2-3 Differential and integral non-linearity in an ADC . . . . . . . . . . . . . . . . . . 12

2-4 Effect of incomplete DAC settling on the conversion result . . . . . . . . . . . . 13

2-5 Dynamic performance of a non-ideal 14-bit ADC . . . . . . . . . . . . . . . . . 14

2-6 Timing in a synchronous clocking scheme . . . . . . . . . . . . . . . . . . . . . 15

2-7 Timing in an asynchronous clocking scheme . . . . . . . . . . . . . . . . . . . . 16

2-8 SAR conversion illustrating easy and hard decisions . . . . . . . . . . . . . . . . 17

2-9 Effect of incomplete DAC settling on the conversion result in the presence of

overranging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2-10 A two-stage, SAR-assisted pipeline ADC . . . . . . . . . . . . . . . . . . . . . . 19

3-2 Code-dependent transients on Vref recovered by the charge supplied by the buffer 22

3-3 Surface plot of the current required in the reference buffer versus sampling fre-

C

quency and the ratio Cref

dac

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3-4 (a) Reference capacitor disconnected during SAR conversion (b) Code-dependent,

deterministic errors on Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3-5 3-bit set-and-down switching procedure . . . . . . . . . . . . . . . . . . . . . . 27

viii List of Figures

3-7 Two different switching scenarios in bit cycle i = 0 . . . . . . . . . . . . . . . . 28

3-8 Different possible reference charges for a 3-bit set-and-down switching procedure 29

3-9 Possible values of reference charge per step for an 8-bit set-and-down switching

procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3-10 Total reference charge versus output code for an 8-bit set-and-down switching

procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3-11 Two-stage, SAR-assisted pipeline ADC . . . . . . . . . . . . . . . . . . . . . . . 32

with Cref = Cdac (simulated in MATLAB) . . . . . . . . . . . . . . . . . . . . . 36

4-2 Reference voltage at the end of the Convert phase versus 8-bit output code (sim-

ulated in MATLAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4-3 Performance of an actual 8-bit ADC with binary-weighted DAC and stand-alone

reference capacitor, Cref = Cdac . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4-4 Performance of an actual 8-bit ADC with binary-weighted DAC and stand-alone

reference capacitor, Cref = 10Cdac . . . . . . . . . . . . . . . . . . . . . . . . . 37

4-5 Conceptual illustration of error compensation in charge domain . . . . . . . . . . 38

4-6 Code-dependent errors on Vref in the case of 5-bit set-and-down switching . . . 39

4-7 Illustration of compensation in bit cycle i = 3 . . . . . . . . . . . . . . . . . . . 40

4-8 Illustration of compensation in bit cycle i = 2 . . . . . . . . . . . . . . . . . . . 41

4-9 Conceptual illustration of reference compensation loop (in grey) along with the

main SAR loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4-10 Compensation for (a) constant Vref , and (b) code-independent, systematically

decreasing Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4-11 Effect of Vref dropping to ′

Vref on effective signal coverage (a) with conventional

capacitive division ratio, and (b) with appropriately changed capacitive division . 43

4-12 Removing the code-dependent spread in Vref (a) by adding charge, and (b) by

removing charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4-13 Effect of DAC capacitor mismatch on the code-dependent errors in Vref (simulated

in MATLAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4-14 Single-ended schematic of the capacitive DAC in the fine stage . . . . . . . . . . 48

4-15 Examples of positive and negative DAC voltage waveforms in the fine stage . . . 48

4-16 Effective signal coverage per bit cycle with the designed cap. radix, taking into

account the code-independent drops in Vref and nominal switch charge injection

in every bit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4-17 Fine ADC performance with the designed reference scheme including charge-based

compensation in 3 bit cycles, and changed capacitive radix to accommodate the

code-independent drop in Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5-2 Ideal residue characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5-3 Effect of reference errors on the DAC tree . . . . . . . . . . . . . . . . . . . . . 54

List of Figures ix

5-5 DAC voltage modulation in an additional step after SAR conversion . . . . . . . 55

5-6 DAC tree with three different cases of DAC voltage modulation . . . . . . . . . . 56

5-7 Determining h1 (j) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5-8 Determining h2 (j) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5-9 Timing for the two ADC lanes in the prototype during calibration . . . . . . . . 59

5-10 Simplified block diagram of the coarse ADC . . . . . . . . . . . . . . . . . . . . 59

5-11 Schematic of the latch in the main SAR loop . . . . . . . . . . . . . . . . . . . 60

5-12 Flipped voltage follower and its output impedance versus frequency . . . . . . . 61

5-13 Schematic of the implemented pre-charge buffer . . . . . . . . . . . . . . . . . . 63

5-14 Transient response of the implemented pre-charge buffer . . . . . . . . . . . . . 64

5-15 Allowed locations for the test voltages required during calibration . . . . . . . . . 64

5-16 Schematic of a unit current cell . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5-17 Schematic of the output network in the calibration DAC . . . . . . . . . . . . . 65

5-18 Transfer function of the implemented calibration DAC . . . . . . . . . . . . . . . 66

5-19 Worst-case INL/ DNL performance of the implemented calibration DAC . . . . . 66

5-20 INL of the capacitive DAC with Cref = 20Cdac before calibration . . . . . . . . . 67

5-21 Coarse ADC performance with Cref = 20Cdac before calibration . . . . . . . . . 68

5-22 INL of the capacitive DAC with Cref = 20Cdac after calibration . . . . . . . . . 68

5-23 Coarse ADC performance with Cref = 20Cdac after calibration . . . . . . . . . . 69

6-1 Schreier FoM plot of the state-of-the-art ADCs along with the prototype . . . . . 72

A-2 Illustration of set-and-down switching algorithm in step i . . . . . . . . . . . . . 77

A-3 Illustration of split-cap switching algorithm in step i . . . . . . . . . . . . . . . . 78

x List of Figures

List of Tables xi

List of Tables

5-2 Specifications for the calibration DAC . . . . . . . . . . . . . . . . . . . . . . . 65

xii List of Tables

Chapter 1

Introduction

At the time of writing this dissertation, it is evident that mobile handset usage has long ago

surpassed critical mass. Room for further sustenance lies in the efforts to deliver a service to

end users that ideally expect instant, on-the-go access to a multitude of wireless services from

their battery-powered handsets. In that regard, the recent past has witnessed standardization

efforts for future wireless usage that accommodate seamless data delivery at faster rates with

better quality of service. What with the ever-growing list of wireless usage scenarios ranging

from telephony and mobile internet to short-range communications and data tethering, the

device manufacturers have a hard time building and integrating interfaces to several such

standards in a single chipset. Achieving a unified, portable hardware platform that supports

simultaneous reception of multiple modes and services from a battery power source requires

rigorous research and innovation efforts from the industry.

Present-day 3G/4G receivers offer simultaneous reception by employing parallel radio

front ends, with the IF and baseband sections for different standards occasionally sharing

resources. The analog-intensive RF portions remain dedicated to each and every standard.

Despite offering flexibility to orthogonally optimize each radio and achieve low power, this

approach does not seem attractive in terms of size and cost for future multi-standard handsets.

An alternative, more promising realization would be the software-defined radio (SDR) as

envisaged by Mitola [1], where the signal is digitized at RF with an analog-to-digital converter

(ADC) close to the antenna, and the entire signal processing definitions are realized in the

completely reconfigurable, low-cost digital domain. This idealistic approach, however, remains

elusive as the specifications imposed on the ADC are not within sight at present.

For a radio platform covering all the current wireless standards from 800 MHz to 6 GHz

[2], Nyquist-sampled data conversion is required at a sampling speed above 12 GS/s. Fur-

thermore, since this approach does not proffer the radio with any tolerance to the interferers,

which could be as high as 100 dB larger than the desired signal, the ADC should also have

an extraordinary dynamic range. Extrapolating from a survey of currently existent data con-

verters [3] as shown by the dotted lines in Figure 1-1, such an ADC would dissipate around

1 kW - far from the tolerable level of 20 mW given currently available batteries - which is

clearly impractical in a portable handset. The requirements could only grow more stringent as

2 Introduction

time progresses, considering the inevitable increase in the number and strength of interferers.

Therefore, it becomes necessary to look at the current directions in ADC design, and work

out the significant challenges towards realizing a low-power, raw ADC located close to the

antenna, which will eventually enable frequency-agile cognitive radios for mobile handsets.

This research work is one such effort.

1-1 Motivation

Figure 1-1 presents the state-of-the-art ADCs published at the recent ISSCC and VLSI confer-

ences with their power efficiency, expressed as energy per Nyquist sample (P ower/fs , where

fs is the sampling clock frequency), logarithmically plotted against the ADC’s signal-to-noise

and distortion ratio (SNDR) in dB. The plot also includes the benchmark lines corresponding

to figures of merit (FoM) commonly used for gauging a converter’s energy efficiency.

1.E+06

ISSCC 2008-2013

1.E+05 VLSI 2008-2012

~ 1 kW for fs = 12 GHz

1.E+04

P/fs [pJ]

1.E+02

1.E+01

FOMW = 10 fJ/conversion-step

1.E+00

1.E-01

10 20 30 40 50 60 70 80 90 100 110

SNDR at fnyq [dB]

P ower

F oMW = , (1-1)

fs ∗ 2EN OB

normalizes the energy per Nyquist sample by the effective number of bits resolved (ENOB)

under the assumption that doubling the precision doubles the power consumption. While this

holds for low-to-medium resolution converters, as illustrated by a benchmark trend line of

1-1 Motivation 3

to alleviate thermal noise call for another figure of merit.

The Schreier FoM [5], given by

fs

F oMS = SN DR + 10 ∗ log , (1-2)

P ower

predicts a 4x increase per every added bit, after approximately 75 dB SNDR, where the

thermal noise limitation mostly supersedes that of quantization. The plot in Figure 1-2

displays Schreier FoMs of aforementioned ADCs against their Nyquist sampling rate, with

the dashed lines representing the limitation of presently available technology. Achieving the

ultimate ADC FoM for simultaneous full-band capture in a mobile radio front end, indicated

by the red asterisk in the top right of the plot, requires several careful steps, and might take

a few years benefiting from technology scaling.

190

Target

180

170

160

FOMS [dB]

150

140

SAR-based

130 Others

120

110

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

f s [Hz]

Besides device scaling, moving the energy efficiency to higher speeds can be expected

from the popular technique of time-interleaving several ADC lanes that operate efficiently at

moderate speeds. The overhead to resolve the problems arising from interleaving, however,

counteracts the improvement in FoM. This necessitates research efforts in two directions:

(1) resolving the errors due to time-interleaving [6] with minimal power overhead, and (2)

improving the speeds of individual, energy-efficient ADC lanes. The latter approach fuels the

motivation of this research.

4 Introduction

The empirical data show that converters based on the successive approximation prin-

ciple (SAR) promise excellent energy efficiency at moderate speeds (as evident in Figure

1-2). Boasting minimal analog complexity, the SAR architecture gets clear benefits from the

continuous scaling of digital circuitry, and seems well-suited to deep-submicron technologies.

However, since the successive approximation is performed by iterations of decision making,

the architecture falters in speed at high resolutions. The goal of this research is to relieve the

SAR architecture of its speed limitations without compromising on its power efficiency.

Before discussing the various speed limitations in the SAR architecture, a brief overview of

its operation is given.

The most popular implementation of the SAR A/D converter is a charge-redistribution SAR

[7], a simplified N-bit schematic of which is shown in Figure 1-3. The core of the converter,

comprising reference voltage circuitry, a binary comparator, SAR control logic, switches and

an array of radix-weighted capacitors (CN , CN −1 , ..., C0 ), implements a radix-based search

for the sampled input through all of the reference quantization levels before converging on

the digital output. The digital-to-analog conversion (DAC) is by virtue of the capacitor array

and switches, which successively approximates the input voltage. The conversion process in

a binary SAR is detailed next with an illustration of a 4-bit binary conversion.

Vdac − Vi

CN CN −1 C1 C0

Vref

Vi Switch array SAR Logic

Dout

Figure 1-3: Simplified schematic of a charge redistribution SAR ADC

The input signal Vi is first sampled onto the array of binary-weighted capacitors as shown

in Figure 1-4.a), after which the conversion process starts. The binary search begins at mid-

scale by comparing the acquired input voltage with one-half of the reference voltage. Halving

the reference at the comparator input is performed by connecting the MSB capacitor, whose

capacitance is equal to the sum of the remaining capacitances in the array, to the reference

voltage, and the rest to ground, as shown in Figure 1-4.b). The output of this comparison

represents the MSB decision.

The SAR control logic learns this decision, and knows which half of the signal range is

to be considered for the next comparison. For a positive decision, the SAR creates a decision

1-2 Limitations of SAR 5

8 4 2 1 1

Vi

(a) Sampling

Vref

8

8Vref

16 − Vi

D3 = 0

4 2 1 1

(b) i = 3

Vref

4

4Vref

16 − Vi

D2 = 1

8 2 1 1

(c) i = 2

Vref

4 2

6Vref

16 − Vi

D1 = 1

8 1 1

(d) i = 1

Vref

4 2 1

7Vref

16 − Vi

D0 = 0

8 1

(e) i = 0

Figure 1-4: Capacitive DAC configurations during different phases of operation for the 4-bit

digital code: 0110

threshold at mid-scale in the upper half by connecting the MSB-1 capacitor to the reference

which drives Vdac from 1/2 Vref to 3/4 Vref. For a negative decision, the voltage has to be

driven in the negative direction by the same amount. This is performed as shown in Figure

6 Introduction

1-4.c), by toggling the MSB capacitor from the reference to ground, and connecting the

MSB-1 capacitor to the reference. This comparison localizes the input to a quarter of the

signal range.

As the conversion process progresses with every decision being made, the effective signal

range (represented by a gray bar in Figure 1-5 for every bit cycle) reduces by a factor of two,

and the decision threshold for next comparison is derived from the reference by toggling the

top plate switches accordingly. This process proceeds in a loop: the comparator makes a

decision, the control logic determines the next decision threshold, the DAC settles to the cor-

responding voltage, and so on, until the algorithm converges at the last cycle. The difference

between Vdac and Vi is then less than one LSB, which represents the residual quantization

error. Figure 1-5 shows how the DAC voltage tracks the input during SAR conversion.

Vref

Vdac

Vref /2

<LSB

0 0 1 1 0

(D3 ) (D2 ) (D1 ) (D0 )

time

Figure 1-5: DAC voltage during the conversion phase for the 4-bit digital code: 0110

Refreshing the voltage (Vdac ) every bit cycle to derive different quantization levels from a single

reference requires that the reference source must supply charge throughout the process. The

charge required depends on from where, and to where the node is driven, which indicates the

strong dependence on the switching decisions being made throughout the whole conversion.

Pulling such signal dependent charge from the reference causes fluctuations in the buffered

reference voltage. However, the accuracy requirements on the reference voltage are stringent

at up to 1/2 LSB precision every bit-cycle, the settling time of which in turn fundamentally

limits the ADC conversion speed. It is therefore important to develop techniques that can

deal with such high-frequency disturbances.

1-3 Research Contribution 7

create a constant reference voltage from an off-chip bandgap. Using a fast active buffer implies

that the disturbances settle to the required precision within a bit cycle, that is, before the

next comparison is performed. In high-speed, high-resolution systems, this demands large

currents to be delivered with fast transitions. Voltage reference buffers (mostly employed

off-chip) have always been the most power-hungry blocks in switched-capacitor SAR ADCs

[8, 9]. Furthermore, as predicted in [10], device scaling exacerbates the power dissipation of

such noise-limited, settling-dominated circuits. Also, using large decoupling capacitors such

that the disturbances are reduced to within an LSB also does not seem to be viable in future,

because the bypass capacitance required is around 2N times the total array capacitance, where

N is the required system resolution.

It can be clearly identified that the reference buffer places a serious limitation on the speed

of a SAR, which can only be overcome at the expense of power and area. A novel reference

buffer scheme suitable for high-end SAR converters is proposed in this research project that

improves the SAR speed without compromising power and area efficiency.

solution for fast settling. Reducing the capacitance for area concerns causes signal-dependent

errors on the reference voltage leading to heavy distortion. The basic idea underlying this

proposal is that those signal-dependent errors, as mentioned earlier, are completely determin-

istic given the knowledge of switching decisions being made and thus can be corrected. This

research explores two different techniques of dealing with reference-induced distortion.

With knowledge of the SAR decisions being made, one solution is to compensate the

charge on the reference capacitance by the same amount of charge being pulled from it every

bit cycle. This solution employs a bank of capacitors, from which an appropriate amount of

capacitance holding the required charge is connected to the main reference capacitor when

a switching decision is made that will compensate it accordingly. The other approach is

to allow errors in the analog domain, and then correct them downstream through a digital

calibration scheme. During calibration, the reference error for every digital code is estimated

by processing the corresponding residue voltage, which contains the required information

about the reference voltage at the end of that SAR conversion.

Netherlands, serves as the platform for this study. With two stages employing each of the

aforementioned reference buffer schemes, implementation choices for both of the calibration

techniques are studied in this dissertation. Reasonably-sized reference capacitances that are

not very much larger than the array capacitance will be used. This work attempts to maintain

the reference-induced distortion below 14-bit linearity with the aid of calibration techniques,

and demonstrates by simulations the improvement in speed and FoM therof.

8 Introduction

The organization of this dissertation is as follows: Chapter 2 gives a detailed account of the

factors limiting the speed of a SAR ADC, and explains how relieving the settling-imposed

limitations translates to stringent requirements on the reference buffer. Chapter 3 states the

main proposal of this work: to replace the active reference buffer with a storage capacitor, and

briefly discusses the ensuing benefits and design problems associated with that. In Chapters

4 and 5, two different calibration schemes for correcting non-linearities due to errors on

reference voltage are proposed and elaborated. The circuit-level implementation details of

the proposed schemes on a two-stage pipelined SAR ADC are also presented along with the

simulation results. Chapter 6 concludes this dissertation and talks about the future scope for

work on this topic.

Chapter 2

A/D Converters

In this chapter, we investigate some basic non idealities associated with charge redistribution

SAR A/D converters and review a number of performance measures commonly used for data

converters. Following this, factors limiting the SAR speed are identified and given a brief

treatment. Finally, we look at a few popular techniques in the recent literature that attempt

to relieve the SAR converter of its speed limitations.

Converters

The quantization error, inherent in any data converter, represents the lowest limit on how

small the error power can be. Due to various circuit imperfections, the total error power is

always larger in an actual implementation. This section identifies the basic nonidealities in a

charge redistribution SAR A/D converter and attributes them to the error sources, which are

essentially those of the capacitive DAC, the comparator and the reference voltage circuitry.

The maximum error an ideal converter makes in digitizing an input signal is ± 1/2 LSB,

as shown in Figure 2-1(a). This quantization error, also referred to as the residue of the

conversion, plotted against input in Figure 2-1(b) is divided into 2N segments, and it changes

linearly with the input within a segment. For a high-resolution converter, it is reasonable

to assume that this error is uniformly distributed with equal probability at any value in the

range ± 1/2 LSB. The root-mean-square value of such a uniformly distributed error can be

√

derived to be equal to ∆/ 12 [11].

10 Speed Limitations in SAR-based A/D Converters

When viewed in the frequency domain, this sawtooth waveform produces harmonics

across the frequency band, which when folded back into the Nyquist bandwidth, sum together

to produce a quantization noise power of ∆2/12. The spectrum in the Nyquist bandwidth

is approximately Gaussian, except (under certain conditions,) when the quantization noise

becomes correlated with the input signal and power is then concentrated close to the signal

harmonics.

Digital

Output

Analog input

+∆/2

Analog input

−∆/2

Besides the inherent quantization noise, a charge-redistribution SAR ADC suffers from ther-

mal noise. All the intrinsic thermal noise sources, when referred to the input of the comparator

input, result in an equivalent noise voltage given by

kT

Vn,eq 2 = + Vn,comp 2 + Vn,ref 2 . (2-1)

Cdac

The thermal noise associated with the on-resistance of the switches, when sampled on Cdac ,

contributes the first term in (2-1), which is the total integrated noise in the Nyquist band-

width. The second term (Vn,comp 2 ) represents the input-referred thermal noise of the compara-

tor, and the last term (Vn,ref 2 ) is the noise contribution from the reference voltage circuitry.

Figure 2-2(a) shows these thermal noise contributions in a simplified representation.

2-1 Basic Nonidealities in Charge Redistribution SAR A/D Converters 11

It should be noted that any noise on the reference voltage is multiplicative with the input

and adds to the total ADC noise floor as shown in Figure 2-2(b). This can be understood given

the basic principle upon which a SAR ADC works: performing approximation by multiplying

the input voltage with 2N /Vref . Therefore, any error on the reference voltage has a signal-

dependent gain towards the output. On a circuit level, it can be understood that the reference

noise is low-pass filtered by the DAC, where the bandwidth is signal-dependent. Thus, from

(2-1), the array capacitance should be adequately high in order to reduce the total equivalent

noise voltage to less than an LSB. Also, the comparator and reference circuitry must be

designed for appropriately low noise.

Vi

Vref

(1 − c) ∗ Cdac

Code-dependent

network

Comparator +

Sampling noise

Code

The common sources of static errors in a charge redistribution SAR ADC are component

mismatches in the capacitive DAC and the comparator. Degrading an ideal ADC transfer

function are offset, gain error and non-ideal code transition points.

The differential non-linearity (DNL) and integral non-linearity (INL) are often used as

performance measures for static linearity. DNL represents the deviation of the step size in a

non-ideal ADC from the ideal size ∆. If Xk is defined as the transition point between two

12 Speed Limitations in SAR-based A/D Converters

Xk − Xk−1 − ∆

DN L(k) = . (2-2)

∆

The total deviation of the actual transfer function from a best-fit line (thus ignoring the

effects of offset and gain-error) is defined as the integral non-linearity. INL is expressed as

k

X

IN L(k) = DN L(l). (2-3)

l=1

Usually, a single number is mentioned for both INL and DNL for an ADC, which rep-

resents the worst deviation among all of the bins. While offset and gain-error are usually

acceptable and, if not, may be corrected through simple digital calibration schemes, the

linearity of the ADC transfer is indispensable. Since the matching properties of the array

capacitors crucially affect the linearity characteristics of an ADC, care has to be taken in the

design and layout of the capacitive DAC.

Digital

output

Xk−1 Xk

Analog input

∆

+0.5 LSB DNL

Besides static errors due to capacitor mismatches, the linearity performance in a charge

redistribution ADC is affected by several other dynamic error sources that challenge the

accuracy of the inherent digital-to-analog conversion.

DAC Settling

Section 1-2-2, different reference levels are derived during conversion by connecting different

amount of capacitance to Vref or the ground. Doing so causes disturbances on the buffered

2-2 Dynamic Performance Measures 13

reference voltage. The buffer recovers to establish the required DAC voltage before com-

parison, limited by its slew rate and settling capabilities. Figure 2-4 shows what happens if

the DAC settles incompletely. The MSB decision goes wrong, and thanks to the sequential,

irrevocable nature of binary search, the error cannot be compensated, thereby leading to an

incorrect digital output. Therefore, the DAC settling before every comparison should be ac-

curate to within 1/2 LSB error, for every decision should be as accurate as the final result of

the conversion [12].

Vref

15

14

13

12

11

10

9

8

Vdac Settling 7

error 6

5

4

3

2

1

0

0

1 0 0 0

(D3 ) (D2 ) (D1 ) (D0 )

time

Ideal decision threshold

Switch Nonidealities

As in any switched-capacitor circuit, nonidealities from MOS switches, namely, clock feedthrough,

channel charge injection and non-linear on-resistance [13], degrade the performance of a charge

redistribution SAR. The top plate switches, those that sample the input and those that per-

form DAC switching, are ideally sized with large aspect ratios for want of low on-resistance

and thereby higher sampling and DAC settling speeds. However, larger transistors worsen

the aforementioned errors, thus posing a trade-off between speed and precision.

Though INL and DNL give a fair measure of static linearity, it is useful to measure the ADC

performance in the frequency domain, which will include the linearity degradation at high

14 Speed Limitations in SAR-based A/D Converters

frequencies and large signal amplitudes. The performance is usually determined by using a

single-tone sinusoidal input signal near the Nyquist frequency, and near full-scale amplitude.

Figure 2-5 shows a typical spectrum of the digital output from a 14-bit non-ideal ADC.

The input sinusoid shows up at the fundamental, and the white noise floor represents the

quantization noise (assuming thermal noise floor is superseded). The visible harmonics in the

spectrum are due to various non-linearities in the system; some of them may have been those

folded from higher Nyquist bands.

-20

Fundamental

Normalized Amplitude [dB]

-40

-60

Largest spur

-80

-100

0 fs /2

Frequency

Signal-to-noise ratio (SNR) is defined as the ratio of the fundamental signal power to the

total noise power at the output, expressed as

Signal Power

SN R = 10log dB. (2-4)

Total noise power

The noise power represents the quantization noise and thermal noise within the Nyquist

bandwidth, excluding the harmonic components. It should be noted that the SNR is limited

only by quantization noise in the case of an input sinusoid, and can be written as

Spurious free dynamic range (SFDR) is the ratio of the power at the fundamental to that

of the largest signal component in the spectrum within the Nyquist bandwidth. Signal-to-

noise and distortion ratio (SNDR) is the ratio of the fundamental signal power to the total

2-3 Speed Limitations of a SAR ADC 15

noise and distortion power within the Nyquist bandwidth. SNDR is written as

Signal Power

SN DR = 10log10 , in dB. (2-6)

Total noise and distortion power

It is useful to measure SNDR as a function of amplitude, which will show that the quantization

and thermal noise dominates at low signal levels, whereas distortion dominates at higher signal

levels. When plotted as a function of frequency, it can be seen that SNDR degrades at high

frequencies due to effects such as clock jitter, high-frequency non-linearities of input sampling

network, comparator and reference buffer, etc.

Effective number of bits (ENOB) is a measure based on the SNDR of an ADC with a

full-scale sinusoidal signal near the Nyquist frequency. It is determined by

SN DR − 1.76

EN OB = . (2-7)

6.02

In a SAR conversion, the circuits are operated serially. After sampling the input, the converter

alternately repeats the operation of DAC settling and comparator resolving. In a conventional

synchronous ADC, an internal high-speed clock allocates every bit cycle to include time for

the digital logic, DAC settling and the comparator as shown in Figure 2-6. The time allocated

for each operation should be long enough so as to ensure proper operation in the worst cases.

The allocated time for DAC settling (t1 ) should cater to the worst-case settling requirement,

which is during MSB settling. The minimum allocated time for comparison (t2 ) has to ensure

that the comparator can resolve any input larger than 1/2 LSB.

t1

Comp. resolving

DAC settling

t2

Digital logic

It can be understood that for higher resolution converters, where more such bit cycles

have to be accommodated within a given clock speed, these allocated times for different

operations have to be reduced. Improving DAC settling, comparator resolution and digital

logic speed all imply power-hungry solutions, that may not be possible to realize at a given

technology node. This explains the absence of SAR converters at high conversion speeds.

SAR converters show excellent energy efficiency at moderate speeds. They are extensively

used in a time-interleaved architecture, which improves the speed of the total ADC by the in-

16 Speed Limitations in SAR-based A/D Converters

terleaving factor. A big wave of current research efforts [14], [15], [16], [17] is working towards

resolving the errors caused by time-interleaving with minimal overhead. Improvements in the

speed of a SAR converter can also be expected from device scaling, which greatly enhances

the digital logic speed, and reduces the comparator resolving time. This section reviews a few

popular techniques reported in the recent literature that attempt to relieve the SAR converter

of its speed limitations at high resolutions.

times allocated for different essential operations are fixed by their respective worst-case re-

quirements. It is to be noted that in a typical regenerative latch-based comparator (with

no loss of generality), that the resolving time has an inverse exponential dependence on the

voltage difference to be resolved [18]. Therefore, with a scheme based on worst-case resolving

time requirements, there are some situations when the comparator resolves very quickly, and

therefore does not use all of the time assigned to it. This wasted comparison time can be

eliminated.

Asynchronous clocking [19] employs a self-timed SAR loop. A fixed amount of time is

given for DAC settling, but not for comparator resolving. Whenever the comparator makes

a decision, it triggers a ready signal that initiates DAC settling for the next bit-cycle, as

illustrated in Figure 2-7. This way, the bit cycles vary dynamically thus eliminating the

wasted comparison time, and thereby improving the SAR speed.

Comp. resolving

ready

DAC settling

t2

While asynchronous clocking saves time with regard to comparator resolving, the time

allocated for DAC settling (fixed by the worse-case settling requirement) is still an impediment

to improving the speed further. A semi-synchronous clocking scheme is proposed in [20] which

attempts to save more time by compromising on DAC settling appropriately. Figure 2-8

illustrates a SAR conversion which involves easy and hard decisions. A decision is easy when

the comparator can resolve quickly because the input voltage is far from the reference. On

the other hand, a hard decision is when metastability occurs because the input voltage is too

close to the reference, and the comparator takes a long time to resolve. It can be noted that

a hard decision is always followed by one or more easy decisions. In that case, DAC settling

can be relaxed for a cycle following a hard decision. Since an easy decision can be followed

by either hard or another easy decision, it is safe not to relax DAC settling for the next cycle.

It can be observed that in a bit cycle, if the comparator takes more time to resolve, DAC

settling can be given less time and vice versa. Given these observations, the semi-synchronous

scheme allocates equal times for all bit cycles, where the two operations - DAC settling and

2-4 Popular Techniques in Relevant Literature 17

comparator resolving - have their times allocated dynamically . With shorter bit-cycles, this

scheme improves the entire SAR speed. For a deeper understanding of this scheme and its

implementation, the reader is directed to [20].

Vref

Vdac easy

Vref /2

easy

hard

hard

0 time

2-4-2 Overranging

It is established from the previous sections that the DAC settling time allocated in a conven-

tional, binary SAR has to be long enough so that the settling error is less than 1/2 LSB in

every bit cycle. If the design is modified such that more settling error can be tolerated, the

converter does not have to wait for the DAC to settle completely and requires a shorter bit

cycle, thereby improving conversion speed. Building tolerance to a certain amount of DAC

settling error is possible by the principle of overranging, which is explained next.

In a binary search, the effective input range is reduced by a factor of two after every

DAC switching event. In such cases, no DAC settling error can be tolerated as exemplified

in Figure 2-4, where incomplete DAC settling led to an erroneous conversion. On the other

hand, if the search follows a non-binary radix, that is, the effective signal range reduces by

a factor less than two every bit cycle (as shown in Figure 2-9), a certain amount of settling

error can be tolerated within the allowable overrange.

In this case, more decision levels are generated and different digital codes can represent

the same input voltage. As Figure 2-9 illustrates, this gives an opportunity to fix the previous

decision error. This way of building in a redundancy, however, comes at the cost of having

to accommodate more bit cycles in order to reach the same accuracy as that of a binary

conversion. For example, assume a converter employing a search with radix 8/5, that is, the

effective signal range in every bit cycle being 5/8th of the previous range. There is 12.5%

overrange built in. In such a case, DAC settling error in the earlier cycles can be up to 12.5%

18 Speed Limitations in SAR-based A/D Converters

Vref

15

14

13

12

11

10

9

Vdac 8

7

6

5

4

3

2

1

0

0

1 0 0 0 0

time

Overrange

Figure 2-9: Effect of incomplete DAC settling on the conversion result in the presence of

overranging

of the desired value without affecting the conversion result. Since log(8/5)/log 2 = 0.68 bit

is resolved each cycle, 21 bit cycles are required to reach 14 bits of accuracy.

Usually, a DAC with non-binary weighted capacitors enables the non-binary search radix

[12]. An arithmetical unit calculates the equivalent binary outputs from all different digital

codes (in this case, the unit maps the 221 comparison patterns to 214 equivalent outputs). With

overranging giving room for DAC settling error in the earlier bit cycles, the time allocated

for DAC settling per bit cycle can be reduced, thereby improving conversion time.

2-4-3 Pipelining

The popular technique of applying a pipeline to SAR ADCs combines the excellent energy

efficiency of SAR with the higher speed possibilities of a pipeline configuration [21], [22],

[23]. Figure 2-10 shows an ADC architecture where two SAR converters are pipelined for

higher speed. The coarse SAR ADC on the left generates the most significant bits. The

residue of this SAR conversion is the difference between the input signal and the final DAC

voltage. It is amplified by a residue amplifier and then fed into the fine SAR ADC on the

right, which generates the least significant bits. In this way, the second stage can be digitizing

the residue from the previous coarse conversion while the first stage is digitizing the input.

With both the stages processing different samples concurrently, the total ADC speed depends

only on the speed of each stage which, being a medium-resolution SAR, can operate at high

2-5 Summary 19

conversion speeds. This architecture offers several other advantages over a conventional SAR-

only architecture besides higher throughput, which will be discussed later in Chapter 5.

Stage 1 Stage 2

Vres

RA

Vref 1 Vi Vref 2

DAC DAC

Dout

Figure 2-10: A two-stage, SAR-assisted pipeline ADC

2-5 Summary

In this chapter, several basic non idealities associated with a charge redistribution SAR ADC

are discussed. The fundamental speed limitations in a SAR ADC are identified as the stringent

requirements on DAC settling and comparator resolving at high resolutions, which can be

overcome at the expense of power-hungry solutions. Finally, we looked at some promising

techniques in the recent literature that attempt to relieve the SAR of its speed limitations.

20 Speed Limitations in SAR-based A/D Converters

Chapter 3

It has been mentioned earlier in Chapter 1 that creating different DAC reference levels by

charge redistribution causes code-dependent errors on the reference voltage during SAR con-

version. In this chapter, we look at how the conventional techniques that deal with these

errors limit the SAR speed in the case of high-resolution converters with given power and

area budgets. Following this, the reference scheme proposed in this research project is pre-

sented. Finally, the reference requirements for the prototype ADC are mentioned briefly.

In a charge redistribution SAR, the capacitive DAC creates the required reference levels by

switching different amounts of capacitance out of the total array capacitance Cdac to/from

the reference source every bit cycle. Figure 3-1 shows a simplified representation of the

DAC during SAR conversion, where the reference circuitry comprising a buffer and bypass

capacitance Cref is loaded dynamically, with α varying every bit cycle as dictated by the

switching decisions.

Vref αCdac

Reference Vdac

from bandgap

Cref (1 − α)Cdac

Code-dependent network

22 Proposed Reference Scheme

Such dynamic loading draws code-dependent charge from the reference circuitry. Since

the buffer is unable to supply this charge instantaneously on account of its finite output

impedance, the voltage Vref suffers instantaneous code-dependent drops, from which the

buffer recovers over time. Figure 3-2 shows the different possible drops on the reference

voltage after every DAC switching event in a 5-bit differential set-and-down switching scheme

(which is explained in the next section), and illustrates how they are recovered by a linear

settling buffer in every bit cycle before comparison.

Convert

Sample #4 #3 #2 #1 #0 Sample

Vref

∆3

time

Figure 3-2: Code-dependent transients on Vref recovered by the charge supplied by the

buffer

After an ith DAC switching event (i is the bit cycle index that takes the values

{N − 1, N − 2, ..., 1, 0} from MSB to LSB in a SAR Convert phase) has caused a drop of

∆i = Qi /Cref in the reference voltage, where Qi represents the corresponding code-dependent

charge drawn from reference, the buffer recovers as given by

Vref (t) = Vref − ∆i e−t/τ . (3-1)

Here,

τ = Rout (Cref + Cdac ) (3-2)

is the settling time constant of the buffer, and Rout , its output impedance. For a binary SAR

ADC with no overrange, the settling error on Vref before every comparison has to be less

than 1/2 LSB [12]. Thus, in every bit cycle, the error in Equation (3-1) should follow the

condition:

1 VF S,dif f

∆i e−tc /τ < volts, (3-3)

2 2N

where tc is the time instant at which the comparator is fired, which can be, for example,

halfway through the bit cycle. VF S,dif f is the differential, full-scale range of the ADC, and

N is the ADC resolution. Enough DAC settling time should be given so that this condition

is satisfied during every bit cycle. In fact, it is usually determined by the worst-case settling

requirement after MSB switching, which involves switching the largest capacitance that causes

the largest drop in reference voltage. In order to reduce the time allocated for DAC settling

and thus improve the conversion speed at a given resolution, the output impedance of the

buffer has to be lowered. The output impedance for a simple source follower is given by 1/gm ,

which can be reduced only by increasing the static bias current. Circuit techniques such as

class-AB operation and shunt feedback are usually employed in order to obtain low output

impedance without requiring large static bias currents.

3-1 Conventional Reference Circuitry 23

As the resolution required of the converter increases to above 12 bits, designing such a

high speed buffer may not be feasible within a given power budget. This is because the settling

requirements on reference voltage, stated by Equation (3-3), grow stringent in multiple ways:

(1) the large array capacitance (for the sake of high resolution) demands large reference charge

during DAC switching, which worsens the drops (∆i ) in the reference voltage. (2) the value

V

of an LSB (= F S,dif

2N

f

) becomes smaller for the same full-scale range. (3) more bit cycles

have to be accommodated. In such a case, reducing the output impedance to a low enough

value becomes impossible within a given static power budget for the reference buffer, which

requires the time allocated for DAC settling to be increased. This essentially limits the whole

ADC conversion speed.

For example, for a 14-bit differential converter having a full-scale range of 2Vref with

differential reference voltages Vref p = Vref and Vref n = 0 V, satisfying Equation (3-3) in the

worst case requires

1 2Vref

∆wce−tc /τ < volts. (3-4)

2 214

The worst-case drop in the reference voltage (∆wc ) happens when the MSB capacitor (Cdac /2)

is switched to halve the reference voltage during the first step in the binary search (Refer

Figure 1-4(a)). The reference charge in that case is given by

Cdac Vref

Qwc = , (3-5)

2 2

which causes the worst-case drop of

Cdac

∆wc = Vref . (3-6)

4Cref

Thus, Equation (3-4) becomes

Cdac −tc /τ 1

e < 14 V. (3-7)

4Cref 2

Assuming Cdac = Cref ,

e−tc /τ < 2−12 V. (3-8)

Thus, 8.32τ of DAC settling is required within each bit cycle before comparison at tc . For

the converter to operate at 100 MHz sampling speed with 50% duty-cycle between Sample

and Convert phases, each bit cycle can be budgeted as

1 1 1

6

× × s = 300 ps + 8.32τ, (3-9)

100 × 10 2 14

where 300 ps is allocated for other operations in a bit cycle, namely, comparison and digital

logic. This is a reasonable assumption for the 28 nm CMOS technology node. This budgeting

yields the required time constant τ = 6.868 ps. In order to calculate the required output

impedance of the buffer from Equation (3-2), an assumption on Cdac can be made based on

the thermal noise budget for the converter. For a 12-bit thermal noise performance (i.e.,

74 dB SNR according to Equation (2-5)) with 1.4 Vpp,dif f signal range, the SNR of the

converter can be written as,

1.4

√

2 2

SN R = 20log q = 74dB, (3-10)

2kT

Cdac

24 Proposed Reference Scheme

q

where C2kTdac

represents the total sampled noise voltage on a differential DAC. This equation

yields the single-ended array capacitance Cdac = 1.4 pF. Thus, with τ = 6.868 ps, and

Cdac = Cref = 1.4 pF, the required output impedance of the buffer has to be less than 3 Ω.

With a simple source follower, this demands Id = gm2Vod = 150mV

2×3 = 25 mA, which from a

1.8 V supply will represent a major fraction of the entire ADC current consumption.

It should be noted that, in the calculation above, the bypass capacitance Cref was as-

sumed to be equal to the array capacitance, Cdac . However, the choice of Cref requires a

careful analysis. Rewriting Equation (3-7) yields

Cref

tc > τ 8.32 − ln . (3-11)

Cdac

This represents the DAC settling time to be allocated every bit cycle. Substituting for τ from

Equation (3-2) gives

" #

Cref

DAC settling time = Rout (Cref + Cdac ) 8.32 − ln . (3-12)

| {z } Cdac

τ | {z }

number of time constants

C

This equation shows that for a given Rout , reducing the ratio of Cref dac

decreases the time

constant and increases the number of time constants required, the former by a greater extent.

Figure 3-3 shows a surface plot of the current required in the reference buffer versus the ratio

140

Current required in the reference buffer [mA]

120

100

80

60

40

20

150

0 100

10 8 6 4 2 50 Sampling clock

0 frequency [MHz]

Cref/Cdac

Figure 3-3: Surface plot of the current required in the reference buffer versus sampling

Cref

frequency and the ratio Cdac

C

( Cref

dac

), and the sampling clock frequency fclk for the aforementioned converter. As the plot

indicates, reducing Cref is beneficial. Thus, it is preferable to leave the buffer’s output node

agile, with only the parasitic capacitances present there comprising Cref [13]. Nevertheless,

3-2 A Stand-alone Capacitor as the Reference Buffer 25

the strong coupling between the power consumption of the buffer and the conversion speed is

evident in this approach.

Another conventional technique is to increase the bypass capacitance Cref to a value

such that switching-induced disturbances from the DAC on the reference voltage are reduced

to less than 1/2 LSB. With this approach, Equation (3-7) requires Cref to be equal to 212

times Cdac , or approximately 6 nF, which will dominate the chip area or requires an off-chip

approach which would limit the speed.

From the section above, it becomes clear that the conventional techniques of dealing with the

switching-induced errors on the reference voltage limit the energy efficiency at higher speeds.

Thus, for high-end converters, a power-conscious scheme to provide reference voltages has to

be devised. The conventional active buffer essentially burns power to provide a low output

impedance (or a high slew rate) that enables quick recovery of the reference voltage from the

switching-induced errors up to the required precision. It should be recalled from Section 2-4

that overranging helps relax the settling precision required, thus promising power savings.

However, it also requires more bit cycles in order to obtain the same accuracy as that of a

binary conversion. Thus, the power-speed trade-off is not completely relaxed.

In that regard, this research project proposes to employ a stand-alone capacitor in place

of the conventional buffer. The capacitor tied to the reference buffer is disconnected during

SAR conversion, thus preventing reference recovery and thereby eliminating the speed limit

set by the output impedance of the buffer. In order to reduce the switching-induced errors

on the reference voltage to less than 1/2 LSB, the capacitance has to be as large as ∼

2N times the array capacitance, as discussed earlier. However, the scheme proposed here

employs a capacitance only 10 - 20 times the array capacitance, and deals with the resulting

code-dependent errors through calibration schemes (discussed in Chapter 4). Figure 3-4(a)

illustrates the proposed reference buffer scheme. The reference capacitor remains tied to the

buffer during the Sample phase of the ADC. As the SAR conversion starts, the capacitor is

disconnected from the buffer and stands alone, holding the reference voltage. DAC switching

pulls code-dependent charge from the stand-alone capacitor. Since its capacitance is not

infinitely high, the reference voltage suffers significant code-dependent errors. Figure 3-4(b)

shows the resulting reference voltage with this scheme for all the possible codes as those

in Figure 3-2. In the next Sample phase, the capacitor is replenished by the buffer, which

removes the code-dependent error in the reference voltage at the end of SAR conversion up

until the precision required of the ADC.

With this scheme, the disturbances on the reference voltage are no longer recovered by

the buffer during the Convert phase and become static errors. They can be formulated,

as illustrated in the next section, given the knowledge of how the DAC is being switched.

Thus, as long as these errors can be handled by the ADC, they can be corrected through

calibration schemes that need not be power-hungry. The ADC may not handle the dropping

reference voltage due to various reasons. For example, the decreasing reference voltage causes

the common mode voltage at the comparator to vary largely, which the comparator may not

handle. Also, in the case of a pipelined-SAR converter, if the reference voltage in the first

26 Proposed Reference Scheme

Convert

Vref

Reference

from bandgap

Cref

(a)

Convert

Sample #4 #3 #2 #1 #0 Sample

Vref

∆3

time

(b)

Figure 3-4: (a) Reference capacitor disconnected during SAR conversion (b) Code-

dependent, deterministic errors on Vref

stage drops considerably, the residue voltage at the end of the conversion may exceed the

range that can be handled by the ensuing back-end. This essentially sets the lower limit on

the value of the reference capacitor relative to the array capacitance, which determines the

magnitude of the drops in the reference. It should be noted that the lower limit on Cref can

also be set by the reference noise, which in this case is simply kT /Cref .

Before discussing the benefits that the proposed reference scheme entails, this section proves

that the switching-induced errors on the reference voltage held by a stand-alone capacitor are

deterministic, which enables them to be corrected by calibration schemes. Formulating these

code-dependent errors requires knowledge of how the DAC is being switched to create the

required reference levels from the reference source. There are several switching algorithms

available in the literature [24, 25, 26, 27, 28, 29], one of which is set-and-down switching [26].

3-3 Deterministic Errors on the Reference Voltage 27

Vref

2C C C

Vip

Vi > 3Vref /4?

Vref Vref Vin

2C C C Yes

2C C C

Vip

Vi > Vref /2?Vref Vref Vref

Vin

Vref Vref

No 2C C C

2C C C

Vref Vref Vref Vip

Vref Vref Vref Vref Vref Vref Vi > Vref /4?

Vin

2C C C 2C C C Yes

Vip Vip 2C C C

Vi > 0? Vref Vref

Vin Vin

Vref Vref

2C C C

2C C C 2C C C

Vref Vref Vref No

Vref Vref Vref Vip

Vi > −Vref /4?

Vref Vref Vref Vin

2C C C

Yes 2C C C

Vip Vref Vref

Vi > −Vref /2?

Vin Vref Vref Vref

2C C C

No

2C C C

Vref Vref Vip

Vi > −3Vref /4?

Vin

2C C C

Vref

Figure 3-5: 3-bit set-and-down switching procedure

Figure 3-5 illustrates a typical set-and-down switching procedure for a 3-bit differential

DAC. During the Sample phase, the differential capacitive DAC (two arrays, each comprising

{2C, 1C, 1C}, where C is the unit capacitance) samples the input voltage Vi on their top plates

that are all connected to the input of the comparator. Meanwhile, the bottom plates of all

the capacitors are connected to the positive reference voltage Vref , as shown in the leftmost

part of the figure. After the input charge is thus trapped in the array during the Sample

phase, the top plates of the array capacitors are disconnected from the input, and the SAR

conversion starts. No switching is required during the MSB bit cycle (i = 2), as the input

voltage is already present at the input of the comparator directly enabling the comparison

(Vi > 0?). Based on the answer to this question, i.e., comparator decision, the next bit-cycle

(i = 1) involves one of these comparisons: (Vi > Vref /2?) and (Vi > −Vref /2?). For the

former, the bottom plate of the MSB capacitor in the positive (upper) DAC is disconnected

from Vref and connected to the negative reference (assumed to be ground). For the latter,

the bottom plate of the MSB capacitor in the negative DAC is switched from Vref to ground.

The comparator decision from this bit cycle decides how the switching is done in the next,

and this continues until the LSB bit cycle (i = 0). The capacitors being switched during

every bit cycle are highlighted (in red) in the figure.

charge pulled out of the reference source in every bit cycle. For example, in the illustration

above, zero charge is required of the reference during the MSB bit cycle as there is no switching

involved. Whereas in the next bit cycle i = 1, there are two cases of switching. It can be

noticed that both the cases can be represented by a single switching scenario, as shown in

Figure 3-6. The MSB capacitor (2C) is switched from Vref to ground, changing the DAC

28 Proposed Reference Scheme

voltage from Vdac = Vref to Vdac′ = Vref /2. The charge supplied by the reference source

during this switching is given by

′

Q1 = −(C + C)(Vdac − Vdac )

Vref

= (2C) = CVref . (3-13)

2

Vref Vref

2C C C Q1 = CVref C C

′ = Vref

Vdac = Vref Vdac 2

2C

Similarly, in the next bit cycle i = 0, there are four cases of switching, which can be

grouped under two different switching scenarios as shown in Figure 3-7.

Vref Vref

CVref

C C Q0,a = 4 C

Vref ′ = Vref

Vdac = 2

Vdac 4

2C 2C C

Vref Vref

3CVref

2C C C Q0,b = 4 2C C

′ = 3Vref

Vdac = Vref Vdac 4

C

3-3 Deterministic Errors on the Reference Voltage 29

In Figure 3-7(a) illustrating one of the scenarios, the MSB - 1 capacitor (C) is switched

in order to change the DAC voltage from Vdac = Vref /2 to Vdac ′ = Vref /4. The reference

charge in this case is given by

Vref Vref CVref

Q0,a = −(C) − = . (3-14)

4 2 4

For the other scenario depicted in Figure 3-7(b), the switching is performed to change the

′ = 3V

DAC voltage from Vdac = Vref to Vdac ref /4. The corresponding reference charge is given

by

3Vref 3CVref

Q0,b = −(2C + C) − Vref = . (3-15)

4 4

Q2 Q1 Q0

CVref

4

CVref

3CVref

0 4

3CVref

4

CVref

CVref

4

Figure 3-8: Different possible reference charges for a 3-bit set-and-down switching procedure

Figure 3-8 shows all of these code-dependent charges supplied by the reference in a sim-

plified representation of the DAC switching tree. A more generalized derivation of reference

charge for any given switching algorithm is provided in Appendix A. For an N-bit set-and-

down switching procedure, it is derived that the charge required in each bit cycle is given

by

!

i

P P

Ci+1 Cl + s

l=0 s∈Sd

Qi = (Vref p − Vref n ) (3-16)

Cdac

for i = N − 2, N − 3, ..., 0.

Sd ⊂ {Cm |(i + 1) < m < N }, the choice of subset being code-dependent. Thus, after every ith

switching event there are 2N −i−2 possibilities of reference charge based on switching decisions.

Figure 3-9 shows all of the possible switching reference charge values for an 8-bit set-and-down

switching algorithm. The code-dependent spread in reference charge reduces over time from

MSB to LSB.

30 Proposed Reference Scheme

35

30

25

20

15

10

0

7 6 5 4 3 2 1 0

i (Bit cycle index)

Figure 3-9: Possible values of reference charge per step for an 8-bit set-and-down switching

procedure

75

Total reference charge [CVref]

70

65

60

55

50

45

40

0 50 100 150 200 250

Output Code

Figure 3-10: Total reference charge versus output code for an 8-bit set-and-down switching

procedure

The total charge supplied by the reference source during the Convert phase is related the

dynamic power dissipated by the reference circuitry. Figure 3-10 shows the total reference

charge versus output code for the 8-bit case. In order to reduce this, the value of the unit

capacitance can be reduced to the limits allowed by kT /C noise and matching requirements.

Moreover, several switching algorithms such as split-capacitor [24], energy-saving [25], merged

3-4 Benefits of the Proposed Reference Scheme 31

capacitor [27], input-range prediction [28], and charge-average switching [29] are proposed in

the literature in attempts to save dynamic power. However, this dynamic power is only a small

fraction of the total power dissipated by the reference circuitry, especially at high conversion

speeds [8], [9]. As discussed earlier in Section 3-1, the main cause of power consumption in

the reference circuitry is that the buffer must provide a low output impedance in order to

settle the code-dependent errors on the reference voltage within every bit cycle.

The proposed reference scheme, in a bid to eliminate the energy limit set by the buffer,

employs a stand-alone capacitor to hold the reference voltage during SAR conversion. As the

employed capacitance is only ∼ 10 - 20 times the DAC array capacitance, DAC switching

causes code-dependent errors on the reference voltage. The previous section illustrated that

those static errors on the reference voltage can be predicted, and thus can be corrected through

calibration schemes.

With this proposed reference scheme, the DAC settling speed and output impedance of

the reference buffer have been decoupled to a certain extent. Since the DAC settling in this

case is limited only by the on-resistance of the switches connecting the reference capacitor

to the capacitive DAC, the bit cycle times can be reduced significantly, thus improving ADC

conversion speed. This may not bring power savings directly, as the buffer still has to replenish

the reference capacitor during the Sample phase (shown in Figure 3-3). However, it can be

noted that in the conventional scheme the buffer has to recover the reference voltage in short

intervals, which demands large currents, especially in case of a high resolution converter.

With the proposed scheme, the buffer can recover the voltage during a longer interval - i.e.,

the whole Sample phase - and thus power savings can be expected. Nonetheless, this scheme

improves the ADC speed without compromising the power efficiency.

The proposed reference scheme is implemented in the two-stage SAR-assisted pipeline ADC

shown in Figure 3-11(a). The effective performance of an ADC is usually limited by ther-

mal noise, quantization noise, and harmonic distortion, of which thermal noise essentially

determines the power dissipated in case of high resolution (> 12-bit) converters. This ADC,

aiming for a 12-bit ENOB performance at 50 MHz sampling clock, is thus designed such that

its effective resolution is limited only by thermal noise. In order for the quantization noise

not to limit the performance, the ADC quantizes the input at a 14-bit level.

With an input full-scale range of 1.4 Vpp,diff , the first stage in the pipeline resolves 7 bits

resulting in a residue voltage in the range 10.9375 mVpp,diff . The residue, after being ampli-

fied 16x, is passed on to the second stage. This residue amplification reduces the precision

requirements on the second stage by 16x. It is to be noted that the input linear range of

this amplifier basically determines the first stage resolution. The second stage, designed for

an input range of 375 mVpp,diff resolves 8 bits. Doing so effectively introduces 2x overrange

32 Proposed Reference Scheme

between the two stages, which is beneficial since comparator noise in first stage can be toler-

ated with the additional ∼ 10 mVpp,diff overrange thus introduced at the input of the residue

amplifier. This overrange also helps the ADC tolerate up to 2x error in the interstage gain.

The timing diagram is shown in Figure 3-11(b). The two stages in the pipeline operate

in a complementary fashion. During their respective Sample phases, the first stage samples

the input, and the second stage samples the residue of the previous conversion from the first

stage. While the Convert phase for the second stage is completely dedicated to its 8-bit SAR

conversion, the first stage employs ∼ 1/10-th of its Convert phase for residue amplification.

16x

10 mVppd

RA

αCdac (1 − α)Cdac Catt αCdac (1 − α)Cdac Catt

1.0 V 7b 0.8 V 8b

0V 0.5 V

RA

5 ns 4 ns 1 ns

As for the reference voltages, the first stage employs Vref p = 0.7 V and Vref n = 0 V in

order to achieve 1.4 Vpp,diff input range, the 0.7 V required being achieved by attenuating

1 V. This reference attenuation is done by connecting a fraction of the total sampling DAC

capacitance to ground during Convert phase. In this case, 0.4 pF out of the total 1.4 pF sam-

pling capacitance Cs (designed for 12-bit kT /C noise) is connected to ground. This grounded

capacitance helps reduce the comparator kickbacks during the Convert phase. Similarly, the

second stage employs attenuated voltages from 0.8 V and 0.5 V for positive and negative

reference voltages, respectively. Reference attenuation in this stage is performed with 100 fF

out of the total 160 fF sampling capacitance, thereby covering a signal range of 375 mVpp,diff .

With the total ADC operating at the 12-bit thermal noise level, noise on first stage

reference is budgeted at 12% of the total noise power, or ∼ 37 uV rms, assuming a uniformly

distributed output code (recall that the reference noise is multiplicative with output code).

The noise on the second stage reference is budgeted at around 5%, or ∼ 25 uV rms. The

precision requirements on the reference voltages for each stage are determined by the amount

3-6 Summary 33

of overrange built into their respective capacitive DACs. More specific details will be given

in the course of the next two chapters.

3-6 Summary

converter. Identifying that such techniques lead us to the point of diminishing returns in

the case of high-end converters, this chapter presented a new reference buffer scheme that

alleviates the strong coupling between ADC speed and static power of the reference buffer.

34 Proposed Reference Scheme

Chapter 4

Charge-based Compensation of

Reference Errors

In this chapter, we investigate the nonlinearity in the ADC transfer caused by code-dependent

errors on the reference voltage held by a stand-alone capacitor. Following this, a simple tech-

nique of dealing with this reference-induced distortion is discussed. Finally, the implementa-

tion details of the proposed scheme in the fine stage of the prototype two-stage, SAR-assisted

pipeline ADC are given.

The code-dependent errors induced on the reference voltage due to DAC switching are signifi-

cant with a stand-alone reference capacitor valued Cref that is not much larger than the DAC

array capacitance, Cdac . Figure 4-1 shows all of the possible code-dependent errors on Vref

= 1 V in the case of an 8-bit, differential, set-and-down DAC with Cref = Cdac (simulated

in MATLAB). When plotted against the code available at the end of every bit cycle, the

total drop in the reference voltage until then shows a parabolic pattern. This is illustrated in

Figure 4-2, where the reference voltage at the end of the last bit cycle is plotted against the

complete 8-bit code. A quadratic dependence of reference voltage on the digital output code

translates to an odd-order non-linearity in the DAC transfer function, and thus the whole

ADC transfer. This is because, as mentioned in Section 2-1-4, any error on the reference

has a signal-dependent gain towards the output. Thus, quadratic error on the reference (in

this case), when multiplied by the signal-dependent gain, leads to odd-order distortion in the

ADC.

Figure 4-3 shows the 4096-point FFT output for an actual 8-bit ADC (with a binary-

weighted DAC array following set-and-down switching algorithm) sampling a 90% FS,

3.1 MHz input signal at 100 MS/s. Using Cref = Cdac leads to odd-order distortion com-

ponents well above the 8-bit quantization noise floor that is represented by the dashed red

line at 50 dB. With the 3rd harmonic representing the largest spur at 22.1 dB below the

36 Charge-based Compensation of Reference Errors

0.95

0.9

0.85

0.8

Vref

0.75

0.7

0.65

0.6

0.55

7 6 5 4 3 2 1 0

i (Bit cycle index)

Figure 4-1: Code-dependent errors on Vref = 1 V in the case of 8-bit set-and-down switching

with Cref = Cdac (simulated in MATLAB)

0.76

0.74

0.72

0.7

0.68

end

Vref

0.66

0.64

0.62

0.6

0.58

0 50 100 150 200 250

8−bit output code

Figure 4-2: Reference voltage at the end of the Convert phase versus 8-bit output code

(simulated in MATLAB)

fundamental, the total harmonic distortion (THD) is equal to 20.1 dB which essentially sets

the SNDR. This represents an ENOB of a mere 3.04 bits. It should be noted that if the spec-

trum of the digital output code were obtained along with the conversion residue, the total

reference-induced distortion would show up as a single, large, third-order harmonic because

of the smooth quadratic dependence of Vref on the output code (shown later in Chapter 5).

4-1 Reference-induced Distortion 37

SNDR = 20.1 dB

−20 ENOB = 3.04 bits

−30

Amplitude [dB]

−40

Quantization noise floor

−50

−60

FFT Gain = 10 log(4096/2)

−70

−90

−100

0 10 20 30 40 50

Frequency [MHz]

Figure 4-3: Performance of an actual 8-bit ADC with binary-weighted DAC and stand-alone

reference capacitor, Cref = Cdac

Increasing the ratio of Cref /Cdac reduces this reference-induced distortion directly, as

evident in Figure 4-4, which shows the FFT output for the same input signal in the case

of Cref = 10Cdac . Values of SFDR, THD and SNDR are 42.3 dB, 38.9 dB and 38.5 dB,

respectively. A 10x increase in the value of Cref thus enhances the THD by 18.8 dB. In

order for the reference-induced distortion components not to degrade the total SNDR beyond

thermal or quantization noise limits, Cref has to be as large as 26 times Cdac (Section 3-1).

−10

SNDR = 38.5 dB

−20 ENOB = 6.1 bits

SFDR = 42.3 dB

−30

Amplitude [dB]

−40

Quantization noise floor

−50

−60

FFT Gain = 10 log(4096/2)

−70

−90

−100

0 10 20 30 40 50

Frequency [MHz]

Figure 4-4: Performance of an actual 8-bit ADC with binary-weighted DAC and stand-alone

reference capacitor, Cref = 10Cdac

38 Charge-based Compensation of Reference Errors

This section introduces a straightforward technique for correcting the switching-induced errors

on Vref held by a stand-alone capacitor, without having to increase its capacitance Cref

to large values and pay a penalty in terms of area. The charge pulled from the reference

capacitor after a DAC switching event can be predicted, given the switching decision and the

knowledge of the algorithm in use, as illustrated in Section 3-3. Knowledge of the charge lost

in a DAC switching event A posteriori enables it to be compensated for precisely. As soon as a

comparator decision initiates a switching event that pulls decision-dependent charge from the

reference capacitor, a corresponding compensation charge can be added to it instantaneously,

thus preventing Vref from suffering a drop. To that end, this technique employs a bank of

capacitors that have been pre-charged before SAR conversion, from which a certain amount

of capacitance is connected to the main reference capacitor after a DAC switching event. The

amount of capacitance chosen holds the charge required for compensation.

Vref Vrefi,α

-Qi,α

Cref Cref

Vc

Vrefi,α Vref

Figure 4-5 illustrates this technique in charge domain. After a DAC switching event i

has pulled Qi,α amount of charge from Cref , where α represents the code dependence, Vref

drops to Vrefi,α . From the compensation bank consisting of capacitors that have all been

pre-charged to a voltage Vc , Cci,α is chosen and connected to Cref . Instantaneous charge

sharing between the capacitors is such that the drop in Vref is compensated for. Though the

figure shows successively timed events of charge being lost, followed by compensation, both

the events can be simultaneous so that Vref does not suffer instantaneous drops.

4-2 Error Compensation in Charge Domain 39

equation given by

Cref Vref − Qi,α + Cci,α Vc = Cref + Cci,α Vref . (4-1)

Since there are 2N −i−2 code-dependent possibilities of reference charge in every bit cycle

from (MSB - 1) to LSB (with i taking values {N − 2, N − 1, ..., 1, 0}) for an N-bit set-

and-down switching DAC, the bank is required to accommodate (2N −1 − 1) capacitors with

unique values. Since this would imply a huge penalty in terms of area, the compensation

bank employs small capacitances that are charged to Vc (i.e., higher than Vref ). Assuming

Cci,α << Cref , Equation 4-1 becomes

Cci,α Vc ≈ Qi,α . (4-2)

For an 8-bit DAC following set-and-down switching algorithm, Qi,α can range from 32Cu Vref

to 0.0078Cu Vref , where Cu represents the unit capacitance of the DAC. Thus, by choosing

Vc appropriately higher than Vref , compensation capacitors can have values less than or

approximately equal to the unit capacitance.

An example of this technique is discussed next. For a 5-bit set-and-down DAC, the

different possible drops in reference voltage are as shown in Figure 4-6. At t3 , the DAC

switching is at the start of bit cycle i = 3, corresponding to either of the previous decisions:

D4 = 0 and D4 = 1. It pulls a code-independent amount of charge Q3 = 4Cu Vref from Cref .

Vref drops to Vref3 . At t2 , the DAC switching in bit cycle i = 2 causes a code-dependent

drop from Vref3 . For D4 D3 = 00 and D4 D3 = 11, the amount of charge pulled from Cref is

Q2,a = Cu Vref3 . For D4 D3 = 01 and D4 D3 = 10, it is Q2,b = 3Cu Vref3 . Accordingly, Vref3

drops to either Vref2,a or Vref2,b . The reference voltage suffers such code-dependent drops as

the SAR conversion progresses.

Vref

Q3 = 4Cu Vref

Vref3

Vref2,a Q2,a = Cu Vref3

Q2,b = 3Cu Vref3

Vref2,b

t3 t2 t1 t0 time

i=4 i=3 i=2 i=1 i=0

Figure 4-6: Code-dependent errors on Vref in the case of 5-bit set-and-down switching

initially pre-charged to a voltage Vc . The first code-independent drop at the start of bit cycle

i = 3 is compensated for by connecting the capacitor Cc3 from the bank to Cref at t3 , as

shown in Figure 4-7. The value of Cc3 is given by

Q3 4Cu Vref

Cc3 = = , (4-3)

Vc Vc

40 Charge-based Compensation of Reference Errors

Vref

Vc

Cref

Cc3

(a) Schematic illustration

Vref

Q2,a = Cu Vref

Q2,b = 3Cu Vref

t3 t2 t1 t0 time

i=4 i=3 i=2 i=1 i=0

(b) Vref after compensation at t3

As Vref3 recovers to Vref , the code-dependent values of charge pulled at the start of bit cycle

i = 2 become Q2,a = Cu Vref and Q2,b = 3Cu Vref . In order to compensate for the former,

Cc2,a given by

Q2,a Cu Vref

Cc2,a = = (4-4)

Vc Vc

is chosen from the bank and connected to Cref at t2 . For the latter case, Cc2,b , given by

Cc2,b = = (4-5)

Vc Vc

is chosen. Both cases are shown in Figure 4-8. Similarly, compensation can be performed

in every bit cycle by choosing an uniquely-valued capacitor from the compensation bank for

each and every comparator decision. The digital logic performing the selection from the bank

should be as fast as the logic triggering the DAC switching event based on the comparator

decision. This prevents the reference voltage from suffering instantaneous drops. Figure 4-9

shows the reference compensation loop (in grey) in action alongside the main SAR loop.

4-2 Error Compensation in Charge Domain 41

Vref

Vc

Cref

Cc2,a Cc2,b

(a) Schematic illustration

Vref

t3 t2 t1 t0 time

i=4 i=3 i=2 i=1 i=0

(b) Vref after compensation at t2

Vref

Cref Selection

Logic

DAC

SAR Logic

Dout

Figure 4-9: Conceptual illustration of reference compensation loop (in grey) along with the

main SAR loop

42 Charge-based Compensation of Reference Errors

This section examines some of the design choices concerning implementation of the technique

discussed above, and proposes the following improvements:

The error in Vref per bit cycle can be considered to consist of two parts: the code-independent

drop and the code-dependent spread. It is the latter that causes distortion in the ADC. If not

for the code-dependent spread, Vref would only decrease systematically every bit cycle. This

is shown in Figure 4-10(b), where only the code-dependent spread is removed per bit cycle,

instead of correcting the total error in Vref (shown in Figure 4-10(a)). As evident, removing

the spread requires less compensation charge than that required when correcting the entire

error. Having smaller compensation capacitors is beneficial when chip area is considered.

Vref

t1 t2 t3 t4 time

i=3 i=2 i=1 i=0

(a)

Vref

t1 t2 t3 t4 time

i=3 i=2 i=1 i=0

(b)

Figure 4-10: Compensation for (a) constant Vref , and (b) code-independent, systematically

decreasing Vref

4-3 Implementation Choices 43

Systematically decreasing Vref implies that the effective signal range in every step of the

binary search is diminishing. For example, if Vref drops to Vref ′ at the start of the 2nd bit

cycle in a binary search, the effective signal range available for the subsequent comparison is

′ /2 instead of V

Vref ref /2, as shown in Figure 4-11(a). This leads to incorrect digital outputs

in the same way as the incomplete reference settling does (Section 2-1-4). Such a systematic

decrease in Vref can be adjusted for by changing the capacitive division ratio. Instead of

performing a binary capacitive division by switching Cdac 2 at the start of the 2nd bit cycle,

Cdac

r is switched. Variable r is chosen so that the effective DAC voltage division seen by the

V

comparator is equal to ref ′

2 regardless of Vref dropping to Vref , as given by

′

Vref Vref

= . (4-6)

r 2

V′

As Figure 4-11(b) shows, by changing the capacitive division ratio to 2 Vref ref

, the required

signal range is covered. Similarly, the capacitive division ratio can be changed in every step

so that, regardless of the systematically decreasing Vref , the effective DAC reference levels

seen by the comparator follow a binary pattern (or a non-binary pattern as dictated by the

overrange required). However, it should be noted that changing r changes the charge pulled

′ . Choosing the right capacitive division ratio per step

from Cref , resulting in a different Vref

requires some design iterations.

Vref Vref

Vref Vref

2 2

Uncovered V′

ref

r=2 r = 2 Vref

0 0

i = MSB i = MSB - 1 i = MSB i = MSB - 1

time time

(a) (b)

′

Figure 4-11: Effect of Vref dropping to Vref on effective signal coverage (a) with conven-

tional capacitive division ratio, and (b) with appropriately changed capacitive division

Removing only the code-dependent spread in Vref per bit cycle can be done in two ways as

shown in Figure 4-12. In the case of correcting ’upward’ as in Figure 4-12(a), the charge

44 Charge-based Compensation of Reference Errors

Cref Vref2,b + Cc2,up Vc = Cref + Cc2,up Vref2,a . (4-7)

Whereas, correcting ’downward’ (in Figure 4-12(b)) can be done by connecting an uncharged

capacitor Cc2,down such that it sinks the code-dependent part of the charge from the reference,

as given by

Cref Vref2,a + Cc2,up .0 = Cref + Cc2,down Vref2,b . (4-8)

Vref

Vref2,a

Vref2,b

t1 t2 t3 t4 time

i=3 i=2 i=1 i=0

(a)

Vref

Vref2,a

Vref2,b

t1 t2 t3 t4 time

i=3 i=2 i=1 i=0

(b)

Figure 4-12: Removing the code-dependent spread in Vref (a) by adding charge, and (b)

by removing charge

Correcting ’downward’ essentially pulls more charge from reference in order to equalize

it over different codes. In order to enable this, the compensation bank has to be discharged

to ground initially instead of having to be pre-charged to Vc . This obviates the need for

providing Vc , which, being greater than Vref , would require a voltage booster in an actual

implementation. Interestingly enough, given this implementation, an analogy can be drawn

between the compensation bank and the capacitive DAC, in that switching a capacitor to the

reference from either of the arrays pulls code-dependent charge from the reference.

4-4 Sources of Inaccuracy 45

If the compensation technique discussed above is employed in each and every bit cycle, the

compensation bank and the digital logic performing selection may represent significant over-

head for high resolution systems. As evident by comparing the reference voltage spread after

compensation in Figures 4-3 and 4-4, compensating in an earlier bit cycle reduces the code-

dependent spread in the ensuing bit cycles by a considerable extent. Therefore, compensation

can be performed only for the first few bit cycles such that in the rest of the bit cycles, the

spread in reference without compensation is within the limits of reference error allowed, that

is, an LSB.

Summarizing the improvements to the compensation technique, Vref can be let to un-

dergo code-independent, systematic drops that are taken care of by changing the capacitive

division ratio per step. The code-dependent spreads in the first few bit cycles are removed

by appropriately sinking charge from Cref . The residual reference error in the rest of the bit

cycles can be tolerated by the ADC.

This section discusses the sources of inaccuracy in the proposed reference scheme. The salient

features of the proposed scheme, namely, changing the capacitive division ratio in order to

adjust for the systematically decreasing Vref , and charge-based compensation, are both based

on the fact that the charge pulled from the reference capacitor after every DAC switching

event is entirely deterministic. Any error source that challenges the accuracy in predicting

the reference charge lessens the effectiveness of this scheme.

As the charge pulled from Cref is essentially determined by ratios of different capacitor values

in the DAC, the processing variations in these capacitor values directly affect the accuracy

of predicting the static errors in Vref . Figure 4-13 shows the results of 100 Monte Carlo

simulation runs in MATLAB, where the effect of DAC capacitor mismatch on the reference

voltage (as compared to Figure 4-1 without mismatch) for a 1 V, 8-bit ADC with Cref = Cdac

is shown. The unit DAC capacitance is assumed to be Cu = 1 fF, and each DAC capacitor is

modelled as

Ci = 2i−1 Cu + δi , (4-9)

where δi is a random variable with a zero mean and a variance of σi2 . The variance is given

by

σi2 = 2i−1 σu2 , (4-10)

where σu is the standard deviation of the unit capacitance [30], [31]. A 3% standard deviation

(i.e., (σu /Cu ) = 0.03) is assumed, which is a rather pessimistic assumption for a metal-finger

1 fF capacitor in 28-nm CMOS. As the figure shows, the deviation of the actual values for the

changes in Vref from the ones that would be predicted without mismatch varies considerably

with respect to DAC capacitor mismatches.

46 Charge-based Compensation of Reference Errors

0.95

0.9

0.85

0.8

Vref

0.75

0.7

0.65

0.6

0.55

7 6 5 4 3 2 1 0

i (Bit cycle index)

Figure 4-13: Effect of DAC capacitor mismatch on the code-dependent errors in Vref

(simulated in MATLAB)

Furthermore, in the bit cycles where the code-dependent spread is removed by sinking

charge, a previously discharged capacitor that is valued appropriately for the code-dependent

spread in reference charge is connected to Cref . Besides the deviation in the reference charge

from the model due to DAC capacitor mismatch, random spread on the value of this com-

pensation capacitor implies that the compensation performed will not be accurate. It is to

be noted that an error in compensation in a bit cycle invalidates the compensation in the

next cycle, and so on. This is because, the charge pulled from Cref depends on the reference

voltage level before the DAC switching event. An inaccurate compensation in a bit cycle

results in a reference voltage level different from the desired value. This, in turn, causes the

reference charge in the next bit cycle to deviate from the model.

Processing variations in the DAC and compensation capacitors can greatly affect the

accuracy of the proposed reference scheme. In order to be able to predict the errors on

the reference with 14-bit accuracy, the DAC capacitors should match to at least 0.0064%.

At present, accuracies up to 12 bits can be expected (in the cases of most of the switch-

ing algorithms [31]) by employing high-quality metal-insulator-metal (MIM) or metal-finger

capacitors with careful layout measures [12]. Further accuracy is by virtue of foreground

and/or background digital calibration algorithms that correct for DAC capacitor mismatches

[21, 19, 32, 33, 34, 35]. Correction parameters determined by such algorithms can be used to

calibrate the errors in the predicted reference model.

Switches that are tied to Cref , namely, the switches connecting to the DAC capacitors and

those to the compensation capacitors introduce errors in Vref through two distinct mecha-

nisms. Firstly, these switches couple their clock transitions to Cref through their overlap

4-5 Reference Scheme Implementation in the Fine SAR ADC 47

capacitances as they turn on and off. Secondly, these switches inject their channel charge into

Cref as they turn off, which appear as negative or positive pedestals on Vref (with NMOS

and PMOS switches respectively). These errors in Vref , although code-independent, affect

the accuracy of the reference scheme in that they affect the predictability of reference charge.

Sizing the MOS switches with small aspect ratios helps reduce the errors due to switch

nonidealities. However, smaller switches have high on-resistance which reduces the DAC

settling speed. Techniques using dummy or complementary switches are usually employed

in order to circumvent this speed-precision trade-off. Using dummy switches to absorb the

charge injected is less attractive, as the dummies need to be sized carefully in order to ensure

exact removal of the fraction of channel charge injected into Cref , which is generally

cumbersome [36]. The approach incorporating complementary switches, such that the op-

posite charge packets injected by the two cancel each other, requires the complementary

switches (NMOS and PMOS) that are matched to each other. Furthermore, this approach

is only good for one input level [13]. Since Vref is systematically decreasing in the proposed

reference scheme, the channel charge injected varies every bit cycle, making this approach

unsuitable.

A simple, viable solution is to include the excess charge introduced by the switches

into the model of the reference charge. Designing the capacitive radix, and choosing the

compensation capacitors can then be performed accordingly. However, processing variations

in MOS switches that introduce randomness in the excess charge still affect the accuracy of

the reference scheme.

Besides the aforementioned sources, power supply variations and capacitor parasitics also

affect the accuracy in predicting the reference charge. Enough power supply rejection should

be provided while charging the reference capacitor during the Sample phase. For the latter,

the compensation capacitors can be designed taking into account the simulator-estimated

parasitics.

The reference scheme discussed so far, being bound in accuracy by the processing variations

of different capacitors and switches present in the ADC, becomes limited to use in medium-

resolution converters. In the prototype two-stage, SAR-assisted pipeline ADC, the fine SAR

ADC can afford relaxed precision because of the interstage gain. The precision requirements

in the coarse SAR ADC are the same as those of the entire ADC. Therefore, the proposed

reference scheme is implemented in the fine SAR ADC. This section discusses the circuit-level

implementation details and the results of the reference correction technique investigated.

The fine ADC, with a rail-to-rail input range of 375 mVpp,dif f , has to resolve 8 bits

effectively. Vref p and Vref n are chosen to be 0.8 V and 0.5 V, respectively. They are attenuated

by connecting a fraction (= 3/8) of the total sampling capacitance, Cs to ground during the

Convert phase, resulting in an effective Vref = 187.5 mV that covers the entire signal range.

The capacitive DAC employs the set-and-down switching algorithm. During the Sample

phase, the input is sampled on the top plates of the array capacitors (tied to the input of

the comparator), while their bottom plates are connected to VCM = 0.5 V. At the start of

the Convert phase, the following actions are performed: 1) the top plates are disconnected

48 Charge-based Compensation of Reference Errors

from the input, 2) 38 Cs is connected to the ground, and 3) the bottom plates of the remaining

capacitors in the array (whose total capacitance is equal to Cdac ) are all connected to Vref p .

At the end of this first bit cycle the result of the MSB comparison is available. As the next

bit cycle begins, the bottom plate of the MSB capacitor in either the positive or the negative

DAC (based on the MSB decision) is switched from Vref p to Vref n . This results in an effective

DAC step of Vref /x, where x is the radix of the search through the DAC. Further DAC

switching proceeds according to the algorithm until 8 bits are resolved (Section 3-3).

VCM

Vref p

Vref n

CN −1 CN −2 C0

Vdacp

Vip

Figure 4-14: Single-ended schematic of the capacitive DAC in the fine stage

Vdacp ,

Vdacn

Vref Vref

(Vref − VCM ) r r2

Vref

Vip r3

Vin

Figure 4-15: Examples of positive and negative DAC voltage waveforms in the fine stage

Figure 4-14 shows a simplified, single-ended version of the DAC with the different switches

involved. Figure 4-15 shows typical waveforms of the positive and negative voltages input

to the comparator. It can be noticed that the jump from VCM to Vref p in the first step is

performed in order to shift the common-mode level of the voltage present at the comparator

input from that of the sampled input (dashed grey lines represent the CM levels). This step

pulls charge from the reference capacitor, which had not been modelled earlier in Figure 4-1.

4-5 Reference Scheme Implementation in the Fine SAR ADC 49

is taken care of by changing the reference attenuation factor.

The proposed reference scheme is implemented with Cref p = Cref n = 1 pF. The capacitive

DAC is designed such that the search radix takes into account the systematically decreasing

Vref . Overrange is also built in to take care of the errors due to processing variations and

residual code-dependence in the bit cycles without compensation. After a number of design

iterations, the final DAC is designed to consist of 10 capacitors whose weights are given by

{66 36 19 10 7 4 3 2 1 1}. With a unit capacitance (Cu ) chosen as 0.7 fF, the total DAC

capacitance is equal to 100 fF. Figure 4-16 shows the DAC signal range considered during

every step of the search. It should be noted that the figure takes into account the code-

independent drops in Vref and the nominal switch charge injection in every bit cycle. With

an average radix of 1.6, it takes 11 bit cycles, including the step involving CM shift, to reach

an ENOB of 8 bits.

Charge-based compensation is performed in the first three bit cycles with code-dependent

spreads (i = 7, 6 and 5) with a bank of compensation capacitors that amount to a total

capacitance of 20 fF. The residual code-dependent spread in Vref at the end of the last bit

cycle is 0.62 mV, which is less than one LSB (= 1.465 mV). The worst-case spread over

process/temperature variations and over 7 different Monte Carlo runs are also less than one

LSB.

1.8

Effective signal range per bit cycle

1.6

normalized to V = 187.5 mV

1.4

1.2

ref

0.8

0.6

0.4

0.2

0

9 8 7 6 5 4 3 2 1 0

i (Bit cycle index)

Figure 4-16: Effective signal coverage per bit cycle with the designed cap. radix, taking

into account the code-independent drops in Vref and nominal switch charge injection in every

bit cycle

50 Charge-based Compensation of Reference Errors

Figure 4-17 shows the 4096-point FFT output for the fine SAR ADC with the designed

reference scheme sampling a 90% FS, 3.1 MHz input signal at 100 MS/s. Total SNDR

including all the noise and distortion components within the Nyquist bandwidth is 50.9 dB,

which corresponds to an ENOB of 8.1 bits. Values of SFDR and THD in a typical corner are

C

61.8 dB and 60.5 dB respectively. Compared to Figure 4-4 for the same Crefdac

ratio (= 10), the

implemented reference correction technique thus reduced the reference-induced distortion by

19.5 dB in SFDR and 21.6 dB in THD. It should be noted that the reference-induced distortion

is reduced to a little more than what is necessary for 8-bit linearity. Even though further

improvement can be expected by not making the simplified implementation choices discussed

in Section 4-3, it is rather important to mention that the effectiveness of this technique is

primarily limited by the processing variations in capacitors and MOS switches.

−10

SNDR = 50.9 dB

−20 ENOB = 8.1 bits

−30

Amplitude [dB]

−40

Quantization noise floor

−50

−60

FFT Gain = 10 log(4096/2)

−70

−90

−100

0 10 20 30 40 50

Frequency [MHz]

Figure 4-17: Fine ADC performance with the designed reference scheme including charge-

based compensation in 3 bit cycles, and changed capacitive radix to accommodate the code-

independent drop in Vref

4-7 Summary

In this chapter, we studied the ADC distortion caused by code-dependent errors in Vref .

A charge-based compensation technique taking advantage of the predictability of reference

errors was proposed to deal with this reference-induced distortion. Finally, we looked at the

proposed reference scheme being implemented in the fine stage of the prototype two-stage,

pipelined SAR ADC.

Chapter 5

Errors

In this chapter, we propose a digital calibration technique to correct for nonlinear errors

arising from the code-dependence in Vref held by a stand-alone capacitor. The implementation

details of the proposed technique in the coarse stage of the prototype, two-stage, SAR-assisted

pipeline ADC are presented in detail. The design methodologies of the critical building blocks

in the proposed reference scheme are discussed, followed by simulation results.

The charge-based compensation of reference errors discussed in the previous chapter, being an

error-correction technique in the analog domain, becomes ineffective at resolutions of 12 bits

or higher thanks to inherent analog impairments, namely, processing variations in capacitors

and switches. Moreover, this technique involves a bank of compensation capacitors which,

when sized for accuracy requirements and designed for compensation in every bit cycle, can

occupy chip area as large as a significant fraction of the area occupied by the main DAC. The

logic performing the selection from the bank alongside corresponding switches also represents

a major overhead. This necessitates a correction technique that can help remove the reference-

induced distortion up to 14-bit precision or higher, meanwhile representing minimal overhead.

In that regard, this chapter proposes a new approach that seeks digital assistance to deal

with the code-dependent errors in Vref held by a stand-alone capacitor. This approach of

resorting to digital calibration techniques in order to improve the ADC linearity is prominent

in the recent literature. Various digital calibration algorithms have been proposed for SAR-

based converters to correct for nonlinear factors such as capacitor mismatch [37, 19, 32,

33, 34, 35], and in the case of a pipelined architecture, inter-stage amplifier nonlinearity

[38, 39, 40, 41, 42, 43]. This growing prevalence of digital assistance is fuelled by the fact

that the aggressive realization of Moore’s law over the past few years has greatly benefited

digital circuit performance (eg., in speed and power), resulting in fast, efficient digital cores

at smaller costs.

52 Digital Correction of Reference Errors

The digital calibration algorithm proposed here derives its inspiration from a popular calibra-

tion technique used in pipelined ADCs that extracts non-idealities such as capacitor mismatch,

finite op-amp gain, comparator mismatch, etc., by processing the conversion residues from the

coarse stages. The idea that the residue voltage contains information about the non-idealities

of the conversion stage, and that it can be processed in a pipeline architecture to extract and

correct such imperfections was first explored in [44]. The algorithm reported here claims that

the reference errors in a coarse stage appear in the residue voltage in the same way as any of

the aforementioned non-idealities would. Therefore, taking advantage of the pipeline archi-

tecture of the prototype ADC, this algorithm is employed to correct for the reference errors in

the coarse stage, which simply uses a medium-valued stand-alone reference capacitor with no

correction in analog domain, by processing its residue. The goal is to achieve at least 14-bit

linearity with respect to reference-induced distortion, while guaranteeing minimal overhead.

In order to develop the algorithm for the correction of reference errors, their effect on the

residue characteristic is first formulated. Figure 5-1 shows the DAC tree for a 2-bit, differ-

ential, binary search with all the ideal reference levels per bit cycle. The full-scale range

2V

{−Vref , Vref } is divided into 22 bins, each bin the size of an LSB (= 2ref2 ). For an input

Vi located in the bin j, an ideal binary search follows the corresponding trajectory (which

represents the digital output code) as shown in the figure. The voltage residual after the

conversion is given by

Vres = Vi − Vdacend , (5-1)

where Vdacend is the final reference level created at the end of the conversion cycle after

switching the LSB capacitor. It is given by

2j − 22 + 1

Vdacend = Vref (5-2)

22

for j = 0, 1, ..., 22 − 1,

with j representing the height of the digital output code. The residue voltage, when plotted

against the input voltage, gives the ideal residue characteristic as shown in Figure 5-2. The

sawtooth in each bin has a constant height and base, both equal to 1 LSB.

After including the effect of reference errors in the case of a stand-alone reference ca-

pacitor, the reference levels become erroneous as shown in Figure 5-3. The residue voltage

becomes

2j − 22 + 1

Vres = Vin − Vrefend,α (5-3)

23

for j = 0, 1, ..., 22 − 1,

where Vrefend,α represents the reference voltage on Cref after the LSB capacitor is switched.

Parameter α implies that this voltage varies in a quadratic fashion with digital output code,

that is, according to j. The resulting residue characteristic is as shown in Figure 5-4.

5-2 Calibration Methodology 53

+Vref

j=3

j=2

Vdac 0

j=1

j=0 LSB =

2Vref

22

−Vref

D1 D0 time

Vres

(Vref , Vref )

Vin

(−Vref , −Vref )

LSB

LSB

54 Digital Correction of Reference Errors

+Vref

Vdac 0

−Vref

D1 D0 time

Vres

(Vref , Vref )

Vin

(−Vref , −Vref )

X 6= Y 6= LSB

It becomes apparent from the figures that the LSB spacings on the DAC tree, affected

by reference errors, become uneven. To that end, the calibration algorithm reported here

attempts to determine the relative LSB spacings on the DAC tree, and therefore estimate the

erroneous DAC transfer, from which the errors on the reference can be corrected.

5-2 Calibration Methodology 55

The proposed algorithm is similar to [38] in that an additional step is introduced after the

conversion where the DAC voltage can be modulated to result in two different residue modes.

In [38], two different residue modes are randomly alternated, and residual differences are

obtained that serve to estimate and correct for the inter-stage gain errors. In the algorithm

used in this work, such residual differences obtained for different trajectories are used to

correct for the reference-induced errors in the DAC transfer.

Vi − Vdac

Three possible residues

0 LSB

time

D1 D0

Extra step

Figure 5-5: DAC voltage modulation in an additional step after SAR conversion

Figure 5-5 shows a typical waveform of the voltage present at the comparator input. After

the conversion has ended, that is, the LSB capacitor has been switched, the DAC voltage is

modulated. The modulation is performed by including an additional capacitor in the DAC

array. Switching this capacitor gives the same step-size as that of the LSB step. As a result,

there are three different possible residue voltages corresponding to the additional capacitor

taking no step, a positive step (Vref p to Vref n ) or a negative step (Vref n to Vref p ), as shown

in the figure.

Figure 5-6 shows the DAC tree with three different cases of modulation (the DAC voltages

in the case of no modulation are not shown in the additional step for the sake of clarity). In

order to estimate the relative LSB spacings on the DAC tree (as shown in the figure) values

of h1 (j) and h2 (j) should be computed for every trajectory j throughout the full-scale range,

as follows:

1. h1 (j) represents the size of the output LSB bin corresponding to the trajectory j. As

Figure 5-7 illustrates, h1 (j) can be obtained by determining the difference between the residue

voltages corresponding to positive and negative DAC voltage modulations for the trajectory

j at a given input voltage V1 (j) in bin j.

56 Digital Correction of Reference Errors

+Vref

h1 (j)

h2 (j)

Vdac 0

−Vref

D1 D0 time

Figure 5-6: DAC tree with three different cases of DAC voltage modulation

Vres

j j+1

h1 (j)

Vin

V1 (j)

Figure 5-7: Determining h1 (j)

2. h2 (j) represents the spacing between the LSB bins j and j+1 on the DAC tree, and

obtaining this through out the full-scale gives the relative locations of the LSB bins.

Figure 5-8 shows the residue voltage in the case of no DAC voltage modulation in the ad-

ditional step. It can be observed from the figure that h2 (j) is the difference between the

two residue values that are obtained by fixing the input voltage at V2 (j) and forcing the

trajectories j and j+1 in the SAR loop.

5-2 Calibration Methodology 57

Vres

j j+1

h2 (j)

Vin

V2 (j)

These differences are formed in the digital domain after the residue voltages concerned

have been digitised by the back-end. Once h1 (j) and h2 (j) have been obtained for each and

every trajectory, the complete DAC transfer can be constructed by stacking the estimated

LSB bins on top of each other. Following this, INL-based correction terms are obtained by

finding the deviation of the estimated transfer from an ideal ’best-fit’ transfer.

This section analyses different possible ways of implementing a digital calibration algorithm,

and derives a convenient, deterministic procedure for the algorithm discussed above. In gen-

eral, operability in the background and fast computation of the required correction parameters

are the two desirable features for any ADC calibration scheme. Without interrupting the nor-

mal ADC operation, the calibration procedure should be short enough to track parameter

variations due to environmental influences such as temperature. However, a review of the re-

lated literature shows that these features are somewhat mutually exclusive, making it difficult

to develop an ideal calibration procedure with minimal overhead.

A complete background calibration procedure that does not impose any restrictions on

the input signal characteristics usually involves randomization of the non-linear error terms

with a pseudo-random noise (PN) sequence, as evident in many of the previously reported

ADC calibration schemes [38, 45, 46, 34]. This idea can be extended to the foregoing al-

gorithm, where the DAC voltage in the additional step can be modulated based on a PN

sequence. This way, the reference errors will become PN-modulated, and multiplying the

digital output by the same PN sequence will help decorrelate and extract the information

required to correct reference-induced nonlinearity. However, such a scheme will suffer from a

major trade-off between measurement accuracy and the computation time. This is because

in order to extract the required information from the ADC output with high precision, a

large number of conversions have to be performed to average out the input. Since the PN-

modulated input content present in the √ digital output can be considered as a white noise

whose standard deviation reduces by 2 as the the number of averaging samples is doubled

58 Digital Correction of Reference Errors

[47], 22N conversions are required to achieve N-bit accuracy. In order to determine the refer-

ence errors in the coarse stage of the prototype ADC resolving 7 bits, 128 trajectories should

be tested. For the whole calibration to be 14-bit accurate, each test should be at least 17.5-bit

accurate [48]. Thus, a background calibration scheme would require 128 × 22×17.5 samples, or

∼12 hours of conversion time with a 100 MS/s sampling clock.

The split-ADC approach [49], a parallel, slow-but-accurate ADC [33], and signal-dependent

dithering [47] are some of the techniques from recent calibration literature that attempt to

achieve higher accuracy and faster calibration cycles simultaneously. However, they mostly

incur additional analog and/or digital complexity [43]. Rapid conversion cycles are possible

with minimal overhead in a simple, ’deterministic’ calibration scheme, as evident in the cali-

bration schemes from the early 90s [44, 50, 51]. The limitation with a deterministic scheme

is that since it is based on providing a known, analog test signal to the ADC, the ADC is

required to go off-line during the calibration procedure, which inhibits its use in the complete

background. However, in ADC architectures with possibilities for some forms of redundancy,

such as additional ADC lanes or extra conversion time, a deterministic calibration scheme

can be employed without such a limitation. The prototype ADC is implemented with a

time-interleaved architecture, thereby allowing an additional lane to accommodate a deter-

ministic calibration scheme. It should be noted that measuring h2 (j) is possible only with a

deterministic scheme.

In order to enable a deterministic scheme for the above-said calibration algorithm, the

test signals, namely, V1 (j) and V2 (j) should be generated in order to help obtain the residual

differences h1 (j) and h2 (j) for every trajectory j. This can be accomplished with the help of a

calibration DAC, the linearity and speed requirements of which are discussed later in Section

5-3-2.

This section presents the implementation details of the reference scheme in the coarse ADC

of the prototype.

The prototype ADC consists of two ADC lanes, one of which is used once a second for reference

calibration. Even though this seems to imply huge penalties in terms of area and power, it

should be mentioned that this research mainly attempts to prove the concept of reference

calibration. In an actual industry-oriented chip with a time-interleaving factor greater than 2,

the penalties of taking a single lane off-line can be considered negligible. The timing diagram

is shown in Figure 5-9. The main conversion lane operates with the sampling clock of 100

MHz and 50% duty-cycle between Sample (φ1 ) and Convert (φ2 ) phases. The calibration

lane is used once a second to perform the conversions required for the complete calibration

procedure. During that period, the calibration lane samples its test input signals from a

calibration DAC which has an update rate of 10 MHz. Thus, the clock for the calibration

lane is 5% duty-cycled as shown in the figure.

5-3 Reference Scheme Implementation in Coarse SAR ADC 59

10 ns

SAR φ1 φ2

100 ns

Calibration φ1 φ2

Figure 5-9: Timing for the two ADC lanes in the prototype during calibration

Vip

Vref p mode

Vref n

FF

Q R cmp_out

hii

CN −1,1 CN −1,2 CN −2,1 CN −2,2 C0,1 C0,2 S

...

selhii

Vdacp

VCM

Figure 5-10 shows a simplified block diagram of the coarse ADC with its essential building

blocks, namely, a capacitive DAC, a comparator and the SAR logic loop alongside calibration

control. There are two modes of operation:

1. During the SAR mode, the ADC operates in a normal fashion with the capacitive

DAC sampling the input and the SAR logic proceeding with corresponding comparator out-

puts.

2. During the Calibration mode, the ADC samples test input voltages from the calibra-

tion DAC in order to obtain the difference estimates h1 and h2 for each and every trajectory.

For the sake of flexibility, each trajectory can actually be forced in the SAR loop by taking the

comparator off-line, and feeding the SAR engine with inputs from latches (FF, as shown in

the figure) that are controlled by MATLAB. This flexibility is indispensable because depend-

ing on the linearity of the calibration DAC, the test voltage corresponding to the trajectory

under test may be off the desired bin, making the residue voltage exceed the range allowed

by the back-end. By observing the output from the fine ADC with external control, tests can

be modified for each trajectory until all the information required to estimate the entire DAC

transfer are obtained. It should be remarked here that an easily-integrable implementation

of this calibration control has yet to be designed.

60 Digital Correction of Reference Errors

SSAR

RSAR Q

Scal

Rcal

SAR clk_conv 1 cmp_out↑selhii 1

Calibration 1 clk_conv 1 FF ↑selhii

The said multiplexing in the SAR engine is implemented with the help of a four-input

NAND-based SR latch, as shown in Figure 5-11. SSAR and RSAR are the active inputs during

the SAR mode, whereas Scal and Rcal are active during the Calibration mode. Their values

during the two modes are given in Table 5-1. clk_conv is used to preset the latch at the start

of every conversion cycle, and selhii is used to enable the latch i during the ith bit cycle.

The coarse ADC resolves the input full-scale range of 1.4 Vppd into 7 bits. With the reference

voltages being Vref p of 1 V and Vref n of 0 V, reference attenuation is performed as explained

in Section 3-5 to obtain the effective Vref of 0.7 V.

Capacitive DAC

The capacitive DAC employs split-cap switching algorithm [24], where every capacitor in the

array Ci is split into two sub-capacitors Ci,1 and Ci,2 , as shown in Figure 5-10. During the

Sample phase, the top plates of all of the array capacitors tied to the input of the comparator

are connected to VCM , whereas the input is sampled on the bottom plates. At the start of

the Convert phase, the bottom plates of every Ci,1 are connected to Vref p , and those of Ci,2

are connected to Vref n . This sets up the DAC voltage for the MSB comparison. As the next

bit cycle begins, depending on the result of the MSB comparison, either CN −1,1 or CN −1,2

is toggled differentially. For a positive decision, CN −1,2 in the positive DAC is connected to

Vref p , and CN −1,1 in the negative DAC is connected to Vref n . For a negative decision, CN −1,1

in the positive DAC is connected to Vref n , and CN −1,2 in the negative DAC is connected to

Vref p . Further DAC switching proceeds in the same way. A clear illustration of the split-cap

switching algorithm is given in Appendix A.

The proposed reference scheme is implemented with a Cref of 20 pF. Even though the

aforementioned calibration technique is implemented to take care of the non-linearity due

to code-dependent errors on the reference voltage, the ADC can not handle significantly

decreasing Vref because the residue voltage at the end of the coarse conversion may exceed

5-3 Reference Scheme Implementation in Coarse SAR ADC 61

the range that can be handled by the back-end (the residue amplifier and the fine SAR).

Therefore, the capacitive DAC is designed such that the capacitive division per bit cycle

accounts for the code-independent drops in Vref , as discussed in Section 4-3-1. The weights

of the sub-capacitors in a single-ended array are given by {34, 19, 11, 7, 4, 3, 2, 1, 1{. With

unit capacitor chosen as 7 fF, the total DAC capacitance equals 1.1 pF. With an average

radix of 1.52, it takes 10 bit cycles (with the MSB step resolving 1 bit) to reach an effective

resolution of 7 bits.

Pre-charge Buffer

With a 20 pF reference capacitor and the designed capacitive DAC, the code-dependent spread

on Vref at the end of SAR conversion is determined to be 10 mV. This residual spread must

be removed before the start of the next conversion up until 14-bit precision, that is, with

an allowed error of 85.5 µV (= 21.4

14 ). For that purpose, a pre-charge buffer replenishes Cref

during the Sample phase. With a 100 MHz sampling clock, 14-bit precise settling has to be

done in 5 ns, as given by

10 mV

5 ns = Rout Cref ln s. (5-4)

85.5 uV

This requires the output impedance of the buffer to be less than 50 Ω.

M2

out Zout 1

∼ gm

in M1

1

2 r

gm o

ω

1 gm2

ro1 Cgs2 Cgs2

Figure 5-12: Flipped voltage follower and its output impedance versus frequency

Such a low output impedance can be achieved with a source follower (Rout = 1/gm ),

which, however, would require a large class-A current. Negative feedback can be employed to

reduce the output impedance further. Figure 5-12(a) shows the circuit diagram of a flipped

voltage follower, which can be described as a voltage follower with shunt feedback [52]. Its

output impedance is derived as follows. When the output node suffers a voltage change of

∆V , M1 acts as a common-gate stage leading to an amplified voltage change of gm1 ro1 ∆V at

the gate of M2. M2, consequently, enables a change of gm2 (gm1 ro1 ∆V ) in the output current,

resulting in an output impedance given by

1

Rout = . (5-5)

gm1 ro1 gm2

62 Digital Correction of Reference Errors

Thus, with this voltage-sensed, current feedback, the output impedance of a simple source

follower is reduced by an amount equal to the intrinsic gain (= gm ro ) at low frequencies.

Figure 5-12(b) shows the output impedance versus frequency. It should be remarked here

that this circuit exhibits excellent current sourcing capability, as the required load current is

provided from the supply through M2, while M1 conducts constant current. This suits the

requirement for the pre-charge buffer, as the buffer is expected to supply current in only one

direction. In order to pre-discharge a capacitor holding the negative reference voltage, an

NMOS version of this circuit can be employed for its excellent current sinking capability.

The implemented pre-charge buffer is shown in Figure 5-13. M1 and M2 constitute the

enhanced source follower. M4 cascodes M3 to form the tail current source. M5 and M6 shield

the output node from power supply variations, together providing 40 dB of rejection. It can

be noticed that for Vref to be 1 V from a 1.8 V supply, the headroom is limited for all the

transistors to operate in saturation. A parallel RC level shifter (R1 ||C1 ) is placed inside the

feedback loop which offers the headroom required [53]. S1 and S2 are the switches connecting

the buffer to Cref . They are placed inside the loop so that they do not degrade the effective

output impedance seen by Cref .

A slow loop is employed to improve the DC accuracy of Vref . It consists of an error

amplifier that adjusts the input to M1 after comparing Vref with the bandgap reference. In

order to decouple the slow loop from the output node glitches, the slow loop senses the output

voltage only for the second half of the Sample phase, after the transients have settled to a

significant precision. The implemented error amplifier is a single, differential stage with a

PMOS-input topology. With a bias current of 0.3 µA, it achieves a DC gain of 50 dB and

a unity-gain bandwidth of 65 kHz. A large capacitance (= 10 pF) is used at its output to

suppress its noise contribution.

Since the buffer is not being used during the Convert phase, power-cycling is employed.

It is advantageous that this buffer exhibits fast turn-on transients. The buffer consumes a

bias current of 50 µA during the Sample phase, and 3 µA during the Convert phase. Figure

5-14 shows the transient waveforms of Vref in blue corresponding to two digital codes that

have the maximum and minimum errors in Vref at the end of SAR conversion. It can be seen

that the code-dependent spread is removed up to 14-bit precision during the Convert phase

of 5 ns. The figure also includes waveforms of currents from the supply for these two extreme

cases. The buffer responds to the voltage steps with currents as large as 1 mA. The average

current consumed by the pre-charge buffer, including the biasing blocks, is 165 µA from a 1.8

V supply.

Calibration DAC

The calibration DAC generates the test voltages required (V1 (j) and V2 (j)) during the cali-

bration procedure. To derive the linearity requirements of the DAC, the allowable deviations

of V1 (j) and V2 (j) from ideal values should be known. While testing for the trajectory j,

as Figure 5-15 shows, V1 (j) should be located within the input bin j, and V2 (j), within the

hatched region around the trip point between bins j and j + 1. Otherwise, the residue volt-

ages exceed the conversion range of the back-end. Since the allowable deviations of the test

voltages are up to the size of an LSB at the 7-bit level, the linearity requirements of the DAC

can be relaxed. Moreover, for the sake of flexibility during the calibration procedure, the test

5-3 Reference Scheme Implementation in Coarse SAR ADC 63

Vb6

M6

Vb5

M5

Ib

M2

S1

R1 C1 S2 Vref

S1

S3 Cref

Vref

M1

Bandgap

Cslow

Ib Vb4

M4

S1

Vb3,a

Vb3,b M3

S2

S1

S2

S3

voltages are generated at 9-bit resolution, offering many test voltages per trajectory. The

specifications for the calibration DAC are given in Table 5-2.

A 9-bit, current-steering DAC is implemented. The architecture is segmented "6 + 3",

where the 6-bit sub-DAC is for the MSBs and the other for the LSBs. While the LSB section

is binary-coded, thermometer coding is used in the MSB section which helps achieve good

DNL performance [54]. Since the DAC is used only for calibration purposes, not much design

effort was invested in optimizing power and high-frequency linearity performance.

64 Digital Correction of Reference Errors

Iref [mA]

Vref [V]

0.5

0.95

50 µA 3 µA

10 mV

4.01 4.011 4.012 4.013 4.014 4.015

time [s] x 10

−6

Vres Vres

j j+1 j j+1

Vin Vin

V1 (j) V2 (j)

(a) Allowed location for V1 (j) (b) Allowed location for V2 (j)

Figure 5-15: Allowed locations for the test voltages required during calibration

With the full-scale current equal to 225 uA, the unit LSB current is given by 440 nA. The

designed unit current cell is shown in Figure 5-16. It consists of a current source transistor

Mcs , a cascode transistor Mcas and a pair of differential switches Msw . Since the matching of

current sources is important for DNL performance, a large current source transistor is used

[55]. With feature sizes at Wcs = 1.4µm and Lcs = 0.75µm, the standard deviation on a unit

current source over 100 Monte Carlo runs is determined to be 0.08 LSB.

Since this DAC operates from a 1.8 V power supply, the amount of voltage headroom

left above the current steering circuitry is not sufficient to provide the required output swing

5-3 Reference Scheme Implementation in Coarse SAR ADC 65

Resolution 9 bits

Update Frequency 10 MHz

|DNL| < 0.5 LSB

|INL| < set by DNL

Output Swing 1.5 Vppd

Output CM-level 0.5 V

z̄ Msw z

Vcas Mcas

Vcs Mcs

1.8 V

2:1 1:2

Vop Von

Vcm

R1 R2

To ADC To ADC

of 1.5 Vppd. This headroom limitation is circumvented by mirroring the output currents from

the current cells, as shown in Figure 5-17. The cascode current mirror is designed to produce

66 Digital Correction of Reference Errors

0.8

0.6

Differential output voltage [V]

0.4

0.2

−0.2

−0.4

−0.6

−0.8

0 100 200 300 400 500

Input code

1

0.5

INL (LSB)

−0.5

−1

0 100 200 300 400 500

0.5

DNL (LSB)

−0.5

−1

0 100 200 300 400 500

Input code

Figure 5-19: Worst-case INL/ DNL performance of the implemented calibration DAC

The common-mode (CM) level at the output is defined and maintained by the DC bleed

5-4 Simulation Results 67

current Ibleed and the common-mode feedback network shown in red. Differential resistors R1

and R2 sense the CM level of the two outputs. The measured CM level is compared with the

reference using an error amplifier, and the error is returned to the output bias leg. The error

amplifier implemented is a single, differential stage, with a DC gain of 20 dB.

The simulated DAC transfer curve is shown in Figure 5-18. Figure 5-19 shows the worst-

case INL and DNL measured over 5 different Monte Carlo simulations. The DNL plot shows

that the DAC is 9-bit monotonic, which is more than sufficient for the calibration procedure.

This section gives the simulation results for the reference scheme implemented in the coarse

SAR. As mentioned earlier, the reference-induced distortion shows up as third-order non-

linearity in the capacitive DAC transfer, and thus the whole ADC transfer. This is evident

in Figure 5-20, where the INL of the capacitive DAC is plotted in LSB values at the 14-bit

level versus the 7-bit output code of the coarse SAR. Figure 5-21 shows the 128-point FFT

output for the coarse ADC with the designed reference scheme sampling a 90% FS, 2.43475

MHz input signal at 100 MS/s. It should be noted here that this spectrum is obtained of the

7-bit coarse code along with the conversion residue. The reference-induced harmonic is 55 dB

below the fundamental, limiting the linearity to around the 9-bit level.

15

10

5

INL (LSB)

−5

−10

−15

0 20 40 60 80 100 120

Output code

Figure 5-20: INL of the capacitive DAC with Cref = 20Cdac before calibration

Since the capacitive DAC has overrange built in, there are multiple possible trajectories

that represent the same digital output which complicates the calibration procedure. However,

it can be assumed that such equivalent trajectories have the same residual error in Vref

since they travel the same distance along the DAC tree. Thus, the calibration procedure is

performed only for the 128 trajectories that represent 128 different digital outputs. Figure

5-22 shows the INL of the capacitive DAC after calibration. The reason for the residual error

68 Digital Correction of Reference Errors

0

SNDR = 54.61 dB

−20

SFDR = 54.64 dB

−40

Amplitude [dB]

−60

−80

−100

−120

0 10 20 30 40 50

Frequency [MHz]

Figure 5-21: Coarse ADC performance with Cref = 20Cdac before calibration

1

0.8

0.6

0.4

0.2

INL (LSB)

−0.2

−0.4

−0.6

−0.8

−1

0 20 40 60 80 100 120

Output code

Figure 5-22: INL of the capacitive DAC with Cref = 20Cdac after calibration

is that this calibration algorithm employs the distance estimates that are obtained in the

additional step to correct for the reference errors during SAR conversion. The error caused

in Vref during this additional switching is unaccounted for. The sine-wave performance after

calibration is shown in Figure 5-23. Thus, the reported calibration scheme brings 30 dB

of improvement in ADC linearity with respect to reference-induced distortion. It should be

remarked here that the accuracy of this calibration scheme is limited by the quantization

effects of the back-end that processes the distance estimates required for the algorithm.

5-5 Summary 69

−40

Amplitude [dB]

SFDR = 84.43 dB

−60

−80

−100

−120

0 10 20 30 40 50

Frequency [MHz]

Figure 5-23: Coarse ADC performance with Cref = 20Cdac after calibration

5-5 Summary

This chapter presented the implementation of the proposed reference scheme in the coarse

stage of the prototype ADC. A digital calibration algorithm was proposed to correct for the

ADC non-linearity caused by errors in Vref stored on a stand-alone capacitor. Finally, the

simulation results before and after calibration were presented, showing that 84 dB of linearity

was achieved with respect to reference-induced distortion.

70 Digital Correction of Reference Errors

Chapter 6

Conclusion

A novel reference scheme suitable for high-end SAR converters has been proposed in this dis-

sertation. In the case of a SAR converter with conventional reference circuitry, the conversion

speed is determined by how fast the reference buffer can settle the transients induced by DAC

switching during every bit cycle. With a large number of bit cycles and capacitive arrays in

the case of high-resolution converters, the reference buffer becomes the most power-hungry

block in order to provide very low output impedance. This essentially limits the SAR con-

verters from achieving good power efficiency at higher speeds. The proposed reference scheme

eliminates this speed limit by employing a stand-alone capacitor to hold the reference voltage

during SAR conversion. Reference settling is limited only by switch resistance and intercon-

nect parasitics. As a result, bit cycles become significantly shorter, which help accommodate

a large number of bit cycles in shorter conversion cycles.

When the stand-alone reference capacitor is valued moderately for area concerns, the

code-dependent errors induced in the reference voltage due to DAC switching become signifi-

cant, leading to heavy distortion. Two different, elaborate calibration techniques are proposed

that help remove the reference-induced linearity. As a proof-of-concept, the proposed refer-

ence scheme is implemented in a 12-bit, 100 MS/s, two-stage, SAR-assisted pipeline ADC in

28 nm CMOS. With both the stages in the pipeline employing moderately-valued, stand-alone

reference capacitors, the calibration techniques help to suppress the thus induced distortion

to less than 84 dB, effectively not degrading the SNDR.

The prototype ADC, designed by the research team in Broadcom Netherlands, along

with the proposed reference scheme consumes a total of 1.81 mW. Twenty-five percent of this

power (460 uW) is spent in pre-charging the reference capacitors during the Sample phase.

With the near-Nyquist SNDR at 68 dB, the Schreier FoM achieved is 175.5 dB. Figure 6-1

shows the reported ADC FoM in the context of the state-of-the-art SAR ADCs (from recent

ISSCC and VLSI publications). With the aid of the implemented reference scheme, this work

clearly pushes the power envelope at moderate speeds. This can serve as an excellent starting

point for time-interleaved architectures, with which we can move the energy efficiency to

higher speeds, ultimately achieving the target FoM for simultaneous full-band capture in a

mobile radio front end.

72 Conclusion

190

Target

180

Prototype ADC

170 with the implemented reference scheme

160

FOMS [dB]

150

140

130 SAR

SAR-TI

120

110

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

f s [Hz]

Figure 6-1: Schreier FoM plot of the state-of-the-art ADCs along with the prototype

Some of the salient features of the implemented reference scheme are summarized in this

section.

a conventional, active buffer to provide the reference voltage during SAR conversion, the

reference settling time has been improved significantly. This enabled the average bit trial

time to be reduced from 1 ns to 350 ps potentially for the same power consumption. Further

speed improvement is limited by other factors in the SAR loop, namely, the comparator

and the digital logic. If not for them, this usage of reference capacitor would have given an

additional 100 ps benefit per bit cycle.

the prototype, using a 1 pF reference capacitor gives an THD of 38.9 dB. Since the reference

errors induced can be determined given the knowledge of the switching decisions being made,

they are corrected through a compensation technique in the charge domain. This improves the

THD to 60.5 dB, more than what is necessary for 8-bit linearity in the fine stage. The overhead

is a small bank of compensation capacitors, whose total capacitance is 20 fF, and digital logic

that performs selection from the bank based on switching decisions, which consumes 30 µW

average power.

6-2 Future work 73

prototype, using a 20 pF reference capacitor gives an THD of 54.6 dB. A digital calibration

algorithm that takes advantage of the pipeline architecture of the prototype is proposed. The

reference errors are estimated and corrected for by processing the residue voltage of the coarse

conversion. This improves the THD to 84.4 dB, essentially not degrading the SNDR of the

whole ADC. The overhead is that the calibration procedure being a deterministic scheme, a

conversion lane is taken off-line and used to measure the estimates required for correction.

A 9-bit, current-steering calibration DAC and digital processing required for calibration also

represent overhead, however, not in terms of power as they are operated once in a second.

Pre-charge buffer with excellent current sourcing capability For pre-charging the ref-

erence capacitors during the Sample phase, a buffer with excellent current sourcing capability

is designed. It achieves very low output impedance with the aid of a negative feedback net-

work that reuses the main bias current. Drive currents as large as 20 times the quiescent

current are obtained.

At this juncture, some remarks have to made about two relevant works in the literature

that also propose replacing the active reference buffer in a SAR converter with a storage

capacitor, or more specifically, a reference in charge domain. Craninckx and Plas [56] proposed

pre-charging a bank of binary-scaled capacitors which will be connected one by one to the

input sampling capacitor, thus adding/subtracting reference charge until the total charge

converges to zero. While they report a good bit trial time of 1 ns, with reference settling

time determined by the charge sharing switches (in 90 nm CMOS), the SNDR achieved

is limited to the 9-bit level. Analog-domain impairments such as switch charge injection,

capacitor parasitics, and more noise sampling events are introduced inside the SAR loop,

which limit linearity. A more recent work by Kapusta, et al. [57] employs a similar pre-

charged reference for the MSB bit trial, where the reference settling is the most stringent.

However, the code-dependence of the reference charge throughout the whole conversion cycle

is not addressed, which implies that they either utilized an auxiliary reference buffer during

the latter bit cycles or that the capacitance is so high that code-dependence is insignificant.

On the other hand, this work stays close to a classical SAR architecture by employing a single

reference source throughout the conversion cycle, and the code-dependence on the reference is

addressed properly through two elaborate compensation techniques that help achieve almost

14-bit linearity.

The design presented in this dissertation gives satisfactory results in simulations. Due to

time constraints, the layout of the proposed new blocks has not been done yet. Realizing a

proof-of-concept test chip is the next step. Meanwhile, this section recognizes some of the

possible improvements that can be made to the proposed reference scheme as follows:

• While this work presented effective ways of removing the code-dependence in the ref-

erence caused by DAC switching, it would be better to first investigate the switching

algorithms that cause this code-dependence, and come up with algorithms that present

less dependence themselves. Set-and-down and split-cap algorithms used in this work

74 Conclusion

exhibit quadratic dependence with fairly large standard deviations of the switching

energies versus code. Whereas, some recently proposed algorithms in the literature,

namely, early-reset merged capacitor switching [58], input-range prediction [28], and

charge-average switching [29], present small code-dependence and the resulting distor-

tion induced would be less to start with.

• The residual INL after digital correction of reference errors in the coarse ADC exhibits

a systematic pattern versus code. Even though this is attributed to the fact that the

errors caused in the reference during the additional step have not been accounted for, a

proper analysis of the residual INL pattern has to be performed. This might help predict

the residual pattern through mathematical models and thus achieve better linearity.

• The digital calibration procedure in this work needs external control to ensure collecting

all of the required information. An on-chip digital machine which can control collecting

the calibration data has to be designed.

• The implemented reference scheme involves a single, stand-alone capacitor holding the

reference voltage. This large capacitor has to be replenished during the Sample phase

which consumes a considerable amount of power. In future implementations, more than

one capacitor can be used in a ping-pong fashion. Proper design choices have to be

made after investigating the trade-off between chip area and power consumption.

Appendix A

from the Reference Source

A DAC switching event in a bit cycle involves switching a capacitor either from a positive to

a negative reference, vice versa or both in a differential manner, as dictated by the switching

decisions and the algorithm being used. This appendix derives a generalized mathematical

model of the charge steered from the reference source during a switching event, and illustrates

the two switching algorithms used in this thesis.

Figure A-1(a) illustrates the switching event for a negative DAC step. Capacitor Csw

is switched from a positive reference (Vref ) to a negative reference (assumed to be ground)

in order to change the DAC voltage from Vdac to Vdac ′ . Capacitors C and C represent the

+ −

capacitances connected to positive and negative references during the switching event. The

corresponding charge steered from the reference source is given by

′

Q− = −(C+ ) (Vref − Vdac ) − (Vref − Vdac ) . (A-1)

The DAC voltages before and after switching are given by

C+ + Csw

Vdac = Vref , (A-2)

Cdac

and

′ C+

Vdac = Vref , (A-3)

Cdac

where Cdac is the total DAC capacitance (= Csw + C+ + C− ). Equation (A-1) becomes

Csw C+

Q− = . (A-4)

Vref

Similarly, if Csw is switched for a positive step, ie., from ground to Vref , as shown in

Figure A-1(b), the charge required is given by

Csw C−

Q+ = . (A-5)

Vref

76 Code-dependent Charge Steering from the Reference Source

Vref Vref

C+ Csw C+

Csw C+

Q− = Cdac Vref

C− C− Csw

Vref Vref

C+ C+ Csw

Csw C−

Q+ = Cdac Vref

C− Csw C−

Based on the switching algorithm, either or both of Equations (A-4) and (A-5) apply

during a switching event. The code-dependence part of the reference charge in a bit cycle

arises from the different possible combinations of C+ and C− .

In set-and-down algorithm [26], all the array capacitors are connected to Vref p at the start

of the Convert phase. During bit cycling, based on the switching decision, a capacitor in

either the positive or the negative DAC is switched to Vref n . Figure A-2 illustrates the DAC

switching events for a positive and a negative switching decision.

As evident, this algorithm always involves a negative DAC step. Equation (A-4) can be

rewritten to derive the reference charge per bit cycle for this algorithm. In an ith bit cycle,

Ci+1 is the switching capacitor (Csw ). The capacitance tied to the positive reference (C+ ) in

a bit cycle is given by the total capacitance of the capacitors that have not been switched yet

i

P

(= Cl ) and those that remain tied to the positive reference after their switching turns.

l=0

A-2 Split-capacitor Switching Algorithm 77

i

X X

C+ = Cl + s, (A-6)

l=0 s∈Sd

where Sd ⊂ {Cm |(i + 1) < m < N }.

The choice of subset Sd is code-dependent. Thus, the total charge required in each bit cycle

is given by

!

i

P P

Ci+1 Cl + s

l=0 s∈Sd

Qi = (Vref p − Vref n ) (A-7)

Cdac

for i = N − 2, N − 3, ..., 0.

Ci

Di−1 = 1

... ... Vdacp

Vref

Ci

Ci

Ci

Ci

Ci

In split-capacitor algorithm [24], every capacitor in the array is split into two sub-capacitors.

At the start of the Convert phase, one sub-capacitor in each is connected to Vref p and the other

to Vref n . During bit-cycling, these sub-capacitors are switched differentially as illustrated in

A-3. With this algorithm, every DAC switching event involves both a positive and a negative

DAC step. The total charge required of the reference source in each cycle can be obtained by

rewriting and summing Equations (A-4) and (A-5) accordingly.

78 Code-dependent Charge Steering from the Reference Source

Vref Vref

Ci,1 Ci,2

Di−1 = 1

... ... Vdacn

Vref

Ci,1 Ci,2

Ci,1 Ci,2

Vref

Di−1 = 0

... ... Vdacn

Ci,1 Ci,2

Vref Vref

79

Bibliography

[1] J. Mitola, “The software radio architecture,” Communications Magazine, IEEE, vol. 33,

no. 5, pp. 26–38, 1995.

[2] A. Abidi, “The path to the software-defined radio receiver,” Solid-State Circuits, IEEE

Journal of, vol. 42, no. 5, pp. 954–966, 2007.

[4] R. Walden, “Analog-to-digital converter survey and analysis,” Selected Areas in Com-

munications, IEEE Journal on, vol. 17, no. 4, pp. 539–550, 1999.

2005.

analysis of channel mismatch effects in time-interleaved adc systems,” Circuits and Sys-

tems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 48, no. 3,

pp. 261–271, 2001.

techniques. i,” Solid-State Circuits, IEEE Journal of, vol. 10, no. 6, pp. 371–379, 1975.

[8] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R. Martins, and F. Maloberti, “A 10-

bit 100-ms/s reference-free sar adc in 90 nm cmos,” Solid-State Circuits, IEEE Journal

of, vol. 45, no. 6, pp. 1111–1121, 2010.

[9] Z. Cao, S. Yan, and Y. Li, “A 32 mw 1.25 gs/s 6b 2b/step sar adc in 0.13 um cmos,”

Solid-State Circuits, IEEE Journal of, vol. 44, no. 3, pp. 862–873, 2009.

[10] K. Bult, “The effect of technology scaling on power dissipation in analog circuits,” in

Analog Circuit Design, pp. 251–294, Springer, 2006.

80 Bibliography

[12] F. Kuttner, “A 1.2v 10b 20msample/s non-binary successive approximation adc in 0.13

um cmos,” in Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC.

2002 IEEE International, vol. 2, pp. 136–137, 2002.

[13] B. Razavi, Design of Analog CMOS Integrated Circuits. New York, NY, USA: McGraw-

Hill, Inc., 1 ed., 2001.

[14] S. Jamal, D. Fu, N.-J. Chang, P. Hurst, and S. Lewis, “A 10-b 120-msample/s time-

interleaved analog-to-digital converter with digital background calibration,” Solid-State

Circuits, IEEE Journal of, vol. 37, no. 12, pp. 1618–1627, 2002.

[15] S. Louwsma, A. J. M. Van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 gs/s, 10 b, 175 mw

time-interleaved ad converter in 0.13 um cmos,” Solid-State Circuits, IEEE Journal of,

vol. 43, no. 4, pp. 778–786, 2008.

[16] D. Stepanovic, Calibration Techniques for Time-Interleaved SAR A/D Converters. PhD

thesis, EECS Department, University of California, Berkeley, Dec 2012.

[17] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. Van Der Weide, “A 480mw

2.6gs/s 10b 65nm cmos time-interleaved adc with 48.5db sndr up to nyquist,” in Solid-

State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International,

pp. 180–182, 2011.

of their failure rate,” Solid-State Circuits, IEEE Journal of, vol. 15, no. 2, pp. 169–176,

1980.

[19] S.-W. Chen and R. Brodersen, “A 6-bit 600-ms/s 5.3-mw asynchronous adc in 0.13-

cmos,” Solid-State Circuits, IEEE Journal of, vol. 41, no. 12, pp. 2669–2680, 2006.

[20] T. Tong, “Design techniques for successive approximation register analog-to-digital con-

verters,” 2011.

[21] C. Lee and M. Flynn, “A sar-assisted two-stage pipeline adc,” Solid-State Circuits, IEEE

Journal of, vol. 46, no. 4, pp. 859–869, 2011.

[22] Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, K.-D. Kim, W.-Y. Lee, K.-T. Hong, and J.-K. Kwon,

“A 9.15mw 0.22mm2 10b 204ms/s pipelined sar adc in 65nm cmos,” in Custom Integrated

Circuits Conference (CICC), 2010 IEEE, pp. 1–4, 2010.

fully dynamic pipelined sar adc in 40nm digital cmos,” in Solid-State Circuits Conference

Digest of Technical Papers (ISSCC), 2012 IEEE International, pp. 466–468, 2012.

[24] B. Ginsburg and A. Chandrakasan, “An energy-efficient charge recycling approach for a

sar converter with capacitive dac,” in Circuits and Systems, 2005. ISCAS 2005. IEEE

International Symposium on, pp. 184–187 Vol. 1, 2005.

[25] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-ks/s low power sar adc for

bio-medical applications,” in Solid-State Circuits Conference, 2007. ASSCC ’07. IEEE

Asian, pp. 228–231, 2007.

81

[26] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-ms/s sar adc with a

monotonic capacitor switching procedure,” Solid-State Circuits, IEEE Journal of, vol. 45,

no. 4, pp. 731–740, 2010.

[27] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching

based sar adc with highest switching energy-efficiency,” Electronics Letters, vol. 46, no. 9,

pp. 620–621, 2010.

[28] H.-Y. Huang, J.-Y. Lin, C.-C. Hsieh, W.-H. Chang, H.-H. Tsai, and C.-F. Chiu, “A 9.2b

47fj/conversion-step asynchronous sar adc with input range prediction dac switching,” in

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, pp. 2353–2356,

2012.

[29] C.-Y. Liou and C.-C. Hsieh, “A 2.4-to-5.2fj/conversion-step 10b 0.5-to-4ms/s sar adc

with charge-average switching dac in 90nm cmos,” in Solid-State Circuits Conference

Digest of Technical Papers (ISSCC), 2013 IEEE International, pp. 280–281, 2013.

[30] B. Ginsburg and A. Chandrakasan, “500-ms/s 5-bit adc in 65-nm cmos with split ca-

pacitor array dac,” Solid-State Circuits, IEEE Journal of, vol. 42, no. 4, pp. 739–747,

2007.

[31] M. Saberi, R. Lotfi, K. Mafinezhad, and W. Serdijn, “Analysis of power consumption

and linearity in capacitive digital-to-analog converters used in successive approximation

adcs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 58, no. 8,

pp. 1736–1748, 2011.

[32] W. Liu and Y. Chiu, “An equalization-based adaptive digital background calibration

technique for successive approximation analog-to-digital converters,” in ASIC, 2007.

ASICON ’07. 7th International Conference on, pp. 289–292, 2007.

[33] W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-

K. Ma, and Y. Chiu, “A 600ms/s 30mw 0.13 um cmos adc array achieving over 60db

sfdr with adaptive digital equalization,” in Solid-State Circuits Conference - Digest of

Technical Papers, 2009. ISSCC 2009. IEEE International, pp. 82–83,83a, 2009.

[34] W. Liu, P. Huang, and Y. Chiu, “A 12b 22.5/45ms/s 3.0mw 0.059mm2 cmos sar adc

achieving over 90db sfdr,” in Solid-State Circuits Conference Digest of Technical Papers

(ISSCC), 2010 IEEE International, pp. 380–381, 2010.

[35] R. Xu, B. Liu, and J. Yuan, “Digitally calibrated 768-ks/s 10-b minimum-size sar adc

array with dithering,” Solid-State Circuits, IEEE Journal of, vol. 47, no. 9, pp. 2129–

2140, 2012.

[36] G. Wegmann, E. Vittoz, and F. Rahali, “Charge injection in analog mos switches,”

Solid-State Circuits, IEEE Journal of, vol. 22, no. 6, pp. 1091–1097, 1987.

[37] H.-S. Lee, D. Hodges, and P. Gray, “A self-calibrating 15 bit cmos a/d converter,” Solid-

State Circuits, IEEE Journal of, vol. 19, no. 6, pp. 813–819, 1984.

[38] B. Murmann and B. Boser, “A 12 b 75 ms/s pipelined adc using open-loop residue

amplification,” in Solid-State Circuits Conference, 2003. Digest of Technical Papers.

ISSCC. 2003 IEEE International, pp. 328–497 vol.1, 2003.

82 Bibliography

[39] C. Grace, P. Hurst, and S. Lewis, “A 12-bit 80-msample/s pipelined adc with boot-

strapped digital calibration,” Solid-State Circuits, IEEE Journal of, vol. 40, no. 5,

pp. 1038–1046, 2005.

[40] J. Keane, P. Hurst, and S. Lewis, “Background interstage gain calibration technique for

pipelined adcs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52,

no. 1, pp. 32–43, 2005.

pipelined adcs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53,

no. 9, pp. 1885–1895, 2006.

[42] B. Sahoo and B. Razavi, “A 12-bit 200-mhz cmos adc,” Solid-State Circuits, IEEE Jour-

nal of, vol. 44, no. 9, pp. 2366–2380, 2009.

[43] N. Sun, “Exploiting process variation and noise in comparators to calibrate interstage

gain nonlinearity in pipelined adcs,” Circuits and Systems I: Regular Papers, IEEE

Transactions on, vol. 59, no. 4, pp. 685–695, 2012.

[44] A. Karanicolas, H.-S. Lee, and K. Barcrania, “A 15-b 1-msample/s digitally self-

calibrated pipeline adc,” Solid-State Circuits, IEEE Journal of, vol. 28, no. 12, pp. 1207–

1215, 1993.

[45] I. Galton, “Digital cancellation of d/a converter noise in pipelined a/d converters,”

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on,

vol. 47, no. 3, pp. 185–196, 2000.

[46] H.-C. Liu, Z.-M. Lee, and J.-T. Wu, “A 15-b 40-ms/s cmos pipelined analog-to-digital

converter with digital background calibration,” Solid-State Circuits, IEEE Journal of,

vol. 40, no. 5, pp. 1047–1056, 2005.

[47] Y.-S. Shu and B.-S. Song, “A 15-bit linear 20-ms/s pipelined adc digitally calibrated

with signal-dependent dithering,” Solid-State Circuits, IEEE Journal of, vol. 43, no. 2,

pp. 342–350, 2008.

and Computer Science). Secaucus, NJ, USA: Springer-Verlag New York, Inc., 2006.

[49] J. McNeill, M. Coln, and B. Larivee, “"split adc" architecture for deterministic digital

background calibration of a 16-bit 1-ms/s adc,” Solid-State Circuits, IEEE Journal of,

vol. 40, no. 12, pp. 2437–2445, 2005.

[50] H.-S. Lee, “A 12 bit 600 ks/s digitally self-calibrated pipeline algorithmic adc,” in VLSI

Circuits, 1993. Digest of Technical Papers. 1993 Symposium on, pp. 121–122, 1993.

in Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE Inter-

national, pp. 144–145, 1998.

[52] P. R. Gray, Analysis and Design of Analog Integrated Circuits. Wiley Publishing, 5th ed.,

2009.

83

and F. Chavero, “The flipped voltage follower: a useful cell for low-voltage low-power

circuit design,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52,

no. 7, pp. 1276–1291, 2005.

[54] C.-H. Lin and K. Bult, “A 10-b, 500-msample/s cmos dac in 0.6 mm2,” Solid-State

Circuits, IEEE Journal of, vol. 33, no. 12, pp. 1948–1958, 1998.

tors,” Solid-State Circuits, IEEE Journal of, vol. 24, no. 5, pp. 1433–1439, 1989.

charge-sharing sar adc in 90nm digital cmos,” in Solid-State Circuits Conference, 2007.

ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 246–600, 2007.

[57] R. Kapusta, J. Shen, S. Decker, H. Li, and E. Ibaragi, “A 14b 80ms/s sar adc with

73.6db sndr in 65nm cmos,” in Solid-State Circuits Conference Digest of Technical Papers

(ISSCC), 2013 IEEE International, pp. 472–473, 2013.

[58] J. Guerber, H. Venkatram, T. Oh, and U.-K. Moon, “Enhanced sar adc energy efficiency

from the early reset merged capacitor switching algorithm,” in Circuits and Systems

(ISCAS), 2012 IEEE International Symposium on, pp. 2361–2364, 2012.

84 Bibliography

- DSP Practical File ProgramsUploaded byShabbir Hasan
- reportFigaroUploaded byNya Nya'
- Analog to DigitalUploaded byIsrarkhalis Khalis
- 7 DigitalUploaded byAnil Yadav
- PCI 6023EUploaded byjoseluisrosglz
- Measurement of Body Temperature and Heart RateUploaded byVibhav Mahale
- IRJET-Low Frequency CMOS Sigma-Delta Analog to Digital Converter for Medical ApplicationUploaded byIRJET Journal
- 5. Kitchen Timer and Room ThermometerUploaded bymiguelcali
- TestMSST2010Uploaded bydangchi_nguyen
- Diagnosis of continuous rotor–stator rubbing in large scale turbine units using acoustic emissionUploaded byRebel Alssaih
- Data Aquisition FundamentalUploaded byStepan81
- Mitra-Ch9 (1) Ch 5 AdspUploaded byGuru Mahesh
- AD7708_7718.pdfUploaded byjuenkkin
- T2 Analog I-O ModulesUploaded byclibro
- Oemax Nx70 Um002a en pUploaded bydautroc13
- slyt640Uploaded byMilan Đorđevic
- Simulation Questions[1]Uploaded bysweethari2009
- job 5Uploaded byKhoirul Anam Al Iman
- aaUploaded byFradj Ghrib
- Placa Del ReceptorUploaded byAlex Alberiano Mamani Quincho
- LBG_ELBGUploaded byWalid A. Sayssouk
- ADC10D040Uploaded byskiziltoprak
- PCM_Sampling.docUploaded bySARAH FAROOQI
- Adc Guide TI cc SOCsUploaded byAndrew Martin de Nicolas
- 07891002Uploaded byjoyce george
- Digital Notch Filter Operating ManualUploaded byalexamod
- 00018582Uploaded byRaghav Chaudhary
- digicomUploaded bySamantha Allen Mae Villanueva
- STM300x_UserManual_May2017Uploaded bymARTIN
- 07824120.pdfUploaded bychaitanya s

- Fork Lift Ge Controller China Single MotorUploaded bylg900df5063
- Energy Through Busy RoadUploaded byLaxman Gautam
- Tv Plasma Lg 42px3rva 42px3rva Zc Chassis Mf 056cUploaded byNani Vellanki
- Chinese USB Boost ChargerUploaded byAnonymous YDF1ID15zJ
- PP 161-166 Transient Stability Analysis of the IEEE 9-Bus Electric Power SwaroopUploaded byEditorijset Ijset
- ANSI Code ProtectionUploaded byhassan karimi
- Formality Debugging Failing Verifications PresentationUploaded byBo Lu
- 1LAB 000280 EasyDry DMB OA Bushing Nov 2012 (1)Uploaded byJason Bourne
- 1P2 Op Amp Circuits L2 Notes CollinsUploaded byFuh Vallery
- L11B-E-02 Ericsson LTE Field Guide Notification Alert - LTE RACH Preamble ChangeUploaded bysarfraz Ahmed
- 1606-td002_-en-pUploaded byErick Rodrigo Peña
- 293263325-aries-answers-unit-5-hardware.pdfUploaded byMarvinDamen
- latiguillo.pdfUploaded byFrederiv Urpìn
- Electrical-Engineering-portal.com-Testing and Commissioning of MVHV CablesUploaded byFernando Patiño Guevara
- Fourth Year EntcUploaded byAbinash Behera
- Asco Medium Voltage Brochure_2Uploaded byJamaludin Muhamad
- Special Stats RequestUploaded byOwen Simwanda
- AC CurrentUploaded bymksayshi
- PT2399_1Uploaded byBengalPro
- Nissan Cube BcsUploaded byulisse_
- Gate Tips Important TopicUploaded byKanoj Kariappa
- 1-ksy10Uploaded byBrayant Rojas
- PIC18F45k50Uploaded byduknow2
- Genex 4009 9 cam multiplexerUploaded bystadawg
- Impedance Matching Lab_4Uploaded byMihail
- CEA Draft Regulation for Construction of Electrical Plants_Aug'10Uploaded bykalgith
- 27432 Samsung HT-DB600 Home Teather 5.1 Dolby Sorround Manual de Servicio ParcialUploaded byFernandoSanchez
- test.pdfUploaded byishak789
- 3406c_02_SISUploaded byBernardo Angulo Cardenas
- 220-601 with answersUploaded byQueetco