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Kurt Hesse


IBULK or 400mA.0 batteries where large amounts of energy must be amps and the maximum overcharge voltage (Voc) stored and low cost is more important than weight will be 14. a discharge voltage of 10. for the circuit (IOCT and ITC) are up to the circuit de- The reader is encouraged to read the references signer.0 amps. This paper be used as the bulk charge enable threshold presents an isolated switch-mode charging circuit (VCHGENB). ity. This charger will float the bat- systems. voltage will be +10/–25%. for lead-acid batteries that operates from a 115Vac The remaining parameters that must be specified circuit. 195 Vdc.Unitrode Corporation Application Note U-166 INTRODUCTION be charged from a 14.95 x V OC VFLOAT BATTERY VOLTAGE VCHGENB UDG-98003 T0 T1 T2 T3 T4 Figure 1.0 volt source that is current limited to 4.6 to 13.8 volts. The tolerances on this input For this design. telephone tery at 13.7 battery as quickly and safely as supply on the primary side can range from 130 to possible to the highest practically attainable capac. This means that the bulk Picher HE12V12.6 to 15. DESIGN REQUIREMENTS The power source for this charger will be a stan- dard 125 Vac circuit. Battery voltage and current over one charging cycle. 2 .8 volts (Vfloat).8 volts. From the battery manufacturer’s data sheet. the bulk Lead-acid batteries are the most commonly used charge current for this charger (Ibulk) will be 4. and maintain this capacity indefinitely. There is much useful current threshold (IOCT) is picked to be 10% of information there that will not be repeated here. The trickle current (ITC) is picked to be 2% of the bulk current or 80mA.5 volts so this value will tronic devices such as a bag-phone. this battery may IBULK BATTERY CURRENT IOCT ITC ISTEADY VOC 0. Therefore. The float voltage is specified to or physical size. the over charge terminate listed at the end of this paper. In this design. the goal is to charge an Eagle. alarm system backup power. Typical applications include UPS be 13. The battery is specified to system backup power and larger portable elec.

the battery current falls below a preset threshold rent than can be programmed in the trickle charge while its voltage is held at Voc.2K 10µF 4 RT2 GND 5 UDG-98075 Figure 2.00K 1. bulk given threshold. Note that trickle rises. 1. Trickle Charge Over Charge (T0 to T1) The charger will supply a small current. 3 DSN 2T 3T MUR160 RSN2 CSN2 20 750pF OI-B H11AB17A Q1 IRF720 FROM FIG. the charger will supply up to Ibulk amperes to disabled by connecting CHGENB to VLOGIC. the voltage control loop will begin to take charging may be skipped depending upon the bat.32K 1. rent to the battery if the battery voltage is above a gorithm. a load and the battery. (T4 and beyond) The float charge is entered when erates from the incoming line and needs more cur. over and regulate the battery voltage to the over tery voltage when the charger is powered. + EMF/RFI SUPRESSION RSN1 C1 R4 50Ω 470µF 24T 470K 6T B1 CSN1 LS L WLO4F 330pF P 120 Vac TO FIG. applications. 3 . the typically C/100 (ITC) to the battery until the battery charger tries to regulate the battery voltage to a voltage reaches a predetermined threshold value constant voltage. When the charger enters the (VCHGENB). The purpose behind trickle charging is over charge state. This current will be applied until charge. The four stages are trickle charge. In some charge voltage Voc (Shown at T3). 3 R2 R3 DSN 2. The stages the battery voltage rises above 95% of the maxi- operate as follows in Fig.0µF CT 3 RT1 OUT 6 1nF + C2 RT2 10. the current control loop will likely to prevent a potentially hazardous condition be dominant and a constant current will continue to caused by continuously pumping bulk charge cur. The charger will remain in the float state until power to the UC3909 is cycled or until the battery voltage drops below 90% of Voc. it may be necessary to disable the trickle charge portion of the algorithm entirely. As the battery voltage rent into a damaged battery. be applied to the battery. over charge and float charge. The trickle charge stage can be permanently state. (T2 to T4) During the over charge state.00K MUR160 R1 CZB 220Ω 220pF UCC3809 1 FB REF 8 RG RCS CSS 10Ω CCS 0. Primary side schematic. An Float Charge example of this might be a device that normally op. mum overcharge voltage.Unitrode Corporation Application Note U-166 DESIGN OVERVIEW Bulk Charge (T1 to T2) The charger will supply a constant cur- The UC3909 implements a four-stage charging al. Voc.27Ω 10nF 1.0µF 2 SS VDD 7 RT1 C3 4. While in the float state.

ROVC1 and ROVC2 determine the current level for the transition from bulk charg- The circuit description presented is a discontinu- ing to float charging. threshold for the UCC3809. RSN2. the charger will wake up in ei. the startup resistor.0K COVC VA– 12 10 CHGENB 1.0K 9 OVCTAP RG2 RVG 649K 10. RCS. R1. Q3. RT2 and CT. ous flyback with peak forward rectifiers on auxiliary windings to derive power for the control IC’s. The secondary side schematic. snubbers. CSN2 and DSN are ring and dV/dt up and begins charging the soft-start capacitor. the charger will re-enter the secondary side electronics. ing upon the battery voltage. The resistor divider string RS1 through RS4 determines CIRCUIT DESCRIPTION all voltage thresholds. shows the ther the trickle or the bulk charge states. D1 and voltage on this capacitor reaches the turn-on C2 form the power supply for the UCC3809. Secondary side schematic.7AH NDF0610 UC3909 R10 20 2T 3T 1 RTHM R7 100K CO OSC 19 2 VLOGIC 5600µF RTHERM RSET 10K D4 Q3 RSET 18 21. Fig. the UC3909 will not be pow- UCC3809 primary side controller being used as a ered and the resistor divider string will be discon- peak current controller. when the bypass capacitor for the chip reference. connect the battery from the voltage divider string when the charger is not powered from the line. CZB and OI-B R4. R3. supplies a small current to charge the supply form the feedback and ramp circuit. First. soft start interval.74K ROVC2 CAO 14 1. 2 and 3. 4 . depend. The operating frequency nected when the charger is not powered from the and maximum switch on time are determined by line.47K OI-A 8 STATLV CA– 13 RS3 10. Second. the UCC3809 wakes CSN1. In order not to cause a current The primary side schematic Fig. RSN1. D2 MBR10100 24T 6T R6 100K R5 12V Q2 10. C2. When line power is applied to the charger. C3 is simply a capacitor. R6 and R7 dis- bulk charge sate. UC3909 reside on the secondary side of the circuit with the battery.47K 100K RS4 7 STAT0 CCP ROVC1 115K 0.Unitrode Corporation Application Note U-166 If power is cycled. R2. 3. Q2.0µF VAO 11 Q4 2N3904 RE 150Ω UDG-98073 Figure 3. 2 shows a drain on the battery. UC3909 and its associated support components.4K CSF RCS RSF2 0. R4. If the battery voltage D4 and C4 form the power supply circuit for the drops to 90% of VOC. See The nature of the application demands that the Figs.5K RSF1 1N4148 2N3904 75Ω 3 GND CS– 17 RS1 46. for the UCC3809. CSS determines the several events take place.1µF 20mΩ 4 VCC 75Ω CS+ 16 + C4 5 OUT 10µF CSO 15 RS2 6 STAT1 RCZ 775Ω RG1 3.01µF 1. components RT1.0K 12.

the sum of the switch voltage is given by: maximum on and reset times will only be allowed N p  to be 85% of a switching period. At this time. these values can be determined: (400V) 1 2 (1) Pin = I p L p F s Vdc is the maximum dc voltage on the input fil. an allowance for losses in the inductor and power switch. the Pout is the output power of the flyback inductor feedback circuit can then command shorter pulse Iout is the maximum average output current widths from the UCC3809 and regulate the current (Ibulk or 4A) and voltage output. The maximum turns ratio (Np/Ns) is determined by the maximum voltage stress that is to be allowed Inductor Values. the turn-off (~ 30% of Vdc) bootstrap supplies for both the UCC3809 and the With these values. Third. 8 In this application. When the bootstrap supplies come up. Maximum “On” and “Reset” on the power switching device. times. The turns ratio. The peak power the circuit remains discontinuous. Fourth. The maximum output power required from the fly- age on C4 falls to the UCC38098 UVLO threshold) back inductor is: ( ) since the feedback mechanism is commanding maximum pulse width until the opto-isolator is Pout = I$out V batt + Vdiode made to pass current into R1.7V level before the volt. power switch.Unitrode Corporation Application Note U-166 CSS. the peak currents and the on and reset times. This cannot happen Where: until the bootstrap supply for the UC3909 comes up. A conservative estimate is (based on 80% Overbar: Vdc – a maximum value efficiency up to the output rectifier diode): Underbar: I ls – a minimum value POUT PIN = Carat: I$ – an average value out 0. the output power is 64W and the Flyback Inductor Turns Ratio input power is 80W.7V. the maximum volt. The circuit is guaranteed to start (provided that the soft start capacitor is not chosen too large and Power Requirements cannot be charged to the 0. the battery according to the charge algorithm de- This is well within safety margins for a 400 volt scribed above and in the references. the UCC3809 will begin to issue Np/Ns is the inductor turns ratio output pulses. To assure that when the power switch turns off. discontinuity requirement and Ns  switching frequency define the values of the pri- Where: mary and secondary inductors. taking a maximum Np/Ns of 4 UC3909 come up and the charger begins charging gives a maximum switch voltage of about 320 volts. Peak Currents and Switching Frequency age that will be seen across the terminals of the The switching frequency was chosen to be 100 secondary inductor winding and the amount of kHz as a compromise between switching losses overshoot that will occur on the primary inductor and energy storage component size. These pulses will be clamped to a width that is less than the maximum pulse width Vspike is the leakage spike expected on switch until the voltage on CSS reaches 1.7V. From the following rela- Vps is the maximum power switch voltage tionships. the UCC3809 issues no output pulses Vls is the maximum voltage across the secon- until the voltage on the soft-start capacitor reaches dary inductor (15V + 1V for the diode) 0. V ps = Vdc + V ls   + V spike power requirements. 2 ter capacitor C1 (195V) 5 . Vbatt is the maximum battery voltage (use 15V to allow for temperature correction) POWER STAGE DESIGN Vdiode is the voltage across the rectifier diode (use 1V to be conservative) Notation Throughout this paper the following notation will be The input power to the inductor is the output plus used.

44A respectively.85 (7) LI (10) τon =  1 + ≤ B=   ( N p V batt + Vdiode )  Fs  NAe From the core data for the Philips EFD30 core: From this. From (4). Since an AL of 150nH is a standard value. I is the current in the inductor in Amperes. From (2). the peak primary inductor current be approximately reduced by the ratio of the un- is 4. this is what will be used. it is obvious tive area of the inductor core (m2) and B is the flux that (I couldn’t resist.85 (6) τon + τ rst ≤ Core Selection and Calculations Fs Inductance may be written as: Where: NΦ L= I Ip is the primary inductor peak current. If Np is Again. At I s Ls (5) 500A/cm2. The re- manent flux density in a 3C85 un-gapped core is RMS Inductor Currents about 160mT at room temperature.3A and less than 7. then Ns is 6. Np must be 23 or more turns.9 × 10 −5 m 2 (11) numbers are “ideal out of the math” and will change somewhat when the real world primary and If B is limited to 250mT (approaching roll-off in the secondary inductances are known. Ls is the secondary inductance. B-H curve). the EFD30 is about 2100 in 3C85 material. L is the inductance in Henries. Ls is then about gapped. τon is the on time. Φ is the total flux linked by the N turns in We- bers. From (3).15A. Therefore the The RMS value of a periodic triangular pulse is: remanent flux density in the gapped core will be: 6 . τon will be less than about 2.): density (Tesla):  Vdc N s  0. the peak secondary inductor gapped AL to the gapped AL. the primary inductor should be wound τ rst = V batt + Vdiode with #24 or equivalent and the secondary inductor with #15 or equivalent. after some manipulation of equations (1) set to 24. Note that these Ae = 69 mm 2 = 6.97µs and τrst will be less than about 6. τrst is the reset time. 0. N is the number of turns of wire in the inductor. Where: Is is the secondary inductor peak current.6A. Fs is the switching frequency Since Φ is also equal to AeB where Ae is the effec- After some algebraic manipulation. These cores are ordered specifying the gap in (τon Vdc ) terms of nH/Turn2 (the AL value).8µH.03µs. the remanent flux density in the core will 5.Unitrode Corporation Application Note U-166 Vdc (2) τ (9) I p = τon I RMS = I p Lp 3T Np (3) Where: Is =Ip Ns Ip is the peak value of the current τ is the width of the base of the pulse 2 (4) N p  Lp =   Ls T is the period of the waveform Ns  The RMS primary and secondary currents are then 1. Note that since the core is Lp is then about 93µH. and (2). Lp is the primary inductance. The un-gapped AL for current is 16. Obtaining an in- 2 (8) Fs Lp = ductance of 93µH from 24 turns requires an AL of 2 Pin 161nH.

the secondary inductor was rent through the opto-isolator is 0. the split primary does have lower leakage inductance and Windings places less stress on the power switch at turn-off.3A. the secon- AL un −gapped dary bootstrap voltage will be between 15. the secondary inductor winding and a the verge of saturation. rangements produce satisfactory results. three layers of UCC3809 FB pin with no current in the current kapton tape were used between the primary side sense resistor (RCS). Likewise. R1 must be chosen with some consideration to the N boot (13) opto-isolator. If the single plies the bootstrap power to the primary side of the layer primary is used. rates.1 and 15. command the minimum attainable pulse width. The 2 turn winding that sup- 400V Vds MOSFET a marginal choice.0 = 1. the tances) from bundles of discrete wires or from litz voltage at pin FB of the UCC3809 must be 1V and still fit the winding in the window of the EFD30 when the current is 5. the bootstrap voltage will be Bremgapped ≈ Bremun −gapped between 10. To limit the current in LP to 5. some resistor values on the primary side can The secondary side of the inductor shows two be adjusted to limit the primary current to a level on windings. = 160 mT = 11. This low . The secondary inductor cannot be wound from peak current (IP) in the primary must be less than (at least not easily and maintain creepage dis. to iso- Current Sensing and Feedback late the high voltage primary inductor winding from To be certain that the flyback inductor never satu- the low voltage bootstrap winding.Unitrode Corporation Application Note U-166 AL gapped (12) For the primary side.75 volts. a 500V Vds MOSFET would circuit can be of practically any small gauge wire be a better choice for the power switch. a voltage of 3. the single layer primary produced windings. that it will be ignored in this computation. RCS 53 = 1.4mT.5 and 150 23. If this level is picked to be bootstrap winding for the secondary side electron. as the secondary 3 . the ics. When the feedback cur- bobbin. as the current level is low. 3M #5413. the following wound from foil. about 5. 2 and 3 are con.007 inch thick condition must be satisfied: strip of copper foil was used. The inductor in the schematic shows 4 separate In the prototype. The secondary bootstrap winding was In addition. gives: nected so that they will supply current when the R3 (15) main power switch is on. 4 mT 2100 The prototype charger was built using two different inductors using different winding arrangements. In the prototype inductor this winding was wound with #30 wire simply be- cause it was readily available. to be certain that the secondary can wound on top of the secondary inductor. This gives a current R 2 + R1 (14) density of about 330A/cm2 in the winding. This The bootstrap windings in Figs.5 inch wide by 0. 0 value of current density was used to help offset R 3 + R 2 + R1 losses caused by the high number of layers in the winding. The value of RCS is so small and secondary side windings. 300mT (from Philips data for 3C85 material).5 volts. Since the saturation flux density of 3C85 material One inductor had the primary winding on one layer. The primary inductor winding is wound leakage spikes that were high enough to make a from #24 magnet wire.3A. Picking R1 to be 220Ω places the operating point of the opto- 7 . R2 must be 2k. The primary side PRIMARY SIDE COMPONENT VALUES windings were placed side by side against the bob- bin with a layer of kapton tape. 0 R3 + R 2 inductor will.0V across R1 should result in 1V at the To satisfy insulation requirements. is well above 250mT.3A. A 0. While both ar- only 11. This means that the voltage applied to the primary and secondary electronics will be equal to: If R3 is arbitrarily chosen as 1k. a flux swing of 250mT will not and the other sandwiched the secondary between saturate the core with a remanent flux density of a primary split between two layers. not off. Therefore. The H11A817A has a current transfer V boot = Vdc − Vdiode Np ratio of 80% to 160% and is fairly linear over a di- ode current range of 2mA to 30mA.

97µs and the total period. chosen more for its ripple current handling capabil- 8 .7V to 1.3V. When the charger is in the bulk charge state.3V bias point of the current sense amplifier.69 CT RT 2 (16) ences in the gain of the sense amplifier from one chip to the next and over temperature for any given Picking CT to be 1nF. The components RT1. RCS is then 0. RSF2. signal from the current sense resistor was filtered put. Larger values of fil- datasheet: tering resistors introduce larger potential differ- τon = 0. τoff will be 7.1W at maximum output current.2K. 2. the will be when a fault condition is present at the out. CSS is chosen so that its power dissipation is within ac- ceptable limits and the voltage presented to the charged by a 6µA current source. ity and low ESR more than its capacitance. be careful not to significantly on and minimum off times. To prevent satura- to increase from 0 to its maximum value. was Fig.15µs. dissipates about 1. the longer the minimum achievable pulse Another resistor. the bulk filter capacitor.Unitrode Corporation Application Note U-166 isolator into its linear range over most of the oper.7V. A 47nF tion. The block labeled the inevitable current spikes through LP from caus. This current must be at least 100µA at minimum the voltage error amplifier will be out of compliance line. The relevant circuit is shown in the UCC3809. RCS was chosen as 20mΩ and 0V to 0. Other Components Bulk Current Setting R4 provides the startup current for the UCC3809. Capacitor CZB serves sion network. 4. should be no more than 400mV. across the current sense resistor. The bulk supply capacitor for the UCC3809 must power dissipation was the determining factor for be able to supply energy to the primary side cir- cuitry while the SS pin makes the transition from selection of RCS. This will catch the leading current spike noise pulses but still allow adequate current ramp sensing at SETTING CURRENT AND VOLTAGE 100kHz.27Ω. The bulk current is set by the values of RG1 and RG2. On the other hand. gives a time constant of about 0.32K and RT2 is chip. When adding a filter like this to an amplifier that Timing and Soft-start has gain and biasing resistors already imple- The UCC3809 has fully programmable maximum mented in silicon. To get around this limitation. It was not implemented in the proto- this purpose in this application. the maximum voltage across CA– and CA+ value for CSS gives a soft start time of about 7.7V. RT1 is 4. Some caution must be The current sense amplifier in the UC3909 does used when picking the values for CZB and CCS.5ms. The small can lead to premature pulse termination and –3dB frequency of this filter was chosen to be erratic charger behavior. T is 10µs the off ratio matched to provide an accurate gain. biased to a level of 2. As the voltage goes from UC3909 is a differential amplifier with a fixed gain 0.03µs. of CZB.69 CT RT 1 and τoff = 0. C1. CCS. was added to preserve the width will be. The pacitors C2 and C3 are filter caps for the power dissipation in RCS is just over 450mW at full UCC3809’s power supply and reference. the output of fier to saturate. Since τon is at son for this is that the silicon resistors are closely most 2. The charge current sense resistor (RS) should be The softstart time is controlled by CSS. EMI/RFI suppression in Fig. the duty cycle of the output is allowed of 5. LEVELS FOR THE UC3909 also helps to attenuate the large leading current spikes caused by the forward peak rectifiers in the Charge Current Sense Resistor bootstrap power circuits.7V. the more lag time that there current waveform. RG is a load. the larger the value 20kHz to have minimal effect on the feedback loop. 10. As the SS pin on current sense amplifier does not cause the ampli- the UCC3809 goes from 0V to 0. but vary time. In this application. The low value resistor intended to prevent gate oscilla- UCC3809 needs a capacitor at its FB pin to keep tions in the power MOSFET. picking the values too with a simple R-C network (RSF1 and CSF). 2 is a typical suppres- ing early pulse termination. so a 1W resistor is recommended here. not have the bandwidth to handle a 100kHz flyback The larger the values. The rea- RT2 and CT determine these times. A value of 220pF type but is shown for completeness. From the UCC3809 significantly in absolute value. A value of 470K will give 240µA at minimum and its output (VAO) will be at its positive rail (or line input voltage and maximum startup voltage for nearly so) of 5V. Ca- ating range of the charger. The current sense amplifier in the the UCC3809 is inhibited. Also. change the nominal gain of the amplifier.

Unitrode Corporation Application Note U-166 RSF1 R 5R CHARGE CURRENT FLOW CURRENT RCZ CCP CSF SENSE AMP RG1 – CSO CURRENT RS + CA– ERROR AMP – CAO + RSF2 R 5R RG2 R=7kΩ VOLTAGE 2. see data sheet) is off.3V at the VA– pin. The desired bulk out of the RSET pin is then 108µA. the STATLV transistor (internal to 5R S the UC3909.0k. high impedance state.5k.02 Ω × 5 (19) GIC to CSO pins. RS3 and RS4.4µA. 0 A × 0. VAO. The transition between charging RG 2 RG1 modes takes place when: If RG2 is set to a value of 10. The float volt- age is the voltage across the battery that will pro- Recall that the trickle current was to be set to duce 2. The Float Voltage Level trickle control current is 5% of the current flowing The float voltage is the voltage that the UC3909 out of the RSET pin on the UC3909.0A.9mV/°C while the reference for the 9 .3V. and the trickle control cur- rent is directed to the CA– pin of the UC3909.0 A × 0.02 Ω = 80mV (17) Overcharge Taper Current The voltage at the output of the current sense am. 3 4. The average voltage the RSET pin is 2. ROCV1 is 1.47k. For the current error amp to be in compliance. goes into a since IOCT is 400mA. Therefore. The voltage on charging current was 4. then RG1 is 1. Bulk current setting. the trol current through RG1 is then 5.292V at the CSO pin.0V UDG-98077 Figure 4. 3 5IOCT R S (21) = ROVC1 ROVC 2 Trickle Current Setting When the UC3909 is in the trickle charge state.3V.47k Voltage error amplifier output. This current level will produce an average voltage thresholds. ITRICKLE = In the float state. The trickle con- justed by –3. OVC- Summing currents at the CA– pin: TAP is the tap of a voltage divider from the VLO- 5 − 2 . so the value of RSET for across RS is then: 80mA trickle charge current is 21. 5 − 2 . with ROVC1 and ROVC2 setting = the divider ratio.9V (18) overcharge to float charge takes place when the voltage on the OVCTAP pin rises above 2. The float voltage (as well as the overcharge rent will be: voltage and bulk charge threshold voltages) is de- ITRICKLECONTROL RG1 (20) termined by the resistors RS1. the If ROVC2 is picked to be 100K.3V ERROR AMP VAO 5. the trickle cur. The current voltage at pin CA– must be 2. Note that for all of the 80mA. 3 − 5V RS = 1. the reference voltage is ad- voltage of 2. V RS = 4 . The trickle will apply to the battery to maintain the battery’s control current can only flow through RG1 since charge level after the overcharge period has VAO is high impedance. The transition from VCSO = 2 .3V. ended. The overcharge taper current (IOCT) is the current plifier is then: level the UC3909 looks for to make its transition from overcharge to float charge. RS2.

3 18.3V. R S 1 + R S 2 + R S 3 ||R S 4 Component in this context refers to a piece of the (24) VCHGENB = 2 .8V. The resistance to ground at the collector of plied to the battery when the charger is in the over. which R S 2 + R S 3 ||R S 4 transforms a current into a voltage. Current control loop components. the optocoupler is about 205Ω. (22) V FLOAT = 2 . RS3 is 1. and VFLOAT to 13. Allowing 0. Since the sum of RS1 and RS2. 5 details the feedback path. the STATLV transistor is on. the STATLV transistor is emitter current in the optocoupler must be at least on. RS4 is found to be 115k.3V at 14.5V of headroom to help prevent saturation. the sum can be put through the LED of the optocoupler to of RS1 and RS2 is 49.Unitrode Corporation Application Note U-166 current thresholds is constant over temperature. If the optocoupler is at the low end of the the VA– pin.0 – 0.0k and VOC is 14.99k. so the value of VCHENB There are several “components” in the current con- is then: trol feedback path. RE is then 150Ω.4k.7V for the b–e voltage on Q4.3mA. The overcharge voltage cause the collector on the optocoupler output to go level (VOC) is the maximum voltage that will be ap. RS2 is 3. LS VDC LP BATTERY CHARGE CURRENT FLOW RSF1 R 5R RCZ CCP VCC 5V CURRENT CSF SENSE AMP Q1 RG1 CURRENT – CSO R2 R3 ERROR + CA– AMP CAO RS Q4 – 2N3904 RCS + R1 RSF2 R 5R RE RG2 1V OUT VOLTAGE 2. to 3V.3mA.7 – Knowing the sum of RS1 and RS2 is 49. and the values of The float voltage is then: RS3 and RS4.74k.8V (5. then the LED current must be at least VOC = 2 . the emitter voltage of Q4 will be 2.99k.0k. From this. VOC is then: current transfer ratio distribution (80%. 10 .0V UDG-98076 Figure 5. RS1 + RS 2 + RS 3 RS1 must be 46. and VOC is the voltage that produces 2. 3 RS 3 Optocoupler LED Current Limit RE must be small enough that sufficient current If RS3 is set to 10. The bulk charge state is entered when the UC3909 senses that the voltage on its CHGENB pin goes CURRENT CONTROL LOOP above 2. 10. for the R S 1 + R S 2 + R S 3 ||R S 4 (23) H11A817A).8) maximum at 18.5 = 2. This means that the charge state. such as a resistor.3V UCC3809 ERROR AMP VAO 5. In the trickle and bulk charge states. In this state. Fig. 3 overall transfer function.6mA. are known. R S 3 ||R S 4 and 1.8V.

RCS and the optocoupler. Since the emitter voltage and the emitter Np (30) resistor determine the emitter current and hence I LS PEAK = I LP PEAK the collector current. R2. These elements will be examined one by one to determine the overall loop characteristics. 6: output voltage. The current in the primary inductor is the The average output current is then: current that results in 1V at the junction of resistors I LS AVG = (32) R2 and R3. which converts the average 2T S output current into a voltage. The current error amplifier. The coupled inductor which. NP/NS times the peak current in the primary induc- 3. see Fig. Differentiating the above yields: I LP = − IC 1 • RCS R 2 R1 + R 2 + R 3 RCS R 2 2 (33) 1  N p  LS G3 =   I L PEAK A T  N s  V LS P A The gain of this stage is the derivative of ILP with respect to IC multiplied by the optocoupler gain or: 11 . For all prac- tical purposes. the gain of this stage is: Ns 1 1 (25) G1 = = A /V and R E 150 V LS (31) τ rst = I LS LS R1. The current sense amplifier. the collector current and the emitter Figure 6. Q4 and RE which converts VCAO into ILED in = −607 A / A the optocoupler. RCS and the Optocoupler The optocoupler may have a current gain up to 160%. R1. current are equal. along with the tor. converts ILP into an average current through RS. The secondary current waveform is triangular and has the average value. 6 are: R1 + R 2 + R 3 RCS R 2 1. RSF1 and CSF. Using the principle of superposition: ( ) 1 2 LS I LS PEAK  R3  (26)  IC • [R1 (R 2 + R 3)] • 2T V LS   R 2 + R3  2 1 N p  (I L PEAK ) 2 LS  R2  =   + I LP • RCS •  = 1. ILP. 0 2T  N s  P V LS  R 2 + R3  The gain of the stage is the derivative of the aver- This simplifies to: age secondary current with respect to the peak pri- R 2 + R3 R (R 2 + R 3 ) R 3 (27) mary current. RS. R2. 2. which amplifies the voltage across CSF. Secondary current waveform. The peak current in the secondary inductor is rent. which Coupled Inductor and Output Voltage convert ILED into a peak primary inductor cur. IPEAK VLS 6. R3. R3. τRST Q4 and RE T UDG-98076 Q4 is configured as an emitter follower. τ rst (29) I LS AVG = I L PEAK 4. 5. which provides gain LS and phase compensation for the feedback loop. and a one volt change in base voltage will produce a one volt change in emitter But since: voltage.Unitrode Corporation Application Note U-166 The individual components of the feedback path R1 (R 2 + R 3 ) R3 (28) G2 = − • • 1.

If 10 the battery voltage is 10. At stability in the loop and to roll the closed loop fre.44dB gain at crossover.5V and the Schottky volt. the voltage loop (made up of the re- 10kHz. with a single pole at 20kHz.05 or 0. The open loop response of the voltage loop is cel the pole in the current sense filter.Unitrode Corporation Application Note U-166 From this. The com. For the re- quency. To do this requires that the current error sistor divider string RS1 through RS4. a zero will be inserted in the the current loop. Although error amp and RVG is an outer control loop around not strictly necessary. The voltage control loop is shown in Fig. the voltage control loop is open. the capacitor value VCSO = 2 . 8. This differ. current error amplifier response at 20 kHz to can. GCOL age is 0. the ILP that produces an average ILS of 0 4. loop closes or comes into compliance.44dB.44dB at 10kHz. RS (34) G4 = 1 + sR SF 1C SF 1 + sRCZ CCP (36) 0. The phase lag through the power stage is small in the frequency range of in- The gain of this stage is the derivative of VCSO with terest and the origin pole of the current error ampli- respect to VRCS.02 G (s ) = = GCEA = V sRG1CCP 1 + 7.5 × 10 −6 s A The R in this integrator has already been deter- Current Sense Amplifier mined to be 1. turns ratio and secondary inductance are constant. Current loop gain.0A is 3. VOLTAGE CONTROL LOOP Current Loop Compensation Fig. 40 entiation yields the gain of the coupled inductor be. the voltage amplifier have –0. fier contributes only 90° to the loop. it is seen that the gain depends upon what the load voltage and current are. To roll the closed loop response off at mainder of the overcharge state and the float 10kHz. In other words: 12 .08A.5V. GCEA GTC cause from a small signal standpoint.47k (RG1). GCOL in this case is 1. 3 − 5VCSF (35) must be around 10nF. some point during the overcharge state the voltage quency response off at 1/10th of the switching fre.6 A/A. This leaves the capacitor The output of the current sense amplifier is: to set the low frequency gain characteristic. For the gain to be –0. GAIN dB The maximum value of the gain is the only value of 20 interest since this will be the point at which the phase margin will be the lowest (in this circuit). ture of this circuit is such that in the trickle and bulk pensation goal here is to provide unconditional charge states. The transfer equal to the closed loop current loop response function of the current error amplifier is: multiplied by the output impedance and the gain of the elements of the voltage loop. This is the point where the current gain is the highest. the open loop crossover frequency must be charge state. This means that The open loop gain of the current loop (without the the loop is unconditionally stable with near 90° of current error amplifier) is the product of all of the G phase margin. switching frequency. the battery 30 voltage (and hence VLS). The gain G5. -10 10 100 1K 10K 100K Current Sense Resistor and Filter FREQUENCY The transfer function of the sense resistor and filter network is: Figure 7. is –5 V/V. at 2. The phase lag of the current sense filter is offset by the zero in the Total Current Loop Gain current error amplifier response. 7 shows the uncompensated and compen. terms described above. The na- sated current loop gain characteristics.

of GVOL at whatever the crossover frequency turns out to be.3V ERROR 1V OUT AMP + VAO UCC3809 RS3 – RS1 RS2 RVG UDG-98072 Figure 8. Ac- Where: cording to the battery manufacturer. charge state. To insure GCCL is the closed loop current transfer func. that the voltage loop will remain stable.Unitrode Corporation Application Note U-166 LS + CO VDC CBAT RBAT LP RESRBAT RESRCAP VCC CCP 5V RCZ CURRENT RSF1 R 5R SENSE AMP CURRENT Q4 ERROR 2N3904 Q1 RG1 CSF + CA– AMP CAO + R2 R3 RS – – RSF2 R R1 RCS RG2 + 5R VOLTAGE RE 2. The frequency of this pole is assumed to be looked at from the VA. it was as- tion sumed that the equivalent load of the battery. × 10 5 ≈ s + 7143 . RS1 + RS 2 + RS 3 change in current sense amplifier output) is given by: The open loop voltage transfer function for this ap- GCCL = (38) plication is then:  1   GCEA G 5 G 4 G 3 G 2 G1  1. Voltage control loop. 743 × 10 4 (40)    GVOL = Z L GVEA  G 4G 5   GCEA G 5 G 4 G 3 G 2 G1 + 1  7143 . × 10 + s 4 7143 . filter ZL is the load impedance capacitor and anything else that may be connected to the charger has an extremely low frequency GDIV is the gain of the battery voltage divider pole. RS 3 (39) sponse (change in output current for a given G DIV = = 0166 . The RG1/RG2 term is simply the summing ratio of the current sense amplifier output and the voltage The divider gain (GDIV). age loop. RG1 (37) The load impedance is difficult to characterize and GVOL = GCCL Z L G DIV GVEA RG 2 is greatly dependent upon the battery being used. is equal to: error amplifier output. The closed loop current re. The battery is a complex device to model and will exhibit parametric shifts depending upon variables like much less than the crossover frequency of the volt- GVEA is the transfer function of the voltage er. × 10 4 13 . RESRBAT. age and history. This will contribute 90° to the phase lag ror amplifier. GVOL is the open loop voltage transfer function CBATT and RBATT vary considerably depending upon what the condition of the battery is.

Higher power IOPTO This paper presents a general scheme for control. CCS.2kHz. While it is not known what the exact imped. Figure 9. 1kW and beyond.2kHz. R2. at least 3750VRMS of isolation and 8mm of creep. the phase shift of for current sensing along with an additional ampli- this circuit is 45° at the current control loop cross. it may be advantageous to use a small value shunt 14 . The minimum pulse width arises from the 5600µF with an ESR of less than 13mΩ. When OTHER ISSUES minimum pulse width is being commanded by the UC3909. switching frequencies without the aid of an input back in order to avoid the additional phase shift averaging filter.5° at changed to a forward buck type. If it is possible that the load (battery in this case) gin. The filter capacitor in the charger is and CZB.2kHz to maintain good phase mar. that it takes to charge CZB to 1V.Unitrode Corporation Application Note U-166 Ignoring the ZL and GVEA terms. The voltage error amplifier was chosen to amplifier in the UC3909 will be useful at higher be a straight gain amplifier with no complex feed.2kHz. the loop. a core with a larger winding window will have to be used since this design fills the window of the EFD30 almost OPTO completely. 9. at less than 3. that comes with introducing more poles into the system. Testing on the prototype charger voltage at FB on the UCC3809 reaches 1V (or showed no signs of instability in the voltage control when the oscillator again starts its down ramp). The gain of the amplifier was Since the output pulse will only terminate when the set at 36dB. the output voltage will run away. fact that the UCC3809 discharges CZB through an sults in a total ZL of 8mΩ to 15mΩ. Power quency below 3. This re. The only source available is the current through the age from the primary to the secondary. R2 VFB R3 ling a primary side PWM from an isolated UC3909. the current sense 3. minimum pulse width is determined by the time ance on the battery is. The gain of the internal FET when the oscillator starts its down voltage error amplifier must be less than 49dB in ramp. The reason for this is that even though the UC3909 Conversations with the battery manufacturer sug- would be commanding zero pulse width. With the phase shift of the load taken to be Disconnection of Load and Minimum Output 90°. Minimum pulse width determination. However. At 3. This is ade. R1 CZB 200W. there is no reason that a higher performance single output PWM or dual output PWM could not be used with suitable design adaptations. it is assumed that the voltage across the Line Isolation current sense resistor will not have a significant im- The transformer design presented here will provide pact on the time necessary to charge CZB to 1V. A means of controlling output GVOL f =3200 = Z L GVEA f =3200 − 12 . sulted in a robust and stable charger. At much higher current levels. the opto-isolator multiplied by the equivalent resis- Check with the regulatory standards for the type of tance seen at the emitter of the opto-isolator. 6 dB (41) voltage must be supplied if this is the case. If more isolation is required. the gested that charging impedance could range from UCC3809 will give a minimum pulse width based 250mΩ to 10mΩ (almost strictly capacitive) at upon the values of components RCS. opto-isolator. 500W. for higher power requirements. R3. product being built to find out if this isolation level is adequate. the open loop gain of the voltage could be disconnected from the charger while the control loop is: charger is powered from the ac mains. the above approach re. The internal FET is turned off when the oscil- order to insure that the control loop will crossover lator starts its up ramp and sends an output pulse. V1 The particular PWM used here is a single output device. A means of getting a handle on the minimum pulse width can be seen by referring to Fig. If the topology is over frequency (10kHz).2kHz. and about 22. 3. The voltage V1 is the current out of quate for some applications. the voltage loop should have a crossover fre. but not for others. fier to boost the signal level.

It will al- gorithm with the UC3909 Switchmode Lead-Acid most certainly be necessary to use the STAT0 and Battery Charger Controller. pp. here though. Control Loop Cookbook. Alternatively. Application Note. the load will add a pole into [7] Philips Components. STAT1 pins to switch the resistor into the circuit Unitrode Applications Handbook. NH 03054 TEL. Soft Ferrites Data Handbook the current control loop. be able to handle the bulk charging current of the Unitrode Power Supply Design Seminar Book. especially in the voltage width is approximately: control loop.3-88. The charger current sense loop will adjust the out- put to a point that will supply the battery with the [4] Bob Mammano.3-234. 1997. U-155 Application Note. the dummy load would be applied to the bat- [2] John A. Second. • MERRIMACK. FRM-11-003 load will draw. Third. load. Simple Switchmode Lead-Acid tery and discharge it when the charger is not Battery Charger. Connection of Loads That Bypass the Current [3] Unitrode Corporation. Guide to Battery Management. a dummy load resistor could be placed across the charger output that would dissi. U-131 Application Note. Portable Power . battery as well as the maximum current that the [6] Eagle-Picher HE12V12. The STAT0 and STAT1 pins could even be decoded to switch the diode into the circuit only when the control loop will not be active if a fault occurs at the charger goes into float mode. 1997. As a means of controlling the output voltage. the minimum pulse design of the feedback. Topic 2. a 5W 15V zener diode at the output would work nicely. This last solu- tion will affect the feedback loops somewhat. and probably most importantly. Improved Methods for Charg- Sense Resistor ing Lead-Acid Batteries Using the UC3906. Other. The particular battery used CHARGER LOAD here was an adequate load to dissipate this power. pp. at the expense of noise immunity or by increasing the ratio of R3 to R2. First. O’Connor. low threshold diode to start conducting and over- heat. wise. the inherent current limiting effect of the current  R + R 3  C ZB R 2 R 3 (42) τon = –ln  1 − 2   V1 • R 3  R 2 + R 3 This application circuit was not designed to operate with a disconnected load. Unitrode Corporation Application Note U-166 When this voltage is known. SEM-1100. Figure 10. Implementing Multi-State Charge Al- temperature compensated float voltage. Applications Handbook. 3-516. (603) 424-2410 • FAX (603) 424-3460 15 . There are some caveats Unitrode Power Supply Design Seminar Book. This would guaran. Some other means of over-current protection tee that the over charge voltage would not cause a must be supplied. 3-78 .7 data-sheet.A Designer’s selected charging current. which can complicate the MA01. U-104 This technique can be useful if properly applied. RS Minimum pulse width can be reduced by using a smaller CZB. 3-226 . Unitrode powered from the line. regardless of what cur. Alternate external load connection. 1997. 3-488 - only when the UC3909 is in the float mode. 1996 UNITRODE CORPORATION 7 CONTINENTAL BLVD. rent the load requires. SEM-1000. pp. Enough load must be ap- plied to dissipate the minimum power output that BATTERY CO the circuit will supply at the highest input line volt- EXTERNAL age (a DC rail of 195V). Unitrode Applications Handbook. the charger power stage must [5] Lloyd Dixon. REFERENCES pate the minimum output power at the minimum [1] Laszlo Balogh.

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