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4/29/2019 Is hold always checked on the same edge?

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Design Problem :
Is hold always checked on the same edge?
Convert A Multiplexer V
To Priority Mux (Logic One of the guys asked me a question, "Why is hold always checked on the same edge?" Normally, it is
Restructuring For A taught in books/colleges that hold is frequency independent because it is checked on same edge. But,
Multiplexer For Timing is it really true? It is true only for some of the many cases. Hold can be checked on the same edge,
You and 1 o
Critical Paths) next edge or previous edge depending upon the scenario. In this post, we will discuss those cases one
by one, and try to generalize if this statement holds true.
Priority Multiplexer
How to determine the edge on which hold check needs to be checked: For most of us, it seems
Design Problem: quite confusing to arrive at the conclusion of how to determine the hold edge. Let us try to use a state
Design A Circuit That
machine perspective here. In state machine theory, we study that synchronous digital circuits can be
Delays The Positive
considered as state machines moving from one state to another. This state transition happens on each
Edge Of A Signal By
clock edge as shown in figure 1 below.
One Cycle

Design Problem: How In digital circuits, we can say that each clock edge (either positive or negative) corresponds to an
Do You Detect If Two independent state.
8-Bit Numbers/Signals Figure 1: Each clock edge corresponds to a design state
Are Equal

Single-Bit Magnitude If we look at each flip-flop, every positive edge-triggered flip-flop changes its state at positive clock
Comparator edge and all negative edge-triggered flip-flops transition state at negative clock edge. Similarly, all
negative edge-triggered flip-flops transition state at negative clock edge as shown in figure 2 below.
STA Query : How
Positive Edge Trigger
Reg To Positive Latch
Path Is Zero Cycle.
But Positive Latch To
Rising Flop Is Full
Cycle?

Figure 2: State transition for positive edge-triggered and negative edge-triggered flip-flops
Design Problem:
Logic Minimization
And Restructuring For Or, we can represent the states of positive edge-triggered and negative edge-triggered flops as
Timing Critical Paths
separate as shown in figure 3 below.

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Would you l
Clock gating others by co
cell write to myb
Figure 3: States of positive and negative edge-triggered flops represented symbolically

Minimum pulse Contributors


width
Let us have a scenario of a timing path from a positive edge-triggered flop to a positive edge-triggered Unknow
flop. In the figure 4 below, flip-flop "2" transitions to state (K+1) depending upon the value of flip-flop
VLSI U
Measure time "1" at state (K).
using candle!!
Popular pos
Setup checks
and hold checks
for latch-to-reg
timing paths
Figure 4: A sample timing path from positive edge-triggered flip-flop to positive edge-triggered flip-flop

16x1 mux using form of win


4x1 muxes Here, the data launched from ff1 should help ff2 transition to state "K+1", meaning, it should be Latchup an
captured at the corresponding clock edge. This represents setup check. Also, it should not disturb

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4/29/2019 Is hold always checked on the same edge?
state "K" of ff2, meaning it should not get captured at this edge. This represents hold check. So, in this
Why is body case hold check is on the same edge as the present state of start and end flops is the same edge.
connected to
ground for all
nmos and not to
VDD
Also read
Synchronizers

Metal ECO - the


process
Figure 5: Setup and hold checks for positive-to-positive edge-triggered timing paths
borrowing, owi
Digital Counters
Now, let us take a look on the scenario where-in hold check is not on the same edge. Let us take a
timing path launching data from negative edge and capturing at positive edge. This scenario is shown
All about clock
in figure 6 below.
signals

Setup check
and hold check
for register-to-
latch timing
paths Figure 6: Timing path from negative-to-positive edge-triggered flop

2X1 MUX
How
Here, positive edge-triggered flip-flop transitions states on positive edge and negative edge-triggered USING
propagation of NAND
‘X’ happens flop transitions on negative edges. So, the data launched from negative edge-triggered flop GATES
through corresponding to state "X" should get captured on positive edge-triggered flop on state "Y+1", which
different logic corresponds to setup check. And it should not get captured on state "Y", which corresponds to hold
gates check.

Can a net have


negative
propagation
delay?

Temperature
inversion – hard to meet in
concept and They can be…

phenomenon Thus, we have looked upon different cases of hold capturing edge being same or different than the
launch edge. For all the possible cases of setup and hold checks, you can follow below posts:

Can hold check


be frequency
dependant? Setup and hold checks
Setup checks and hold checks for register to register timing paths
C function that Setup checks and hold checks for register-to-latch timing paths
converts Setup checks and hold checks for latch-to-reg timing paths
hexadecimal
Can hold check be frequency dependant
value to decimal
value.

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XOR/XNOR gate Labels: STA, Static timing analysis, Zero cycle hold check
using 2:1 MUX

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MUX
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4/29/2019 Is hold always checked on the same edge?

Measure time
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timing paths

16x1 mux using


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Why is body
connected to
ground for all
nmos and not to
VDD

Airtable Project Setup checks and hold Human Resource What makes timing
Planning checks for reg-to-reg Management, Text &... paths both setup
paths critical and hold critical

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How to fix min pulse Clock gating checks Can hold check be Interesting problem –
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