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org

Published in IET Power Electronics

Received on 24th May 2013

Revised on 31st July 2013

Accepted on 27th August 2013

doi: 10.1049/iet-pel.2013.0410

ISSN 1755-4535

islanded microgrid inverters

Quanwei Liu, Yong Tao, Xunhao Liu, Yan Deng, Xiangning He

College of Electrical Engineering, Zhejiang University, Hangzhou 310027, People’s Republic of China

E-mail: dengyan@zju.edu.cn

Abstract: Voltage source inverters (VSIs) are usually used for all kinds of distributed generation interfaces in a microgrid. It is the

microgrid’s superiority to power the local loads continuously when the utility fails. When in islanded mode, the voltage and

frequency of the microgrid are determined by the VSIs; therefore the power quality can be deteriorated under unbalanced and

non-linear loads. A voltage unbalance and harmonics compensation strategy for the VSIs in islanded microgrid is proposed in

this study. This method is implemented in a single synchronous reference frame (SRF) and is responsible for both the voltage

unbalance and harmonic compensation. Furthermore, the virtual impedance loop is modiﬁed to improve the compensation

effect. The impedance model of the VSI is built to explain the compensation ability of the proposed strategy. The whole

control system mainly includes power droop controllers, a modiﬁed virtual impedance loop and inner SRF-based voltage

unbalance and harmonics compensators. The proposed strategy is demonstrated in detail and validated with simulations and

experiments.

1 Introduction at ﬁrst [11]. Then the DC–AC VSIs are utilised as the

interfaces to connect the prime movers to the local AC bus

The concept of microgrid is an effective way to integrate all of the microgrid. The main function of the VSIs is the

kinds of distributed generators (DGs) as a utility-friendly power transfer and control. Besides, the voltage unbalance

customer [1, 2]. A typical AC microgrid usually consists of and harmonics compensation ability can be achieved by

DGs like wind generation, photovoltaic (PV) generation, proper control of the VSIs when the output is of

fuel cell generation, energy storage systems (ESS) like voltage-source type [3, 12].

batteries, super capacitors, ﬂy wheels, local loads like Some works have been done on voltage unbalance

lighting, air-conditioners and computers. Most of the DGs compensation through controlling of the VSIs [7, 13–16].

and ESS are in DC form or have middle DC bus, thus Negative-sequence current is injected into the microgrid

voltage source inverters (VSIs) are usually adopted as the using the surplus capacity of the inverters to balance the

interfaces to the AC bus [3–5]. voltage of the microgrid in [13], in which only

There might be a large number of unbalanced and unbalanced voltage is solved and the injecting current

non-linear loads in the three-phase microgrid, such as might be too large under severe conditions. Extra series

single-phase loads, rectiﬁer loads and so on [6]. inverter is used for power quality compensator in [7, 14],

Unfortunately, power quality of the islanded microgrid can which is uneconomic for the microgrid situation. In [15,

be deteriorated under unbalanced and non-linear loads since 16], a compensation method in stationary reference frame

it lacks the voltage and frequency support from the utility is discussed, in which the unbalanced voltage is

[7]. Unbalanced and harmonic-distorted voltage can cause compensated with a resonant voltage controller inside the

severe problems on equipment such as vibration, power droop loop and the virtual impedance loop.

over-voltage, over-heat and so on. However, the unbalanced voltage drop across the virtual

Active power ﬁlters (APFs) are commonly utilised to impedance is not considered, which ﬁnally leads to

ensure power quality in the utility [8, 9]. Series APFs are unbalance of the output voltage and the compensation

usually utilised to compensate the voltage unbalance and effect weakened.

harmonics by injecting negative-sequence and harmonic To solve the problem and accomplish the voltage

voltage to the distribution line through coupling harmonics compensation simultaneously, a proportional-

transformers [10]. However, for the microgrid situation, it is integral (PI) plus multi-resonant voltage controller based

uneconomic to install extra APFs for each of the DGs. The compensation strategy in a single fundamental

DGs include prime movers and conversion interfaces. The positive-sequence (FPS) synchronous reference frame (SRF)

output of the prime movers is DC form (such as PVs, fuel is proposed, and the virtual impedance loop is modiﬁed to

cells, batteries, etc.) or AC form (such as wind generators, reduce the impact of the unbalanced and harmonics voltage

micro-turbine generators) but usually converted to DC form drop. The impedance models of the VSIs under different

doi: 10.1049/iet-pel.2013.0410 & The Institution of Engineering and Technology 2014

www.ietdl.org

control strategies are built to explain the compensation ability 2.1 Power droop control

of the proposed strategy.

This paper is organised as follows: Control strategy of the Supposing a VSI that is connected to the grid through the

VSIs in microgrid is introduced in Section 2. The proposed impedance Zejθ, then the active power and reactive power

control strategy for voltage unbalance and harmonics injected into the grid are given in (1) and (2) [21]

compensation as well as the impedance models of the VSIs

are discussed in detail in Section 3. The modiﬁed virtual U EU

P= (E cos d − U ) cos u + sin d sin u (1)

impedance loop is demonstrated to improve the Z Z

compensation effect in Section 4. Simulation and U EU

experimental validation is given in Section 5. At last, the Q= (E cos d − U ) sin u − sin d cos u (2)

paper is concluded in Section 6. Z Z

where E is the voltage of the VSI and U is the voltage of the

grid, δ represents the voltage phase angle difference between

2 Control strategy of VSIs in microgrid E and U, Z and θ are the amplitude and phase of the

impedance, respectively. On most occasions, the line

A typical AC microgrid with DGs and loads is given in impedance of the grid is mainly inductive, which means

Fig. 1a. VSIs are usually used as the DGs interface to u ≃ p/2 and Z ≃ X . In practical applications, the voltage

connect with the local AC bus, and the schematic of a VSI phase angle difference δ is designed very small to ensure

is illustrated in Fig. 1b. To achieve active power and the system stability, and thus (1) and (2) can be simpliﬁed

reactive power sharing capability between DGs without into (3) and (4)

high speed communication, power droop control is

commonly adopted as illustrated in Fig. 1c. The whole EU

control strategy mainly consists of P−ω and Q−V droop P= d (3)

X

control loop, virtual impedance loop, inner voltage and

current loops [17–20]. In Fig. 1c, the power droop control U (E − U )

Q= (4)

loop produces the reference u∗sdq for the inner voltage loop, X

and the inner voltage closed-loop transfer function

is Gudq(s). The virtual impedance loop is implemented by As a result, it can be concluded that the active power of the

subtracting the virtual impedance voltage drop from u∗sdq , VSI that injected into the grid is mainly proportional to the

while the current loop lies inside the voltage loop which is voltage phase angle difference δ, whereas the reactive

not shown in the ﬁgure. Detailed description of inner power is mainly proportional to the voltage amplitude

voltage and current loops are given in Section 2.2. difference E − U. Therefore, the typical active and reactive

power droop control strategies expressed in (5) and (6) can

be applied to the VSI for power regulation

v = v0 − kp · DP (5)

E = E0 − kq · DQ (6)

amplitude, kp/kq is the active power/reactive power droop

coefﬁcient and ΔP/ΔQ is the feedback active power/reactive

power error between output power and power reference,

respectively. There are many improved power droop control

strategies over the basic P−ω and Q−V droop control [3].

However, they are not discussed in this paper since the

focus of this paper is on the inner control loops inside the

power droop control loop.

VSI

variables given in stationary reference frame. The following

list gives the variables vectors in both the stationary

reference frame ‘abc’ and the fundamental positive

synchronous reference frame ‘dq’.

bipolar transistor bridge

iLabc, iLdq: ﬁltering inductors’ current

usabc, usdq: AC bus voltage

Fig. 1 Schematic and control of DGs interface in an AC microgrid ioabc, iodq: output current of the VSI

a Typical AC microgrid structure with DGs and loads

b Schematic of a VSI as the DG interface Traditionally, the inner voltage and current loops are

c Power droop control loop of DGs interface implemented with PI controllers. The model of the VSI, the

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0410

www.ietdl.org

loop

a Control diagram

b Equivalent model of the VSI

Fig. 2 Voltage and current control loops

a VSI model

Gus (s) · Gi (s) · (1/sC)

b Voltage and current controllers Gu (s) = (9)

c Voltage and current loop controlled model of the VSI 1 + Gus (s) · Gi (s) · (1/sC)

(1/sC)

voltage and current control loops in SRF are presented in Zo (s) = (10)

Figs. 2a and b, where u∗sdq , i∗Ldq and ddq are the voltage 1 + Gus (s) · Gi (s) · (1/sC)

reference from the power droop loop, the current reference

from the voltage loop and the duty ratio of the PWM

modulator from the current loop, respectively. 2.3 Virtual impedance loop

The closed-loop transfer function of the current loop and

voltage loop in Fig. 2 can be derived as presented in (7) Virtual output impedance is realised by adding an extra

and (8) control loop to the inner voltage loop, thus it is lossless and

costless. Furthermore, the virtual impedance value can be in

any desired form by changing the extra control loop [22,

iLdq (s) GiL (s) · 1/(sL + rL ) 23]. Therefore, virtual output impedance is an excellent

Gi (s) = = (7)

i∗Ldq (s) 1 + GiL (s) · 1/(sL + rL ) choice for VSI-based DG interface. The resistive–inductive

virtual impedance in SRF is expressed in (11). The voltage

Gus (s) · Gi (s) · (1/sC) and current loop integrated with the virtual impedance loop

usdq (s) = · u∗ (s) is given in Fig. 3a.

1 + Gus (s) · Gi (s) · (1/sC) sdq

(1/sC) sLv + rv −vLv

− · i (s) (8) Zvdq (s) = (11)

1 + Gus (s) · Gi (s) · (1/sC) odq vLv sLv + rv

controllers are used. Therefore, the voltage and current loop The voltage loop reference is modiﬁed by the virtual

of the VSI can be modelled as a controlled voltage source impedance loop. Then the output voltage of the VSI can be

Table 1 Converted results from ‘abc’ coordination to the fundamental positive SRF

1st 1st 5th 7th 11th 13th 17th …

in positive f0 SRF 0 2f0 6f0 6f0 12f0 12f0 18f0 ···

doi: 10.1049/iet-pel.2013.0410 & The Institution of Engineering and Technology 2014

www.ietdl.org

calculated as given in (12)

usdq (s) = Gu (s) · u∗sdq (s) − Gu (s) · Zvdq (s) + Zodq (s)

· iodq (s) (12)

function and the output impedance without virtual

impedance loop as given in (9) and (10). Deﬁne

when the virtual impedance loop exists. Additionally, the

dynamic performance of the virtual output impedance is

limited by the voltage loop. Consequently, the VSI can be

re-modelled as shown in Fig. 3b.

A comparison can be made between the equivalent models

of the VSI in Figs. 3b and 2c to observe the effect of the

virtual output impedance loop. As seen, the equivalent

controlled voltage sources are the same while the output

impedance can be shaped by the virtual impedance loop.

unbalance and harmonic compensation

In low-voltage three-phase microgrid applications, three-wire

AC bus is widely used in VSIs, rectiﬁers, induction motors,

and so on. The unbalanced voltage of VSI caused by

unbalanced loads includes the FPS, negative-sequence and

zero-sequence components. However, in a three-phase

three-wire system, the zero-sequence voltage does not

produce zero-sequence current, and thus it is not under

consideration. Typical voltage harmonics of the VSI are the

5th, 7th, 11th, and so on, which are caused by non-linear

loads such as diode bridge rectiﬁer.

The FPS voltage is converted to ‘DC’ under the

fundamental positive SRF. The fundamental

negative-sequence voltage is 2f0 ( f0 is the fundamental

frequency) ‘AC’ component under the same SRF. The

typical voltage harmonics such as the 5th, 7th, 11th and so

on are still ‘AC’ components under the fundamental

positive SRF. The detailed transformed results of each

components from ‘abc’ coordination to the fundamental

positive SRF are given in Table 1, where ‘ + ’ and

‘ − ’ means positive-sequence and negative-sequence,

respectively.

To simplify the closed-loop control and compensation

calculation, it is desired to implement all the compensation

loops under the same SRF. Conventional PI controller

in FPS SRF can only provide zero-error tracking capability

Fig. 5 Bode plots of the closed-loop voltage gain and the output

impedance of the VSI

a Closed-loop voltage gain Gu(s) with PI controller when loaded with pure R

(solid line), PI controller Gus(s) (dotted line)

b Closed-loop voltage gain with PI plus multi-resonant controller Gur(s)

(solid line), PI plus multi-resonant controller GPIR(s) (dotted line)

c The output impedance under PI controller without the virtual impedance

loop Zo(s) (solid line), the output impedance under PI controller with the

virtual impedance loop ZD(s) (dashed line) and the output impedance under

PI plus multi-resonant controller with the virtual impedance loop ZDr(s)

Fig. 4 PI plus multi-resonant controller (dotted line)

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0410

www.ietdl.org

on 0 Hz components and thus can be utilised to regulate the closed-loop voltage gain with rated load. The voltage loop

‘DC’ component. However, to achieve the zero-error PI controller’s parameters kvp and kvi are selected to ensure

tracking capability on the 2f0, 6f0 and 12f0 ‘AC’ high bandwidth and stability. The same rule is adopted to

components, resonant controllers on these frequencies could decide the current loop PI controller’s parameters kip and

be employed simultaneously. kii. The multi-resonant controllers’ parameters k2, k6 and k12

Based on the above analysis, to compensate for the are chosen to obtain high open-loop gain of the voltage

unbalanced and distorted output voltage of the VSI, the PI loop at the concerned harmonic frequencies, whereas ωc2,

plus multi-resonant controller shown in Fig. 4 is adopted. ωc6 and ωc12 are chosen to ensure a damping ratio of 0.01

The utilised PIR controller is given in (14). Consequently, at each resonant frequency [24]. Power droop coefﬁcients kp

the closed-loop voltage transfer function is modiﬁed as given and kq are determined by the ratio of the maximum

in (15) allowable frequency/voltage deviation and the active/

reactive power.

kvi k2 s As seen in Fig. 5a, the closed-loop voltage gain of the VSI

GPIR (s) = kvp + + 2 with PI controller when loaded with R is 0 dB at 0 Hz.

s s2 + 2vc2 s + 2v0

However, it begins to decrease as the frequency increases to

k6 s about 50 Hz since the PI controller can only provide

+ 2 + · · · (14)

s2 + 2vc6 s + 6v0 zero-error tracking capability for the ‘DC’ component. The

total output impedance ZD(s) of the VSI under PI controller

plus virtual impedance loop is given in Fig. 5c. As

usdq (s) = Gur (s) · u∗sdq (s) observed, the total output impedance ZD(s) is too large

(about 40 dB) under the considered frequencies such as 2f0,

− Gur (s) · Zvdq (s) + Zordq (s) · iodq (s) (15) 6f0, 12f0, and so on. Large output impedance leads to large

harmonic voltage drop under current harmonics, hence the

output voltage is distorted.

where Gur(s) and Zordq(s) are the closed-loop voltage transfer The proposed control strategy with PI plus multi-resonant

function and the output impedance without virtual impedance controller is applied, hoping to reduce the output impedance

loop as given in (16) and (17), respectively of the VSI under the considered frequencies. Bode plots of

the closed-loop voltage gain and the proposed controller is

GPIR (s) · Gi (s) · (1/sC) given in Fig. 5b. It can be seen that the closed-loop voltage

Gur (s) = (16)

1 + GPIR (s) · Gi (s) · (1/sC) gain is 0 dB at 0 Hz owing to the PI controller.

Simultaneously, the gain at the considered frequencies such

(1/sC) as 2f0, 6f0 and 12f0 is also brought up to 0 dB by the

Zordq (s) = (17)

1 + GPIR (s) · Gi (s) · (1/sC) multi-resonant controllers, which means the voltage loop

obtains the zero-error tracking capability not only at the

Deﬁne fundamental frequency but also at the typical voltage

harmonic frequencies.

ZDr (s) = Gur (s) · Zvdq (s) + Zordq (s) (18) The total output impedance ZD(s) or ZDr(s) of the VSI

under the conventional PI controller and the proposed PI

To demonstrate the different performance of the conventional plus multi-resonant controller is shown in Fig. 5c. ZDr(s) is

PI controller-based voltage loop and the proposed PI plus greatly reduced compared with ZD(s) owing to proposed

multi-resonant controller-based voltage loop, bode plots of control strategy, hence lower output voltage distortion can

the closed-loop voltage gain and the output impedance are be expected under unbalanced and non-linear loads.

illustrated in Fig. 5 with the circuit components parameters Unfortunately, although 0 dB closed-loop voltage gain is

and controller parameters given in Tables 2 and 3, where obtained under the proposed control strategy, unbalance and

Vdc is the DC side voltage, L, rL and C is the inverter harmonic voltage drop can exist across the total output

output ﬁlter, Lv and rv is the virtual output impedance, impedance caused by unbalance and harmonic current,

U0 and ω0 are the rated output voltage amplitude and especially when the output current is directly fed back to

frequency, fs and P0 are the switching frequency and the the virtual impedance loop.

rated power of the inverter.

Bode plots are utilised to determine the inner voltage and 4 Modified virtual impedance loop

current loops’ control parameters given in Table 3. As seen

in Fig. 5a, the dotted line is the bode plot of the voltage PI To reduce the harmonic voltage drop across the total output

controller whereas the solid line is the bode plot of the impedance, a low-pass ﬁlter (LPF) is inserted into the

Vdc, V L, mH rL, Ω C, μF Lv, mH Rv, Ω U0, V ω0, rad/s fs, Hz P0, W

kp kq kip kii kvp kvi k2 k6 k12 ωc2 ωc6 ωc12

doi: 10.1049/iet-pel.2013.0410 & The Institution of Engineering and Technology 2014

www.ietdl.org

To observe how the LPF virtual impedance loop affects the

total output impedance of the VSI, bode plots of ZDr(s) and

ZDf(s) are illustrated in Fig. 6b with the parameters given in

Tables 2 and 3. The impedance values of Zv(s), Zo(s), ZD(s),

ZDr(s) and ZDf(s) under the considered frequencies are

output impedance loop and the total output impedance

a Voltage control plus LPF virtual impedance loop

b The output impedance under PI plus multi-resonant controller with the

regular virtual impedance loop ZDr(s) (dotted line), with the LPF virtual

impedance loop ZDf(s) (solid line)

iodq as shown in Fig. 6a.

The LPF(s) in Fig. 6a is given in (19). The cutoff frequency

of the LPF should be designed lower than the considered

voltage harmonic frequencies to ﬁlter out the harmonic

current in iodq, and it should also be not too low to worsen

the dynamic performance of the virtual impedance loop,

where ωf = 2π × 10 rad/s in this case. With the LPF virtual

impedance loop, the voltage loop is modiﬁed as given in (20)

vf

LPF(s) = (19)

s + vf

− Gur (s) · Zvdq (s) · LPF(s) + Zordq (s) · iodq (s)

(20)

function and output impedance without virtual impedance

loop as given in (16) and (17). Deﬁne

ZDf (s) = Gur (s) · Zvdq (s) · LPF(s) + Zordq (s) (21)

Table 4 Zv(s), Z0(s), ZD (s), ZDr (s), and ZDf (s), at each

considered frequency in SRF

Fig. 7 Simulation results of the VSI in the islanded microgrid with

0 2f0 6 f0 12 f0 …

different control strategies

|Zv(Ω)| 0.5 6.30 18.86 37.70 … a Conventional PI controller

|Zo(Ω)| 0 57.34 107.15 104.71 … b The proposed PI plus multi-resonant controller

|ZD(Ω)| 0 63.52 121.67 128.55 … c The proposed PI plus multi-resonant controller with modiﬁed virtual

|ZDr(Ω)| 0 6.58 19.24 39.36 … impedance loop

|ZDf (Ω)| 0 1.87 2.48 4.27 … d Comparison between the output voltage unbalances and THDs under

different control strategies

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0410

www.ietdl.org

presented in Table 4 in order to distinguish the different † Stage III: A 300 W single-phase resistive load is in

strategies more speciﬁcally, where Zv is the virtual output between phase AB at 0.06 s

impedance given in (11), Zo and ZD are given in (10) and † Stage IV: A 250 W three-phase diode bridge rectiﬁer load

(13), ZDr and ZDf are given in (18) and (21). is at 0.12 s

It can be concluded from Table 4 that all the discussed

control strategies have the zero-error tracking capability for To obtain a direct viewing of the proposed control strategy,

the positive-sequence fundamental frequency output voltage comparisons of the output voltage unbalance and total

since all the output impedance is 0 dB at 0 Hz in SRF. harmonic distortion (THD) are illustrated in Fig. 7d with

However, for the conventional PI controlled voltage loop, both the unbalanced and non-linear loads (Stage IV of the

the total output impedance at 2f0, 6f0 and 12f0 are too large, simulation). As seen, the conventional PI voltage controller

which indicates large unbalance and harmonic voltage drop performs unsatisﬁed enough, while the proposed controller

across the output impedance, and the output voltage is reduces the voltage unbalance and harmonics greatly.

distorted. The proposed PI plus multi-resonant voltage However, owing to the harmonic voltage drop across the

controller reduces the total output impedance at the virtual impedance, the output voltage is still distorted.

considered frequencies to about 1/10 of the regular PI Additionally, the virtual impedance loop is modiﬁed and

controlled voltage loops. Unfortunately, owing to the high the output voltage is improved further.

speed virtual impedance loop, the total output impedance is

still too large to optimise the output voltage distortion

under unbalanced and non-linear loads. With the modiﬁed

virtual impedance loop, the total output impedance of the 5.2 Experimental prototype and validation

VSI at the considered frequencies is reduced to a great

amount so that lower output voltage distortion could be Finally, an experimental prototype is built up based on a

expected. RT-LAB environment as illustrated in Fig. 8 to validate

the proposed control strategy. The circuit and control

5 Simulation and experimental validation parameters used in the experiment are the same as given in

Tables 2 and 3 with three-phase balanced resistive load

5.1 Simulation results R1 = 320 Ω, unbalanced resistive load R2 = 480 Ω and diode

bridge rectiﬁer load R3 = 1000 Ω. The three different control

The proposed PI plus multi-resonant voltage controller for strategies mentioned in the simulation section are all tested

voltage unbalance and harmonic compensation of the VSI in the experiments with all the balanced load, unbalanced

in the islanded microgrid is validated through simulation in load and rectiﬁer load on. The steady-state output voltage

MATLAB/SIMULINK ﬁrst. The simulation results are and current are presented in Figs. 9a–c.

presented in Fig. 7 using the parameters given in Tables 2 Comparisons of the output voltage unbalance and

and 3 to prove the effectiveness of the proposed control THD are presented in Fig. 9e. It can be concluded that

strategy. The simulation is implemented with three different the proposed PI plus multi-resonant voltage controller

control strategies under the same load condition: (a) the obtains lower output voltage unbalance and THD than the

conventional PI voltage controller, (b) the proposed PI plus conventional PI controller. Additionally, the modiﬁed

multi-resonant voltage controller and (c) the proposed PI virtual impedance loop helps to improve the output

plus multi-resonant voltage controller under modiﬁed voltage quality further. To demonstrate the compensation

virtual impedance loop. The load condition of the ability of the proposed strategy at extreme conditions, a

simulations is as follows: single-phase load is connected to the system between

phases A and B. The experimental results are given in

† Stage I: The VSI is started with no load at 0 s Fig. 9d, and the voltage unbalance under such condition is

† Stage II: A 500 W three-phase balanced resistive load is on 0.97%, which proves the effectiveness of the proposed

at 0.02 s strategy.

doi: 10.1049/iet-pel.2013.0410 & The Institution of Engineering and Technology 2014

www.ietdl.org

6 Conclusion

This paper proposes a FPS SRF-based control strategy for

voltage unbalance and harmonic compensation of the VSIs

used as interfaces in islanded microgrid. The voltage

compensation loops are integrated within the power droop

loops and the virtual output impedance loop. The proposed

strategy is implemented in a single SRF with a PI controller

for the voltage’s fundamental component regulation and

multi-resonant controller for voltage unbalance and selected

harmonics compensation. The impedance model of the DG

interface inverter is built when controlled by three different

control methods to explain the compensation ability of the

proposed strategy, which are the conventional PI voltage

controller, the PI plus multi-resonant voltage controller and

the PI plus multi-resonant voltage controller with modiﬁed

virtual impedance loop.

The simulation and experimental results of the three

different control strategies with balanced load, unbalanced

load and diode bridge rectiﬁer load are given to validate the

effectiveness of the proposed control strategy.

7 Acknowledgment

This work is sponsored by the National High-Tech R&D

Program of China (2011AA050202).

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& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0410

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