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# Lecture 17:

## Timing Diagram and D Flip-Flop

Bo Wang
Division of Information & Computing Technology
Hamad Bin Khalifa University
bwang@hbku.edu.qa

## © B. Wang, 2017 CPEG - Lecture 17 1

Digital Timing Diagram

## • Representation of a set of signals in the time domain usually uses the

clock signal as reference

• Higher value is a logic “1”; lower value is a logic “0”; may have don’t care
values (represented by shaded grey area)

## © B. Wang, 2017 CPEG - Lecture 17 2

Timing Diagram Example

• Clocked RS latch

CLK R S Q (n)
0 X X Q (n-1)
1 0 0 Q (n-1)
1 0 1 1
1 1 0 0 CLK
1 1 1 X
R
Output only changes at the rising Reset Take effect
S
edge of the clock When clk=1
Set

Q Keep state
Keep state

D Flip-Flop

## • A D flip-flop can be constructed from an RS flip-flip to allow clocking and

synchronization (D is derived from “Data” and “Delay”)

## • When the clock is high, it acquires an input data

• When the clock is low, the memory remembers the data, no matter how
the input changes, the output will not change

In Clk R S Out
0 0 0 0 Q (n)=Q (n-1)
1 0 0 0 Q (n)=Q (n-1)
0 1 1 0 Q=0
1 1 0 1 Q=1

## © B. Wang, 2017 CPEG - Lecture 17 4

D Flip -Flop

• Transparent D Flip-flop
In Clk Out
0 0 Q (n)=Q (n-1)
1 0 Q (n)=Q (n-1)
0 1 Q=0
1 1 Q=1
D flip-flop symbol Truth table

## © B. Wang, 2017 CPEG - Lecture 17 5

Problem of D Flip-Flop in Sequential Logic

## • Transparent D flip-flops require their D inputs remain constant when

clock (CLK) = 1

• This means that the preceding logic circuits cannot start computing the
next operation while clock =1

input

between 0 and 1

## © B. Wang, 2017 CPEG - Lecture 17 6

Master-Slave D Flip –Flop

## • We can fix this by using two separate transparent D flip-flops cascading

together

• We call the first flip-flop a MASTER and the second one a SLAVE, and
hence we call this new memory element a MASTER-SLAVE D flip-flop

## Input changes when clk = 1,

without changing the output

## © B. Wang, 2017 CPEG - Lecture 17 7

Falling Edge Trigger D Flip –Flop

## • The inverter can be connected to the slave flip-flop to provide a falling

edge triggered Master-Slave D flip-flop

## © B. Wang, 2017 CPEG - Lecture 17 8

Frequency Divider

## • D Flip-Flop can be used to form a frequency divider

• The frequency at the output of the circuit becomes half of that of the input

## © B. Wang, 2017 CPEG - Lecture 17 9

Constructing Binary Counter

## • The circuit and timing diagram of a binary counter:

• Each flip-flop divides the clock frequency of the input from the previous
flip-flop/ clock

## © B. Wang, 2017 CPEG - Lecture 17 10

Combinational and Sequential Logic: A
summary
Input Output

Combinational Logic
Input Output
Combinational Logic

Memory

Clock

## • Sequential logic: output may change only at a specific time, depending

on whether it is Synchronous or Asynchronous and the type of flip-flop

## − Transparent flip-flop  changes with the input during the clock = 1

− Edge-triggered flip-flop  only changes at the clock edge