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Birla Institute of Technology and Science Pilani, Hyderabad Campus

II Semester 2018-2019 7. Which of the following is NOT a data transfer instruction in an 8086
CS/ECE/EEE/INSTR F241 microprocessor?
Microprocessor Programming and Interfacing (A) MOV (B) XCHG (C) SBB (D) PUSH
Comprehensive Examination - Part A (Closed Book)
8. During comparison operation, the result of comparison is stored in
Time: 90 min. Date: 01-05-2019 MM: 60 (A) Memory (B) Registers (C) Stack (D) None
(NOTE: Q1 to Q30: Every correct answer carries +2 marks; Every incorrect answer carries
-1 mark; All the answers should be written with pen in CAPITALS in the box given below. 9. If an 8086 processor is working at 10 MHz – how much time does two MEMR
Any overwriting/ambiguity/answers written somewhere else (if not found inside the given cycles take if there are no wait states
box) will be awarded 0 marks.)
(A) 800 ns (B) 1200ns (C) 600ns (D) 900ns
ID No.: Faculty Copy Name: Faculty Copy 10. Number of machine cycles required for the instruction PUSH 3324H are
(Assume processor is operating in 16 bit mode). (Format: 011010s0 data)
Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (A) 2MEMR, 2MEMW (B) 1MEMR, 1MEMW
Q 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 11. The expression No. of clocks = 22(CX-1) + 1,441,802 (DX-1) + 36 can be used
A D D A C B C D C B A A B B C A to compute delay. For example, it results in 0.758 sec for CX=4150H and
DX=0006H in an 8086 CPU based program. The frequency of operation of CPU
1. Size of address bus in 80286 and data bus in 8088 respectively are (in bits) is 10 MHz. The maximum delay which could possibly be achieved using the
(A) 24, 8 (B) 20, 8 (C) 24, 16 (D) 20, 16
expression is
2. Which segment is referred for the instruction MOV [BX+50], AX (A) 9496 µs (B) 3782 µs (C) 7774 µs (D) 10060 µs
(A) Extra (B) Stack (C) Code (D) Data 12. When queue status bits (QS1, QS0) is 10 (binary) then it implies
3. Initially, AL and CF are cleared. Find the correct sequence of instructions to get (A) First byte of opcode (B) Queue is empty
AL=34H and CF=1. (C) Subsequent byte of opcode (D) Queue is idle
1. MOV AX, 0FF35H 4. MOV AL, 13H 13. Consider the following program:
2. MOV DX, 1221H 5. ADD AX, DX MOV AL, 23H
3. MOV AL, 35H 6. DEC AL MOV BL, 20H
(A) 1,6 (B) 1,2,4,5 (C) 1,3,6 (D) 1,3,5 XCHG AL, BL
4. Which of the following is not true? MOV CL, 45H
(A) BIU is responsible for calculating the physical address XCHG AL, CL
(B) Same offset address value is valid across the segments OUT PORT1, CL
(C) Each program should have at least two segments The output at PORT1 is
(D) Segments can overlap (A) 23H (B) 20H (C) 45H (D) None
5. If CS contents are 0FC2H, and the volume of code is 2400 bytes, which is the 14. In the pin diagram of 8086 microprocessor, the pin numbers of INTR and NMI
last address in this code segment? are ________ and ____________ respectively.
(A) 12020H (B) 66944H (C) 73760 (D) 10580H (A) 18, 19 (B) 19, 18 (C) 17, 18 (D) 18, 17
6. What is the output of the following code, if AX = 37D7H, BH = 151 15. In 8086 microprocessor, which of the following is a Break Point Interrupt:
DIV BH (A) INT 4 (B) INT 5 (C) INT 3 (D) None
(A) AL=65H, AH=94 (B) AL=5EH, AH=101
(C) AH=E5H, AL=5EH (D) AL=56H, AH=5EH
16. The interrupts related to Trap and Bound are _____ and _______ interrupts 25. In mode 2 of the timer IC 8254, if N is loaded as the count value, then after N-1
respectively. cycles after the countdown starts, the output becomes low for how many clock
(A) Software and Hardware (B) Hardware and Software cycles
(C) Hardware and Hardware (D) None of the options (A) 1 (B) 2 (C) 3 (D) N/2
17. In the indirect input/output (I/O) addressing, which of the following register is 26. The mode that is used in the timer IC 8254 to interrupt the process by setting a
used to preload the port address: suitable terminal count value is
(A) AX (B) BX (C) Either AX or AL (D) None (A) Mode 0 (B) Mode 1 (C) Mode 2 (D) Mode 3
18. In mode-1 operation of 8255 PPI, which lines of Port-C may be used as 27. If 8086 is interfaced with the timer IC 8254, the maximum number by which the
independent data lines: clock frequency is divided using one of the timers is
(A) PC6 and PC7 (B) PC0 and PC1 (A) 28 (B) 216 (C) 220 (D) 210
(C) PC2 and PC3 (D) PC4 and PC5
28. When the status of BHE, A0 are 1, 1 (in binary) it implies that the
19. In 8255 PPI, which mode of operation is the Strobed Bidirectional I/O Mode: (A) 16 bits selected in memory (B) No bit is selected in memory
(A) Mode 0 (B) Mode 1 (C) Mode 2 (D) Mode 3 (C) Lower byte is selected in memory (D) Higher byte is selected in memory
20. In 8255 PPI, the BSR control word to reset the bit PC3 is: 29. Which of the following instruction cannot be combined with REP prefix.
(A) 07H (B) 06H (C) 03H (D) 83H (A) MOVS (B) STOS (C) LODS (D) INS
21. Which of the following is not true: 30. 8086 microprocessor has the starting address of the memory as 92727H. 20
(A) CLI is used to clear IF flag memory chips of size 64K bytes are available. What is the maximum number of
(B) Resetting the processor clears IF flag memory locations that could be interfaced to the processor?
(C) 9th bit of Flag register can be reset with AND operation directly (A) 393216 (B) 60000 (C) 393216H (D) 6FFFFH
(D) Non maskable interrupt can be generated using INT instruction
22. Instruction Addressing Mode
(a) MOV BX, [1245H] (1) Immediate
(b) ADD CX, [SI+BX+200] (2) Base relative plus index
(c) SUB AX, 2345H (3) Direct
(d) MUL BX (4) Register
The correct match is
(A) a-1, b-2, c-4, d-3 (B) a-2, b-3, c-1, d- 4
(C) a-3, b-2, c-4, d- 1 (D) a-3, b-2, c-1, d- 4
23. The instruction, JMP 5000H : 2000H; is an example of
(A) Intrasegment direct mode (B) Intrasegment indirect mode
(C) Intersegment direct mode (D) Intersegment indirect mode
24. In mode 2 of the timer IC 8254, if a new value is loaded before the previous
countdown finishes,
(A) The new value is loaded immediately.
(B) The new value is loaded only upon completion of previous countdown.
(C) The new value must be loaded only by giving a trigger.
(D) Nothing will happen because the new value must be given only