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369 Tesla

1. Any signed negative binary number is recognised by its


a) MSB b) LSB c) Bits d) Nibble

2. The parameter through which 16 distinct values can be represented is known as:
a) Bit b) Byte c) Nibble d) Word

3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the
number continuously by 2.
a) Dividing b) Multiplying c) Adding d) Subtracting

4. The representation of octal number (532.2)8 in decimal is :


a) (346.25)10 b) (532.864)10 c) (340.67)10 d) (531.668)10

5. The decimal equivalent of the binary number (1011.011)2 is


a) (11.375)10 b) (10.123)10 c) (11.175)10 d) (9.23)10

6. An important drawback of binary system is


a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) None of the Mentioned

7. The decimal equivalent of the octal number (645)8 is ______


a) (450)10 b) (451)10 c) (421)10 d) (501)10

8) The code where all successive numbers differ from their preceding number by single bit is
a) Binary code b) BCD c) Excess 3 d) Gray

9) The following switching functions are to be implemented using a decoder:


f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be
a) 2 to 4 line b) 3 to 8 line c) 4 to 16 line d) 5 to 32 line

10) How many AND gates are required to realize Y = CD + EF + G ?


a) 4 b) 5 c) 3 d) 2
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11) The NOR gate output will be high if the two inputs are
a) 00 b) 01 c) 10 d) 11

12) How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2 b) 2, 3 c) 3, 3 d) None of the Mentioned

13) A universal logic gate is one which can be used to generate any logic function. Which of the
following is a universal logic gate?
a) OR b) AND c) XOR d) NAND

14) A full adder logic circuit will have


a) Two inputs and one output b) Three inputs and three outputs
c) Two inputs and two outputs d) Three inputs and two outputs

15) The output of an EX-NOR gate is 1. Which input combination is correct?


a) A = 1, B = 0 b) A = 0, B = 1
c) A = 0, B = 0 d) None of the Mentioned

16) In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND b) NOR c) NAND d) OR

17) The time required for a gate or inverter to change its state is called
a) Rise time b) Decay time c) Propagation time d) Charging time

18) . What is the minimum number of two input NAND gates used to perform the function of
two input OR gates?
a) One b) Two c) Three d) Four

19) Odd parity of word can be conveniently tested by


a) OR gate b) AND gate c) NAND gate d) XOR gate

20) The number of full and half adders are required to add 16-bit number is
a) 8 half adders, 8 full adders b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders d) 4 half adders, 12 full adders

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21) Which of the following will give the sum of full adders as output?
a) Three point major circuit b) Three bit parity checker
c) Three bit comparator d) Three bit counter

22) Which of the following gate is known as coincidence detector?


a) AND gate b) OR gate c) NOR gate d) NAND gate

23) An OR gate can be imagined as


a) Switches connected in series b) Switches connected in parallel
c) MOS transistor connected in series d) None of the mentioned

24) How many full adders are required to construct an m-bit parallel adder?
a) m/2 b) m c) m-1 d) m+1 View Answer

25) A latch is an example of a


a) Monostable multivibrator b) Astable multivibrator
c) Bistable multivibrator d) None of the Mentioned

26) Latch is a device with


a) One stable state b) Two stable state
c) Three stable state d) None of the Mentioned

27) Why latches are called a memory devices?


a) It has capability to stare 8 bits of data b) It has internal memory of 4 bit
c) It can store one bit of data d) None of the Mentioned

28) Two stable states of latches are


a) Astable & Monostable b) Low input & high output
c) High output & low output d) Low output & high input

29) How many types of latches are


a) 2 b) 3 c) 4 d) 5

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30) The full form of SR is
a) System rated b) Set reset
c) Set ready d) None of the Mentioned

31) The SR latch consists of


a) 1 input b) 2 inputs c) 3 inputs d) 4 inputs

32) The outputs of SR latch are


a) x and y b) a and b c) s and r d) q and q’

33) . The NAND latch works when both inputs are


a) 1 b) 0 c) Inverted d) Don’t cares

34) The first step of analysis procedure of SR latch is to


a) label inputs b) label outputs c) label states d) label tables

35) When a high is applied to the Set line of an SR latch, then


a) Q output goes high b) Q’ output goes high
c) Q output goes low d) None of the Mentioned

36) When both inputs of SR latches are low, the latch


a) Q output goes high b) Q’ output goes high
c) It remains in its previously set or reset state d) it goes to its next set or reset state

37) When both inputs of SR latches are high, the latch goes
a) Unstable b) Stable c) Metastable d) None of the Mentioned

38) The logical sum of two or more logical product terms is called
a) SOP b) POS c) OR operation d) NAND operation

39) The expression Y=AB+BC+AC shows the _________ operation.


a) EX-OR b) SOP c) POS d) NOR

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40) The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.
a) AND b) POS c) SOP d) NAND

41)A product term containing all K variables of the function in either complemented or
uncomplemented form is called a
a) Minterm b) Maxterm c) Midterm d) None of the Mentioned

42) According to the property of minterm, how many combinations will have value equal to 1 for
K input variables?
a) 0 b) 1 c) 2 d) 3

43) The canonical sum of product form of the function y(A,B) = A + B is


a) AB + BB + A’A b) AB + AB’ + A’B
c) BA + BA’ + A’B’ d) None of the Mentioned

44) A variable on its own or in its complemented form is known as a


a) Product Term b) Literal c) Sum Term d) None of the Mentioned

45) Maxterm is the sum of __________of the corresponding Minterm with its literal
complemented.
a) Terms b) Words c) Numbers d) None of the Mentioned

46) Canonical form is a unique way of representing________________


a) SOP b) Minterm c) Boolean Expressions d) A page

47) 10. There are _____________ Minterms for 3 variables (a, b, c).
a) 0 b) 2 c) 8 d) None of the Mentioned

48) What is a multiplexer?


a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) None of the Mentioned

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49) Which combinational circuit is renowned for selecting a single input from multiple inputs &
directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) None of the Mentioned

50) It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs
to the digital multiplexer with the proficiency of large number of
a) Inputs b) Outputs c) Selection lines d) All of the Mentioned

51) Which is the major functioning responsibility of the multiplexing combinational circuit?
a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) All of the Mentioned

52) What is the function of an enable input on a multiplexer chip?


a) To apply Vcc b) To connect ground
c) To active the entire chip d) To active one half of the chip

53) One multiplexer can take the place of


a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits

54) A digital multiplexer is a combinational circuit that selects


a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) None of the Mentioned

55) In a multiplexer, the selection of a particular input line is controlled by


a) Data controller b) Selected lines
c) Logic gates d) Both data controller and selected lines

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56) If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2 b) m c) n d) None of the Mentioned

57) How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2 b) 4 c) 8 d) 3

58) A basic multiplexer principle can be demonstrated through the use of a


a) Single-pole relay b) DPDT switch
c) Rotary switch d) Linear stepper

59) How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3 b) 4 c) 2 d) 5

60) In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is

a) X0 b) X1 c) X2 d) X3

61) The enable input is also known as


a) Select input b) Decoded input c) Strobe d) Sink

62) 4 to 1 MUX would have


a) 2 inputs b) 3 inputs c) 4 inputs d) 5 inputs

63) . The two input MUX would have


a) 1 select line b) 2 select lines c) 4 select lines d) 3 select lines

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64) . A combinational circuit that selects one from many inputs
a) Encoder b) Decoder c) Demultiplexer d) Multiplexer

65) Which of the following circuit can be used as parallel to serial converter?
a) Multiplexer b) Demultiplexer
c) Decoder d) Digital counter

66) A combinational circuit is one in which the output depends on the


a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output

67) Without any additional circuitry an 8:1 MUX can be used to obtain
a) Some but not all Boolean functions of 3 variables
b) All function of 3 variables but none of 4 variables
c) All functions of 3 variables and some but not all of 4 variables
d) All functions of 4 variables

68) A basic multiplexer principle can be demonstrated through the use of a


a) Single-pole relay b) DPDT switch
c) Rotary switch d) Linear stepper

69) One multiplexer can take the place of


a) Several SSI logic gates b) Combinational logic circuits
c) Several Ex-NOR gates d) Several SSI logic gates or combinational logic circuits

70) The inputs/outputs of an analog multiplexer/demultiplexer are


a) Bidirectional b) Unidirectional c) Even parity d) Binary-coded decimal

71) If enable input is high then the multiplexer is


a) Enable b) Disable c) Saturation d) None of the Mentioned

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72) What is data routing in a multiplexer?
a) It spreads the information to the control unit
b) It can be used to route data from one of several source to destination
c) It is an application of multiplexer
d) Both it can be used to route data and it is an application of multiplexer

73) A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a


matrix of squares.
a) Venn Diagram b) Cycle Diagram
c) Block diagram d) Triangular Diagram

74) There are ______ cells in a 4-variable K-map.


a) 12 b) 16 c) 18 d) None of the Mentioned

75) The K-mapbasedBoolean reduction is based on the following UnifyingTheorem: A + A’ = 1.


a) Impact b) Non Impact c) Force d) None of the Mentioned

76) Each product term of a group, w’.x.y’ and w.y, represents the ____________in that group.
a) Input b) POS c) Sum-of-Minterms d) None of the Mentioned

77) The prime implicant which has at least one element that is not present in any other implicant
is known as
a) Essential Prime Implicant b) Implicant
c) Complement d) None of the Mentioned

78) Product-of-Sums expressions can be implemented using


a) 2-level OR-AND logic circuits b) 2-level NOR logic circuits
c) 2-level XOR logic circuits d) Both 2-level OR-AND and NOR logic circuits

79) Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible
product term of the given
a) Function b) Value c) Set d) None of the Mentioned

80) Don’t care conditions can be used for simplifying Boolean expressions in
a) Examples b) Terms c) K-maps d) Latches

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81) It should be kept in mind that don’t care terms should be used along with the terms that are
present in
a) Minterms b) Maxterm c) K-Map d) Latches

82) Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR b) NAND c) AND d) NOR

83) There are many situations in logic design in which simplification of logic expression is
possible in terms of XOR and _________________ operations.
a) X-NOR b) XOR c) NOR d) NAND

84) These logic gates are widely used in _______________ design and therefore are available in
IC form.
a) Circuit b) Digital c) Analog d) Block

85) In case of XOR/XNOR simplification we have to look for the


following____________________
a) Diagonal Adjacencies b) Offset Adjacencies
c) Straight Adjacencies d) Both diagonal and offset adjencies

86) Entries known as _______________ mapping.


a) Diagonal b) Straight c) K d) None of the Mentioned

87) Latches constructed with NOR and NAND gates tend to remain in the latched condition due
to which configuration feature?
a) Low input voltages b) Synchronous operation
c) Gate impedance d) Cross coupling

88) One example of the use of an S-R flip-flop is as:


a) Transition pulse generator b) Racer
c) Switch debouncer d) Astable oscillator

89) . The truth table for an S-R flip-flop has how many VALID entries?
a) 1 b) 2 c) 3 d) 4

90) When both inputs of a J-K flip-flop cycle, the output will
a) Be invalid b) Change c) Not change d) Toggle

91) Which of the following is correct for a gated D-type flip-flop?


a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH

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92) A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates b) XOR or XNOR gates
c) NOR or NAND gates d) AND or NOR gates

93) The logic circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called
a) Combinational circuits b) Sequential circuits
c) Latches d) Flip-flops

94) Whose operations are more faster among the following?


a) Combinational circuits b) Sequential circuits
c) Latches d) Flip-flops

95) In boolean algebra, the OR operation is performed by which properties?


a) Associative properties b) Commutative properties
c) Distributive properties d) All of the Mentioned

96) The expression for Absorption law is given by


a) A+AB = A b) A+AB = B c) AB+AA’ = A d) None of the Mentioned

97) The involution of A is equal to


a) A b) A’ c) 1 d) 0

98) . A(A + B) = ?
a) AB b) 1 c) (1 + AB) d) A

99) DeMorgan’s theorem states that


a) (AB)’ = A’ + B’ b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’ d) None of the Mentioned

100) (A + B)(A’ * B’) = ?


a) 1 b) 0 c) AB d) AB’

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101) Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

a) a b) b c) c d) d

102) Which of the following logic expressions represents the logic diagram shown?

a) X=AB’+A’B b) X=(AB)’+AB
c) X=(AB)’+A’B’ d) X=A’B’+AB

103) The device shown here is most likely a ________

a) Comparator b) Multiplexer c) Inverter d) Demultiplexer

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104) What type of logic circuit is represented by the figure shown below?

a) XOR b) XNOR c) AND d) XAND

105) For a two-input XNOR gate, with the input waveforms as shown below, which output
waveform is correct?

a) d b) a c) c d) b

106) Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate d) One 4-input NAND gate, one inverter

107) What is the indication of a short to ground in the output of a driving gate?
a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state

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108) For the device shown here, assume the D input is LOW, both S inputs are LOW and the
input is LOW. What is the status of the Y’ outputs?

a) All are HIGH b) All are LOW


c) All but are LOW d) All but are HIGH

109) The carry propagation can be expressed as ________


a) Cp = AB b) Cp = A + B
c) Cp = A XOR B d) Cp = A + B’

110) 3 bits full adder contains


a) 3 combinational inputs b) 4 combinational inputs
c) 6 combinational inputs d) 8 combinational inputs

111) In digital logic, a counter is a device which


a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) None of the Mentioned

112) A counter circuit is usually constructed of


a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) None of the Mentioned

113) What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n b) 0 to 2n-1 c) 0 to 2n+1 d) 0 to 2n+1/2

114) How many types of counter are?


a) 2 b) 3 c) 4 d) 5
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115) A decimal counter has ______ states.
a) 5 b) 10 c) 15 d) 20

116) Ripple counters are also called


a) SSI counters b) Asynchronous counters
c) Synchronous counters d) VLSI counters

117) Synchronous counter is a type of


a) SSI counters b) LSI counters ) MSI counters d) VLSI counters

118) Three decade counter would have


a) 2 BCD counters b) 3 BCD counters c) 4 BCD counters d) 5 BCD counters

119) BCD counter is also known as


a) Parallel counter b) Decade counter
c) Synchronous counter d) VLSI counter

120) The parallel outputs of a counter circuit represent the


a) Parallel data word b) Clock frequency
c) Counter modulus d) Clock count
View Answer

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