BÀI THÍ NGHIỆM 2

Prelab:

2.1 Thiết kế bộ cộng toàn phần (Full-Adder)

 Code VHDL

library ieee;

use ieee.std_logic_1164.all;

entity huy is
port(
x,y,z: in std_logic;
c,s: out std_logic
);
end entity;

architecture Func of huy is

begin
c <= (x AND y) OR (y AND z) OR (x AND z);
s <= x XOR y XOR z;
end architecture;

 Mô phỏng :
2.2 Thiết kế bộ dồn kênh 4-1 (Mux 4-1)

 Code VHDL

library ieee;

use ieee.std_logic_1164.all;

entity huy2 is
port(
d0, d1, d2, d3: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out std_logic
);
end entity;

architecture func of huy2 is

begin
y <= d0 when s = "00" else
d1 when s = "01" else
d2 when s = "10" else
d3;
end architecture;

 Mô phỏng
 2.3 Thiết kế bộ giải mã 2-4 (Decoder 2-4)
 Code VHDL
library ieee;
use ieee.std_logic_1164.all;

entity bai3 is
port(
x: in std_logic_vector(1 downto 0);
c: in std_logic;
y: out std_logic_vector(3 downto 0)
);
 end entity;

architecture func of bai3 is

signal
c_x: std_logic_vector(2 downto 0);

begin
c_x <= c&x;
with c_x select
y <= "0001" when "100" ,
"0010" when "101" ,
"0100" when "110" ,
"1000" when "111" ,
"0000" when others;
end architecture;

 Mô phỏng
I.Thí nghiệm 2.1 - Thiết kế bộ cộng 2 số 4 bit (Full Adder)

 Code VHDL

library ieee;
use ieee.std_logic_1164.all;
entity bai4 is
port(
a,b: in std_logic_vector(3 downto 0);
Cin: in std_logic;
s: out std_logic_vector(3 downto 0);
Cout:out std_logic
);
end entity;

architecture Structure of bai4 is

signal c: std_logic_vector(1 to 3);
component fulladder
port(
x,y,z: in std_logic;
s,c: out std_logic
);
end component;
 begin
stage0: fulladder port map (x => a(0),y => b(0),z => Cin,s => s(0),c =>
c(1));
stage1: fulladder port map (x => a(1),y => b(1),z => c(1),s => s(1),c =>
c(2));
stage2: fulladder port map (x => a(2),y => b(2),z => c(2),s => s(2),c =>
c(3));
stage3: fulladder port map (x => a(3),y => b(3),z => c(3),s => s(3),c =>
Cout);
end architecture;
 Mô phỏng

 Wave form
II. Thí nghiệm 2.2 – Thiết kế bộ ALU 4-bit

 Code VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.numeric_STD.ALL;
entity alu is
port(
A, B : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(2 downto 0);
Cin:in std_logic;
COut : out std_logic;
ketqua : out std_logic_vector(3 downto 0)
);
end entity alu;

architecture Behavioral of alu is

signal Temp: std_logic_vector(4 downto 0);
begin
process(A,B, sel, temp) is
 begin
case sel is
when "000" =>
temp<=('0'&a)+b+Cin;
ketqua<=temp(3 downto 0);
Cout<=temp(4);
when "001" =>
temp<= ('0'&a)-b-Cin;
ketqua<=temp(3 downto 0);
Cout<=temp(4);
when "010" =>
ketqua<= A or B;
when "011" =>
ketqua <= A and B;
when "100" =>
ketqua <= A(2 downto 0) & '0';
when "101" =>
ketqua <= '0' & A(3 downto 1);
when "110" =>
ketqua <= A(2 downto 0) & A(3);
when others =>
ketqua<= A(0) & A(3 downto 1);
end case;
end process;
end architecture Behavioral;
 Mô phỏng

BÀI THÍ NGHIỆM 3

I, Thí nghiệm 3.1 – Bộ đếm mã BCD

 Code VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity bodemmaBCD is
port(
enable, load, up, reset, clk: in std_logic;
d: in std_logic_vector(3 downto 0);
co: out std_logic;
q: out std_logic_vector(3 downto 0)
);
end entity;
architecture behavioral of bodemmaBCD is
signal count: std_logic_vector(3 downto 0);
begin
process(reset, up, load, enable, clk, d)
begin
if (reset = '0') then
count <= "0000";
elsif(rising_edge(clk)) then
if (enable = '1') then
if (load = '0') then
if (up = '1') then
if count = "1001" then
count <= "0000";
else
count <= count + 1;
end if;
else
if count = "0000" then
count <= "1001";
else
count <= count - 1;
end if;
end if;
 else
count <= d;
end if;
end if;
end if;
end process;
q <= count;
end architecture;
 Mô phỏng

 Wave form
 I,.Thí nghiệm 3.2 - Bộ đếm lên xuống thập phân từ 0-99
 Code VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity bodem99 is
port(
d0,d1: in std_logic_vector (3 downto 0);
enable,load,up,clr,clk: in std_logic;
q0,q1: out std_logic_vector (3 downto 0);
co1: out std_logic
);
end entity;
architecture structure of bodem99 is
signal c : std_logic;
component bodemmaBCD
port(
enable, load, up, reset, clk: in std_logic;
d: in std_logic_vector(3 downto 0);
co: out std_logic;
q: out std_logic_vector(3 downto 0)
);
end component;
 begin
u1: bodemmaBCD port map (enable,load,up,clr,clk,d0,c,q0);
u2: bodemmaBCD port map (enable,load,up,clr,c,d1,co1,q1);
end architecture;
 Mô phỏng

 Wave form