You are on page 1of 3

VLSI Design

Assignment No. 1

1. Describe different levels of abstraction in VHDL.

2. Draw and explain VLSI design flow.
3. Briefly write about need of HDL and explain various features and capabilities of
VHDL language.
4. Write meaning of “Identifiers” used in VHDL. With suitable examples write the
various rules to look at before choosing any Identifiers.
5. Explain any three types of operators in VHDL with examples for each.
6. What is configuration in VHDL? Explain with suitable example.
7. Explain attributes in VHDL with examples.
8. With suitable examples briefly differentiate ‘Signals’ and ‘Variables’ used in

Assignment No. 2

1. Write VHDL code for 4:1 Multiplexer using any concurrent statement.
2. Write circuit diagram and VHDL code for 4 bit ripple carry adder using full adder
as a component.
3. Write VHDL code for 2 bit comparator.
4. Using two half adder circuits draw the circuit for full adder. Write a VHDL code
for full adder using process statement.
5. Write a VHDL code for 4 bit priority encoder using process statement.
6. Write a VHDL code for 4 bit ALU, which will perform following operations;
Addition, Subtraction, And-ing, Or-ing, Exor-ring, and reverse Subtraction.
VLSI Design

Assignment No. 3

1. Explain Inertial and Transport delays in VHDL.

2. Write truth table, entity diagram and VHDL code for synchronous reset D-Flip
Flop using wait statement.
3. Write VHDL code for D- Flip Flop with Asynchrous set and reset inputs. Draw
entity diagram also.
4. Write entity diagram, truth table and VHDL code for asynchronous reset JK Flip
5. Write VHDL code for MOD – 6 counter.
6. Design a Mealy FSM to detect 1001 overlapping sequence. Write a VHDL code
for the same.
7. Draw a state diagram for a sequence detector “1011” which is realized as a
Mealy machine. Write VHDL code for the same.
8. Design a Moore machine to detect 1011 overlapping sequence. Write VHDL
code for the same.

VLSI Design

Assignment No. 4

1. Briefly explain about Assignment and Control statements in Verilog with

2. Briefly explain about operators in Verilog with examples.
3. Write Verilog code for
i. 4:2 Encoder ii. 1:4 De-Multiplexer
iii. 4 Bit counter which counts only even numbers with reset input
iv. 4 bit serial in serial out shift register using D flip flop as a component
v. Grey to Binary Convertor
vi. 4 bit ripple carry adder, using full adder as component
4. Draw physical structure of MOS Transistor (MOSFET). Explain the V-I
characteristics of the same.
5. Derive the expression for Drain current Id of MOSFET in
i. Linear / Resistive Region ii. Saturation Region
VLSI Design
Assignment No. 5

1. Neatly draw and explain functional block diagram of XC9500 macrocell.

2. Draw and explain briefly architectural block diagram of XC9500 CPLD
3. Draw the neat circuit diagram for Configurable Logic Block (CLB) used in
Spartan 3E series of Xilinx make FPGA. Explain functionality of each
component used inside.
4. Using neat suitable clock diagram elaborate Input / Output block of Spartan 3E
5. Explain the following methodologies for testing combinational circuits. Take an
example for each.
i. Stuck – At – Fault Models
ii. Path Sensitization
6. Briefly write about Built – In – Self – Test used for testing digital ICs. With a
neat diagram explain of 4 bit BILBO register.
7. With a neat diagram briefly explain the role of Multiple Input Signature Register