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Appendix A: Digital Logic

Principles of Computer Architecture
Miles Murdocca and Vincent Heuring

Appendix A: Digital Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Chapter Contents
A.1 Introduction A.2 Combinational Logic A.3 Truth Tables A.4 Logic Gates A.5 Properties of Boolean Algebra A.6 The Sum-of-Products Form, and Logic Diagrams A.7 The Product-of-Sums Form A.8 Positive vs. Negative Logic A.9 The Data Sheet A.10 Digital Components A.11 Sequential Logic A.12 Design of Finite State Machines A.13 Mealy vs. Moore Machines A.14 Registers A.15 Counters
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Some Definitions
• Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder. • Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit. • Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller.

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

The Combinational Logic Unit
• Translates a set of inputs into a set of outputs according to one or more mapping functions. • Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, 1 and 0, 0 and 1, or 5 V and 0 V for example. • The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. A set of inputs i0 – in are presented to the CLU, which produces a set of outputs according to mapping functions f0 – fm.

i0 i1
...

Combinational logic unit

f0 (i0, i1) f1 (i1, i3, i4)
...

in
Principles of Computer Architecture by M. Murdocca and V. Heuring

fm(i9, in)
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

A Truth Table
• Developed in 1854 by George Boole. • Further developed by Claude Shannon (Bell Labs). • Outputs are computed for all possible input combinations (how many input combinations are there?) • Consider a room with two light switches. How must they work?
Inputs Output Z 0 1 1 0

GND Light Z “Hot”

A 0 0 1 1

B 0 1 0 1

Switch A
Principles of Computer Architecture by M. Murdocca and V. Heuring

Switch B

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Alternate Assignment of Outputs to Switch Settings
• We can make the assignment of output values to input combinations any way that we want to achieve the desired input-output behavior.

Inputs Output A B 0 0 1 1
Principles of Computer Architecture by M. Murdocca and V. Heuring

Z 1 0 0 1
© 1999 M. Murdocca and V. Heuring

0 1 0 1

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Appendix A: Digital Logic

Truth Tables Showing All Possible Functions of Two Binary Variables
Inputs Outputs False AND 0 0 0 0 0 0 0 1 AB 0 0 1 0 A 0 0 1 1 AB 0 1 0 0 B 0 1 0 1 XOR 0 1 1 0 OR 0 1 1 1

• The more frequently used functions have names: AND, XOR, OR, NOR, XOR, and NAND. (Always use upper case spelling.)

A 0 0 1 1

B 0 1 0 1

Inputs A 0 0 1 1 B 0 1 0 1 NOR XNOR 1 0 0 0 1 0 0 1 B 1 0 1 0

Outputs A+B 1 0 1 1 A 1 1 0 0 A + B NAND True 1 1 0 1 1 1 1 0 1 1 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Logic Gates and Their Symbols
• Logic symbols shown for AND, OR, buffer, and NOT Boolean functions. • Note the use of the “inversion bubble.” • (Be careful about the “nose” of the gate when drawing AND vs. OR.)
A B AND A 0 0 1 1 B 0 1 0 1 F 0 0 0 1 A B OR A 0 0 1 1 B 0 1 0 1 F 0 1 1 1

F=AB

F=A+B

A 0 1

F 0 1

A 0 1

F 1 0

A Buffer
Principles of Computer Architecture by M. Murdocca and V. Heuring

F=A

A

F= A NOT (Inverter)
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Logic Gates and their Symbols (cont’)
A 0 0 1 1 A B NAND B 0 1 0 1 F 1 1 1 0 A B NOR A 0 0 1 1 B 0 1 0 1 F 1 0 0 0

F= A B

F= A + B

A 0 0 1 1 A B

B 0 1 0 1

F 0 1 1 0 A B

A 0 0 1 1

B 0 1 0 1

F 1 0 0 1

F=A⊕B Exclusive-OR (XOR)

. F=A⊕B Exclusive-NOR (XNOR)
© 1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Variations of Logic Gate Symbols
A B C (a) A B (c)
(a) 3 inputs (b) A Negated input (c) Complementary outputs

F = ABC

A B (b) A+ B A+ B

F = A+ B

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Transistor Operation of Inverter
OUTPUT VOLTAGE vs. INPUT VOLTAGE 4.0

VCC
V Output Voltage– VO–

3.5 3.0 2.5 2.0 1.5 1.0 0.5 0

V CC = 5 V R L = 400 Ω

VCC = +5 V A A Base GND = 0 V

VCC Collector Emitter Vin A

RL Vout A

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Input Voltage– V V I–

(a)

(b)

(c)

(d)

(a) Inverter showing power terminals; (b) transistor symbol; (c) transistor configured as an inverter; (d) inverter transfer function.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Assignments of 0 and 1 to Voltages
+5 V Logical 1 2.4 V Forbidden Range 0.4 V 0V (a)
Principles of Computer Architecture by M. Murdocca and V. Heuring

+5 V Logical 1 2.0 V Forbidden Range 0.8 V Logical 0 0V (b)
© 1999 M. Murdocca and V. Heuring

Logical 0

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Appendix A: Digital Logic

Transistor Operation of Logic Gates
VCC

(a) NAND; (b) NOR
VCC AB Vout A+B V1 A V2 B

Vout V1 A

V2 B

(a)
Principles of Computer Architecture by M. Murdocca and V. Heuring

(b)
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Tri-State Buffers
• Outputs can be 0, 1, or “electrically disconnected.”

C 0 0 1 1

A 0 1 0 1

F ø ø 0 1

C 0 0 1 1

A 0 1 0 1

F 0 1 ø ø

A C

F=AC or F=ø Tri-state buffer

A C

F = AC or F=ø

Tri-state buffer, inverted control

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Properties of Boolean Algebra
Relationship Dual A+B = B+A A + B C = (A + B) (A + C) 0+A = A A+A = 1 1+A = 1 A+A = A A + (B + C) = (A + B) + C Property Commutative Distributive Identity Complement Zero and one theorems Idempotence Associative Involution A+ B = A B ( A + B )( A + C )( B +C) = ( A + B)(A + C ) A+AB = A Absorption Theorem DeMorgan’s Theorem Consensus Theorem

• Principle of duality: The dual of a Boolean function is obtained by replacing AND with OR and OR with AND, 1s with 0s, and 0s with 1s.

Postulates Theorems

AB = BA A (B + C) = A B + A C 1A=A AA = 0 0A = 0 AA =A A (B C) = (A B) C A = A AB= A+ B AB + AC + BC = AB + AC A (A + B) = A

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

DeMorgan’s Theorem
A B 0 0 1 1 0 1 0 1 AB = A + B 1 1 1 0 1 1 1 0 A + B = AB 1 0 0 0
A+B = A+B = AB A B

1 0 0 0

DeMorgan’s theorem: A B

F=A+B

F=AB

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

All-NAND Implementation of OR
• NAND alone implements all other Boolean logic gates.

A A B A+B B A+ B

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Sum-of-Products Form: The Majority Function
• The SOP form for the 3-input majority function is: M = ABC + ABC + ABC + ABC = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7). • Each of the 2n terms are called minterms, ranging from 0 to 2n - 1. • Note relationship between minterm number and boolean value.
Minterm Index 0 1 2 3 4 5 6 7 A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F 1 0 0 0 1 0 1 1 1 0 0 0-side 1-side

A balance tips to the left or right depending on whether there are more 0’s or 1’s.
© 1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

AND-OR Implementation of Majority
A B C

• Gate count is 8, gate input count is 19.
ABC

ABC F AB C ABC
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Appendix A: Digital Logic

Notation Used at Circuit Intersections

Connection

No connection

Connection
Principles of Computer Architecture by M. Murdocca and V. Heuring

No connection
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

OR-AND Implementation of Majority
A B C

A+ B+ C

A+ B+C F A+ B+ C A+ B+ C
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Appendix A: Digital Logic

Positive/Negative Logic Assignments
• Positive logic: logic 1 is represented by high voltage; logic 0 is represented by low voltage. • Negative logic: logic 0 is represented by high voltage; logic 1 is represented by low voltage.
Gate Logic: Positive vs. Negative Logic Normal Convention: Postive Logic/Active High Low Voltage = 0; High Voltage = 1 Alternative Convention sometimes used: Negative Logic/Active Low
F Voltage T ruth T able A low low high high B low high low high F low low low high Positive Logic A 0 0 1 1 B 0 1 0 1 F 0 0 0 1 Negative Logic A 1 1 0 0 B 1 0 1 0 F 1 1 1 0

Behavior in terms of Electrical Levels

Two Alternative Interpretations Positive Logic AND Negative Logic OR

Principles of Computer Architecture by M. Murdocca and V. Heuring

Dual Operations

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Positive/Negative Logic Assignments (Cont’)
Voltage Levels A low low high high A B B low high low high F low low low high A B Positive Logic Levels A 0 0 1 1 B 0 1 0 1 F 0 0 0 1 A B Negative Logic Levels A 1 1 0 0 B 1 0 1 0 F 1 1 1 0

Physical AND gate

F

F=AB

F=A+B

Voltage Levels A low low high high A B B low high low high F high high high low

Positive Logic Levels A 0 0 1 1 B 0 1 0 1 F 1 1 1 0

Negative Logic Levels A 1 1 0 0 B 1 0 1 0 F 0 0 0 1

Physical NAND gate

F

A B

F= A B

A B

F = A + B

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Bubble Matching
Positive logic x0 Positive logic x1 (a) Negative logic Negative Logic Negative logic Bubble mismatch (c) x1 Bubble match (d) Negative Logic Positive Logic Negative logic x0 Negative logic x1 (b) x0 Bubble match Negative logic x0 Negative logic x1 Negative Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic
description These devices contain four independent 2-input NAND gates. schematic (each gate) V CC 4 kΩ 1.6 kΩ 130 Ω

Example Data Sheet
• Simplified data sheet for 7400 NAND gate, adapted from Texas Instruments TTL Databook [Texas Instruments, 1988]

function table (each gate) INPUTS A B H L X H X L OUTPUT Y L H H

package (top view)
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7 14 13 12 11 10 9 8

VCC 4B 4A 4Y 3B 3A 3Y

A B Y

absolute maximum ratings Supply voltage, VCC 7V Input voltage: 5.5 V Operating free-air temperature range: 0 ˚C to 70 ˚C Storage temperature range – 65 ˚ C to 150 ˚C recommended operating conditions logic diagram (positive logic)
1A 1B 2A 2B 3A 3B 4A 4B Y = AB 1Y 2Y 3Y 4Y

1 kΩ GND

MIN NOM MAX V CC V IH V IL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 0 4.75 2 0.8 – 0.4 16 70 5 5.25

UNIT V V V mA mA ˚C

electrical characteristics over recommended operating free-air temperature range MIN V OH V OL IIH IIL ICCH ICCL V CC = MIN, V IL = 0.8 V, IOH = – 0.4 mA V CC = MIN, V IH = 2 V, IOL = 16 mA V CC = MAX, V I = 2.4 V V CC = MAX, V I = 0.4 V V CC = MAX, V I = 0 V V CC = MAX, V I = 4.5 V 4 12 2.4 TYP MAX 3.4 0.2 0.4 40 – 1.6 8 22 UNIT V V µ A mA mA mA

switching characteristics, V CC = 5 V, T A = 25˚ C PARAMETER tPLH tPHL FROM (input) A or B TO (output) Y TEST CONDITIONS R L = 400 Ω C L = 15 pF MIN TYP MAX 11 7 22 15 UNIT ns ns

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Digital Components
• High level digital circuit designs are normally created using collections of logic gates referred to as components, rather than using individual logic gates. • Levels of integration (numbers of gates) in an integrated circuit (IC) can roughly be considered as: • Small scale integration (SSI): 10-100 gates. • Medium scale integration (MSI): 100 to 1000 gates. • Large scale integration (LSI): 1000-10,000 logic gates. • Very large scale integration (VLSI): 10,000-upward logic gates. • These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits.

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Multiplexer
Data Inputs

D0 D1 D2 D3

00 01 10 11

A B F 0 0 1 1 0 1 0 1

F D0 D1 D2 D3

A B Control Inputs F = A B D0 + A B D1 + A B D2 + A B D3

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

AND-OR Implementation of MUX
D0

D1 F D2

D3

A

B
© 1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

MUX Implementation of Majority
• Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs.
0 0 0 1 0 1 1 1 000 001 010 011 100 101 110 111

A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

M 0 0 0 1 0 1 1 1

F

A B C
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Appendix A: Digital Logic

4-to-1 MUX Implements 3-Var Function
• Principle: Use the A and B inputs to select a pair of minterms. The value applied to the MUX data input is selected from {0, 1, C, C} to achieve the desired behavior of the minterm pair.
A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F 0 0 1 1 0 1 1 0 0 0 1 C C A B 1 C C 00 01 10 11 F

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Appendix A: Digital Logic

Demultiplexer
00 D 01 10 11 F0 F1 F2 F3 D A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F0 F1 F2 F3 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1

A B F0 = D A B F1 = D A B F2 = D A B F3 = D A B

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Gate-Level Implementation of DEMUX
F0

F1 D F2

F3

A

B
© 1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Decoder

Enable = 1 A B A B Enable 00 01 10 11 D0 D1 D2 D3 0 0 1 1 0 1 0 1 D 0 D1 D2 D3 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A B 0 0 1 1 0 1 0 1

Enable = 0 D0 D 1 D 2 D 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D0 = A B

D1 = A B

D2 = A B

D3 = A B

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Gate-Level Implementation of Decoder
D0

D1 A B D2

D3 Enable
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Decoder Implementation of Majority Function
• Note that the enable input is not always present. We use it when discussing decoders for memory.

000 001 A B C 010 011 100 101 110 111 M

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Priority Encoder
• • • • An encoder translates a set of inputs into a binary encoding. Can be thought of as the converse of a decoder. A priority encoder imposes an order on the inputs. Ai has a higher priority than Ai+1
A0 A1 A2 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F0 F1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0

A0 A1 A2 A3

00 01 10 11

F0 F1

F0 = A0 A1 A3 + A0 A1 A2 F1 = A0 A2 A3 + A0 A1

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

AND-OR Implementation of Priority Encoder
A0 F0

A1

A2 F1

A3

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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A

B

C

Appendix A: Digital Logic

Programmable Logic Array
• A PLA is a customizable AND matrix followed by a customizable OR matrix. • Black box view of PLA:
A B C PLA F0 F1
Fuses AND matrix

OR matrix

F0

F1
© 1999 M. Murdocca and V. Heuring

Principles of Computer Architecture by M. Murdocca and V. Heuring

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A

B

C

Appendix A: Digital Logic

Simplified Representation of PLA Implementation of Majority Function

ABC

AB C

ABC

ABC

F0 F1 (Majority) (Unused)

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Carry In Operand A Operand B 0 0 + 0 0 0 0 0 + 1 0 1 0 1 + 0 0 1 0 1 + 1 1 0 1 0 + 0 0 1 1 0 + 1 1 0 1 1 + 0 1 0 1 1 + 1 1 1

Carry Sum Out

Example: Carry Operand A Operand B Sum 1 0 0 0 0 1 0 0 + 0 1 1 0 1 0 1 0

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Ai Bi Ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Si 0 1 1 0 1 0 0 1 Ci+1 0 0 0 1 0 1 1 1 Bi Ai Ci Full adder Ci+1 Si

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

• Four full adders connected in a ripple-carry chain form a four-bit ripple-carry adder.

b3 a3

c3

b2 a2

c2

b1 a1

c1

b0 a0

c0

0

s2

s1

s0
© 1999 M. Murdocca and V. Heuring

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A B Cin

Appendix A: Digital Logic

Sum

Cout

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Appendix A: Digital Logic

Sequential Logic
• The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. • There is a need for circuits with memory, which behave differently depending upon their previous state. • An example is a vending machine, which must remember how many and what kinds of coins have been inserted. The machine should behave according to not only the current coin inserted, but also upon how many and what kinds of coins have been inserted previously. • These are referred to as finite state machines, because they can have at most a finite number of states.

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Classical Model of a Finite State Machine
• An FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information.
Inputs io ik fo fm
... ...

Outputs

Combinational logic unit

sn Synchronization signal Delay elements (one per state bit)
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

...

...

State bits
Q0 D0 s0

Qn Dn

...

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Appendix A: Digital Logic

NOR Gate with Lumped Delay
A A B B A+ B A+ B
1 0 1 0 1 0

∆τ

∆τ Timing Behavior
• The delay between input and output (which is lumped at the output for the purpose of analysis) is at the basis of the functioning of an important memory element, the flip-flop.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

S-R Flip-Flop
• The S-R flip-flop is an active high (positive logic) device.

Qt St Rt S Q 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Qi+1 0 0 1 (disallowed) 1 0 1 (disallowed)

S R Q Q ∆τ 2∆τ ∆τ 2∆τ

R

Q

Timing Behavior

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

NAND Implementation of S-R Flip-Flop

S

Q

S

Q

S

Q

R

Q

R

Q

R

Q

R

Q

S

Q

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

A Hazard
A B C AB C B A S Q AB R Q S ∆τ R Q Q ∆τ 2∆τ Timing Behavior Glitch caused by a hazard

• It is desirable to be able to “turn off” the flip-flop so it does not respond to such hazards.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

A Clock Waveform: The Clock Paces the System
Amplitude

Time Cycle time = 25ns

• In a positive logic system, the “action” happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs settle at the correct value when the clock next goes high.
Principles of Computer Architecture by M. Murdocca and V. Heuring
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Appendix A: Digital Logic

Scientific Prefixes
• For computer memory, 1K = 210 = 1024. For everything else, like clock speeds, 1K = 1000, and likewise for 1M, 1G, etc.

Prefix Abbrev. Quantity milli micro nano pico femto atto m µ n p f a 10–3 10–6 10–9 10–12 10–15 10–18

Prefix Abbrev. Quantity Kilo Mega Giga Tera Peta Exa K M G T P E 103 106 109 1012 1015 1018

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

A-52

Appendix A: Digital Logic

Clocked S-R Flip-Flop
S S Q CLK CLK Q R Q ∆τ 2∆τ Timing Behavior Q R

• The clock signal, CLK, enables the S and R inputs to the flip-flop.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Clocked D Flip-Flop
• The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop (next slide) addresses this problem.
D CLK Circuit Q Q CLK Q Q ∆τ D Q Symbol C Q 2∆τ 2∆τ ∆τ D

Timing Behavior

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Master-Slave Flip-Flop
• The rising edge of the clock loads new data into the master, while the slave continues to hold previous data. The falling edge of the clock loads the new master data into the slave.
Master D D QM Circuit CLK C C QS QM QS D Q Symbol Q 3∆τ 2∆τ QS ∆τ 2∆τ 2∆τ ∆τ Slave D QS D CLK

Timing Behavior
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Clocked J-K Flip-Flop
• The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-R flip-flop, because Q enables J while Q’ disables K, and vice-versa. • However, there is still a problem. If J goes momentarily to 1 and then back to 0 while the flip-flop is active and in the reset state, the flip-flop will “catch” the 1. This is referred to as “1’s catching.” • The J-K Master-Slave flip-flop (next slide) addresses this problem.

J CLK K

Q

J Q K Q

Q

Circuit
Principles of Computer Architecture by M. Murdocca and V. Heuring

Symbol
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Master-Slave J-K Flip-Flop

J CLK K

Q

J Q K Q

Q

Circuit

Symbol

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Clocked T Flip-Flop
• The presence of a constant 1 at J and K means that the flip-flop will change its state from 0 to 1 or 1 to 0 each time it is clocked by the T (Toggle) input.

1 T

J

Q T

Q

K Q Circuit

Q Symbol

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Negative Edge-Triggered D Flip-Flop
• When the clock is high, the two input latches output 0, so the Main latch remains in its previous state, regardless of changes in D. • When the clock goes high-to-low, values in the two input latches will affect the state of the Main latch. • While the clock is low, D cannot affect the Main latch.
CLK Q S Main latch D Stores D Stores D

R Q

Principles of Computer Architecture by M. Murdocca and V. Heuring

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A-59

Appendix A: Digital Logic

Example: Modulo-4 Counter
• Counter has a clock input (CLK) and a RESET input. • Counter has two output lines, which take on values of 00, 01, 10, and 11 on subsequent clock cycles.
Time (t) 4 3 2 1 0 00001 RESET q0 4 3 2 1 0 Time (t) 01100 01010 D Q D Q s1 CLK Q s0 Q

3-bit q1 Synchronous s0 Counter s1

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Output 00 state

Output 01 state 0/01

State Transition Diagram for Mod-4 Counter

RESET 1/00

A
1/00

B

q1 q0

1/00 0/10 0/00 1/00

C

0/11

D

Output 10 state
Principles of Computer Architecture by M. Murdocca and V. Heuring

Output 11 state
© 1999 M. Murdocca and V. Heuring

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Appendix A: Digital Logic

State Table for Mod-4 Counter

Input Present state A B C D Next state 0

RESET 1 A/00 A/00 A/00 A/00 Output

B/01 C/10 D/11 A/00

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

State Assignment for Mod-4 Counter

Present state (St)

Input 0 A:00 B:01 C:10 D:11

RESET 1 00/00 00/00 00/00 00/00

01/01 10/10 11/11 00/00

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Truth Table for Mod-4 Counter
RESET s1 (t) r(t) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 s0 (t) 0 1 0 1 0 1 0 1 s1 s0 (t+1) q1 q0 (t+1) 01 10 11 00 00 00 00 00 01 10 11 00 00 00 00 00 s0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t) s1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t) q0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t) q1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Logic Design for Mod-4 Counter
RESET

CLK

DQ s1 Q

q1

DQ s0 Q

q0

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Example: A Sequence Detector
• Example: Design a machine that outputs a 1 when exactly two of the last three inputs are 1. • e.g. input sequence of 011011100 produces an output sequence of 001111010. • Assume input is a 1-bit serial line. • Use D flip-flops and 8-to-1 Multiplexers. • Start by constructing a state transition diagram (next slide).

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

A-66

Appendix A: Digital Logic

Sequence Detector State Transition Diagram 0/0
• Design a machine that outputs a 1 when exactly two of the last three inputs are 1.
0/0

D
1/0 0/0

B
0/0 1/0

E
1/1 0/0

A
0/0 1/0

F
0/1

1/1

C
1/0

G
1/0

Principles of Computer Architecture by M. Murdocca and V. Heuring

© 1999 M. Murdocca and V. Heuring

A-67

Appendix A: Digital Logic

Sequence Detector State Table
Input Present state A B C D E F G 0 B/0 D/0 F/0 D/0 F/0 D/0 F/1 X 1 C/0 E/0 G/0 E/0 G/1 E/1 G/0

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Sequence Detector State Assignment
Input and Next state state at and output at time t time t+1 s 2 s1 s 0 x Input Present state A: B: C: D: E: F: G:
S 2S 1S 0

s2 s1 s0 z 0 0 0 1 1 1 0 1 1 1 0 1 1 1 d d 0 1 1 0 0 1 1 0 0 1 1 0 0 1 d d 1 0 1 0 1 0 1 0 1 0 1 0 1 0 d d 0 0 0 0 0 0 0 0 0 1 0 1 1 0 d d

X 0
S 2S 1S 0Z

1
S 2S 1S 0Z

000 001 010 011 100 101 110

001/0 011/0 101/0 011/0 101/0 011/0 101/1

010/0 100/0 110/0 100/0 110/1 100/1 110/0

(a)

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (b)

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Sequence Detector Logic Diagram

0 x 1 x 1 x 1 0

000 001 010 011 100 101 110 111

x x x x x x x 0

000 001 010 011 100 101 110 111

D Q S2 Q

D Q S1 Q

x x x x x x x 0

000 001 010 011 100 101 110 111

0 0 0 0 x x x 0

000 001 010 011 100 101 110 111

D Q S0 Q

Z

CLK

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Example: A Vending Machine Controller
• Example: Design a finite state machine for a vending machine controller that accepts nickels (5 cents each), dimes (10 cents each), and quarters (25 cents each). When the value of the money inserted equals or exceeds twenty cents, the machine vends the item and returns change if any, and waits for next transaction. • Implement with PLA and D flip-flops.

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Vending Machine State Transition Diagram
1/0 = Dispense/Do not dispense merchandise A dime is 1/0 = Return/Do not return inserted a nickel in change 1/0 = Return/Do not N/100 D/110 return a dime in change N/000 A 0¢ Q/101 B 5¢ D/000 Q/111 D/000 N/000 Q/111 D/100
Principles of Computer Architecture by M. Murdocca and V. Heuring

Q/110

D 15 ¢ N/000 N = Nickel D = Dime Q = Quarter
© 1999 M. Murdocca and V. Heuring

C 10 ¢

A-72

Appendix A: Digital Logic

Vending Machine State Table and State Assignment
Input P.S. A B C D N 00 B/000 C/000 D/000 A/100 D 01 C/000 D/000 A/100 A/110 Q 10 A/110 A/101 A/111 B/111 Input P.S. s 1 s0 A:00 B:01 C:10 D:11 N x1 x0 00 01/000 10/000 11/000 00/100 Q D x1 x0 x1 x0 01 10 s 1 s0 / z 2 z 1 z 0 10/000 11/000 00/100 00/110 (b) 00/110 00/101 00/111 01/111

(a)

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

PLA Vending Machine Controller
x1 x0 5×5 PLA z2 z1 z0
s1 s0 x1 x0

Q D s0 (a) Q D s1 CLK

0 1 2 4

P resent state C oin B ase 10 equivalent

D ispense N ext R eturn nickel state R eturn dim e

5 6 8 9 10 12 13 14

s1 s0 x1 x0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (b)

s1 s 0 z 2 z 1 z 0 0 1 0 d 1 1 0 d 1 0 0 d 0 0 0 d 1 0 0 d 0 1 0 d 1 0 0 d 0 0 1 d 0 0 1 d 0 0 1 d 0 1 1 d 1 1 1 d 0 0 1 d 0 0 0 d 0 0 1 d 0 1 1 d 0 0 0 d 0 0 1 d 0 0 1 d 0 0 1 d (c)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

s1

s0

z2

z1

z0

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Moore Counter
• Mealy Model: Outputs are functions of Inputs and Present State. • Previous FSM designs were Mealy Machines, in which next state was computed from present state and inputs. • Moore Model: Outputs are functions of Present State only.
0 0 z0 z1 1 0 x 1 00 01 4-to-1 10 MUX 11 D Q S0 Q z0

00

01

1

1 00 01 4-to-1 MUX 10 11 0 CLK

11
0 1

10

D Q S1 Q

z1

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Four-Bit Register
• Makes use of tri-state buffers so that multiple registers can gang their outputs to common output lines.
D3 D Q D2 D Q D1 D Q D0 D Q

Write (WR) CLK Enable (EN)

WR D3 D2 D1 D0 EN Q3 Q2 Q1 Q0

Q3

Q2

Q1

Q0

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Left-Right Shift Register with Parallel Read and Write
c0 c1

c1 c0 D3 Shift left output Shift right input D2 D1 D0 Shift right input

D Q CLK Enable (EN)

D Q

D Q

D Q

Shift right output

Q3

Q2

Q1

Q0

Control c1 c0 0 0 1 1 0 1 0 1

Function No change Shift left Shift right Parallel load Shift right input Shift left output c c0 1 D3 D2 D1 D0 Q 3 Q2 Q1 Q 0 Shift right output Shift right input

Principles of Computer Architecture by M. Murdocca and V. Heuring

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Appendix A: Digital Logic

Modulo-8 Counter
• Note the use of the T flip-flops, implemented as J-K’s. They are used to toggle the input of the next flip-flop when its output is 1.
1 CLK Enable (EN) RESET J Q K 1 J Q K 1 J Q K

Q2

Q1

Q0

CLK ENABLE RESET MOD(8) COUNTER Q2 Q1 Q0 Q0 Q1 Q2 Timing Behavior
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring