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1 Research Article

2 Aggressive Exclusion of Scan Flip-Flops from

3 Compression Architecture for better Coverage and
4 Reduced TDV: Hybrid Approach
5 Pralhadrao Shantagiri 1 and Rohit Kapur 2,*
6 1 Research Scholar, Department of Computer Science, Jain University, #1/1-1, Atria Towers Palace Road,,
7 Bangalore, Karnataka 560 001, India;

8 2 IEEE Fellow and Research Guide, Department of Computer Science, Jain University, #1/1-1, Atria Towers
9 Palace Road, Bangalore, Karnataka 560 001, India;

10 * Correspondence:;

11 Received: date; Accepted: date; Published: date

12 Abstract: The scan-based structural testing methods went through numerous invention in scan and
13 compression technique to reduce TDV (Test Data Volume) and TAT (Test Application Time). The
14 compression techniques lead to test coverage (TC) loss and test patterns count (TPC) inflation when
15 higher compression ratio is targeted. This happens because of correlation issues introduced by
16 these techniques. To overcome this issue, we propose new hybrid scan compression technique,
17 aggressive exclusion (AE) of scan cells from compression for increasing overall TC and reduce TPC.
18 This is achieved by excluding scan cells which contribute to 12% to 43% of overall care bits, from
19 compression architecture and placing them in multiple scan chains with dedicated scan-data-in
20 and scan-data-out port. The scan cells selection to be excluded from compression technique is done
21 based on detailed analysis of the last 95% of patterns from patterns set to reduce correlation. The
22 results show the significant improvement in TC up to 1.33% and reduction in TPC up to 77.13%.

23 Keywords: Design For Test, Scan Compression, Patterns inflation, Patterns count, Test coverage,
24 Automatic Test Pattern Generator, Test Data Volume, Test Application Time, Scan Chain.


26 1. Introduction
27 Scan compression technology is improving with technology node shrinking from µm to 5 nm
28 and also further reducing. So, more and more logic is being packed in to the design. This lead to
29 introduction of new faults specific to process technology and need of methodology to detect them.
30 The cost of IC (Integrated Circuit) structural testing is increasing and it is most significant part of the
31 overall manufacturing cost. In the last few decades, many DFT (Design for Test) techniques
32 including scan compression schemes have been developed. These are being used in the industry to
33 do structural tests to detect manufacturing defects for structural correctness of DUT (Design under
34 Test). The basic idea behind structural test is to ensure combinational and sequential logic present in
35 the design function as expected without any defects in them. The scan-based techniques are required
36 to reduce TAT, TDV and cost of IC testing. The reduction in TDV helps to lower the number of test
37 data bits being stored on the ATE (Automatic Test Equipment).

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39 Figure 1. Showing stages of scan methodologies evolution.

40 In scan mode, all the scan cells of chains need to have input test pattern get loaded into them
41 before applying into circuit to detect the targeted faults. In scan mode TAT increases because of
42 serial shifting of test data into the scan chain. It also increases power consumption as many scan cells
43 get toggled simultaneously. The scan architecture is shown in Figure 1(a). To overcome the demerits
44 of scan mode testing, scan chains partitioning is proposed and one such method is described in[1].
45 This is a framework based multiple scan paths[2-3] having unique scan-data-input and
46 scan-data-output. This architecture has been shown in Figure 1(b). The dis-advantage of this method
47 is the need of many scan-data-input and scan-data-output ports. This drawback lead to further
48 invention in scan-based testing. This invention lead to numerous scan compression techniques of
49 different types. The various scan compression techniques researched in the last few decades have
50 been reviewed in the Sec. 2. Today scan compression technique is the most popular structural faults
51 testing method of IC Testing. The general scan compression architecture[2-3] has been shown in
52 Figure 1(c).
53 Though scan compression techniques reduce TDV and TAT but lacks to detect certain faults
54 which are detectable in scan mode. This is because of the ATPG constraint for correlation of scan
55 cells value. The correlation across scan cells is introduced by scan compression architecture when
56 same ATE channel broadcasts test data into multiple internal scan chains. Hence because of this
57 correlation, it reduces overall TC. Few of the TC reduction cases introduced by compression scheme
58 have been described in detail in Sec. 3. Maintaining high TC is very important in IC testing. More
59 the test coverage, the IC is more defect free and safer to use in an Automotive, Medical,
60 Aeronautical, safety critical devices and etc.

61 Both scan mode and scan compression mode have advantages and dis-advantages. Let us
62 consider scan mode, in which all scan cells are controllable and observable. Hence there is no
63 correlation introduced by the scan mode and achieves better test coverage. But need more TAT as
64 the length of the scan chain in scan mode is larger and needs more shift cycles to shift one pattern.
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65 This is equal to the total number of scan cells present in the scan chain. Where as in scan
66 compression mode, scan chain is partitioned into many internal scan chains and test data is fed into
67 these internal scan chains through few scan-data-in ports. This reduces many shift cycles per
68 pattern and helps to reduce overall TAT. These factors help to reduce the cost of IC testing. But scan
69 compression introduces correlation across scan cells in the internal scan chains which is not present
70 in the full scan mode. This affects the TC and shoots up the TPC when compression ratio is
71 increased. Hence to take advantage of both scan mode and scan compression mode, need hybrid
72 approach, which is mixture of both to reduces TPC at same test coverage. This led to the research of
73 the method proposed.

74 The method proposed in this paper is referred to as “Aggressive Exclusion of scan cells from
75 Compression”. In short we refer it as ‘AE method’ in the subsequent sections of this paper. This
76 method helps to reduce the correlation among free variables and spread out (fan-out cone) of scan
77 cells output. We analyzed scan load test patterns. The initial 5% patterns achieve 56% to 86% of
78 overall TC. The last 95% of patterns achieve remaining 18% to 39.17% of the TC. Hence we
79 considered last 95% of test patterns for our analysis. Our research is focused on these patterns to
80 analyze correlation and TC loss issues to reduce TPC and increase TC. There are scan cells those
81 need to have specified value in most of the scan load test patterns. The main focus of the AE
82 method is to increase the TC and reduce TPC by detecting faults which are non-detectable in
83 compression technique. This is essential in an Automotive, Medical, Avionics and safety critical
84 devices which use ICs. The AE method motto is to increase TC and reduce TPC by excluding scan
85 cells those contribute to higher correlation in compression architecture and stitching them in
86 separate scan chains with dedicated assignment of scan-data-input and scan-data-output port. The
87 AE method is a hybrid compression architecture which incorporates the advantages of both scan
88 and scan compression. The AE method architecture is shown in Figure 1(d).

89 This paper is structured as follows: Sec. 2, details out the background of scan compression
90 technology including different types of compression technologies. Sec. 3 provides different TC loss
91 and TPC inflation cases introduced by scan compression technique. Sec. 4 depicts the proposed “AE
92 Method” in detail and flow chart describing pre and post AE method in steps. Sec. 5 details out the
93 algorithm developed in the AE method to exclude scan cells from compression technique. The Sec. 6
94 presents the procedure of AE Method. The Sec. 7 presents the results and Sec. 8 summaries the
95 conclusion of the AE method.

96 2. Background of Scan Compression Technology

97 Various scan-based techniques have been proposed in the literature. Following are the
98 categories of scan compression technologies invented by different researchers in the past.

99 The structural scan-based testing methods can be classified into following categories:

100 2.1. Partial scan

101 In Partial scan design some percentage of flip-flops are converted into scan flip-flops and
102 remaining remains as non-scan cells. This methodology uses sequential ATPG to detect faults as
103 many non-scan cells need one or more capture cycles to detect the faults. Numerous techniques have
104 been proposed to select the subset of scan cells to be selected to convert them into scan cells. Merits
105 of partial scan are reduced area overhead and improved performance. It reduces achievable fault
106 coverage because limited contrallability and observability of the sub set of scan cells. Increased
107 sequential depth in partial scan contributes to increase in TAT. The various category of partial scan
108 compression techniques have been invented. Namely Testability Analysis[2], Test patterns
109 generation[2-5], Structural analysis[2-5], Hybrid approaches[2-7], Layout driven[8], Timing and
110 retiming driven[9-10] and Order scan cells or reset sequence based[11].
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111 2.2. Fully scan-based techniques

112 2.2.1. Random access

113 In Random Access Scan[2] each scan cell is directly controlled and observed as unique address
114 is assigned to it through decoder circuit. This is similar to the way we access memory location by
115 address. Each and every scan cell can be controlled and observed directly and no need to shift in test
116 load data into all the scan cells of the chain. Hence, it leads to reduced TDV and TAT. This method
117 suffers from issue of increased area overhead due to huge address decoder and routing scan data
118 input to each and every scan cell. This also needs additional logic circuit and routing to observe the
119 actual output of each scan cell. Hence it is not adopted by the industry.

120 2.2.2. Code based techniques

121 The code based techniques[2] partition the scan load test pattern into the sub set and assign
122 code to each such partition. So that overall TDV is reduced. These techniques achieve good scan
123 compression. The decompressor which gets coded word from the ATE and decodes them and
124 supplies to the internal scan chains. These techniques are not employed by industry as increased
125 TAT, area overhead and complex control logic. These techniques are weak in exploiting correlation
126 in test patterns. The Fixed to Fixed, Fixed to Variable, Variable to Fixed and Variable to Variable are
127 types of code based compression techniques[2].

128 2.2.3. Linear decompressor based techniques

129 In this technique test data is supplied by ATE to combinational or sequential circuit or both
130 linear and sequential circuit which in turn transfers data into the internal scan chains. These
131 networks act as expanding network. These techniques are good in exploiting the unknown values in
132 the scan load test pattern. These decompressors can be expressed in the form of set of linear
133 equations and computation can be done rapidly. The demerit of these techniques is the need of
134 change in the ATPG process.

135 For example: Suppose tester is supplying input test data through m-bits chains to linear
136 decompressor. The linear decompressor expands these data bits into n-bits internal scan channel
137 (output sub-space of decompressor), such that n >= m.

138 There are two types of linear decompressor namely:

139 (a) Linear combinational decompressor: The linear combinational decompressor is made up of
140 combinational logic, which spreads the input test data received from ATE into output space of
141 decompressor. The output space of decompressor is connected into many internal scan chains.
142 The XOR[2] network is the commonly used circuit in linear decompressor[2-3, 12].

143 (b) Linear sequential decompressor: These decompressors are constructed using LFSRs, ring
144 generator and cellular automata[2-3]. There are two types of sequential decompressors.

145 (1) Fixed length sequential decompressor: The fixed length sequential decompressor
146 techniques make use of the previous state value of scan slice to calculate new value in
147 current clock cycle. The linear combinational decompressors suffer from handling more
148 specified values in scan load test patterns and is the worst case scenario. This is handled
149 better in sequential decompressors to achieve better compression. The sequential
150 decompressor performance increases with increased number of sequential cells in it. This
151 compression technique gets test load patterns fed from ATE to sequential logic (LFSR or
152 cellular automata or ring generators) and then distributes this data to internal scan chains
153 through combinational logic like XOR network. This compression technique suffers from
154 encoding efficiency when more care bits are specified in the scan load test set[2-3].

155 (2) Variable length sequential decompressor: This scan compression technique allows varying
156 number of free variables to be used for each test cube. The method provides improved
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157 encoding efficiency and increased cost as need of control logic. The demerit of this
158 technique is need of gating channel. Various variable length linear sequential
159 decompressors are proposed[2-3].

160 (3) Hybrid (both linear and non-linear) linear decompressor: These scan compression
161 techniques exploit the don’t care bits and correlation in scan load test patterns. Hence this
162 technique achieves better compression compared to Linear sequential and combinational
163 decompressors[2-3].

164 2.2.4. Broadcasting based techniques

165 The popular scan compression techniques which broadcast the same load test data into many
166 internal scan chains through decompressor. These techniques are independent of patterns and
167 inserts internal scan chains between decompressor and compressor. These techniques reduce TAT
168 and TDV to the large extent compared to other compression techniques and are adopted by the
169 industry. These techniques introduces structural dependencies in internal scan chains which leads to
170 loss of TC. Numerous research has been carried out in this area. Following are the categories of
171 broadcast based scan compression techniques. These techniques have low routing and area
172 overhead.

173 (a) General (without reconfiguration) broadcasting based techniques: The scan compression
174 technique[13] proposed supplies scan load test patterns through single dedicate scan-data-input
175 to multiple scan chains which are connected to it in fan-out fashion. Compared to scan mode,
176 this technique reduces TDV and TAT but suffers from correlation of specified values in the scan
177 cells.The technique proposed in [14] shares scan-data-in among multiple circuits to supply scan
178 load test patterns. Various scan compression techniques in this category are proposed in [2-3, 4,
179 15-17].


181 Figure 2: Showing a) General streaming scan compression architecture and b) Hybrid Compression
182 architecture of proposed AE method.

184 (b) Broadcasting techniques with static reconfiguration: The static reconfiguration based
185 broadcasting scan decompressor techniques use sequential and combinational logic at
186 decompressor with reconfiguration capability to handle correlation among scan cells in the scan
187 chains. These techniques are adopted and being used in the industry. In this technique
188 reconfiguration of scan chains takes place while applying new scan load test pattern. The
189 method proposed in Illinois scan dual mode[19] architecture reduces length of scan chain in
190 shared scan-data-in mode and reduced TAT [18-20].

191 (c) Broadcasting techniques with dynamic reconfiguration: In this scan compression technique,
192 selection of different configuration of scan chains happens while loading scan load test patterns.
193 This feature of the broadcast scan compression leads to better compression, TAT and TDV. The
194 demerit of these techniques is need of more control information.
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195 a) Broadcasting techniques with streaming dynamic reconfiguration: The streaming

196 decompressor based broadcasting scan compression[21] which supports reconfiguration of
197 scan compression for better compression ratio, reduced TAT and TDV. In this technique
198 each clock cycle is applied when data fed from the ATE to decompressor and same data is
199 streamed into internal scan chains in diagonal fashion. The Figure 2(a) shows this
200 architecture. The Figure 3(a) shows diagonal correlation introduced in the streaming
201 compression technique. Our proposed AE method is validated using scan synthesis
202 technique and details are provided in subsequent sections.

203 b) Broadcasting techniques with non-streaming dynamic reconfiguration: In these scan

204 compression techniques scan load test data is loaded from ATE into shift register of
205 decompressor. Then data is shifted into each scan slice of scan chains per clock cycle basis.
206 These compression techniques have horizontal dependency which is shown in Figure 3(b).
207 These techniques are adopted by the industry and provide better compression, TAT and
208 TDV. But suffer from compression induced correlation of scan cells. See [22-27] for more
209 details.
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211 Figure 3. Showing both streaming and non-streaming

212 compression correlation in free variables when scan load
213 test data is shifted into them.

214 (d) Broadcasting techniques with patterns overlapping: The theme behind pattern overlapping is to
215 identifying the overlap of scan load test pattern for the given scan load pattern, which is already
216 generated by the ATPG. The test pattern overlap is identified by shifting non-overlapping
217 beginning bits and finding overlapping bits at the end of the current scan load test set with next
218 scan load test set. This way new pattern is created. This technique is good in achieving higher
219 compression ratio and TDV reduction. Statistical analysis based patterns overlapping method for
220 scan architecture has been proposed in[28]. The patterns overlapping based technique to reduce
221 TDV and TAT is proposed in[29]. Dynamic structures used to store the test data by encoding
222 sparse test vector. The patterns overlapping technique by exploiting the unknown values in scan
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223 load test patterns is proposed in [30]. The deterministic patterns slice overlapping technique
224 based on LFSR reseeding is proposed in [31] to reduce TDV.

225 (e) Broadcasting techniques with hybrid approach

226 a) Broadcasting and patterns overlapping: This hybrid technique takes advantage of both the
227 broadcasting and the pattern overlapping scan compression techniques. These techniques
228 achieve better compression ratio and TDV. The TAT of these techniques is huge as they need
229 to figure out next pattern based on current to identify the overlapping pattern. The hybrid
230 approach combining broadcast based scan architecture along with patterns overlapping is
231 proposed in [32]. The broadcast based patterns overlapping technique has been proposed in
232 [33]. It is claimed to reduced TAT with increased TDV.

233 b) Broadcasting techniques with mixture of both compression and scan mode: The hybrid
234 approach which is combination of scan and compression to improve patterns count in
235 presence of unknown in scan unload patterns is proposed in [34]. This reduced patterns
236 count significantly. The proposed AE method does improvement in TC and reduction in
237 TPC based on analysis of scan load patterns.

238 (f) Broadcasting techniques with circular scan architecture: In this architecture first scan load test
239 pattern is loaded into all the internal scan chains. Each scan channel output is connected back to
240 the input of the same channel. These chains have option to get scan load data from ATE or
241 shift-in capture response of current pattern as next scan load test pattern for the chain. The
242 demerit of these techniques is pattern being circulated is non-deterministic and no industry
243 adoption.

244 (g) Broadcasting techniques with tree based architecture: The scan tree based compression
245 techniques based on compatible scan cells considering ATPG generated test patterns. The scan
246 tree based techniques’ success depends on the presence of compatible sets of scan cells. These
247 techniques are not feasible for highly compacted scan test patterns. A scan tree based
248 compression technique algorithm which is suitable to handle the scan cells having least or no
249 compatible in the given scan test patterns is proposed in [38]. The dynamically configurable dual
250 mode scan tree based compression architecture is proposed in [39]. This works in both scan mode
251 and scan tree mode. The tree based LFSR exploiting the merits of both input scan-data-in sharing
252 and re-use methodology is presented in [40] to test both sequential and combinational circuits.

253 3. Coverage reduction cases because of scan compression

254 The AE method proposed is validated using scan synthesis tool which is broadcasting based
255 scan compression technique. The TC reduction happens in scan compression technique as each data
256 bit of decompressor register distributes same test data into multiple internal scan chains which are
257 connected between codec. The Figure 3 (a) and Figure 3(b) shows streaming and non-streaming
258 decompressor with the data being shifted into an internal scan chains through decompressor
259 register. The free variables show the correlation in scan cells. The correlation among scan cells of
260 internal scan chains exist as many internal scan chains are driven by same data bit. Different
261 compression techniques have different correlation issues. Consider streaming compression
262 technique, where in diagonal correlation introduced by scan compression technique causes TC loss
263 and TPC inflation when high compression ratio is targeted. In case of sequential decompressor with
264 scan slice correlation (horizontal correlation) causes the TC loss as the scan cells of slice are
265 structurally dependent. Both the scenarios have been depicted in Figure 3 (a) and Figure 3(b).

266 The correlation introduced by streaming and non-streaming decompressor are handled with
267 different load modes. The hardware which is part of decompressor decides the mode bits decoding
268 and choosing of internal scan chains group. Each mode represents different group of scan chains to
269 be chosen to shift-in data from decompressor serial register into them. These load modes help to
270 reduce this correlation issue some extent as modes are limited in number but not completely. This
271 leads to TC loss and TPC inflation.
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272 The reduced TC in scan compression has direct influence on DPM (Defects Per Million) i.e.
273 test escapes that are delivered to users. This impacts yield issues. Hence to overcome this issue,
274 need compression technique which increases TC by detecting additional faults and reduces TPC.

275 The ATPG generates test patterns for all the detectable faults in DUT. This set of patterns is
276 called patters set. Each and every pattern present in the ATPG patterns set generated for DUT
277 contains specified value as logic-0, logic-1 and logic-X. The logic-0 and logic-1 is called as care bit.
278 The number of such bits present in the pattern are called as care bits. The percentage of care bits
279 present in the pattern set is called as care bits density. The calculation of care bits and percentage of
280 care bits is shown in Eq. (1) and Eq. (2) respectively. The care bit to be loaded into desired scan cell
281 is decided by the ATPG tool to detect the target faults from the faults list.

282 The test sets generated for scan mode comprises bits having logic-0, logic-1 and logic-x. The
283 care bits present in the scan load test patterns set is calculated as follows:

1 aij  1 or aij  0
284 cb   aij Where  (1)
r 1 c 1 0 otherwise .

285 Where A is the decompressor outerspace matrix of size r x c having all the test sets. Total
286 number of bits present in the whole test set is calculated as

287 tb  r x c (2)

288 Where ‘r’ is the number of test patterns present in the test set and ‘c’ is length of pattern. The
289 percentage of care bits present in the test set generated for DUT is calculated as follows:

291 pcb  (100 x cb)  tb (3)

293 Where ‘cb’ and 'tb' are shown in Eq. (1) and Eq. (2) respectively.

294 Such care bits generated by the ATPG tool to detect faults for each scan cells varies. Some scan
295 cells need to have specified values most of the time, some very few times and some not at all. It
296 means some scan cells will have always logic-X. Usually scan cell(s) those have wide fan-out
297 combinational logic or shared wide combinational logic, need to be specified more number of times.
298 If such scan cells are driven by same ATE channel, then it becomes difficult for the ATPG tool to
299 load different desired values when required to detect the faults. The Figure 4 shows the fan-out
300 cone which depicts this scenario. The number of load modes are limited and not possible to load
301 desired value into necessary scan cells of chain because of dependency.
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303 Figure 4. Showing Fan-out cone correlation a) correlation of fan-out cone b) correlation of
304 fan-out cone introduced by scan compression architectures.

306 As shown in Figure 4 (a), FF1, FF2, FF3, FF4, FF5 and FF6 are driving combinational fan-out
307 cone. These are overlapping cones. The cone area has been numbered from 1 to 15. Here area
308 numbered 1 to 6 have no correlation and easy to detect the faults present in these area. Whereas
309 combinational logic cones numbered from 7 to 15 have scan cells correlation. To detect the faults
310 present in area 13, the scan cells FF4, FF5 and FF6 need to have desired specified values. So these
311 cells will have specified values in most of the patterns based on number of faults exist in the area
312 13. Here FF5 has wide fan-out cone and need to have desired value most of the time to detect faults
313 in it. Suppose if those scan cells are fan-out from same Data bit of serial register of decompressor,
314 then most of the faults present in area 1 to 15 could not be detected. This leads to loss of TC and
315 patterns inflation. The Figure 4 (b) shows the fan-out of Data bit D0 and D1. So FF1, FF2 and FF3
316 will have same ATPG desired values most of the time in a load mode. The FF4, FF5 and FF6 are
317 connected to D1 as fan-out. If these scan cells need to have different desired values, it is not
318 possible. So these FF4, FF5 and FF6 have value in a load mode. This creates structural correlation
319 and leads to patterns inflation and loss of TC.

320 The conflict introduced by the decompressor has two important property which leads to TC
321 loss and TPC inflation are:

322 1) The fault being detected must have structural correlation on two or more scan cells.

323 2) These two or more scan cells must be present in different scan chains and fan-out from
324 same data bit/ATE channel.

325 The diagonal scan slice in the streaming decompressor and horizontal scan slice in
326 non-streaming decompressor will have two or more scan chains correlated to each other as free
327 variables being shifted from same data bit/ATE channel.

328 The number of diagonal correlation ‘Ndc’ (streaming decompressor) depends on the length of
329 the longest internal scan chain connected between codec and number of internal scan chains. Let us
330 take ‘L’ as length of longest internal scan chain and ‘M’ as the number of internal scan chains.

331 Ndc  L  M - 3 (4)

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332 Nff  (L x M) - 2 (5)

333 Where as Nff is the number of scan cells in correlation.

334 The number of horizontal correlation present in non-streaming decompressor based

335 architecture is calculated as follows:

336 Nhc  L (6)

337 Nffh  L x M (7)

338 Where as Nhc is horizontal correlation and Nffh is the number of scan cells in horizontal
339 correlation..

340 But at least two scan cells are not in correlation in diagonal correlation of each mode and in
341 horizontal correlation all scan cells are in correlation.

342 Figure 5 shows coverage loss case in both streaming and non-streaming decompressor
343 broadcasting architecture. Here scan cells SFF31, SFF22 and SFF13 will always have either logic-0 or
344 logic-1. Hence ‘G2’ XOR gate will always produce logic-0 as an output. Hence stuck-at-0 fault on
345 output of ‘G2’ can not be detected. The fault on ‘G1’ is difficult to detect as always gate produces
346 logic-0. Hence stuck-at-0 on gate ‘G1’ can not be detected. The reason is, structural correlation
347 introduced by compression technique. Such faults can be detected in scan mode as there is no such
348 structural correlation. Similarly the faults on fan-out cone also difficult to detect because of
349 structural correlation. The Figure 5 shows fan-out cone correlation and issues of coverage loss. The
350 coverage loss seen because of fan-out cone correlation. To overcome such coverage loss, the AE
351 method is proposed.

353 Figure 5. Showing coverage loss cases
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354 3.1 Sparseness in output space of decompressor

355 When the load test data is loaded into the internal scan chains, the content of scan cells of
356 internal scan chains look as shown in Figure 6. These scan chains and cells represent a matrix having
357 logic-0, logic-1 and logic-X before replacing logic-X with care bit. The sparseness of this matrix is
358 calculated based on the specified values for each scan cell. This decompressor output space (Matrix)
359 can be sparse or dense of specified value. The dense output space indicates the chance of TPC
360 inflation and TC loss. This can be linked to care bits density. The Figure 6 shows the output space of
361 decompressor with sample values loaded into all the scan cells. We can see diagonal correlation of
362 values for one pattern. The AE method increases sparseness of care bits in this space by pulling scan
363 cells those need to be specified in most of the test patterns. It is shown in the Figure 7, which shows
364 the representative AE method. The sparseness of care bits ‘scb’ in the output space of decompressor
365 and sparse density ‘sd’ is defined as follows:


367 Figure 6. Showing sparseness of care bits in Compression technique along with correlation in
368 scan load test patterns shifted-in.

369 scb  cb  tb (8)

370 sd  100 - scb (9)

371 Where ‘cb’ and ‘tb’ are from Eq. (1) and Eq. (2) respectively.
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373 Figure 7. Showing sparseness of care bits in AE method compression architecture and external chains are
374 packed with more care bits.

375 The AE method reduces the sparseness and sparse density of the output space of
376 decompressor in compression technique.

377 4. The AE Method Proposed

378 4.1 Scan Cells Exclusion and Care Bits Density

379 The AE method excludes very few percentage of scan cells from compression architecture to
380 place them into the multiple external chains. The Figure 8 shows the percentage of cells being moved
381 out of compression technique. Such scan cells contribute to 12% to 43% of overall care bits density
382 of the DUT which is shown in Figure 9. The AE method performs better in this range. If care bits
383 density of excluded scan cells increases above 43% of overall care bits density takes away the
384 advantage of the AE method achieved.


386 Figure 8. Showing percentage of scan cells being excluded in the AE method.

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388 The number of scan cells to be excluded ‘Ce’ from compression technique is calculated as
389 follows:

390 Ce  L x N (10)

391 Where ‘L’ is length of the external chain and ‘N’ is the number of external chains being created
392 by the AE method.

394 Figure 9. Showing percentage of care bits contribution of scan cells being excluded from compression
395 technique.

396 The ‘L’ is calculated as follow:

397 L  Lich x Sr (11)

398 Where Lich is length of the longest internal scan chain between codec and ‘Sr’ is the length of
399 decompressor serial register.

400 The AE method is shown in Figure 7 with sparseness of specified bits and Figure 2(b) shows
401 general AE method architecture. The number of the external chains need to be calculated is as
402 follows:

403 Nech  Chcs / 2 (12)

404 Where Nech represents the number of external scan chains being created in the AE method and
405 Chcs. The number of external chains created are half of the total scan-data-in budget of compression
406 technique. This increases sparseness of care bits in output space of decompressor and leads to
407 improved TC and reduced TPC. Hence remaining ATE channels are allotted to compression
408 technique in the AE method maintaining overall scan-data-in and scan-data-out ports budget same.

409 4.2 The AE method

410 In this proposed work, we analyzed the scan load test patterns generated for the different
411 designs for different scan configuration synthesis. Generally first 5% of the test patterns detect most
412 of the faults which are easy to detect faults. It includes faults which can be detected using random
413 test patterns and deterministic patterns. Hence we notice first 5% of patterns contain more care bits
414 specified to detect faults. This first 5% of patterns detect around 56% to 86% of faults of total
415 detectable fault set generated by the ATPG tool. So, it means remaining 18% to 39.17% faults are
416 detected by last 95% of the patterns. Table 1 shows percentage of TC achieved with first 5% of TPC
417 and last 95% of TPC. Hence we consider this remaining 95% of the patterns for our analysis to
418 increase the overall TC and reduced TPC. We find the issues which cause coverage loss due to
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419 compression technique introduced correlation, fan-out cone of Data bits of serial register and the AE
420 method to overcome this.

421 Table 1. Showing percentage of TC achieved with 5% and last 95% of TPC

Percentage of
Test Patterns Type of Faults
TC achieved

Easy to detect faults including

First 5% of TPC 56% to 86%
random and deterministic.

Last 95% of TPC 18% to 39.17% Hard-to-detect faults

423 The compression techniques reduces TC to some extent because of structural correlation
424 introduced by them not detecting certain faults. But these faults are detectable in scan mode. So, in
425 the AE method, we identify such scan cells and exclude them from the compression architecture.
426 Such excluded scan cells are placed in an external scan chains. The placing of such scan cells in the
427 external chain is left to the scan synthesis tool to decide. Hence it does not affect the scan routing.
428 Moreover excluded scan cells are very few in number compared to total number of scan cells
429 present in the DUT. The excluded scan cells in the external scan chains with dedicated scan-data-in
430 and scan-data-out ports provide more controllability and observability without structural
431 correlation. This helps to detect more faults which are not detectable in compression technique as
432 they take all the advantages of scan mode. Same time compression technique after excluding these
433 scan cells provide better compressibility as care bits in the output space of the decompressor are
434 more sparse.

435 Once the TC reaches 90%, the ATPG needs to produce many patterns to achieve every fraction of
436 percentage of test coverage. To detect last few percentage of faults, the ATPG produces most of the
437 patterns in the patterns set as shown in Table 1.

438 The AE method proposed not only improves overall TC but also helps to reduce TPC. The
439 detailed procedure to select scan cells to be excluded from the compression architecture is shown in
440 Sec. 5. The AE method shows the scan cells to be excluded contributing 12% to 43% of total care bits
441 density leads to improved TC and reduced TPC.

442 The range of percentage of care bits contributed by scan cells are being excluded from the
443 compression architecture is as follows:

min_ cb  (cb x 12)  100

444 (13)
max_ cb  (cb x 43)  100

445 Whether the scan cells which have more specified values in the first 5% of patterns may reside
446 inside or outside compression technique. There is no difference as these are detecting large
447 percentage of faults. Hence retained them in compression technique. If the number of external
448 chains increase more than 50% of I/O budget, it increases patterns inflation, reduces TC and takes
449 away the benefit achieved in the AE method. If DUT has more scan cells having fan-out cone as
450 shown in Figure 6, the percentage of care bits of scan cells being excluded increases. Our study
451 shows up to 43% is acceptable in most of the cases to take the advantage of both scan mode and
452 scan compression technique. The detailed procedure to decide the number of scan cells to be
453 excluded is described in Sec. 5. Calculating the length of each external scan chain is shown in Eq.
454 (11). The procedure to select the scan cells to be excluded is described in the Sec. 5. The detailed
455 steps to implement the AE method is shown in Sec. 6.
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456 4.3 The Flow Chart Showing Execution flow of AE method

458 Figure 10. Diagram showing top level flow of execution.

460 The detailed flow of execution of the scan compression and AE method is shown in Figure 10.
461 The flow of execution of scan synthesis is same for both the scan compression and AE method. The
462 only difference is the specification of the external scan chains in AE method. The detailed procedure
463 is depicted in Sec. 6, which has “Phase1_FlowOfExecution()” and “PhaseII_FlowOfExecution()”.
464 The numbers written at left of each box in Figure 10 to indicate step number. In flow diagram step 1
465 and step 2 are part of the “Phase1_FlowOfExecution()” and step 4 and step 5 are part of
466 “PhaseII_FlowOfExecution()”. The algorithm to extract scan cells to include them into the external
467 scan chains is depicted in Sec. 5 and same has been shown in step 3 of flow diagram.

468 5. Aggressive Exclusion of scan cells Algorithm from Compression Architecture

469 The following algorithm GetExtScanChains() takes set of scan mode test patterns as an input
470 and does analysis of last 95% of patterns which are contributing to the majority of hard to detect
471 targeted faults. Hence first 5% patterns are not considered for analysis. Certain scan cells in these
472 patterns have specified values logic-0 and logic-1. This algorithm extracts some scan cells among
473 large number of scan cells present in the design which need specified values in most of the last 95%
474 of the patterns and contributing to patterns inflation. To reduce correlation introduced by the scan
475 compression, we put such scan cells into multiple external scan chains equal to half of the total
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 17 of 29

476 scan-data-in ports budget. This algorithm returns Chains[] array which includes scan cells for all the
477 external scan chains to be created. If the total care bits density of the scan cells selected for external
478 scan chain between 12% and 43% are considered for AE method. The detailed steps to extract scan
479 cells is presented in this algorithm. This analysis helps to improve TC and reduce TPC at same
480 coverage level. So, method proposed has both external chains and remaining scan cells in the
481 compression mode to take advantage of both the modes. The time complexity of this algorithm is
482 around O(n) + O (n log n). The run time of this algorithm is less and varies according to the design
483 complexity and size of the patterns set.


485 Algorithm: GetExtScanChains()

486 Inputs:

487 Ts - Set of scan load test stimulus

488 Si - Number of Scan-Data-In Ports assigned to scan compression technique


490 Output:

491 Chains[] - Array of external chains holding relevant scan cells excluded from compression technique


493 Let Np = SizeOf(Ts) // Number of scan load test stimulus

494 Let Skip5Per = Np X (5/100) // Skipping first 5% Patterns

495 Let C = 1

496 While (Ts[C] < Skip5Per)

497 Let C=C+1

498 EndWhile

499 While (C <= Np)

500 Let Tp = Ts[C]

501 Let Len = Length[Tp]

502 Let N = Len

503 While (Len > 0)

504 If (Tp[Len] == ‘0’ OR Tp[Len] == ‘1’) // considering care bit 0 or 1

505 SFF[Len] = SFF[Len] + 1

506 CB = CB + 1

507 EndIF
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508 Let Len = Len -1

509 EndWhile

510 Let C = C + 1

511 EndWhile

512 O_SFF[] = ORDER_IN_DESCENDING(SFF, N) // sorting scan cells in descending order based on

513 specified value ranking of scan cell

514 Let LenExt = FindLenCh() // Finding length of the external scan chains

515 Let N_Ext = Si / 2 // Number of external scan chains equal to 50% of scan-data-in ports

516 Let Max = CB X (43/100) // maximum up to 43% of total cbd

517 Let Min = CB X (12 /100) // minimum 12% of total cbd

518 Let Chains[] = CreateExtChains(N_Ext, O_SFF, LenExt, Max, Min) // set of external scan chains

519 Return Chains[] // Set of external scan chains

520 End

522 This algorithm calls FindLenCh() to find the length of the external chain and which is also
523 shown in Eq. (11). The FindLenCh() algorithm considers two inputs namely longest internal scan
524 chain present in the codec and length of the decompressor register to arrive length of an external
525 scan chain.


527 Algorithm: FindLenCh()

528 Input:

529 Test Protocol file of compression technique


531 Output:

532 eChLen - length of an external chain


534 Read Test protocol file of compression technique

535 Find length of longest internal scan chain as ‘L’

536 Find serial register length as ‘Srl’

537 eChLen = L + Srl // Length of an external scan chain calculation

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538 Return eChLen

539 End

541 Finally ‘GetExtScanChains()’ calls CreateExtChains() algorithm to create external scan chains
542 and returns it back. Then it returns the Chains() sent back to PhaseII_FlowOfExecution() algorithm
543 depicted in the Sec. 6. The criteria to create external scan chains is the range of care bits density the
544 the scan cells contribute. If this care bits density is less than minimum threshold or more than
545 maximum limit chains will be descarded.


547 Function: CreateExtChains()

548 Inputs:

549 N_Ext - Number of external chains to be formed

550 O_SFF - Set scan cells having specified value in number of scan load test stimulus

551 LenExt - Length of each external chain being formed

552 Max - 43% value of care bits density

553 Min - 12% value of care bits density


555 Output:

556 Chains[] - To hold scan cells of an external chains


558 Let Cnt = 1

559 Let CB = 0

560 Let N = SizeOf(O_SFF)

561 Let X = 1

562 While (Cnt < N)

563 Let CB = CB + O_SFF[Cnt] // care bits density

564 If (CB <=Max) // Check whether care bits density of scan chain is less than or equal to max limit

565 Let Chains[N_Ext][x] = O_SFF[Cnt]

566 If (X < LenExt)

567 Let X = X + 1
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568 Else

569 Let X = 1

570 Let N_Ext = N_Ext - 1

571 EndIf

572 Else

573 Break

574 EndIf

575 EndWhile

576 If (CB < Min) // if care bits density is less than minimum threshold ignore such chains

577 delete Chains[]

578 EndIf

579 Return Chains[]

580 End


582 6. Procedure of Aggressive Exclusion Method

583 The complete procedure of execution of proposed AE method has been depicted in two phases.
584 The Phase-I is used to generate the ATPG patterns for scan compression architecture considering the
585 input DFT configuration provided. The total TPC and TC are measured and recorded. The Phase-I
586 flow of execution is shown in the algorithm ‘PhaseI_FlowOfExecution()’. Below given is the
587 algorithm for same.


589 Algorithm: Phase I_FlowOfExecution()

590 Inputs:

591 Verilog_netlist - Verilog netlist which is DUT

592 Verilog_libraries - Verilog libraries for lib cells

593 DFT configuration - ATE channels, Internal chains and etc.


595 Outputs:

596 TC - Test coverage

597 TPC - Test Patterns Count

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599 Read verilog_netlist

600 Read verilig_libraries

601 Input scan synthesis configuration, including chains count, ATE channels, and etc.

602 Invoke scan synthesis and insertion engine

603 Write out scan synthesized output netlist

604 Write out scan protocol file

605 Invoke ATPG engine to generate test patterns for all the faults including stuck-at, transition and etc.

606 Measure percentage of TC and TPC

607 End

609 Before invoking Phase-II of execution which is the AE method, we invoke the algorithm
610 named ‘GetExtScanChains()’. This is depicted in Sec. 5 along with detailed steps. The algorithm
611 returns the ‘Chains[]’ array having created external scan chains based on the AE method’s scan cells
612 exclusion algorithm.

613 The invocation of PhaseII_FlowOfExecution() will take place by passing ‘Chains[]’ array which
614 has the external scan chains specified to create external scan chains. Once Phase-II of execution is
615 completed, we measure TPC and TC for full run and TPC is compared at same TC level as of
616 Phase-I are measured and recorded.

617 Then percentage of TC improvement is calculated as shown in Eq. 16 and TPC reduction at
618 same TC as of compression technique is calculated and shown in Eq. 15.

619 The percentage of test coverage is calculated as follows:

620 TC  Ndf / Ntdf (14)

621 Where Ndf is number of detected faults and Ntdf is number of detectable faults.

622 The improvement in TPC ‘TPCimpr’ when both compression technique and AE method are
623 compared is as follows:

624 TPCimpr  100 x TPcae / TPCcs (15)

625 Where TPCcs and TPcae are test patterns count achieved by compression technique and the
626 AE Method at same TC of compression technique respectively. Both TPCcs and TPcae are shown in
627 column 5 and 7 of Table 4. respectively.

628 The percentage of improvements in TC ‘TCimp’ when compression technique is compared

629 with AE method is as given below:

630 TCimp  (100 xTCae)  TCcs (16)

631 Where TCae and TCcs are TC achieved by AE method and compression technique
632 respectively. These are shown in column 6 and 10 of Table 4.

633 Below given is the algorithm for Phase-II flow of the execution.
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635 Algorithm: PhaseII_FlowOfExecution()

636 Inputs:

637 Verilog _netlist - Verilog netlist which is DUT

638 Verilog_libraries - Verilog libraries for lib cells

639 DFT configuration - ATE Channels, Internal scan chains and External scan chains specification


641 Outputs:

642 TC - Test Coverage

643 TPC - Test Patterns Count

644 TCF - Test Coverage at full run of AE method

645 TPCF - Test Patterns Count at full run of AE method



648 Read verilog_netlist

649 Read verilig_libraries

650 Input scan synthesis configuration, including internal scan chains, number of ATE channels, and etc.

651 Allot 50% scan -data-in ports into the external chains

652 Allot 50% of scan-data-in ports into compression technique

653 Specification for external scan chains creation

654 Invoke scan synthesis and insertion engine

655 Write out scan synthesized output netlist

656 Write out scan protocol file

657 Invoke ATPG engine to generate test patterns for all the faults including stuck-at, transition and etc.

658 Measure percentage of TC and TPC at same coverage as produced at Step (8) of Phase I

659 Measure percentage of TCF and TPCF at the end of full run and compare it with Step (8) of Phase I

660 End

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662 7. Experimental Results

663 The experiments were carried out on the designs shown in Table 4. These designs are of varying
664 sizes ranging from 28K to 530K scan cells. The results were generated for both with AE method and
665 without AE method. The without AE method includes scan compression technique where as ‘with
666 AE method’ includes both external scan chains and scan compression technique. The AE method
667 excludes certain scan cells based on the procedure depicted in Sec. 5 and puts them into the multiple
668 external scan chains. The column 1, 2 ,3 and 4 represent name of the circuit, number of scan cells
669 present in the circuit, total number of ATE channels allocated in each configuration for scan
670 synthesis and total number of internal scan chains used respectively.

671 Each external scan chain is assigned scan-data-in and scan-data-out port to it. The total
672 scan-data-in and scan-data-out budget for the compression scheme remains same. In AE method
673 50% of the scan-data-in and scan-data-out ports are assigned to the external scan chains and
674 remaining into compression scheme. The results generated for compression scheme is shown in
675 column 5 and column 6. The column 5 shows the TPC generated to achieve the TC shown in Column
676 6 for compression scheme. The results generated for AE method and measured at same coverage as
677 shown in column 6 are presented in column 7 and column 8. The column 7 represents the TPC
678 generated to achieve TC shown in column 8 for AE method at same coverage as column 6. The
679 results for complete run of the AE method are shown in column 9 and column 10. The column 9 has
680 TPC to achieve the TC shown in column 10 by detecting faults which are not detectable in
681 compression technique. The column having heading “#TPC” and “%TC” represents the total
682 patterns count and test coverage achieved by respective configuration of the circuit. The column 11
683 shows percentage of overall test coverage improvement for each configuration and column 12
684 represents the percentage of TPC reduction when compared with scan compression technique at
685 same TC level. The column 13 represents the percentage of care bits density of the total care bits
686 density of the circuit contributed by the scan cells which are part of the external scan chains of the
687 respective configuration of the AE method.

688 Both the results have been compared and shown in Table 4. The “AE method” column indicates
689 the results generated for proposed method. The “scan compression” method has say 16 inputs, then
690 these inputs have been distributed between multiple external chains and compression architecture
691 of the AE method. So overall scan-data-input and scan-data-output ports budget remains same. We
692 compared both “#TPC” and “%TC” of scan compression technique with the AE method. The AE
693 method shows good improvement in the TC and also in TPC at same TC level. Both TC and TPC are
694 very important in structural tests. The better TC helps to achieve improved yield and reduced DPM.
695 Where as patterns count helps to reduce the overall TAT and test cost of the IC. The AE method has
696 no area overhead. The AE method need no change in the ATPG to generate test patterns. The AE
697 method proposed improves TPC and TC significantly in the DUT. Our experiments on 6 designs
698 show improvements in both TPC and TC. The results have been shown in Table 4. with totally
699 having 13 columns.

700 We observed both TPC reduction and TC improvement in AE method. The summary of
701 percentage of improvements in TPC reduction for each design when compared at same TC of
702 compression technique for each circuit is shown in Table 2. The circuit C1 achieved highest TPC
703 reduction up-to 77.13% and C2 achieved TPC reduction up-to 76.13%. This is significant
704 improvements in the TPC reduction. It means same TC as compression scheme is achieved with the
705 less number of TPC. This reduces TAT and shift cycles. Proportionately reduces over all cost of the
706 IC testing.

707 Table 2: The overall percentage of TPC reduction in circuits

Name of the circuit Overall TPC reduction

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C1 Up to 77.13%

C2 Up to 76.13%

C3 Up to 24.91%

C5 Up to 22.68%

C6 Up to 17.55%

709 The summary of percentage of improvements in TC for each design when compared to scan
710 compression technique for each circuit is shown in Table 3. Each fraction of TC improvement improves
711 the QoR (Quality of Results) of IC production. This helps to reduce DPM and which is significant. This
712 shows more targeted faults than scan compression method are detected with the AE method and which is
713 significant in terms of TC. Once TC crosses 90% it is hard to improve the coverage and for each fraction of
714 TC, ATPG generates many patterns to achieve it. Significant improvements in TC is achieved in C1 and C2
715 and good improvements in other circuits.

716 Table 3. Showing overall TC improvement in the circuits

Percentage of TC
Name of Circuit

C1 Up to 1.33%

C2 Up to 1.22%

C3 Up to 0.09%

C4 Up to 0.08%

C5 Up to 0.16%

C6 Up to 0.16%

718 In Table 4, column 12, we have not shown percentage of TPC reduction for some
719 configurations as those configuration are producing better TC rather than TPC reduction. Hence
720 they are compared for percentage of TC improvement as TC is not negotiable.

721 The AE method proposed performs better for both TPC reduction and TC for the designs
722 having fan-out cone correlation. Otherwise it produces better TC compared to scan compression.

723 The AE method achieved significant TPC reduction in C1 and C2. In C1 it achieved up to
724 77.13% TPC reduction and 1.33% TC improvements where as in C2 it achieved up to 76.13% TPC
725 and 1.22% TC improvements. The TPC reduction is compared at same TC level as of compression
726 technique. The TC is compared at full runs of both the method.

727 8. Conclusions
728 The AE method proposed significantly increases fault detection and improves TC. The TC is
729 very critical to enhance the yield of the product and to reduce DPM. The AE method combines
730 merits of scan compression and scan. Hence it improves controllability and observability of the scan
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 25 of 29

731 cells which need to be specified most of the times in scan load test patterns. This is achieved by
732 excluding very few percentage of scan cells from compression architecture and placing them into the
733 multiple scan chains outside compression technique. The scan cells being excluded is decided based
734 on the correlation analysis carried out considering free variables and scan compression technique
735 introduced correlation. The number of the external scan chains are always equal to half the
736 scan-data-inputs assigned to compression technique. Hence in the AE method compression
737 technique and external scan chains, each use 50% of the total scan-data-input and scan-data-output
738 ports budget. Hence over all scan-data-input and scan-data-output ports budget remains the same.
739 The AE method increases TC when total care bits density of the scan cells excluded from
740 compression technique is in the range of 12% to 43%.

741 The AE method proposed does not introduce restriction on placing scan cells in the external
742 scan chains and this is decided by the scan synthesis tool used. The AE method proposed has no
743 area overhead. The scan synthesis in AE method is carried out using DFTMax-Ultra[41] and test
744 patterns generation using TetraMax[42]. The AE method increased TC in all the cases and reduced
745 TPC for same TC for most of the designs used in our experiment.

746 Author Contributions: Research is carried out by the first author under the guidance and
747 supervision of second author. Both authors contributed to make this manuscript and research.

748 Funding: This research received no external funding.

750 Conflicts of Interest: The authors declare no conflict of interest.


752 Table 4. Showing results comparison of scan compression technique with AE method proposed.

AE Method at same Full Run of AE External Chains

Scan Compression Improvements
#Scan #SI /
coverage Method contributing
Circuit #Chains
cells SO
#TPC %TC #TPC %TC #TPC %TC %TC %TPC %Care bits

1 2 3 4 5 6 7 8 9 10 11 12 13

C1 28K

6 200 2207 74.71 1058 74.74 2791 75.04 0.33 52.06 30%

8 200 2339 74.66 1577 74.68 2797 74.89 0.23 32.58 29%

8 400 2765 75.61 888 76.20 3111 76.83 1.22 67.88 26%

10 500 2851 7595 652 76.43 3494 77.45 0.50 77.13 26%

16 400 1782 75.42 2306 75.42 2820 75.50 0.08 -- 34%

16 800 2139 76.95 568 77.76 2650 79.09% 1.33 73.45 26%

C2 147K

8 800 6889 94.42 4117 94.42 7337 94.66 0.24 40.24 24%
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 26 of 29

8 1000 6151 94.74 4925 94.74 7427 94.90 0.16 19.93 20%

8 2000 8266 92.43 4150 92.80 9253 93.76 0.33 49.79 12%

10 500 9658 84.56 13644 84.56 16539 84.60 0.04 -- 36%

10 1000 5657 94.37 5481 94.37 7317 94.48 0.11 3 28%

12 600 9784 95.17% 6478 95.00% 0.17 33.79 43%

12 1200 13326 93.50 3181 93.53 8040 94.61 1.11 76.13 24%

16 1000 5380 94.51 3272 94.5 6411 94.78 0.27 39.18 36%

16 1500 12310 92.94 3586 92.94 7563 93.31 0.37 70.87 31%

16 1600 6950 93.02 2333 93.03 8408 94.24 1.22 66.43 25%

16 2000 7550 92.28 5922 92.28 8484 92.43 0.15 21.56 21%

24 2000 6378 93,76 5365 93.76 7735 93.90 0.14 15.88 29%


8 400 12080 84.57 15787 84.57 17528 84.59 0.02 -- 37%

36 1800 11979 84.63 8995 84.63 12683 84.72 0.09 24.91 38%

40 2000 9615 84.64 10557 84.64 13499 84.70 0.06 -- 37%


8 1000 8198 95.90 9052 95.90 9651 95.95 0.05 --


20 2000 8596 10396 95.90 11137 95.93 0.03 -- 27%


8 1600 8654 95.88 12445 95.88 13245 95.94 0.06 -- 22%

24 1200 6906 95.90 7676 95.90 8252 95.93 0.03 -- 37%

12 2000 9770 95.89 10374 95.89 11951 95.97 0.08 -- 25%

36 1800 6444 95.88 7020 95.88 7402 95.93 0.05 -- 37%

C5 530K

20 13024 92.90 11925 92.90 13746 93.06 0.16 8.84 36%

12 600 6625 92.91 7182 92.92 7361 92.94 0.03 -- 40%

12 1200 6773 92.91 7786 92.91 8233 92.97 0.06 -- 38%

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 27 of 29

20 1000 6461 92.88 8658 92.88 9226 92.91 0.03 -- 40%

16 800 8351 92.87 7491 92.87 8197 92.93 0.06 10.30 40%

16 1600 7352 92.92 9696 92.93 9947 92.95 0.03 -- 38%

10 800 9650 92.88 7461 92.88 7674 92.90 0.02 22.68 40%

10 1600 11054 92.89 15392 92.89 16452 92.96 0.07 -- 36%

20 2000 8309 92.93 10182(9+11) 92.95 10329 92.96 0.03 -- 38%

10 3000 14389 92.95 15945 92.95 17594 93.03 0.08 -- 32%


16 800 6027 93.29 6653 93.29 7812 93.32 0.03 -- 29%

20 1000 6033 93.29 6453 93.29 7474 93.31 0.02 -- 29%

8 400 6199 93.29 6871 93.29 7803 93.31 0.02 -- 28%

36 1800 6305 93.27 5169 93.27 7822 93.36 0.09 18 29%

36 3600 7270 93.29 5994 93.29 10100 93.45 0.16 17.55 22%


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