You are on page 1of 14

# LNA Design (v3) Prof.

Patrick Yue

## Low-Noise amplifiers – Input matching

1) Resistor match:

RS RL

R1=RS

- Attenuates signal
- Estimate noise factor F: (ignore 1/f and induced gate noise)

RS

+ +
vR12 vgs vo
vRS2 gmvgs ind2 RL -
-
R1

𝑅1
𝑣𝑂 = [𝑅 (𝑣𝑅𝑠 + 𝑣𝑅1 )𝑔𝑚 + 𝑖𝑛𝑑 ] 𝑅𝐿
1 +𝑅𝑠

2
⇒ ̅̅̅̅̅̅ ̅̅̅̅ ̅̅̅̅ ̅̅̅̅
𝑅1
𝑣𝑂2𝑡𝑜𝑡 = [(𝑅 ) (𝑣 2 2 2 2 2
𝑅𝑠 + 𝑣𝑅1 )𝑔𝑚 + 𝑖𝑛𝑑 ] 𝑅𝐿
1 +𝑅𝑠
2
̅̅̅̅ 𝑅1
𝑣𝑂2𝑠 = (𝑅 +𝑅 ) ̅̅̅̅
𝑣𝑅2𝑠 𝑔𝑚
2
𝑅𝐿2
1 𝑠
̅̅̅̅̅
𝑅1 +𝑅𝑠 2 ̅̅̅̅̅
2
𝑣𝑅 1 𝑖2
⇒ 𝐹 =1+ 1
̅̅̅̅̅ +( ) ∙ 𝑔2 ∙ ̅̅̅̅̅
𝑛𝑑
𝑣2 𝑅𝑠 𝑅1 𝑚
2
𝑣𝑅𝑠

𝑅1 = 𝑅𝑆 , ̅̅̅̅
𝑖2𝑛𝑑 = 4𝑘𝑇𝛾𝑔𝑑𝑜 ∆𝑓 and ̅̅̅̅
𝑣𝑅2𝑠 = 4𝑘𝑇𝑅𝑆 ∆𝑓
𝑅 4 4𝑘𝑇𝛾𝑔𝑑𝑜 ∆𝑓
⇒ 𝐹 = 1 + 𝑅1 + 𝑔2 ∙
𝑠 𝑚 4𝑘𝑇𝑅𝑆 ∆𝑓

4 𝛾𝑔𝑑𝑜
⇒ 𝐹 =2+ ∙
𝑔𝑚 𝑅𝑠 𝑔𝑚

𝑔 𝛾 1
Define 𝛼 = 𝑔 𝑚 , Long-channel ⇒ 𝛼 ≃ 1, Typically ≃ 1.8 due to short-channel effects
𝑑𝑜 𝛼

4 𝛾
⇒ 𝐹 =2+𝑔 ∙𝛼
𝑚 𝑅𝑠

1
LNA Design (v3) Prof. Patrick Yue

⇒ 𝑁𝐹 = 10 log10 (2 + ⋯ ) >3dB!

2) Common-gate stage:

RL

RS

vRS2
Rin=RS
- No input attenuation
- No extra noise sources
- Estimate F due to thermal noise only

G D io

+ +
vgs gmvgs ind2 vo
- RL -
vx
RS S

vRS2

𝑣𝑥 −𝑣𝑅𝑠
𝑖𝑜 = = −𝑔𝑚 𝑣𝑥 + 𝑖𝑛𝑑
𝑅𝑠

⇒ 𝑣𝑥 = 𝑖𝑜 𝑅𝑠 + 𝑣𝑅𝑠
∴ 𝑖𝑜 = −𝑔𝑚 (𝑣𝑅𝑠 + 𝑖𝑜 𝑅𝑠 ) + 𝑖𝑛𝑑
⇒ 𝑖𝑜 (1 + 𝑔𝑚 𝑅𝑠 ) = −𝑔𝑚 𝑣𝑅𝑠 + 𝑖𝑛𝑑
𝑔𝑚 𝑖𝑛𝑑
⇒ 𝑖𝑜 = − 𝑣𝑅𝑠 +
1+𝑔𝑚 𝑅𝑠 1+𝑔𝑚 𝑅𝑠

## Calculate input impedance for power match:

2
LNA Design (v3) Prof. Patrick Yue

+
vgs gmvgs
- RL
vtest
Rin itest

𝑣𝑡𝑒𝑠𝑡 1
⇒ 𝑅𝑖𝑛 = =𝑔
𝑖𝑡𝑒𝑠𝑡 𝑚

## ⇒ Set 𝑅𝑖𝑛 = 𝑅𝑠 = 1⁄𝑔𝑚 for power match

𝑔 𝑖 𝑣 𝑖𝑛𝑑
𝑖𝑜 = − 1+𝑔𝑚 𝑅 𝑣𝑅𝑠 + 1+𝑔𝑛𝑑 𝑅 = − 2𝑅𝑅𝑠 +
𝑚 𝑠 𝑚 𝑠 𝑠 2

̅̅̅̅̅̅
𝑣2𝑅𝑠 𝑖𝑛𝑑
̅̅̅̅̅̅
2
𝑖̅̅̅̅̅̅̅
2 + ̅̅̅̅̅
𝑜𝑡𝑜𝑡 4𝑅2 4 𝑖2
⇒𝐹= ̅̅̅̅ = 𝑠
̅̅̅̅̅̅
𝑣2
= 1 + 𝑅𝑠2 ̅̅̅̅̅
𝑛𝑑
2
𝑖2𝑜𝑠 𝑅𝑠 𝑣𝑅𝑠
4𝑅2 𝑠

4𝑘𝑇𝛾𝑔𝑑𝑜 ∆𝑓 𝛾𝑔𝑑𝑜
⇒ 𝐹 = 1 + 𝑅𝑠2 ∙ = 1 + 𝛾𝑔𝑑𝑜 𝑅𝑆 = 1 +
4𝑘𝑇𝑅𝑆 ∆𝑓 𝑔𝑚

⇒ 𝐹 =1+𝛼
𝛾
← Long-channel lower bound = 2.2 dB

## 3) Obtain resistive input without resistors or C-G input:

it

RL + +
vt vgs Cgs gmvgs
- RL
-

ZS
ZS
Zin

𝑖 𝑣𝑡 −𝑣𝑔𝑠
𝑣𝑔𝑠 = 𝑠𝐶𝑡 , = 𝑖𝑡 + 𝑔𝑚 𝑣𝑔𝑠
𝑔𝑠 𝑍𝑠

𝑖
⇒ 𝑣𝑡 = 𝑖𝑡 𝑍𝑠 + (1 + 𝑔𝑚 𝑍𝑠 )𝑣𝑔𝑠 = 𝑖𝑡 𝑍𝑠 + (1 + 𝑔𝑚 𝑍𝑠 ) ∙ 𝑠𝐶𝑡
𝑔𝑠

𝑣𝑡 1 𝑔𝑚 𝑍𝑠
⇒ 𝑍𝑖𝑛 = = 𝑍𝑠 + 𝑠𝐶 +
𝑖𝑡 𝑔𝑠 𝑠𝐶𝑔𝑠

## (a) 𝑍𝑠 = 𝑅𝑠 (resistor degeneration)

3
LNA Design (v3) Prof. Patrick Yue

RS

Zin Cgs
𝑔𝑚 𝑅𝑠 1 1+𝑔𝑚 𝑅𝑠 1+gmRs
𝑍𝑖𝑛 = 𝑅𝑠 + + 𝑠𝐶 = 𝑅𝑠 +
𝑠𝐶𝑔𝑠 𝑔𝑠 𝑠𝐶𝑔𝑠

1
(b) Capacitive degeneration: 𝑍𝑠 =
𝑠𝐶𝑠

-gm
ω CsCgs
2

Negative CsCgs
1 1 𝑔 1 1 𝐶 𝑔 resistance Cs+Cgs
⇒ 𝑍𝑖𝑛 = 𝑠𝐶 + 𝑠𝐶 + 𝑠𝐶𝑚 ∙ 𝑠𝐶 = 𝑠𝐶 (1 + 𝐶 𝑠 ) − 𝜔2 𝐶𝑚𝐶
𝑠 𝑔𝑠 𝑔𝑠 𝑠 𝑠 𝑔𝑠 𝑠 𝑔𝑠

→ Used in oscillators

Ls

gmLs
Cgs
1 𝑔𝑚 𝐿𝑠 Cgs
⇒ 𝑍𝑖𝑛 = 𝑠𝐿𝑠 + +
𝑠𝐶𝑔𝑠 𝐶𝑔𝑠

## → We have created a real part in 𝑍𝑖𝑛 without a resistor

⇒ Low-noise power match
𝑔𝑚 𝐿𝑠
Set = 50Ω (𝑅𝑠𝑜𝑢𝑟𝑐𝑒 )
𝐶𝑔𝑠

𝜔 𝑇 𝐿𝑠

4
LNA Design (v3) Prof. Patrick Yue

## • Assume frequency of operation is ω0

• Input impedance at ω0

𝑔𝑚 𝐿𝑠 1
• 𝑍𝑖𝑛 = + 𝑗 [𝜔(𝐿𝑠 + 𝐿𝑔 ) − ]
𝐶𝑔𝑠 𝜔0 𝐶𝑔𝑠

Set 𝜔 𝑇 𝐿𝑠 = 𝑅0 resonance at ω0
1
for power match 𝜔0 =
√(𝐿𝑠 +𝐿𝑔 )𝐶𝑔𝑠

## • At ω0, the load is a pure resistor RP (or conductor CP)

• For the present, we will assume that the cascode device does not contribute noise. Of course, this
is not accurate; however, as long as the parasitic capacitance Cx is small, M2’s noise contribution can
be ignored.

## → We have a total of three noise sources:

̅̅̅̅
--- source noise: 𝑉 2
𝑅0

2 = 4𝑘𝑇𝛿𝑔 Δ𝑓
𝑔

## → id and ig are correlated through a correlation coefficient, c,

which is defined as follows:

̅̅̅̅̅

## (Van der Zied: 𝑐 = −𝑗0.395 for long-channel saturated FET)

5
LNA Design (v3) Prof. Patrick Yue

→ We shall consider each noise source separately and pay attention to correlation between id and

𝑖2𝑜𝑢𝑡,𝑡𝑜𝑡 .

## (a) Source noise contribution

𝜔0 (𝐿𝑠 +𝐿𝑔 ) 1
Define 𝑄 = =
𝜔𝑇 𝐿𝑠 +𝑅0 𝜔0 𝐶𝑔𝑠 (𝑅0 +𝜔𝑇 𝐿𝑠 )

𝜔0 (𝐿𝑠 +𝐿𝑔 ) 1
or 𝑄 = =
2𝑅0 2𝜔0 𝐶𝑔𝑠 𝑅0

## (b) Drain noise contribution

𝑣𝑠
KCL at S: 𝑔𝑚 𝑣𝑔𝑠 + 𝑖𝑑 + 𝑠𝐶𝑔𝑠 𝑣𝑔𝑠 =
𝑠𝐿𝑠

𝑣𝑔𝑠 +𝑣𝑠
KCL at G: + 𝑠𝐶𝑔𝑠 𝑣𝑔𝑠 = 0
𝑅0 +𝑠𝐿𝑔

𝑠𝐿𝑠 𝑖𝑑
Solve: 𝑣𝑔𝑠 = −
1+𝑠(𝐿𝑠 𝑔𝑚 +𝐶𝑔𝑠 𝑅0 )+𝑠 2 (𝐿𝑠 +𝐿𝑔 )𝐶𝑔𝑠

𝐿𝑠
𝑖
𝑗𝜔0 𝐿𝑠 𝑖𝑑 𝐶𝑔𝑠 𝑑
At 𝑠 = 𝑗𝜔0 : 𝑣𝑔𝑠 = − 𝑔 𝑚 𝐿𝑠 =−
[1−𝜔02 (𝐿𝑠 +𝐿𝑔 )𝐶𝑔𝑠 ]+𝑗𝜔0 ( +𝑅0 )𝐶𝑔𝑠 2𝑅0
𝐶𝑔𝑠

0 at 𝜔0

6
LNA Design (v3) Prof. Patrick Yue

𝐿
𝑔𝑚 𝐶 𝑠
𝑔𝑠 𝑅0
𝑖𝑜𝑢𝑡2 = 𝑖𝑑 + 𝑔𝑚 𝑣𝑔𝑠 = 𝑖𝑑 − 𝑖𝑑 = 𝑖𝑑 − 𝑖 ,
2𝑅0 2𝑅0 𝑑
1
𝑖𝑜𝑢𝑡2 = 𝑖𝑑
2

## (c) Gate Noise Contribution

Lg G iout
+
ig Cgs vgs gmvgs
R0 -
Ls S

𝑣𝑠
KCL at S: 𝑖𝑔 + = (𝑔𝑚 + 𝑠𝐶𝑔𝑠 )𝑣𝑔𝑠
𝑠𝐿𝑠

𝑣𝑔𝑠 +𝑣𝑠
KCL at G: 𝑖𝑔 = 𝑠𝐶𝑔𝑠 𝑣𝑔𝑠 +
𝑅0 +𝑠𝐿𝑔

𝑅0 +𝑠(𝐿𝑠 +𝐿𝑔 )
Solve: 𝑣𝑔𝑠 =
1+𝑠 2 (𝐿 𝑠 +𝐿𝑔 )𝐶𝑔𝑠 +𝑠(𝐶𝑔𝑠 𝑅0 +𝐿𝑠 𝑔𝑚 )

## 𝑅0 +𝑗𝜔0 (𝐿𝑠 +𝐿𝑔 )

At 𝑠 = 𝑗𝜔0 : 𝑣𝑔𝑠 = [1−𝜔2 (𝐿
0 𝑠 +𝐿𝑔 )𝐶𝑔𝑠 ]+𝑠(𝐶𝑔𝑠 𝑅0 +𝐿𝑠 𝑔𝑚 )

## 𝑗𝜔0 (𝐿𝑠 +𝐿𝑔 )

[1+ ]𝑅0
𝑅0
0 at 𝜔0 = 𝐿 𝑖𝑔
𝑗𝜔0 (𝑅0 +𝑔𝑚 𝐶 𝑠 )𝐶𝑔𝑠
𝑔𝑠

1 1+𝑗2𝑄 1
𝑄= = 𝑖𝑔 𝑄𝑅0 = (2𝑄 − 𝑗) 𝑖
2𝜔0 𝐶𝑔𝑠 𝑅0 𝑗 2𝜔0 𝐶𝑔𝑠 𝑔
𝜔0 (𝐿𝑠 +𝐿𝑔 )
=
2𝑅0

1 𝑔𝑚 1 𝜔𝑇
𝑖𝑜𝑢𝑡3 = 𝑔𝑚 𝑣𝑔𝑠 = (2𝑄 − 𝑗) 𝑖𝑔 𝑖𝑜𝑢𝑡3 = (2𝑄 − 𝑗) 𝑖
2 𝜔0 𝐶𝑔𝑠 2 𝜔0 𝑔

7
LNA Design (v3) Prof. Patrick Yue

1 1 𝜔𝑇
𝑖𝑜𝑢𝑡,𝑡𝑜𝑡 = 𝑖𝑜𝑢𝑡1 + 𝑖𝑜𝑢𝑡2 + 𝑖𝑜𝑢𝑡3 = 𝑄𝑔𝑚 𝑣𝑅0 + 𝑖𝑑 + (2𝑄 − 𝑗) 𝑖
2 2 𝜔0 𝑔

## Note ̅̅̅̅̅̅̅̅̅̅̅ (𝑋 + 𝑌)(𝑋 + 𝑌)∗ = ̅̅̅̅̅

|𝑋 + 𝑌|2 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ |𝑋|2 + ̅̅̅̅̅
|𝑌|2 + ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑋𝑌 ∗ + 𝑋 ∗ 𝑌

= ̅̅̅̅̅
|𝑋|2 + ̅̅̅̅̅
|𝑌|2 + ̅̅̅̅̅̅̅̅̅̅̅̅̅
2𝑅𝑒(𝑋𝑌 ∗ )

𝑖̅̅̅̅̅̅̅̅̅
2 2 2 ̅̅̅̅̅
2 1 ̅
2 1 2 𝜔𝑇 2 ̅
2 1 ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
∗ 𝜔𝑇
𝑜𝑢𝑡,𝑡𝑜𝑡 = 𝑄 𝑔𝑚 𝑣𝑅0 + 𝑖𝑑 + |2𝑄 − 𝑗| ( ) 𝑖𝑔 + 2𝑅𝑒 {𝑖𝑑 (2𝑄 − 𝑗)
4 4 𝜔0
𝑖𝑔 }
4 𝜔0
2 ̅̅̅̅̅
+ 𝑖̅2𝑑 + (4𝑄 2 + 1)( 𝑇 )2 𝑖̅𝑔2 + 𝑅𝑒 {(2𝑄 − 𝑗) 𝑇 𝑖̅̅̅̅̅
1 1 𝜔 2 𝜔 ∗
= 𝑄 2 𝑔𝑚 2
𝑣𝑅0 𝑑 𝑖𝑔 }
4 4 𝜔0 4 𝜔0

𝑖𝑔 ̅̅̅
2
𝜔 𝑖 𝑖𝑔 ̅̅̅̅̅̅

2 ̅̅̅̅̅
+ 𝑖̅2𝑑 [1 + (4𝑄 2 + 1)( 𝑇 )2 ̅2 + 2𝑅𝑒 {(2𝑄 − 𝑗) 𝑇 𝑑̅2 }]
1 𝜔
= 𝑄 2 𝑔𝑚 2
𝑣𝑅0
4 𝜔0 𝑖𝑑 𝜔0 𝑖𝑑

̅̅̅ ̅̅̅̅̅̅
𝑖∗𝑑 𝑖𝑔 ̅̅̅
𝑖2𝑔
𝑖2𝑔 4𝑘𝑇𝛿𝑔𝑔 Δ𝑓 𝛿𝑔𝑔
Also, ̅̅̅ = = √ ̅2
𝑖2 4𝑘𝑇𝛾𝑔𝑑0 Δ𝑓 𝛾𝑔𝑑0 𝑖
𝑑 √𝑖̅2𝑑 ̅̅̅
𝑖2𝑔 𝑑

## and 𝑐 = −𝑗0.395 = −𝑗|𝑐 | = c!

2 𝛿𝑔 𝛿𝑔𝑔
𝑖̅̅̅̅̅̅̅̅̅ 2 2 ̅̅̅̅̅
2 2 1 ̅
2 2 𝜔𝑇 𝑔 𝜔𝑇
𝑜𝑢𝑡,𝑡𝑜𝑡 = 𝑄 𝑔𝑚 𝑣𝑅0 + 𝑖𝑑 [1 + (4𝑄 + 1) ( )
4 𝜔0 𝛾𝑔𝑑0
−2
𝜔0
|𝑐|√
𝛾𝑔𝑑0
]

𝜔2 𝐶𝑔𝑠
2
Finally, substitute 𝑔𝑔 = and 𝑔𝑚 = 𝜔 𝑇 𝐶𝑔𝑠
5𝑔𝑑0

8
LNA Design (v3) Prof. Patrick Yue

2 𝛿
̅̅̅̅̅̅̅̅̅ 2 ̅̅̅̅̅
𝑖2𝑜𝑢𝑡,𝑡𝑜𝑡 = 𝑄 2 𝑔𝑚 2
𝑣𝑅0 + 𝑖̅2𝑑 [1 + (4𝑄 2 + 1) ( 𝑚 )
1 𝑔
− 2|𝑐|
𝑔𝑚 𝛿
√ ]
4 𝑔𝑑0 5𝛾 𝑔𝑑0 5𝛾

̅̅̅̅̅̅̅̅̅̅̅̅̅
2
𝑜𝑢𝑡,𝑡𝑜𝑡𝑖
Finally, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
2
𝑖𝑜𝑢𝑡,𝑠𝑜𝑢𝑟𝑐𝑒

1 𝑖̅2𝑑 𝑔𝑚 2 𝛿 𝑔𝑚 𝛿
𝐹 =1+ 2 ̅̅̅̅̅ [1 + (4𝑄 2 + 1) ( ) − 2|𝑐| √ ]
4𝑄2 𝑔𝑚 𝑣2 𝑅0 𝑔𝑑0 5𝛾 𝑔𝑑0 5𝛾

1 1 𝛾𝑔𝑑0 1 𝜔0 𝛾𝑔𝑑0
=
2𝑄 2𝑄𝑔𝑚 𝑅0 𝑔𝑚 2𝑄 𝜔𝑇 𝑔𝑚

1 𝜔0 𝛾𝑔𝑑0 𝑔𝑚 2 𝛿 𝑔𝑚 𝛿
𝐹 =1+ [1 + (4𝑄 2 + 1) ( ) − 2|𝑐| √ ]
2𝑄 𝜔𝑇 𝑔𝑚 𝑔𝑑0 5𝛾 𝑔𝑑0 5𝛾

## SN = scaling coefficient, dependent only on Q and process technology

• This is a lower bound on the total noise. Parasitic resistances (due to layout, gate resistance,

𝜔0
• 𝐹 =1+ 𝑆
𝜔𝑇 𝑁

See plot of SN vs Q for different c’s on the next page. We have assumed the following:

𝑔𝑚 1
= , 𝛾 = 3 , 𝛿 = 2𝛾 = 6
𝑔𝑑0 1.8

3 𝜇𝑛
and using long-channel device approximation, 𝜔𝑇 = (𝑉𝑔𝑠 − 𝑉𝑇 )
2 𝐿2

## On the other hand, for short-channel devices (<0.13um),

3𝜇𝑛 𝐸𝑐
𝜔𝑇 ∝
4𝐿
→ linear dependency on L with CMOS device scaling.

9
LNA Design (v3) Prof. Patrick Yue

10
LNA Design (v3) Prof. Patrick Yue

How to set the optimal bias point (for gm) to acheieve low noise?

Recall for a source degenerated C-S LNA, the noise contribution of the device is:

𝜔𝑜 2 𝛾𝑔𝑑𝑜 1 𝑔𝑚 2 𝛿 𝑔𝑚 𝛿
𝐹 =1+( ) [1 + (4𝑄2 + 1) ( ) − 2 |𝐶 | √ ]
𝜔𝑇 𝑔𝑚 2𝑄 𝑔𝑑𝑜 5𝛾 𝑔𝑑𝑜 5𝛾

## If we ignore gate-noise (ie 𝛿 → 0),

𝜔𝑜 2 𝛾𝑔𝑑𝑜 1
𝐹 ≃1+( )
𝜔𝑇 𝑔𝑚 2𝑄

𝑊
For a velocity saturated device, 𝑔𝑑𝑜 = 𝜇𝑛 𝐶𝑜𝑥 ( ) (𝑉𝐺𝑆 − 𝑉𝑇 ),
𝐿

1 𝑊 3 𝜇𝑛 𝐸𝑐
𝑔𝑚 ≃ 2 𝜇𝑛 𝐶𝑜𝑥 ( 𝐿 ) 𝐿𝐸𝑐 and 𝜔 𝑇 = 2 𝐿
2 1
Also, 𝐶𝑔𝑠 = 3 𝐶𝑜𝑥 𝑊𝐿 and 𝑄 = 2𝜔
𝑜 𝑅𝑜 𝐶𝑔𝑠

3 𝜔𝑜 1
⇒ 𝐹𝑉𝑠𝑎𝑡 = 1 + ∙ ∙ 2 𝐸2
(𝑉𝐺𝑆 − 𝑉𝑇 )
2 𝐶𝑜𝑥 𝑊𝑅𝑜 𝜇𝑛 𝑐

⇒ For a given device size, 𝐹𝑉𝑠𝑎𝑡 ↑ as (𝑉𝐺𝑆 − 𝑉𝑇 ) ↑ (or 𝐹𝑉𝑠𝑎𝑡 ↑ as current density ↑)

## For a long-channel device without velocity saturation:

𝑊
𝑔𝑚 = 𝑔𝑑𝑜 = 𝜇𝑛 𝐶𝑜𝑥 ( 𝐿 ) (𝑉𝐺𝑆 − 𝑉𝑇 )
3 𝜇𝑛 (𝑉𝐺𝑆 −𝑉𝑇 )
𝜔𝑇 =
2 𝐿2
𝛾 4 𝜔𝑜2 𝐿4
⇒ 𝐹𝑙𝑜𝑛𝑔 ≃ 1 + ∙
2 (𝑉 −𝑉 )2
2𝑄 9 𝜇𝑛 𝐺𝑆 𝑇

## ⇒ 𝐹𝑙𝑜𝑛𝑔 ↓ as (𝑉𝐺𝑆 − 𝑉𝑇 ) ↑ (or as 𝐼𝑑𝑒𝑛 ↑)

⇒ Optimally want to operate close to the velocity saturation limit for low-noise
gm,gd0
gd0

gm

Iden

11
LNA Design (v3) Prof. Patrick Yue

## LNA Design Procedure:

Typical specifications:

## Supply voltage Vdd 1~4V

(1) First set Rp. In general, this is highly dependent on the process technology. A plot of RP vs Ld
(the drain inductance might look like this):

maximum RP.

## (2) From 𝐴𝑉 = 𝐺𝑚 𝑅𝑃 , calculate the effective transconductance 𝐺𝑚 . Note that 𝐺𝑚 = 𝑄𝑔𝑚 .

(3) For a minimum channel-length device, plot (by simulation or otherwise) gm, gd0, and VGS as
functions of current density ID/W. One way to do this is:
gm, gd0
gd0
(mS/μm)
&
VGS
Vgs (V)
Id gm

## W Iden Id/W (μA/μm)

Lmin +
VGS Higher density,
- Higher IIP3,
Higher noise.
12
LNA Design (v3) Prof. Patrick Yue

## Another option is to plot these in Matlab using analytical expressions:

(𝑉𝐺𝑆 −𝑉𝑇 )2
• 𝐼𝐷 = 𝛽 where
1+𝜂(𝑉𝐺𝑆 −𝑉𝑇 )
1 𝑊
𝛽 = 𝜇0𝐶𝑜𝑥
2 𝐿
and
(𝑉𝐺𝑆 −𝑉𝑇 ) 1 𝜇0
• 𝑔𝑚 = 𝛽 [1 + ] 𝜂=𝜃+
1+𝜂(𝑉𝐺𝑆 −𝑉𝑇 ) 1+𝜂(𝑉𝐺𝑆 −𝑉𝑇 ) 2𝑣𝑠𝑎𝑡 𝐿
𝐼𝐷 1 10−7
= [1 + ] 𝜃≈ 𝑉 −1
𝑉𝐺𝑆 −𝑉𝑇 1+𝜂(𝑉𝐺𝑆 −𝑉𝑇 ) 𝑡𝑜𝑥

μ0, Cox, tox, θ, and vsat can be found from the simulation model file.

• 𝑔𝑑0 = 2𝛽(𝑉𝐺𝑆 − 𝑉𝑇 )

(4) Pick a current density Iden from the plot. We know from analysis that as Iden ↗, (𝑉𝐺𝑆 − 𝑉𝑇 )↗,
F↗, because 𝑔𝑑0 /𝑔𝑚↗ and IIP3↗. Noise vs linearity trade-off. A good compromise is
to operate the device in weak-to-moderate inversion, i.e. (𝑉𝐺𝑆 − 𝑉𝑇 ) ≈ 100~200𝑚𝑉. Once we
know (𝑉𝐺𝑆 − 𝑉𝑇 ), pick off gm from the graph. Note that this is a normalized gm (mS/μm).

(5) Under the assumption that the correlation coeffient c is know, find Q for minimum noise
1 2
scaling factor. Then, Use 𝑄 = to find Cgs, and calculate W from 𝐶𝑔𝑠 = 3 𝐶𝑜𝑥 𝑊𝐿.
2𝜔0 𝐶𝑔𝑠 𝑅0

## (6) Calculate the gm: 𝑔𝑚 = 𝑤 × (𝑛𝑜𝑟𝑚𝑎𝑙𝑖𝑧𝑒𝑑 𝑔𝑚 )

13
LNA Design (v3) Prof. Patrick Yue

𝑔𝑚
(7) Find 𝜔 𝑇 = and use 𝑅0 = 𝜔 𝑇 𝐿𝑠 to find Ls.
𝐶𝑔𝑠

1
(8) Use 𝜔02 = to find Lg.
(𝐿𝑠 +𝐿𝑔 )𝐶𝑔𝑠

(9) For the cascade device, set W and L to be the same as that of M1 as a starting point.

## Usually, the gate of M2 is tied to the power supply Vdd. Since we

know the bias current 𝐼𝑏𝑖𝑎𝑠 = 𝐼𝑑𝑒𝑛 ∙ 𝑊1 , and also the size of M1,
the bias voltage Vx is now fixed.

At this point, verify stability by simulation. | S11| must not exhibit “funny” behavior – you should see
something like

(10) Simulate to find AV, F, and IIP3, and verify that they meet specifications. Also check that Pdiss
is within specifications. If not, iterate steps (4)~(10).

14