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Design 8085 Microprocessor System

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8085 Microprocessor System Block
Diagram

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8085 CPU
U1
36 12
RST-IN AD0 13
1 AD1 14
X1 AD2 15
AD3 16
2 AD4 17
X2 AD5 18
5 AD6 19
6 SID AD7 21
TRAP A8 22
9 A9 23
8 RST 5.5 A10 24
7 RST 6.5 A11 25
RST 7.5 A12 26
10 A13 27
INTR A14 28
11 A15
INTA 30
29 ALE 31
S0 WR 32
33 RD 34
S1 IO/M 3
39 RST-OT 37
HOLD CLKO 4
35 SOD 38
READY HLDA
8085 3
Memory EPROM

U3
10 11
9 A0 O0 12
8 A1 O1 13
7 A2 O2 15
6 A3 O3 16
5 A4 O4 17
4 A5 O5 18
3 A6 O6 19
25 A7 O7
24 A8
21 A9
23 A10
2 A11
A12
20
22 CE
27 OE
1 PGM
VPP
2764

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Memory RAM
U4
10 11
9 A0 D0 12
8 A1 D1 13
7 A2 D2 15
6 A3 D3 16
5 A4 D4 17
4 A5 D5 18
3 A6 D6 19
25 A7 D7
24 A8
21 A9
23 A10
2 A11
A12
20
26 CS1
22 CS2
27 OE
WE
HM6264A

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I/O 8255
U6
34 4
33 D0 PA0 3
32 D1 PA1 2
31 D2 PA2 1
30 D3 PA3 40
29 D4 PA4 39
28 D5 PA5 38
27 D6 PA6 37
D7 PA7
5 18
36 RD PB0 19
9 WR PB1 20
8 A0 PB2 21
35 A1 PB3 22
6 RESET PB4 23
CS PB5 24
PB6 25
PB7
14
PC0 15
PC1 16
PC2 17
PC3 13
PC4 12
PC5 11
PC6 10
PC7
8255

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ROM & RAM Size

• ROM size 8K x 8 bit


13 bit address line A0 - A12
213 = 8192 (0000H - 1FFFH)
• RAM size 8K x 8 bit
13 bit address line A0 - A12
213 = 8192 (0000H - 1FFFH)

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Memory Map

0000H
1FFFH ROM
2000H
3FFFH
RAM
4000H

Not Used

FFFFH
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Address Decoding
A15..A12 A11..A8 A7..A4 A3..A0
ROM 0000 0000 0000 0000
0001 1111 1111 1111
RAM 0010 0000 0000 0000
0011 1111 1111 1111

Note: ROM A13 = 0 , RAM A13 = 1


Memory access, signal IO/M = 0

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Implementation of Address Decoders
• Using random logic
Using logic gates such as AND, OR, NOT and
etc.
• Using M-Line to N-Line Decoder
Use existing general decoders such as
74LS138, 74LS154 and etc.
• Using PAL or FPGA
Using Programmable logic array devices
such as PAL22V10 , PAL16L8 or Field
Programmable Gate Array, ie XILINK.

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Memory Decoding Using Random Logic

OR
A 15
A 14 ROM CS
A 13

RA M CS

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3 to 8 Decoder

U5
1 15
2 A Y0 14
3 B Y1 13
C Y2 12
Y3 11
6 Y4 10
4 G1 Y5 9
5 G2A Y6 7
G2B Y7
74LS138
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Truth Table 74LS138
C B A G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXX 0 X X 1 1 1 1 1 1 1 1
XXX 1 1 X 1 1 1 1 1 1 1 1
XXX 1 0 1 1 1 1 1 1 1 1 1
000 1 0 0 0 1 1 1 1 1 1 1
001 1 0 0 1 0 1 1 1 1 1 1
010 1 0 0 1 1 0 1 1 1 1 1
011 1 0 0 1 1 1 0 1 1 1 1
100 1 0 0 1 1 1 1 0 1 1 1
101 1 0 0 1 1 1 1 1 0 1 1
110 1 0 0 1 1 1 1 1 1 0 1
111 1 0 0 1 1 1 1 1 1 1 0

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Decoder connections

U5
A13 1 15 ROM CS
2 A Y0 14
A14 B Y1 RAM CS
A15 3 13
C Y2 12
Y3 11
6 Y4 10
+5V G1 Y5
IO/M
4 9
5 G2A Y6 7
GND G2B Y7
74LS138
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I/O Map

00H
Not Used

7FH
80H
83H
I/O 8255

Not Used

FFH

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I/O Address Decoding

A7..A4 A3..A0
PORT A 1000 0000
PORT B 1000 0001
PORT C 1000 0010
CNTL PORT 1000 0011

Note: I/O access, signal IO/M = 1

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I/O Decoding Using Random Logic

A3
A4
A5
8255 CS
A6
A7
IO/M

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Reset
• Microprocessor must be reset in order to fetch
the first instruction (TR state).
• The microprocessor is automatically reset at
power on by an RC circuit connected to the
/RESET IN (active low) input of the 8085.
• For proper resetting, the /RESET IN input must
remain at logic 0 for three clock pulses.

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Reset Circuit

VCC

/RESET IN pin 8085


microprocessor
SW PUS HBUTTON C

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8085A Bus Interfaces
• The 8085A microprocessor uses only 16 connections
to interface the 8-bit data bus and 16-bit address bus.
• Address bus lines A0-A7 are time multiplexed
with data bus lines D0-D7

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Address Latches
• Peripheral devices ( memory and IO ) require stable address
data throughout a read or write operation.

• The processor only provides A0 - A7 during the period ALE is in


the logic ‘1’ state after which the multiplexed lines AD0 - AD7
assume the role of the data bus. ( D0 - D7 )

• To provide external devices with stable address data throughout


a read or write operation it is necessary to latch the low byte of
the address using the ALE control signal.

• By this mechanism it is possible for the 8085A computer system


to have a 16-bit address bus and an 8-bit data bus whilst only
using 16 processor connections ( AD0 - AD7 and A8 - A15 )

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De-multiplexing AD0 - AD7

Note : See through latches ( eg 74LS573 ) are the preferred type of


latch. When clk (ALE) is logic ‘1’ the latch outputs follow the inputs and
on the negative edge of clk the data is latched.

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De-multiplexing AD0 - AD7

AD0 3 2 A0
AD1 4 D0 Q0 5 A1
AD2 7 D1 Q1 6 A2
AD3 D2 Q2 A3
DATA / AD4
8
13 D3 Q3
9
12 A4 ADDRESS BUS
ADDRESS BUS AD5
AD6
14
17
D4
D5
Q4
Q5
15
16
A5
A6
AD7 18 D6 Q6 19 A7
D7 Q7
1
ALE 11 OC
G
74LS373

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U1 U2 U3 U6
36 12 3 2 10 11 34 4
RST-IN AD0 13 D0 Q0 9 A0 O0 12 D0 PA0
4 5 33 3
1 AD1 14 D1 Q1 8 A1 O1 13 D1 PA1
7 6 32 2
X1 AD2 15 D2 Q2 7 A2 O2 15 D2 PA2
8 9 31 1
AD3 16 D3 Q3 6 A3 O3 16 D3 PA3
13 12 30 40
2 AD4 17 D4 Q4 5 A4 O4 17 D4 PA4
14 15 29 39
X2 AD5 18 D5 Q5 4 A5 O5 18 D5 PA5
17 16 28 38
5 AD6 19 D6 Q6 3 A6 O6 19 D6 PA6
18 19 27 37
SID AD7 D7 Q7 25 A7 O7 D7 PA7
6 21
TRAP A8 24 A8
22 1 5 18
A9 OC 21 A9 RD PB0
9 23 11 36 19
RST 5.5 A10 G 23 A10 WR PB1
8 24 9 20
RST 6.5 A11 2 A11 A0 PB2
7 25 74LS373 8 21
RST 7.5 A12 A12 A1 PB3
26 35 22
10 A13 27 20 RESET PB4
6 23
INTR A14 22 CE CS PB5
28 24
A15 27 OE PB6
11 25
INTA 1 PGM PB7
30
ALE VPP
29 31 14
S0 WR 32 2764 PC0 15
33 RD 34 PC1 16
S1 IO/M 3 PC2 17
39 RST-OT 37 PC3
U4 13
HOLD CLKO 4 PC4
10 11 12
35 SOD 38 A0 D0 PC5
9 12 11
READY HLDA A1 D1 PC6
8 13 10
8085 A2 D2 PC7
7 15
6 A3 D3 16 8255
5 A4 D4 17
4 A5 D5 18
3 A6 D6 19
25 A7 D7
24 A8
21 A9
23 A10
2 A11
A12
20
26 CS1
22 CS2
27 OE
WE
HM6264A

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