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WSP Upstream Perim Upstream Perim Downstream

250MHz max AXI4 (64)


Async AXI2AXI
clk_fic64_2 fic2_aclk
WSP Downstream

fic_2 DLL (FIC2)


Feedthroughs
250MHz max AXI4 (64)
Async AXI2AXI
Redund clk_fic64_0 fic0_aclk
ATPG DLL (FIC0)
WTAP MBIST ancy AXI4 (64)
AXI Bus Trace

FPGA Fabric
OCCs fic_0 Async AXI2AXI
Control Trace
Note: All AXI buses with red dot are Async AXI2AXI 250MHz max AXI4 (64)
Fed into Trace block for monitoring
clk_fic64_1 fic1_aclk
Processor DLL (FIC1)
AXI4 (64)

AXI4 (64)
Instruction Trace fic_1 Async AXI2AXI
fic4_hclk
JTAG DLL (FIC4)

AXI4 (64)
clk_crypto
AHBL (32)
(WSP overlay)

mss_cpu_core MPU AHBL (32) Streaming i/f


AHBL (32)
Async AHB2AXI
JTAG

User
AHBL (32) Crypto
Async AXI2AHB AHBL (32) GMII
M15 /MII
AXI4 (64) AXI4 (64)
JTAG M3 AHBL (32)
corecomplex AXI4 (64) AXI4 (64) fic_4 200MHz max
S9 M1 125MHz
AXI4 (64) AXI4 (64)
M2

SGMII
PHY
AXI4 (64) AXI4 (64)
M4 TBI

AXI to TileLink
Debug Module
Platform Level
Interrupt Control SCB
TileLink
FPGA Fabric

AXI4 (64) AXI4 (64) AXI4 (64)


S8 M5 GEM_0

Downstream
DMA Engine

MPU
JTAG 800MHz Private

IOSCB
AXI4 (64) AXI4 (64) SCB
max M6 GEM_1 SysReg BRIDGE SCB
E51 U54 U54 U54 U54
16KB L1 I$ 32KB L1 I$ or 32KB L1 I$ or 32KB L1 I$ or 32KB L1 I$ or
AXI4 (64) AXI4 (64) AHB AHBL (32) USB
M7 2AXI
or 8KB ITIM 28KB ITIM 28KB ITIM 28KB ITIM 28KB ITIM 2.0 AXI4 (64)

AXI Switch
SCB clk_ioscb
AXI4 (64) P (80MHz)
AXI4 (64) AXI AXI4 (64) eMMC/
RV64IMAC RV64GC RV64GC RV64GC RV64GC M8 2AXI
H
Async
SD/SDIO Y
AXI2AXI

Upstream
8KB DTIM 32KB L1 D$ 32KB L1 D$ 32KB L1 D$ 32KB L1 D$ AXI4 (64) SCB
AXI4 (64)

IOSCB
M9 MASTER SCB
AXI4 (64) (MSS
AXI4 (64) S4 DRI)
D0 M10 AXI4 (64) ULPI
S1

TileLink to AXI
AXI4 (64)
D1 M11 AXI4 (64)
clk_cpu S2
MSS AXI4 (64)
(800MHz max) F0 M12 AXI4 AXI2 AHBL (32)
Clock TileLink B64 D128 Switch S5
clk_axi F1 AXI4 (64) M13 (64) AHB
AHB2 APB (32) eNVM
Control Controller
eNVM
(400MHz max) AXI4 (64) APB
WCB NC M14 AXI4 AXI2
S6 AHBL (32)
(64) AHB
MSS Corner

clk_in_mss AHB2
(800MHz) APB QSPI-XIP
TileLink Coherence Manager AXI4 (64)
S3 Watchdog_0
AXI4 (64) Watchdog_1
400MHz S7 APB (32) Watchdog_2
Watchdog_3

MSS IO
max
clk_in_reference 2MB L2 Cache/Scratchpad or 1.875MB LIM Watchdog_4 clk_usb (60MHz)
APB (32) MSS_GPIO_0
(125MHz) eMMC Device
MSS_GPIO_1
Note: Secondary APB is also SDINBDG4-8G
connected MSS_GPIO_2
to all peripherals and user may
Timer configure each peripheral to be CDC CAN_0
accessed by primary or secondary
CDC CAN_1
TL2AXI4 400MHz SPI_0
max IOMUX
(128)
AXI4

SPI_1
MMUART_0
clk_rtc MMUART_1
MMUART_2
(1MHz) MMUART_3
MMUART_4

FPGA Fabric
Seg Seg
400MHz I2C_0
AXI4
(128)

(64)
AXI4

max
Cacheable DDR Non-cacheable DDR I2C_1

CDC CDC APB (32)


PROJECT FRQMETER
G5SoC DDR Controller MSTIMER
H2FINTCTRL interrupt
(400MHz)
clk_in_dfi

TITLE MSS Functional L2 Cache MBIST fic3_pclk


fic_3 clk_fic64_3 DLL (FIC3)
Partition DFI (half rate) RTC
3850 North 1st Street 128b @ 400MHz Async APB (32)
REV 1.37
San Jose, CA 95134 AXI2APB 250MHz max
DRAWN
Ciaran Murphy MSS DDR PHY SGMII PHY
BY
(32/36b DDR-1600 @ IO pads)
MSS DDR Training
DATE 21 Mar 2019 SHEET 1 of 1