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EECS 115: Intro.

VLSI Design

Fadi J. Kurdahi
EECS Dept.
UCI

MOS Transistor Review

[Adapted from Rabaey’s Digital Integrated Circuits, Copyright 2003 Prentice Hall/Pearson]
{Adapted from Mary Jane Irwin, Penn State]
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Overview of Last Lecture
Digital integrated circuits experience exponential
growth in complexity (Moore’s law) and performance
 Design in the deep submicron (DSM) era creates new
challenges
 Devices become somewhat different
 Global clocking becomes more challenging
 Interconnect effects play a more significant role
 Power dissipation may be the limiting factor
 Our goal in this class will be to understand and design
digital integrated circuits in the deep submicron era

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Goal of this chapter
 Present intuitive understanding of device
operation
 Introduction of basic device equations
 Introduction of models for manual
analysis
 Introduction of models for SPICE
simulation
 Analysis of secondary and deep-sub-
micron effects
 Future trends

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Semiconductors
 Pure semiconductors have low and equal
concentrations of electrons and holes  low
electrical conductivity
 Si has 4 valence electrons
 Phosphorous, arsenic, etc.. Have 5 electrons
 provide one free electron
 Silicon doped w/these material becomes n-
type
 Dual argument applies for trivalent material
(e.g. Boron, gallium)  p-type

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The Diode Doped
B Al A w/acceptor
SiO2 impurities
(e.g. Boron).
p Mostly Holes

n Doped
w/donor
Cross-section of pn-junction in an IC process impurities
(e.g.
Phosphorus).
A Al Mostly
Electrons
p A

B B
One-dimensional
representation diode symbol

Mostly occurring as parasitic element in Digital ICs

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Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n

hole drift
electron drift
Charge ρ
Density
+ x (b) Charge density.
Distance
-

Electrical ξ
Field x
(c) Electric field.

V
Potential
ψ0 (d) Electrostatic
x potential.
-W 1 W2

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Forward Bias

p n (W 2)
p n0
hole diffusion
electron diffusion
L p
p n
n p0
hole drift
electron drift

-W 1
0 W 2 x
p -re g io n n -re g io n

d iffu s io n
P region potential raised wrt N region
More electrons diffuse n->p, holes p->n
Current flow p->n

Typically avoided in Digital ICs


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Reverse Bias
pn0

hole diffusion
electron diffusion

p n
np0
hole drift
electron drift

-W 1 0 W2 x
p-region n-region

diffusion

n region potential raised wrt p region


Less electrons diffuse n->p, holes p->n
Mostly drift Current flows p->n: very small
The Dominant Operation Mode
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Review: Diode Diode Animation

 The ideal diode equation (for both forward and reverse-


bias conditions) is
+ ID = IS(e VD/ φT – 1)
VD
-

where VD is the voltage applied to2.5the junction


 a forward-bias lowers the
potential barrier allowing

ID (mA)
1.5
carriers to flow across the
diode junction 0.5
 a reverse-bias raises the
potential barrier and the -0.5
diode becomes nonconducting -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
VD (V)
φT = kT/q = 26mV at 300K
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Diode Current

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Models for Manual Analysis

ID = IS(eV D/φ T – 1) ID
+ +
+
VD VD VDon

– –

(a) Ideal diode model (b) First-order diode model

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Junction Capacitance

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Diffusion Capacitance

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Secondary Effects
0.1
ID (A)

–0.1
–25.0 –15.0 –5.0 0 5.0
VD (V)

Avalanche Breakdown

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Diode Model

RS

VD ID CD

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SPICE Parameters

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Review: Design Abstraction Levels
SYSTEM

MODULE
+
GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

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What is a Transistor?

A Switch! An MOS Transistor

VG S ≥V T |VGS|

R on
S D

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MOS Transistors -
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion


D D

G G B

S S

PMOS Enhancement NMOS with


Bulk Contact

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The MOS Transistor
Polysilicon
Aluminum

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The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND - electrons
are the majority carriers

Gate oxide
Polysilicon
W Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L
p substrate
p+ stopper

Bulk (Body)

p areas have been doped with acceptor


ions (boron) of concentration NA - holes
are the majority carriers
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Switch Model of NMOS Transistor
| VGS | Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)


Ron

| VGS | < | VT | | VGS | > | VT |

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Switch Model of PMOS Transistor
| VGS |
Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)


Ron

| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |

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Threshold Voltage Concept
G
VGS
+
S D

n+ n+

depletion
n channel p substrate region

The value of VGS where strong inversion occurs is called


the threshold voltage, VT
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The Threshold Voltage
VT = VT0 + γ(√|-2φF + VSB| - √|-2φF|)

where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
 Difference in work-function between gate and substrate material, oxide
thickness, Fermi voltage, charge of impurities trapped at the surface,
dosage of implanted ions, etc.
VSB is the source-bulk voltage
φF = -φTln(NA/ni) is the Fermi potential (φT = kT/q = 26mV at 300K is the
thermal voltage; NA is the acceptor ion concentration; ni ≈ 1.5x1010 cm-3 at
300K is the intrinsic carrier concentration in pure silicon)
γ = √(2qεsiNA)/Cox is the body-effect coefficient (impact of changes in
VSB) (εsi=1.053x10-10F/m is the permittivity of silicon; Cox = εox/tox is the gate
oxide capacitance with εox=3.5x10-11F/m)
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The Threshold Voltage

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The Body Effect
0.9
● VSB is the substrate bias
0.85
voltage (normally positive for n-
0.8 channel devices with the body
tied to ground)
0.75
0.7 ● A negative bias causes VT to
increase from 0.45V to 0.85V
VT (V)

0.65
0.6 ● Can use this trick to help with
power consumption – reduces
0.55
leakage currents (but slows down
0.5 the gate)
0.45 ● VSB always has to be larger
0.4 than –0.6V in an NMOS device;
otherwise the source-body diode
-2.5 -2 -1.5 -1 -0.5 0 becomes forward biased
VBS (V)

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Transistor in Linear Mode
Assuming VGS > VT
VGS
VDS
S G
D ID

n+ - V(x) + n+

The current is a linear function of both VGS and VDS

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Voltage-Current Relation: Linear
Mode
For long-channel devices (L > 0.25 micron)
 When VDS ≤ VGS – VT

ID = k’n W/L [(VGS – VT)VDS – VDS2/2]


where
k’n = µnCox = µnεox/tox = is the process transconductance
parameter (µn is the carrier mobility (m2/Vsec))
kn = k’n W/L is the gain factor of the device
For small VDS, there is a linear dependence between VDS
and ID, hence the name resistive or linear region

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Transistor in Saturation Mode
Assuming VGS > VT

VGS VDS > VGS - VT


VDS
S G
D ID

n+ - V -V + n+
GS T

Pinch-off

The current remains constant (saturates).

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Voltage-Current Relation:
Saturation Mode
For long channel devices
 When VDS ≥ VGS – VT

ID’ = k’n/2 W/L [(VGS – VT) 2]


since the voltage difference over the induced
channel (from the pinch-off point to the source)
remains fixed at VGS – VT
 However, the effective length of the conductive
channel is modulated by the applied VDS, so
ID = ID’ (1 + λVDS)
where λ is the channel-length modulation (varies
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Current Determinates
 For a fixed VDS and VGS (> VT), IDS is a function of
 the distance between the source and drain – L
 the channel width – W
 the threshold voltage – VT
 the thickness of the SiO2 – tox
 the dielectric of the gate insulator (SiO2) – εox
 the carrier mobility
–for nfets: µn = 500 cm2/V-sec
–for pfets: µp = 180 cm2/V-sec

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Long Channel I-V Plot (NMOS) X 10-4
6
VGS = 2.5V
VDS = VGS - VT
5

Quadratic dependence
4
VGS = 2.0V
3
ID (A)

Linear Saturation
2 VGS = 1.5V
1
VGS = 1.0V
0
0 0.5 1 1.5 2 2.5
cut-off
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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Current-Voltage Relations
Long-Channel Device

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Long Channel I-V Plot (NMOS)
X 10-4

6 VGS = 2.5V
VDS = VGS - VT
5

Quadratic dependence
4
VGS = 2.0V
3
ID (A)

Linear Saturation
2
VGS = 1.5V
1
0 VGS = 1.0V

0 0.5 1 1.5 2 2.5


cut-off
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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A model for manual analysis

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Short Channel Effects
● Behavior of short channel device mainly due to
10
5 υsat =105
Constant ● Velocity saturation
velocity
– the velocity of the
carriers saturates due
υn (m/s)

Constant mobility
to scattering (collisions
(slope = µ) suffered by the
carriers)

0
0 ξc= 1.5 3
ξ(V/µm)

● For an NMOS device with L of .25µm, only a couple of volts


difference between D and S are needed to reach velocity
saturation
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Voltage-Current Relation:
Velocity Saturation
For short channel devices
 Linear: When VDS ≤ VGS – VT

ID = κ(VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]


where
κ(V) = 1/(1 + (V/ξcL)) is a measure of the degree
of velocity saturation

 Saturation: When VDS = VDSAT ≥ VGS – VT


IDSat = κ(VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
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Velocity Saturation Effects
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VGS = VDD For short channel devices
and large enough VGS – VT

● VDSAT < VGS – VT so


Short
channel the device enters
devices saturation before VDS
reaches VGS – VT and
0
operates more often in
VDSAT VGS-VT
saturation
● IDSAT has a linear dependence wrt VGS so a reduced
amount of current is delivered for a given control
voltage
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Short Channel I-V Plot (NMOS)
X 10-4
2.5
Early Velocity
VGS = 2.5V
Saturation
2

Linear dependence
VGS = 2.0V
1.5
ID (A)

Linear Saturation VGS = 1.5V


1

0.5 VGS = 1.0V

0
0 0.5 1 1.5 2 2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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MOS ID-VGS Characteristics
X 10-4 ● Linear (short-channel)
6 versus quadratic (long-
5 long-channel channel) dependence of
quadratic
4 ID on VGS in saturation
ID (A)

3
short-channel ● Velocity-saturation
2 linear causes the short-
1 channel device to
0 saturate at substantially
smaller values of VDS
0 0.5 1 1.5 2 2.5
resulting in a substantial
VGS (V)
drop in current drive
(for VDS = 2.5V, W/L = 1.5)
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Short Channel I-V Plot (PMOS)
● All polarities of all voltages and currents are reversed
-2 VDS (V) -1 0
0

VGS = -1.0V -0.2

VGS = -1.5V -0.4

ID (A)
-0.6
VGS = -2.0V

-0.8

VGS = -2.5V
-1 X 10 -4

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 42


-0.4V
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A unified model
for manual analysis

S D

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Simple Model versus SPICE
-4
x 10
2.5

VDS=VDSAT
2

Velocity
1.5
Saturated
ID (A)

Linear
1

VDSAT=VGT
0.5

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
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Transistor Model
for Manual Analysis

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The MOS Current-Source
Model
I = 0 for V – V ≤ 0
G D GS T

ID ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+λVDS)


S D for VGS – VT ≥ 0

with Vmin = min(VGS – VT, VDS, VDSAT)


B
and VGT = VGS - VT

● Determined by the voltages at the four terminals and


a set of five device parameters

VT0(V) γ(V0.5) VDSAT(V) k’(A/V2) λ(V-1)


NMOS 0.43 0.4 0.63 115 x 10-6 0.06
PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1
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The Transistor Modeled as a Switch
x105
7 Modeled as a switch with
6 infinite off resistance and a
5
VGS ≥ VT finite on resistance, Ron
Req (Ohm)

4
Ron
S D ● Resistance inversely
3 proportional to W/L (doubling
2 W halves Ron)
1
● For VDD>>VT+VDSAT/2, Ron
0
0.5 1 1.5 2 2.5
independent of VDD
VDD (V)
(for VGS = VDD,
VDS = VDD →VDD/2) ●Once VDD approaches VT,
Ron increases dramatically
VDD(V) 1 1.5 2 2.5
Ron (for W/L = 1)
NMOS(kΩ) 35 19 15 13 For larger devices
PMOS (kΩ) 115 55 38 31 divide Req by W/L
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MOS Capacitances
Dynamic Behavior

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Dynamic Behavior of MOS
Transistor
G

C GS C GD

S D

C SB C GB C DB

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The Gate Capacitance
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+

Cross section

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Gate Capacitance
G G G

CGC CGC CGC


S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

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Gate Capacitance

CG C
WLC ox W LC ox CG C
2W LC o x
CG C S
C G C S = CG C D 3
WLC ox CGC B W LC ox
2 2 CGC D

VG S 0 V DS /( V G S-V T) 1

Capacitance as a function of VGS Capacitance as a function of the


(with VDS = 0) degree of saturation

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Measuring the Gate Cap

3 102 16
10

V GS 9

Gate Capacitance (F)


8
I 7
6
5
4
3
2
2 2 2 1.52 1 2 0.5 0 0.5 1 1.5 2
V GS (V)

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Diffusion Capacitance
C hannel-st
opi
mpl
ant
NA 1

Si
dewal
l
Sour
ce
W
ND

B ot
tom

xj Si
dewal
l
C hannel
LS Subst
rat
eN A

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Junction Capacitance

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Linearizing the Junction
Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest

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Capacitances in 0.25 µm
CMOS process

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Other (Submicon) MOS
Transistor Concerns
 Velocity saturation
 Subthreshold conduction
 Transistor is already partially conducting for voltages below VT
 Threshold variations
 In long-channel devices, the threshold is a function of the
length (for low VDS)
 In short-channel devices, there is a drain-induced threshold
barrier lowering at the upper end of the VDS range (for low L)
 Parasitic resistances G

 resistances associated with the


source and drain contacts S D
RS RD
 Latch-up
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Subthreshold Conductance
10-2 ● Transition from ON to
Linear region OFF is gradual (decays
Quadratic region
exponentially)
● Current roll-off (slope
factor) is also affected by
ID (A)

increase in temperature
Subthreshold
exponential
region S = n (kT/q) ln (10)
(typical values 60 to 100
10-12 VT mV/decade)

0 0.5 1 1.5 2 2.5 ● Has repercussions in


VGS (V) dynamic circuits and for
ID ~ IS e (qVGS/nkT) where n ≥ 1 power consumption
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Sub-Threshold Conduction
-2
10 The Slope Factor
Linear qVGS
CD
10
-4
I D ~ I 0e nkT
, n = 1+
Cox
-6
10 Quadratic
S is ∆VGS for ID2/ID1 =10
I D (A)

-8
10

-10 Exponential
10

-12 VT Typical values for S:


10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

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Subthreshold ID vs VGS
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + λVDS)

VDS from 0 to 0.5V

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Subthreshold ID vs VDS
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + λVDS)

VGS from 0 to 0.3V

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Threshold Variations
VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering


the length (for low VDS ) (for low L)

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Summary of MOSFET
Operating Regions
 Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS ≥ VDSAT
 Weak Inversion (Sub-Threshold) VGS ≤ VT
 Exponential in VGS with linear VDS dependence

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Parasitic Resistances

Polysilicon gate
Drain
contact
G LD

VGS,eff

W
S D

RS RD

Drain

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Latch-up

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