VLSI Design
Fadi J. Kurdahi
EECS Dept.
UCI
[Adapted from Rabaey’s Digital Integrated Circuits, Copyright 2003 Prentice Hall/Pearson]
{Adapted from Mary Jane Irwin, Penn State]
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Overview of Last Lecture
Digital integrated circuits experience exponential
growth in complexity (Moore’s law) and performance
Design in the deep submicron (DSM) era creates new
challenges
Devices become somewhat different
Global clocking becomes more challenging
Interconnect effects play a more significant role
Power dissipation may be the limiting factor
Our goal in this class will be to understand and design
digital integrated circuits in the deep submicron era
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Goal of this chapter
Present intuitive understanding of device
operation
Introduction of basic device equations
Introduction of models for manual
analysis
Introduction of models for SPICE
simulation
Analysis of secondary and deepsub
micron effects
Future trends
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Semiconductors
Pure semiconductors have low and equal
concentrations of electrons and holes low
electrical conductivity
Si has 4 valence electrons
Phosphorous, arsenic, etc.. Have 5 electrons
provide one free electron
Silicon doped w/these material becomes n
type
Dual argument applies for trivalent material
(e.g. Boron, gallium) ptype
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The Diode Doped
B Al A w/acceptor
SiO2 impurities
(e.g. Boron).
p Mostly Holes
n Doped
w/donor
Crosssection of pnjunction in an IC process impurities
(e.g.
Phosphorus).
A Al Mostly
Electrons
p A
B B
Onedimensional
representation diode symbol
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Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n
hole drift
electron drift
Charge ρ
Density
+ x (b) Charge density.
Distance

Electrical ξ
Field x
(c) Electric field.
V
Potential
ψ0 (d) Electrostatic
x potential.
W 1 W2
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Forward Bias
p n (W 2)
p n0
hole diffusion
electron diffusion
L p
p n
n p0
hole drift
electron drift
W 1
0 W 2 x
p re g io n n re g io n
d iffu s io n
P region potential raised wrt N region
More electrons diffuse n>p, holes p>n
Current flow p>n
hole diffusion
electron diffusion
p n
np0
hole drift
electron drift
W 1 0 W2 x
pregion nregion
diffusion
ID (mA)
1.5
carriers to flow across the
diode junction 0.5
a reversebias raises the
potential barrier and the 0.5
diode becomes nonconducting 1 0.75 0.5 0.25 0 0.25 0.5 0.75 1
VD (V)
φT = kT/q = 26mV at 300K
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Diode Current
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Models for Manual Analysis
ID = IS(eV D/φ T – 1) ID
+ +
+
VD VD VDon
–
– –
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Junction Capacitance
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Diffusion Capacitance
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Secondary Effects
0.1
ID (A)
–0.1
–25.0 –15.0 –5.0 0 5.0
VD (V)
Avalanche Breakdown
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Diode Model
RS
VD ID CD
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SPICE Parameters
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Review: Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
Vin Vout
DEVICE
G
S D
n+ n+
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What is a Transistor?
VG S ≥V T VGS
R on
S D
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MOS Transistors 
Types and Symbols
D D
G G
S S
G G B
S S
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The MOS Transistor
Polysilicon
Aluminum
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The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND  electrons
are the majority carriers
Gate oxide
Polysilicon
W Gate
Source Drain FieldOxide
n+ n+ (SiO2)
L
p substrate
p+ stopper
Bulk (Body)
Source Drain
(of carriers) (of carriers)
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Switch Model of PMOS Transistor
 VGS 
Gate
Source Drain
(of carriers) (of carriers)
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Threshold Voltage Concept
G
VGS
+
S D
n+ n+
depletion
n channel p substrate region
where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
Difference in workfunction between gate and substrate material, oxide
thickness, Fermi voltage, charge of impurities trapped at the surface,
dosage of implanted ions, etc.
VSB is the sourcebulk voltage
φF = φTln(NA/ni) is the Fermi potential (φT = kT/q = 26mV at 300K is the
thermal voltage; NA is the acceptor ion concentration; ni ≈ 1.5x1010 cm3 at
300K is the intrinsic carrier concentration in pure silicon)
γ = √(2qεsiNA)/Cox is the bodyeffect coefficient (impact of changes in
VSB) (εsi=1.053x1010F/m is the permittivity of silicon; Cox = εox/tox is the gate
oxide capacitance with εox=3.5x1011F/m)
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The Threshold Voltage
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The Body Effect
0.9
● VSB is the substrate bias
0.85
voltage (normally positive for n
0.8 channel devices with the body
tied to ground)
0.75
0.7 ● A negative bias causes VT to
increase from 0.45V to 0.85V
VT (V)
0.65
0.6 ● Can use this trick to help with
power consumption – reduces
0.55
leakage currents (but slows down
0.5 the gate)
0.45 ● VSB always has to be larger
0.4 than –0.6V in an NMOS device;
otherwise the sourcebody diode
2.5 2 1.5 1 0.5 0 becomes forward biased
VBS (V)
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Transistor in Linear Mode
Assuming VGS > VT
VGS
VDS
S G
D ID
n+  V(x) + n+
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VoltageCurrent Relation: Linear
Mode
For longchannel devices (L > 0.25 micron)
When VDS ≤ VGS – VT
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Transistor in Saturation Mode
Assuming VGS > VT
n+  V V + n+
GS T
Pinchoff
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VoltageCurrent Relation:
Saturation Mode
For long channel devices
When VDS ≥ VGS – VT
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Long Channel IV Plot (NMOS) X 104
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VGS = 2.5V
VDS = VGS  VT
5
Quadratic dependence
4
VGS = 2.0V
3
ID (A)
Linear Saturation
2 VGS = 1.5V
1
VGS = 1.0V
0
0 0.5 1 1.5 2 2.5
cutoff
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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CurrentVoltage Relations
LongChannel Device
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Long Channel IV Plot (NMOS)
X 104
6 VGS = 2.5V
VDS = VGS  VT
5
Quadratic dependence
4
VGS = 2.0V
3
ID (A)
Linear Saturation
2
VGS = 1.5V
1
0 VGS = 1.0V
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Short Channel Effects
● Behavior of short channel device mainly due to
10
5 υsat =105
Constant ● Velocity saturation
velocity
– the velocity of the
carriers saturates due
υn (m/s)
Constant mobility
to scattering (collisions
(slope = µ) suffered by the
carriers)
0
0 ξc= 1.5 3
ξ(V/µm)
Linear dependence
VGS = 2.0V
1.5
ID (A)
0
0 0.5 1 1.5 2 2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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MOS IDVGS Characteristics
X 104 ● Linear (shortchannel)
6 versus quadratic (long
5 longchannel channel) dependence of
quadratic
4 ID on VGS in saturation
ID (A)
3
shortchannel ● Velocitysaturation
2 linear causes the short
1 channel device to
0 saturate at substantially
smaller values of VDS
0 0.5 1 1.5 2 2.5
resulting in a substantial
VGS (V)
drop in current drive
(for VDS = 2.5V, W/L = 1.5)
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Short Channel IV Plot (PMOS)
● All polarities of all voltages and currents are reversed
2 VDS (V) 1 0
0
ID (A)
0.6
VGS = 2.0V
0.8
VGS = 2.5V
1 X 10 4
S D
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Simple Model versus SPICE
4
x 10
2.5
VDS=VDSAT
2
Velocity
1.5
Saturated
ID (A)
Linear
1
VDSAT=VGT
0.5
VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
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Transistor Model
for Manual Analysis
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The MOS CurrentSource
Model
I = 0 for V – V ≤ 0
G D GS T
4
Ron
S D ● Resistance inversely
3 proportional to W/L (doubling
2 W halves Ron)
1
● For VDD>>VT+VDSAT/2, Ron
0
0.5 1 1.5 2 2.5
independent of VDD
VDD (V)
(for VGS = VDD,
VDS = VDD →VDD/2) ●Once VDD approaches VT,
Ron increases dramatically
VDD(V) 1 1.5 2 2.5
Ron (for W/L = 1)
NMOS(kΩ) 35 19 15 13 For larger devices
PMOS (kΩ) 115 55 38 31 divide Req by W/L
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MOS Capacitances
Dynamic Behavior
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Dynamic Behavior of MOS
Transistor
G
C GS C GD
S D
C SB C GB C DB
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The Gate Capacitance
Polysilicon gate
Source Drain
W
n+ xd xd n+
Gatebulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+
Cross section
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Gate Capacitance
G G G
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Gate Capacitance
CG C
WLC ox W LC ox CG C
2W LC o x
CG C S
C G C S = CG C D 3
WLC ox CGC B W LC ox
2 2 CGC D
VG S 0 V DS /( V G SV T) 1
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Measuring the Gate Cap
3 102 16
10
V GS 9
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Diffusion Capacitance
C hannelst
opi
mpl
ant
NA 1
Si
dewal
l
Sour
ce
W
ND
B ot
tom
xj Si
dewal
l
C hannel
LS Subst
rat
eN A
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Junction Capacitance
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Linearizing the Junction
Capacitance
Replace nonlinear capacitance by
largesignal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest
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Capacitances in 0.25 µm
CMOS process
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Other (Submicon) MOS
Transistor Concerns
Velocity saturation
Subthreshold conduction
Transistor is already partially conducting for voltages below VT
Threshold variations
In longchannel devices, the threshold is a function of the
length (for low VDS)
In shortchannel devices, there is a draininduced threshold
barrier lowering at the upper end of the VDS range (for low L)
Parasitic resistances G
increase in temperature
Subthreshold
exponential
region S = n (kT/q) ln (10)
(typical values 60 to 100
1012 VT mV/decade)
8
10
10 Exponential
10
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Subthreshold ID vs VGS
ID = IS e (qVGS/nkT) (1  e –(qVDS/kT))(1 + λVDS)
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Subthreshold ID vs VDS
ID = IS e (qVGS/nkT) (1  e –(qVDS/kT))(1 + λVDS)
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Threshold Variations
VT VT
VDS
L
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Summary of MOSFET
Operating Regions
Strong Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS ≥ VDSAT
Weak Inversion (SubThreshold) VGS ≤ VT
Exponential in VGS with linear VDS dependence
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Parasitic Resistances
Polysilicon gate
Drain
contact
G LD
VGS,eff
W
S D
RS RD
Drain
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Latchup
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