Power Swing Detection (PSD)

The Power Swing Detection function, PSD, as the name suggests detect power swings
which can be the result of a sudden load change. Power system conditions demand that a
swing time as low as 200ms which corresponds to a slip frequency of 10% of the rated 50
Hz frequency be detected. The PSD function detects swings under normal operating
conditions as well as the dead time of the single phase reclosing cycle.

The most widely used and well proven technique is to "measure the speed of the
impedance locus. This is done by measuring the transition time of the impedance locus
between passing the outer and inner lines of two impedance characteristics. The principle
of measurement of the characteristics is the same as the distance protection zones. The
time measurement is phase segregated. Different timers for initial and consecutive swings
are provided which secures a high degree of differentiation between faults and power
swing. Also, the built in logic and configurable function inputs makes it possible to
combine the function with other functions and different conditions.

jX
Impedance locus at power swing
KX*X1IN

X1IN

-KR*R1IN -R1IN R1IN KR*R1IN

t
-X1IN
-KX*X1IN
Operating principle & characteristic of PSD function
PSB Typical settings Powerswing blocking
Operation On,Off On Power swing function on/off
Detection On,Off On Operating mode of internal PSD
function
X1IN 0.1-400 1.1*Zone 3 positive sequence Positive sequence reactive reach of
reactance the inner boundary
R1IN 0.1-400 1.1*(2*positive sequence resistance Positive sequence resistive reach of
+ fault resistance) of Zone-3 the inner boundary
KX 120-200% 125% of X1IN Reach multiplication for the outer
reactive boundary
KR 120-200% 125% of R1IN Reach multiplication for the outer
resistive boundary
t P1 0-60 0.045 Initial PSD timer for the first swing
t P2 0-60 0.015 Fast PSD timer for the consecutive
swings within 't W'
tW 0-60 0.250 Hold timer for activation of fast PSD
timer.
tH 0-60 0.5 S Hold timer for PSD detected
t EF 0-60 3S Timer overcoming 1-PH reclosing
dead time
t R1 0-60 0.300 Timer to time delay block by the
residual current
t R2 0-60 2.000 On delay timer for blocking of output
signal at very slow swings.

The above table gives typical settings for PSD function. These settings are entered from
the HMI or downloaded using SMS.

In addition to the settings, the logical inputs and outputs from the PSD function block is
configured using configuration tool CAP 531. The PSD function can operate in two
modes, viz. "1-of-3" mode based on the detection of power swing in any of the 3 phases
and "2-of-3" mode based on the detection of power swing in two of three phases. The
corresponding input is set to logical one. The pickup of phase-earth element from GFC
or PHS (for terminal 511 or 521 respectively) is made to block PSD.

Function Block
We will consider the case of "1-of-3" mode and a swing in phase L1 (R-phase) for
understanding the signal flow.

During a power swing, as the impedance locus passes through the outer characteristic,
ZOUTPSL1 picks up. At this instant, the AND gate output is high as the other signal
which is low(ZINPSL1 connected is still not picked up) is inverted. The output of this
AND gate is connected to timer tP1(delay on pick-up) and OR gate. After the elapse of
the set time (typically = 45ms), the timer output picks up which is connected to a OR
gate. The output of this OR gate releases the signal "DET of 1-of-3". Also this signal
starts a timer tW.

Simultaneously, the output of the other OR gate which is picked up with timer tP1 goes
high and the corresponding input to the AND gate is high. The other input to this AND
gate is the output from the timer tW (delay on drop-off). The output of this timer remains
picked up till the elapse of set time (typically set to 0.25 secs). In this state, if a second
power swing occurs, the signal is routed through timer tP2 which has a setting (typically
= 15ms) shorter than tP1. This is done to ensure that the second swing follows the first
swing within 250ms, the speed of the locus is faster than the first swing. If we had only
one timer, then there would be chances that it may not be detected as the power swing
and relay might go for tripping.

The signal from the final OR gate is locked in by routing it to an AND gate shown at the
bottom whose other input is the same signal ZOUTPSL1. The output of this AND gate is
again given back to the final OR gate. This signal remains picked up and will be in the
same status till ZOUTPSL1 is reset (the impedance locus goes out of the outer
characteristic).

During the case of a fault, the same ZOUTPSL1 will no doubt pick up but the locus
passes through the inner characteristic ZINPSL1 before the set time of tP1. As this input
is inverted and given to the AND gate, the output of goes low thereby resetting the timer
tP1.
The same explanation holds god for the other two phases.

In the case of "2-of-3" mode, the logic diagram is as follows and the signal flow is almost
similar to the "1-of-3" mode except that two phases need to pick up at the same time for it
to start processing.

Operation of the PSD function can be blocked by activating the PSD-BLOCK function
block input.