‘‘‘‘‘‘‘‘Tri-Mode

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Tri-Mode Ethernet MAC v4.1
DS297 April 24, 2009
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Product Specification

Introduction
The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) core supports half-duplex and full-duplex operation at 10 Mbps, 100 Mbps, and 1 Gbps.

LogiCORE IP Facts
Core Specifics
Supported FPGA Families Speed Grade

Features
• Designed to the IEEE 802.3-2005 specification • Configurable half-duplex and full-duplex operation • Optional support for full-duplex only • Optional support for 10/100 Mbps only, 1Gbps only or full Tri-speed • Internal GMII physical-side (PHY) that can be connected to - An embedded PHY core, such as the LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII core or other custom logic - IOBs to provide an external GMII/MII 4 - A shim to provide an external RGMII • Configured and monitored through an optional independent microprocessor-neutral interface • Configurable flow control through MAC Control pause frames; symmetrically or asymmetrically enabled • Optional MDIO interface to managed objects in PHY layers (MII Management) • Optional Address Filter with selectable number of address table entries • Optional clock enables to reduce clock resources • Support of VLAN frames designed to IEEE 802.3-2005 • Configurable support of jumbo frames of any length • Configurable interframe gap adjustment • Configurable in-band FCS field passing on both transmit and receive paths • Available under the terms of the SignOnce IP Site License agreement

Virtex®-6, Virtex-5 Virtex-4 Spartan®-6 Spartan-3, Spartan-3E1 Spartan-3A/3AN/3A DSP Performance Slices LUTs FFs DCM BUFG

-1 -10 -2 -4 10 Mbps, 100 Mbps, 1 Gbps Core Resources 445-9002 or 900-18502 700-15803 or 855-20803 815-14353 or 820-15103 0-23 2-63 Core Highlights

Designed to IEEE Hardware Verified specification 802.3-2005 Provided with Core Product Specification Documentation Getting Started Guide User Guide NGC Netlist, HDL Example Design Design File Formats Demonstration Test Bench, Scripts Constraints File User Constraints File (UCF) Tri-Mode Ethernet MAC with MII, Example Design GMII/MII4 or RGMII interface Demo Test Environment Design Tool Requirements Supported HDL VHDL, Verilog Synthesis XST 11.1 Xilinx Tools ISE® software v11.1 Mentor Graphics ModelSim v6.4b and above Simulation tools Cadence IUS v8.1-s009 and above
Synopsys 2008.095 and above

Support Provided by Xilinx @ www.xilinx.com/support
1. Spartan-3E devices support only the GMII protocol. 2. Virtex-5 FPGA slices and LUTs are different from previous families (see Tables 22 and 23). 3. See Tables 22 and 23; precise number depends on user configuration. 4. Virtex-6 devices support GMII and MII at 2.5V only; please see the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics for more information. Virtex-5, Virtex-4, Spartan-6 and Spartan-3 devices support MII and GMII at 3.3V or lower. 5. Scripts provided for listed simulators only.

© 2004-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

DS297 April 24, 2009 Product Specification

www.xilinx.com

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Tri-Mode Ethernet MAC v4.1

Applications
Typical applications for the TEMAC core include the following: 4 • Ethernet 1000BASE-X Port • Ethernet Tri-Speed BASE-T Port (SGMII) • Ethernet BASE-X Port

Ethernet 1000BASE-X Port
Figure 1 illustrates a typical 1Gbps MAC application. The TEMAC can be generated with both 1 Gbps only and full-duplex only to remove unnecessary logic. The PHY side of the core is connected to internally integrated RocketIO™ Multi-Gigabit Transceivers, available in certain families, to connect to an external off-the-shelf GBIC or SFP optical transceiver. The 1000BASE-X logic can be provided by the Ethernet 1000BASE-X PCS/PMA or SGMII core. The client side of the core is shown connected to the 10Mbps, 100 Mbps, 1 Gbps Ethernet FIFO, delivered with the TEMAC core to complete a single Ethernet port. This port is shown connected to a Switch or Routing matrix, which may contain several ports.
Figure Top x-ref 1

PMA Xilinx FPGA Tri-Mode Ethernet MAC Core 10Mbps, 100 Mbps, 1 Gbps Ethernet FIFO

Switch or Router

Client I/F

GMII

1000BASE-X PCS and PMA Sublayers using RocketIO

TXP/TXN

GBIC or SFP Optical Transceiver

Optical Fiber

RXP/RXN

Figure 1: Typical MAC 1000BASE-X Application

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www.xilinx.com

DS297 April 24, 2009 Product Specification

100 Mbps. 1 Gbps Figure 2: Typical BASE-T Application for TEMAC Core: MII/GMII/RGMII DS297 April 24. which performs the BASE-T standard at 1 Gbps.com 3 . Alternatively. and 10 Mbps speeds. Figure Top x-ref 1 Xilinx FPGA Tri-Mode Ethernet MAC GMII/MII (or RGMII) Switch or Router 10 Mbps.xilinx. HDL example designs are provided with the core to demonstrate external GMII or RGMII. The client side of the TEMAC is shown connected to the 10 Mbps. which may contain several ports. 1 Gbps Ethernet FIFO Client I/F GMII IOBs Tri-Speed BASE-T PHY Twisted Copper Pair 10 Mbps.1 Ethernet Tri-Speed BASE-T Port (MII/GMII or RGMII) Figure 2 illustrates a typical application for the TEMAC core. 100 Mbps. 100 Mbps. 2009 Product Specification www. The PHY side of the core is implementing an external GMII/MII by connecting it to IOBs. 100 Mbps. This port is shown connected to a Switch or Routing matrix. 1 Gbps Ethernet FIFO (delivered with the example design) to complete a single Ethernet port. the external GMII/MII may be replaced with an RGMII using a small logic shim. The external GMII/MII is connected to an off-the-shelf Ethernet PHY device.Tri-Mode Ethernet MAC v4.

Figure Top x-ref 2 SGMII Xilinx FPGA Tri-Mode Ethernet MAC Core Switch or Router 10 Mbps. 2009 Product Specification . 100 Mbps. This port is shown connected to a Switch or Routing matrix.com DS297 April 24. The client side of the core is shown connected to the 10 Mbps. The SGMII logic can be provided by the Ethernet 1000BASE-X PCS/PMA or SGMII core. 1 Gbps Figure 3: Typical BASE-T Application for TEMAC Core: SGMII 4 www. 100 Mbps.1 Ethernet Tri-Speed BASE-T Port (SGMII) Figure 3 illustrates a typical application for the TEMAC core. and 10 Mbps speeds. 100 Mbps.Tri-Mode Ethernet MAC v4. 1 Gbps Ethernet FIFO SGMII TXP/TXN using RocketIO Transceiver RXP/RXN Tri-Speed BASE-T PHY Twisted Copper Pair Client I/F GMII 10 Mbps. 1 Gbps Ethernet FIFO. 100 Mbps. delivered with the TEMAC core. to complete a single Ethernet port. which performs the BASE-T standard at 1 Gbps. which may contain several ports. The PHY side of the core is connected to internally integrated SGMII logic using the device-specific RocketIO transceiver to connect to an off-the-shelf Ethernet PHY device.xilinx.

from the MAC to the right. is defined in IEEE 802. compared with GMII. The MAC is independent of. RGMII The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the GMII. HDL example designs are provided with the core which implement either the GMII or RGMII protocols. a copper standard using twisted pair cabling systems • BASE-X. 3. PMA. However.3-2005 clause 22. radically reducing the I/O count (and for this reason often favored by PCB designers). This is achieved with the use of double-data-rate (DDR) flip-flops. See the Tri-Mode Ethernet MAC User Guide. GMII / MII The Gigabit Media Independent Interface (GMII) is defined in IEEE 802. and PMD). The portion of the architecture. and for this reason is preferred over GMII by PCB designers. A MAC is responsible for the Ethernet framing protocols and error detection of these frames. RGMII achieves a 50 percent reduction in the pin count. and PMD The combination of the Physical Coding Sublayer (PCS). and the Physical Medium Dependent (PMD) sublayer comprise the physical layers of the Ethernet protocol. which converts the parallel interface of the GMII into a serial format. and 4. the Media Independent Interface (MII) is used as defined in IEEE 802.3.xilinx.3-2005 clause 35. the Physical Medium Attachment (PMA).1 Ethernet Architecture Overview The TEMAC sublayer provided by this core is part of the Ethernet architecture displayed in Figure 4. the clock management logic and IOB logic around the core will change. any type of physical layer. No change in the operation of the core is required to select between GMII and RGMII. Figure Top x-ref 3 TCP IP FIFO I/F MAC GMII/MII RGMII/ SGMII PCS PMA PMD Figure 4: Typical Ethernet Architecture MAC The Ethernet Medium Access Controller (MAC) is defined in IEEE 802.3-2005 clauses 2. 2009 Product Specification www. The TEMAC core can be extended to include SGMII functionality by internally connecting its PHY side GMII to the Ethernet 1000BASE-X PCS/PMA or SGMII core from Xilinx. PMA. usually a fibre optical physical standard using short and long wavelength laser DS297 April 24.com 5 . These are parallel interfaces connecting a MAC to the physical sublayers (PCS. At 10 Mbps and 100 Mbps.Tri-Mode Ethernet MAC v4. Two main physical standards are specified for Ethernet: • BASE-T. and can connected to. This figure also illustrates where the supported interfaces fit into the architecture. SGMII The Serial-GMII (SGMII) is an alternative interface to the GMII. PCS.

The 1000BASE-X architecture illustrated in Figure 1 can be provided by connecting the TEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core. supporting 10 Mbps. Descriptions of the functional blocks and interfaces are provided in the subsequent sections. As illustrated in Figure 2. Figure Top x-ref 4 Tri-Mode Ethernet MAC Core Client Transmitter Interface Transmit Engine Client Interface Flow Control GMII / MII Block To Physical Sublayers Client Receiver Interface Receive Engine Optional Address Filter Optional Management Client Management Interface Configuration MDIO Figure 5: TEMAC Functional Block Diagram 6 www. Core Overview Figure 5 identifies the major functional blocks of the TEMAC core. 100 Mbps. RGMII. 2009 Product Specification .1 BASE-T devices.Tri-Mode Ethernet MAC v4. or SGMII to provide a tri-speed Ethernet port. and 1 Gbps Ethernet speeds.xilinx. are readily available as off-the-shelf parts.com DS297 April 24. these can be connected using GMII/MII.

data. Transmit Engine The transmit engine takes data from the client and converts it to GMII format.1 Client Interface The client interface is designed for maximum flexibility in matching to a client switching fabric or network processor interface. the data is simply passed through. These two behaviors can be configured asymmetrically. Receive Engine The receive engine takes the data from the GMII/MII interface and checks it for compliance to the IEEE 802. Management Interface The optional Management Interface is a processor-independent interface with standard address.3-2005 clause 31.3 clause 22. Address Filter The TEMAC core can be implemented with an optional address filter.3.com 7 . the device can be configured using a configuration vector. The MAC can be configured to send pause frames with a programmable pause value and to act on their reception. The MDIO Interface is defined in IEEE 802. the device does not pass frames that do not contain one of a set of known addresses to the client. Padding fields are removed and the client is presented with the data along with a good or bad frame indicator. If it is not present.Tri-Mode Ethernet MAC v4. Flow Control The flow control block is designed to IEEE 802. If the address filter is enabled. At 1 Gbps. This interface is optional. MDIO Interface The optional MDIO interface can be written to and read from using the Management Interface. It is used for the configuration and monitoring of the TEMAC and for access to the MDIO Interface.xilinx. The receive engine also provides the receive statists vector for each received packet. GMII/MII Block The GMII/MII interface takes the data from the transmitter and converts it to MII format if the device is operating at speeds under 1 Gbps. The received data is converted into GMII format. The transmit engine also provides the transmit statistics vector for each packet and transmits the pause frames generated by the flow control module. The MDIO is used to monitor and configure PHY devices. and control signals. Each pathway is synchronous to txgmiimiiclk and rxgmiimiiclk respectively with transmit and receive enable inputs being driven to control the data throughput. It can be used as is or a wrapper can be applied (not supplied) to interface to common bus architectures. DS297 April 24. Preamble and frame check sequence fields are added and the data is padded if necessary. The data pathway is 8-bits wide in both the transmit and receive directions. 2009 Product Specification www.

Handshaking signal. Transmitter Client Side Interface Signal Definition Table 1 defines the client-side transmit signals of the TEMAC core. 2009 Product Specification . The example design connects the core to a FIFO-based loopback example design and adds IOB flip-flops to the external signals of the GMII/MII (or RGMII). This signal is present when: clientemactxenable Input txgmiimiiclk The TEMAC is generated for 10/100 Mbps only ethernet speed support. allowing you more flexibility in implementation (for example. clientemactxifgdelay[7:0] emacclienttxack clientemactxunderrun Input Output Input txgmiimiiclk txgmiimiiclk txgmiimiiclk Control signal for configurable interframe gap adjustment. For information about the example design. An example HDL design. Transmitter clock enable signal. which are used to transmit data from the client to the TEMAC core. Table 1: Transmit Client Interface Signal Pins (With Optional Clock Enables) Signal clientemactxd[7:0] clientemactxdvld Direction Input Input Clock Domain txgmiimiiclk txgmiimiiclk Description Frame data to be transmitted. emacclienttxcollision Output txgmiimiiclk emacclienttxretransmit Output txgmiimiiclk emacclienttxstats[31:0] emacclienttxstatsvld Note: All signals are active high.1 Interface Descriptions All ports of the core are internal connections in the FPGA fabric.Tri-Mode Ethernet MAC v4. provided in both VHDL and Verilog. The TEMAC is generated for tri-speed ethernet support when using the optional clock enables. When asserted at the same time as the emacclienttxcollision signal. this signals to the client that the aborted frame should be resupplied to the MAC core for retransmission. Asserted by the MAC core to signal a collision on the medium and that any transmission in progress should be aborted. A statistics vector that gives information on the last frame transmitted. All clock management logic is placed in this example design. is delivered with the core. Asserted by client to force MAC core to corrupt the current frame.xilinx.com DS297 April 24. Output Output txgmiimiiclk txgmiimiiclk 8 www. in designs using multiple cores). see the Tri-Mode Ethernet MAC Getting Started Guide. Asserted when the current data on clientemactxd has been accepted. Always 0 when the MAC core is in full-duplex mode. Asserted at end of frame transmission. Control signal for clientemactxd port. Always ’0’ when the MAC core is in full-duplex mode. indicating that the emacclienttxstats is valid.

See the User Guide for further information. At the end of the frame. All signals are synchronous to the txgmiimiiclk clock (not shown). The vertical dotted lines represent either a rising edge of the txgmiimiiclk clock (when clock enables are not in use).xilinx. at 10 Mbps.com 9 . at 100 Mbps. or a clock-enabled cycle (when clock enables are in use). At 1 Gbps. If used. each clock-enabled cycle is 80 ns apart. The client then waits until the TEMAC asserts emacclienttxack before sending the rest of the data. To transmit a frame the client asserts clientemactxdvld and puts the first byte of frame data on the clientemactxd bus. clientemactxenable is the clock enable signal. 2009 Product Specification www.1 Transmitter Client Interface Timing Figure 6 displays a typical frame transmission at the client interface. each clock-enabled cycle is 8 ns apart. each clock-enabled cycle is 800 ns apart. Figure Top x-ref 5 clientemactxd[7:0] DA SA L/T DATA clientemactxdvld emacclienttxack entemactxunderrun macclienttxcollision acclienttxretransmit Figure 6: Normal Frame Transmission across Client interface DS297 April 24.Tri-Mode Ethernet MAC v4. clientemactxdvld is deasserted.

com DS297 April 24. Provides information about the last frame received. Table 2: Receive Client Interface Signal Pins Signal emacclientrxd[7:0] emacclientrxdvld Direction Output Output Clock Domain rxgmiimiiclk rxgmiimiiclk Description Frame data received is supplied on this port. 2009 Product Specification . Asserted at end of frame reception to indicate that the frame should be discarded by the MAC client. Output rxgmiimiiclk 10 www. Receiver clock enable signal. Control signal for the emacclientrxd port.1 Receiver Client Side Interface Signal Definition Table 2 describes the client-side receive signals used by the core to transfer data to the client. indicating that the emacclientrxstats is valid.Tri-Mode Ethernet MAC v4.xilinx. The TEMAC is generated for tri-speed ethernet support when using the optional clock enables. This signal is present when: clientemacrxenable Input rxgmiimiiclk The TEMAC is generated for 10/100 Mbps only ethernet speed support. emacclientrxbadframe Output rxgmiimiiclk emacclientrxstats[27:0] Output rxgmiimiiclk emacclientrxstatsvld Note: All signals are active high. emacclientrxgoodframe Output rxgmiimiiclk Asserted at end of frame reception to indicate that the frame should be processed by the MAC client. Asserted at end of frame reception.

2009 Product Specification www. each clock-enabled cycle is 80 ns apart. All signals are synchronous to the rxgmiimiiclk clock (not shown). DS297 April 24. Table 3: Flow Control Interface Signal Pinout Signal clientemacpausereq clientemacpauseval[15:0] Note: All signals are active high.com 11 . each clock-enabled cycle is 8 ns apart. When receiving a frame. If used. at 10 Mbps. the emacclientrxgoodframe signal is asserted to indicate that the frame passed all error checks. At 1 Gbps. The vertical dotted lines represent either a single clock period of the rxgmiimiiclk clock (when clock enables are not in use). at 100 Mbps.xilinx. or a clock-enabled cycle (when clock enables are in use). See the User Guide for further information.1 Receiver Client Interface Timing Figure 7 displays the reception of a good frame at the client interface. Pause value: inserted into the parameter field of the transmitted pause frame. Figure Top x-ref 6 emacclientrxd[7:0] DA SA L/T DATA emacclientrxdvld emacclientrxgoodframe emacclientrxbadframe Figure 7: Normal Frame Reception at Client Interface Flow Control Client Side Interface Signal Definition Table 3 describes the signals used by the client to request a flow control action from the transmit engine. Direction Input Input Description Pause request: Upon request the MAC transmits a pause frame upon the completion of the current data packet.Tri-Mode Ethernet MAC v4. each clock-enabled cycle is 800 ns apart. clientemacrxenable is the clock enable signal. The frame is then passed to the client with emacclientrxbadframe asserted to indicate to the client that it should be dropped. the core asserts emacclientdvld for the duration of the frame data.3-2005. At the end of the frame. Valid flow control frames received by the MAC are automatically handled (if the MAC is configured to do so). The pause value in the received frame is used to inhibit the transmitter operation for the time defined in IEEE 802.

the MDIO interface has completed any pending transaction and is ready for a new transaction. including configuration. Data read from register. the address has some implicit don’t care bits. the MAC internal configuration is accessed.Tri-Mode Ethernet MAC v4. Defines operation to be performed over MDIO interface. Data to write to register. As can be seen. When asserted. 2009 Product Specification . Used to signal a transaction on the MDIO interface or to read from the statistic registers. Bit 1 is also used in configuration register access. such as flow control support. Configuration changes can be written at any time. When deasserted. The exceptions to this are the configurable resets which take effect immediately. Output hostclk Configuration Registers After power up or reset. Configuration of the TEMAC core is performed through a register bank accessed through the Management Interface. any access to an address in the ranges shown performs a 32-bit read or write from the same configuration word.xilinx. status and MDIO access. Address of register to be accessed.1 Management Interface Signal Definition Table 4 describes the optional signals used by the client to access the management features of the MAC core. hostreq Input hostclk hostmiimrdy Note: All signals are active high. Both the receiver and transmitter logic only sample configuration changes at the start of frame transmission/reception. the MDIO interface is accessed.com DS297 April 24. The configuration registers available in the core are detailed in Table 5. the client may reconfigure the core parameters from their defaults. Table 5: Configuration Registers Address 0x200-0x23F 0x240-0x27F 0x280-0x2BF 0x2C0-0x2FF 0x300-0x31F 0x320-0x33F 0x340-0x37F Description Receiver Configuration (Word 0) Receiver Configuration (Word 1) Transmitter Configuration Flow Control Configuration MAC Speed Configuration Reserved Management Configuration 12 www. When high. Table 4: Optional Management Interface Signal Pinout Signal hostclk hostopcode[1:0] hostaddr[9:0] hostwrdata[31:0] hostrddata[31:0] hostmiimsel Direction Input Input Input Input Output Input Clock Domain N/A hostclk hostclk hostclk hostclk hostclk Description Clock for Management Interface.

Table 6: Receiver Configuration Word 0 Bit Default Value Description Pause frame MAC Source Address[31:0] This address is used by the MAC to match against the destination address of any incoming flow control frames. Half Duplex If ‘1. a MAC address of AA-BB-CC-DD-EE-FF would be stored in Address[47:0] as 0xFFEEDDCCBBAA. 31-0 All 0s Table 7: Receiver Configuration Word 1 Bit 15-0 23-16 24 Default Value All 0s N/A 0 Description Pause frame MAC Source Address[47:32] See description in Table 6. 25 0 26 27 0 0 DS297 April 24.’ the core does not mark control frames as ‘bad’ if they are greater than the minimum frame length. 2009 Product Specification www. Length/Type Error Check Disable When this bit is set to ‘1.com 13 . for example. The address is ordered so the first byte transmitted/received is the lowest positioned byte in the register.duplex mode.1 Table 5: Configuration Registers Address 0x380-0x383 0x384-0x387 0x388-0x38B 0x38C-0x38F 0x390-0x3BF Description Unicast Address (Word 0) (if address filter is present) Unicast Address (Word 1) (if address filter is present) Address Table Configuration (Word 0) (if address filter is present) Address Table Configuration (Word 1) (if address filter is present) Address Filter Mode (if address filter is present) Configuration Register Definition Receiver Configuration The register contents for the two receiver configuration words can be seen in Table 6 and Table 7. If ‘0.xilinx. It is also used by the flow control block as the source address (SA) for any outbound flow control frames.’ the receiver operates in full.’ the core does not perform the length/type field error checks as described in the Tri-Mode Ethernet MAC User Guide.’ VLAN tagged frames are accepted by the receiver. When this bit is set to ‘0. Reserved Control Frame Length Check Disable When this bit is set to ‘1. VLAN Enable When this bit is set to ‘1.Tri-Mode Ethernet MAC v4.’ the length/type field checks is performed: this is normal operation.’ the receiver operates in half.duplex mode.

Reset When this bit is set to ‘1.’ the block ignores activity on the physical interface RX port.’ the MAC only accepts frames up to the specified maximum.’ This reset also sets all of the receiver configuration registers to their default values.1 Table 7: Receiver Configuration Word 1 Bit 28 Default Value 1 Description Receiver Enable If set to ‘1. In-band FCS Enable When this bit is ‘1.com DS297 April 24. the FCS is verified on the frame. 2009 Product Specification .’ the receiver is reset. In both cases. When this bit is ‘0. When it is ‘0.’ the receiver block is operational.xilinx. If set to ‘0. Jumbo Frame Enable When this bit is set to ‘1. 29 0 30 0 31 0 14 www.3-2005 maximum legal length.’ the client is not passed to the FCS.’ the MAC receiver accepts frames over the specified IEEE 802.Tri-Mode Ethernet MAC v4.’ the MAC receiver passes the FCS field up to the client as described in the Tri-Mode Ethernet MAC User Guide. The bit then automatically reverts to ‘0.

3-2005 maximum legal length.’ the transmitter operates in half-duplex mode. When this bit is ‘0. Table 8: Transmitter Configuration Word Bit 24-0 Default Value N/A Reserved Description 25 0 Interframe Gap Adjust Enable If ‘1.’ the MAC transmitter appends padding as required.Tri-Mode Ethernet MAC v4. In-band FCS Enable When this bit is ‘1. If ‘0. When this bit is ‘0.’ the MAC transmitter expects the FCS field to be passed in by the client as described in the Tri-Mode Ethernet MAC User Guide. 26 27 28 0 0 1 29 0 30 0 31 0 Flow Control Configuration The register contents for the Flow Control Configuration Word are described in Table 9. When it is ‘0.’ the transmitter is reset. VLAN Enable When this bit is set to ‘1. computes the FCS and appends it to the frame. When this bit is ‘0. Reset When this bit is set to ‘1.1 Transmitter Configuration The register contents for the Transmitter Configuration Word are described in Table 8.’ This reset also sets all of the transmitter configuration registers to their default values.’ received flow control frames are always passed up to the client. Table 9: Flow Control Configuration Word Bit 28-0 Default Value N/A Reserved Description 29 1 Flow Control Enable (RX) When this bit is ‘1. Jumbo Frame Enable When this bit is set to ‘1.’ the transmitter recognizes the transmission of VLAN tagged frames. Transmit Enable When this bit is ‘1. 2009 Product Specification www.’ the transmitter reads the value on the port clientemactxifgdelay at the start of frame transmission and adjusts the interframe gap following the frame accordingly (see Tri-Mode Ethernet MAC User Guide). DS297 April 24.3-2005.’ the transmitter is disabled. The bit then automatically reverts to ‘0.com 15 .’ the transmitter is operational.’ the transmitter outputs a minimum interframe gap of at least twelve clock cycles.’ received flow control frames inhibits the transmitter operation as described in the Tri-Mode Ethernet MAC User Guide.xilinx.’ the MAC transmitter sends frames that are greater than the specified IEEE 802. as specified in IEEE 802.’ the MAC only sends frames up to the specified maximum. Half Duplex If ‘1.

com DS297 April 24.xilinx. 16 www.1 Gbps Note: The setting of the MAC Speed Configuration register is not affected by a reset.are hard-coded to the value “10”.’ asserting the clientemacpausereq signal sends a flow control frame out from the transmitter as described in the Tri-Mode Ethernet MAC User Guide. When this bit is ‘0. Table 11: MAC Speed Configuration Word Bits 29-0 Default Value N/A Reserved Description MAC Speed Configuration 31-30 “10” “00” . .Tri-Mode Ethernet MAC v4. bits 31-3. MDIO Enable When this bit is ‘1. or “01” to configure for 100 Mbps operation. when the TEMAC core has been generated with tri-speed support. 2009 Product Specification .100 Mbps “10” .1 Table 9: Flow Control Configuration Word Bit Default Value Description Flow Control Enable (TX) When this bit is ‘1. A write to this bit only takes effect if Clock Divide is set to a non-zero value. Table 10: MDIO Configuration Word Bits 5-0 Default Value All 0s Description Clock Divide[5:0] See Tri-Mode Ethernet MAC User Guide. When the TEMAC core has been generated for only 10 Mbps and 100 Mbps speed support.’ asserting the clientemacpausereq signal has no effect.10 Mbps “01” . When this bit is ‘0.’ the MDIO interface is disabled and the MDIO signals remain inactive.’ the MDIO interface can be used to access attached PHY devices. When the TEMAC core has been generated for only 1 Gbps speed support. Reserved 30 1 31 MDIO Configuration N/A The register contents for the MDIO Configuration Word are described in Table 10. bits 31-30 only accept the values of “00” to configure for 10 Mbps operation. are described in Table 11. Reserved 6 0 31-7 N/A TEMAC Operational Speed Configuration The register contents for the MAC Speed Configuration Word.

com 17 . Unicast Address Configuration The register contents for the two unicast address registers are described in Table 12 and Table 13. The MAC address is ordered so that the first byte transmitted/received is the lowest positioned byte in the register. 2009 Product Specification www. These are stored in an address table within the address filter. a MAC address of AA-BB-CC-DD-EE-FF would be stored in Address[47:0] as 0xFFEEDDCCBBAA. Reserved In addition to the unicast address.1 Address Filter Configuration Table 12 through Table 16 describe the registers used to access the optional Address Filter configuration when the TEMAC core is implemented with an Address Filter. these registers will not exist and will return 0s for a read from the stated addresses. for example.If the TEMAC is generated without Address Table functionality then the following registers will not exist and will return 0s for a read from the stated addresses.Tri-Mode Ethernet MAC v4. for example. See description in Table 12. 31-0 tieemacunicastaddr[31-0] Table 13: Unicast Address (Word 1) Bits 15-0 31-16 Optional Address Table Default Value tieemacunicastaddr[47 downto 32] N/A Description Address filter unicast address[47:32]. This address is used by the MAC to match against the destination address of any incoming frames. Table 12: Unicast Address (Word 0) Bits Default Value Description Address filter unicast address[31:0]. See Tri-Mode Ethernet MAC User Guide. Table 14: Address Table Configuration (Word 0) Bits Default Value MAC Address[31:0]. broadcast address and pause addresses. Description 31-0 All 0s The lower 31 bits of MAC address that is to be written to the address table. If no address filter is present. DS297 April 24.xilinx. . the address filter can optionally be generated to respond to up to four additional separate addresses. a MAC address of AA-BB-CC-DD-EE-FF would be stored in Address[47:0] as 0xFFEEDDCCBBAA. Table 14 and Table 15 show how the contents of the table are set. The address is ordered so the first byte transmitted/received is the lowest positioned byte in the register.

2009 Product Specification . Reserved 17-16 22-18 All 0s N/A 23 0 31-24 N/A The contents of the address table mode register are described in Table 16. If it is set to ‘0. All 0s Description The upper 16 bits of MAC address: see the description in Table 14.1 Table 15: Address Table Configuration (Word 1) Bits 15-0 Default Value MAC Address[47:32].xilinx. Reserved Read not write This bit is set to ‘1’ to read from the address table. which uses direct inputs to the core to replace the functionality of the MAC configuration bits when the Management Interface is not used. Tables 11 through 13.Tri-Mode Ethernet MAC v4. There are up to 4 entries in the table (Location 0 to 3). Table 16: Address Filter Mode Bits 31 30-0 Default Value 1 N/A Description Promiscuous Mode If this bit is set to ‘1. The location in the address table that the MAC address is to be written to or read from. 18 www.com DS297 April 24.’ the contents of the table entry that is being accessed by bits 17-16 is output on the hostrddata bus in consecutive cycles (Least Significant Word first). Note: All bits of tieemacconfigvec are registered on input but can be treated as asynchronous inputs. If it is set to ‘1. and Table 16 are included in the vector. Table 17: Alternative to the Optional Management Interface: Configuration Vector Signal Pinout Signal tieemacconfigvec[67:0] Direction Input Description The Configuration Vector is used to replace the functionality of the MAC Configuration Registers when the Management Interface is not used.’ the data on bits 15-0 is written into the table at the address specified by bits 17-16. The configuration settings described in Tables 6 through 9. See the Tri-Mode Ethernet MAC User Guide for detailed information.’ the address filter is set to operate in promiscuous mode. Reserved Configuration Vector Signal Definition Table 17 describes the configuration vector. All frames are passed to the receiver client regardless of the destination address.

This output is asserted when the core is operating at either 10 Mbps or 100 Mbps. txgmiimiiclk Input rxgmiimiiclk Input speedis100 Output speedis10100 Output DS297 April 24.1 Address Filter Signal Definition Table 18 describes the address filter unicast address input. Output asserted when the core is operating at 100 Mbps. This clock should be used to clock the physical interface transmit circuitry. Table 19: Clock and Speed Indication Signals Signal reset Direction Input Description Asynchronous reset for entire core. Clock for the reception of data on the physical interface. If the core is generated with the clock enable option. Clock. Speed Indication.Tri-Mode Ethernet MAC v4. the clock signals that are input to the core.com 19 . 25 MHz at 100 Mbps. If the core is generated with the clock enable option. and 2. and Reset Signal Definition Table 19 describes the reset signal. 125 MHz at 1 Gbps. this clock is also used to clock the client receiver circuitry. 2009 Product Specification www. 25 MHz at 100 Mbps. and the outputs that can be used to select between the three operating speeds. Table 18: Address Filter Unicast Address Signal tieemacunicastaddr[47:0] Direction Input Description Vector used to set the default address for the MAC.xilinx. and 2. It is derived from a configuration register (if the optional Management Interface is present) or from the tieemacconfigvec configuration vector (if the optional Management Interface is not present). 125 MHz at 1 Gbps. this clock is also used to clock the client transmit circuitry. This clock should be used to clock the physical interface receive circuitry. It is derived from a configuration register (if the optional Management Interface is present) or from the tieemacconfigvec configuration vector (if the optional Management Interface is not present). The clock signals are generated in the top-level wrapper provided with the core.5 MHz at 10 Mbps.5 MHz at 10 Mbps. Clock for the transmission of data on the physical interface.

Output data signal for communication with PHY configuration and status.com DS297 April 24. Input data signal for communication with PHY configuration and status.3-2005 clause 35. emacphytxd[7:0] emacphytxen emacphytxer phyemaccrs phyemaccol phyemacrxd[7:0] phyemacrxdv phyemacrxer Output Output Output Input Input Input Input Input gmiimiitxclk gmiimiitxclk gmiimiitxclk N/A N/A gmiimiirxclk gmiimiirxclk gmiimiirxclk Transmit data to PHY Data Enable control signal to PHY Error control signal to PHY Control signal from PHY Control signal from PHY Received data from PHY Data Valid control signal from PHY Error control signal from PHY 20 www.3-2005 clause 22. Table 21: Optional GMII Interface Signal Pinout Signal Direction Clock Domain Description Transmitter clock enable signal for the GMII/MII logic within the TEMAC core. Table 21 describes the GMII/MII signals of the TEMAC core.Tri-Mode Ethernet MAC v4.xilinx. ’0’ signals that the value on MDIO_OUT should be asserted onto the MDIO bus. The TEMAC is generated for tri-speed ethernet support when using the optional clock enables. Tie high if unused. which are typically connected to the MDIO port of a PHY device.3-2005 clause 22. either off-chip or internally integrated. Table 20: MDIO Interface Signal Pinout Signal emacphymclkout emacphymdin emacphymdout emacphymdtri Direction Output Input Output Output Description MDIO Management Clock: derived from hostclk on the basis of supplied configuration data when the optional Management Interface is used. either off-chip or an SoC-integrated core. The MDIO format is defined in IEEE 802. The GMII is defined in IEEE 802. which are typically attached to a PHY module. Tristate control for MDIO signals.1 Physical Interface Signal Definition Table 20 describes the MDIO (MII Management) interface signals of the TEMAC core. and MII is defined in IEEE 802. This signal is present when: phyemactxenable Input gmiimiitxclk The TEMAC is generated for 10/100 Mbps only ethernet speed support. 2009 Product Specification .

status and statistical counter registers. including a back-end FIFO capable of performing a simple ping function and a test pattern generator. Software running on the embedded PowerPC® processor was used to provide access to all configuration. 2009 Product Specification www.1 Verification The TEMAC core has been verified with extensive simulation and hardware testing. Tests include: • Register Access • MDIO Access • Frame Transmission and Error Handling • Frame Reception and Error Handling • Address Filtering Hardware Verification The TEMAC core has been tested in a variety of hardware test platforms at Xilinx to address specific parameterizations.xilinx. The MAC has been connected to external BASE-T PHY devices using both GMII and RGMII interfaces. • Testing with an external PHY device. A test platform was built around these cores. Virtex-5 and Spartan-3A DSP devices. including a back-end FIFO capable of performing a simple ping function and a test pattern generator. Software running on an embedded processor (PowerPC or MicroBlaze™) was used to provide access to all configuration. as detailed in this section. Virtex-6 and Spartan-6 FPGA families contain six input LUTs. Device Utilization The Virtex-5. the device utilization for these families are listed separately. Testing has been performed in Virtex-4. Simulation A highly parameterizable transaction-based test bench was used to test the core. Testing has been performed in Virtex-4 and Virtex-5 devices. as illustrated in the architecture displayed in Figure 2. all other families contain four input LUTs. A test platform was built around the core. as illustrated in the architecture displayed in Figure 3.Tri-Mode Ethernet MAC v4. including the following: • Testing with the Ethernet 1000BASE-X PCS/PMA or SGMII core.com 21 . For this reason. Please see either of the following sections: • New Device Families (including Virtex-5 Devices) • Other Device Families DS297 April 24. status and statistical counter registers.

5V only. Virtex-4. BUFG usage: • does not consider multiple instantiations of the core. please see the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics for more information. LUT and FF figures will be slightly reduced. Other families (Spartan-6. Table 22 does not differentiate between tri-speed support and 1 Gbps only support for GMII and RGMII Physical Interfaces. Spartan-6 and Spartan-3 devices support MII and GMII at 3. The numbers quoted are for tri-speed support. Virtex-5.Tri-Mode Ethernet MAC v4. Table 22: Device Utilization for New Device Families Core Parameters Physical Interface GMII GMII GMII GMII GMII GMII GMII GMII GMII GMII RGMII RGMII RGMII RGMII RGMII RGMII RGMII RGMII Management Interface Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes Half Duplex support No No No No No Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Address Filter Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Addr Table Entries 4 0 N/A 0 N/A 4 0 N/A 0 N/A 4 0 N/A 0 N/A 4 0 N/A Slices 740 665 590 510 490 950 830 800 690 675 741 610 600 515 490 900 775 775 Device Resources LUTs 1190 990 850 780 720 1540 1340 1200 1130 1070 1220 1010 880 810 750 1580 1400 1230 FFs 1200 1150 1010 890 840 1420 1365 1230 1100 1050 1220 1160 1030 905 740 1435 1380 1245 BUFGs 3 3 3 2 2 3 3 3 2 2 3 3 3 2 2 3 3 3 22 www.xilinx.1 New Device Families (including Virtex-5 Devices) Table 22 provides approximate utilization figures for various core options when a single instance of the core is instantiated in a Virtex-5 device. This wrapper is part of the example design and connects the core to the selected physical interface. 1 Gbps only support Slice. This clock source can be shared across the entire device and is not core specific. Virtex-6) have similar utilization figures. Utilization figures are obtained by implementing the block level wrapper for the core. 2009 Product Specification . where clock resources can often be shared. Note: Virtex-6 devices support GMII and MII at 2.3V or lower.com DS297 April 24. • does not include the reference clock required for IDELAYCTRL.

2009 Product Specification www. where clock resources can often be shared.com 23 . DS297 April 24. 1 Gbps only support Slice. Table 23 does not differentiate between tri-speed support and 1 Gbps only support for GMII and RGMII Physical Interface. BUFG usage does not consider multiple instantiations of the core. Spartan-4. LUT and FF figures will be slightly reduced.Tri-Mode Ethernet MAC v4. Spartan-3E. Spartan-3A DSP) have similar utilization figures.1 Table 22: Device Utilization for New Device Families Core Parameters RGMII RGMII MII MII MII MII MII MII MII MII MII MII No No Yes Yes Yes No No Yes Yes Yes No No Yes Yes No No No No No Yes Yes Yes Yes Yes Yes No Yes Yes No Yes No Yes Yes No Yes No 0 N/A 4 0 N/A 0 N/A 4 0 N/A 0 N/A 685 642 700 620 560 475 445 880 800 795 670 610 Device Resources 1160 1095 1180 1010 830 760 700 1530 1355 1180 1095 1040 1120 1070 1180 1125 990 865 815 1400 1340 1210 1080 1030 2 2 3 3 3 2 2 3 3 3 2 2 Other Device Families Table 23 provides approximate utilization figures for various core options when a single instance of the core is instantiated in a Spartan-3A device. Other families (Virtex-4.xilinx. The numbers quoted are for tri-speed support. Utilization figures are obtained by implementing the block-level wrapper for the core. This wrapper is part of the example design and connects the core to the selected physical interface.

2009 Product Specification .1 Table 23: Device Utilization for Spartan-3 and Virtex-4 Families Core Parameters Physical Interface GMII GMII GMII GMII GMII GMII GMII GMII GMII GMII RGMII RGMII RGMII RGMII RGMII RGMII RGMII RGMII RGMII RGMII MII MII MII MII MII MII MII MII MII MII Management Interface Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes No No Half Duplex support No No No No No Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Address Filter Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Yes No Addr Table Entries 4 0 N/A 0 N/A 4 0 N/A 0 N/A 4 0 N/A 0 N/A 4 0 N/A 0 N/A 4 0 N/A 0 N/A 4 0 N/A 0 N/A Slices 1470 1260 1180 970 955 1725 1670 1420 1310 1255 1605 1370 1260 1040 1030 1850 1750 1550 1390 1355 1410 1250 1070 930 900 1730 1565 1420 1225 1210 Device Resources LUTs 1610 1190 1040 930 895 2045 1660 1470 1360 1300 1645 1260 1080 970 1000 2080 1660 1510 1400 1340 1600 1205 1020 915 855 2000 1620 1440 1335 1275 FFs 1230 1170 1040 915 860 1445 1390 1255 1130 1075 1295 1240 1100 980 930 1510 1455 1320 1195 1140 1180 1125 990 870 820 1400 1345 1210 1080 1030 BUFGs 3 3 3 2 2 3 3 3 2 2 4 4 4 3 3 4 4 4 3 3 3 3 3 2 2 3 3 3 2 2 DCM 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 24 www.Tri-Mode Ethernet MAC v4.xilinx.com DS297 April 24.

Please contact your local Xilinx sales representative for pricing and availability about Xilinx LogiCORE IP modules and software or see the Xilinx IP Center. Acronym DA DCM DDR FCS FF FIFO FPGA GBIC Gbps GMII HDL IO Spelled Out Destination Address Digital Clock Manager Double Data Rate Frame Check Sequence flip-flop First In First Out Field Programmable Gate Array. and the Full System Hardware Evaluation license. Ordering Information This Xilinx LogiCORE IP module is provided under the SignOnce IP Site License. visit www. or support of product if implemented in devices that are not listed in the documentation. Spartan-3A. if customized beyond that allowed in the product documentation.1 References [1] Virtex-4. functionality. Spartan-3A DSP FPGA Data Sheets [3] IEEE 802. both in simulation and in hardware. List of Acronyms The following table describes acronyms used in this manual. and Virtex-6 FPGA User Guides [2] Spartan-6. or if any changes are made in sections of design marked DO NOT MODIFY. Xilinx cannot guarantee timing. please go to the TEMAC product page for more information on generating your TEMAC license key for use with the Xilinx Core Generator System v11.3-2005 specification Support For technical support. which lets you test your designs in hardware for a limited period of time. For full access to all core functionality. 2009 Product Specification www.xilinx.Tri-Mode Ethernet MAC v4.1.com 25 . Xilinx provides technical support for this product when used as described in the product documentation. Spartan-3AN. and Virtex-5.xilinx. Spartan-3E. After purchasing. Gigabit Interface Converter Gigabits per second Gigabit Media Independent Interface Hardware Description Language Input/Output DS297 April 24.com/support. you must purchase the core. Two free evaluation licenses are provided: The Simulation Only license is provided with the CORE Generator™ software. can be downloaded from the TEMAC product page. Spartan-3.

2009 Product Specification .1 Acronym IOB IP ISE LUT MAC Mbps MDIO NGC NGD PCS PHY PMA PMD RGMII SA SFP SGMII TEMAC UCF VHDL Spelled Out Input/Output Block Intellectual Property Integrated Software Environment Lookup Table Media Access Controller Megabits per second Management Data Input/Output Native Generic Circuit Native Generic Database Physical Coding Sublayer physical-side interface Physical Medium Attachment Physical Medium Dependent Reduced Gigabit Media Independent Interface Source Address Small Form-Factor Pluggable Serial Gigabit Media Independent Interface Tri-Mode Ethernet MAC User Constraints File VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits).Tri-Mode Ethernet MAC v4.com DS297 April 24.xilinx. Virtual LAN (Local Area Network) VLAN 26 www.

2 of the core. DS297 April 24.8.1 of the core. without the prior written consent of Xilinx. © 2009 Xilinx.3. Core version updated to 3. Xilinx makes no representation that the Information. The PowerPC name and logo are registered trademarks of IBM Corp. version 2. or otherwise. Except as stated herein.1 3. reproduced. Revision Updated to version 2.” to you “AS IS” with no warranty of any kind.com 27 .1i. 2009 Product Specification www.2 3. express or implied. photocopying.09 Notice of Disclaimer Xilinx is providing this product documentation. is free from any claims of infringement.1 3. Added Spartan-6 and Virtex-6 devices. none of the Information may be copied. posted. All specifications are subject to change without notice. Mentor Graphics ModelSim v6.2. republished. Synopsys 2008.Tri-Mode Ethernet MAC v4. Update core to version 3. and used under license.4b.6 Initial draft. Cadence IUS v6.1.1 Revision History The following table provides the document revision history. Initial Xilinx release.xilinx. XILINX. Xilinx tools v9.0 2. distributed. or transmitted in any form or by any means including. displayed. electronic. Spartan.2i. and support for Spartan-3E devices.5 3. Update core to version 4.4.1.1.5. and Xilinx tools 8.0 1. recording. the Xilinx logo.1i Core version 3. Cadence IUS v5. hereinafter “Information. but not limited to. All other trademarks are the property of their respective owners. INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.1i. Xilinx tools v11. Virtex. Spartan-3A device added to supported device family in Facts table. Updated core to version 3. You are responsible for obtaining any rights you may require for any implementation based on the Information.4 3. mechanical.1. Xilinx tools 8. Xilinx tools v10.3 3. or any particular implementation thereof.2i. downloaded.1 2. Updated to version 3.1-s009.1. Date 7/06/04 9/24/04 4/28/05 1/18/06 7/13/06 9/21/06 2/15/07 8/8/07 3/24/08 4/24/09 Version 1. Inc. Updated to release date. Cadence IUS v8. ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Xilinx tools v7. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON. Xilinx tools 9.

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