CONTENTS

Bonafide………………………………………………………………………………. .i
Acknowledgement……………………………………………………………………. ii
Abstract……………………………………………………………………………......iii
Company Bonafide
1 Introduction 1
1.1 Restrictions 1
1.2 About instruction set simulator 1
1.2.1 Flow of input in the system software development tool chain 2
1.3 Format of the Intel Hex Record 3
1.4 E.g. Intel Hex files: 4
2 Problem Definition 5
2.1 Absolute file reader 5
2.2 Loader 5
2.3 Instruction decoder 5
2.4 Disassembler 5
2.5 Simulation engine 5
2.6 Simulator user-interface 5
3 Requirements 6
3.1 System requirement 6
3.2 Software requirement 6
3.3 Prerequisites: 6
4 Modules and Design 7
4.1 Absolute Reader 7
4.1.1 Algorithm 7
4.1.2 Note 8
4.1.3 Structure for IntelHexrecord 9
4.1.4 Prototypes of internal functions 10
4.1.5 Algorithm DecodeIntelHexRecords 10
4.1.6 Algorithm ConvertStringToInteger 11
 4.1.7 Algorithm StoreIntelHexRecord 12
4.2 Loader 13
4.2.1 Algorithm for load the opcode 13
4.2.2 Reset the ProgramCounter 14
4.2.3 Algorithm for Initialize the Program Counter 14

4.3 Instruction Decoder 15

4.3.1 Algorithm for Decode Instruction 16
4.3.2 Structure for Decode Instruction 16
4.3.3 Note 20
4.3.4 Prototypes of internal functions 20
4.4 Disassembler 22
4.4.1 Algorithm 22
4.4.2 Prototypes of internal functions 22
4.5 Simulation Engine 23
4.5.1 Algorithm 23
4.5.2 Structure for storing address (push & pop Instruction) 23
4.5.3 Algorithm for update memory value 24
4.5.4 Prototypes of internal functions 24
4.6 Simulator user-interface 27
4.6.1 Structure for Register values & PSWFlag 27
4.6.2 Algorithm for Display the Memory Value 28
4.6.3 Display register value & Flag values 29
5 Results and Discussion 30
5.1 Workspace 30
5.2 Input Object File 31
5.3 Absolute Reader output 32
5.3.1 The output for this input is shown below 32
5.3.2 Now we change the original object file 33
5.3.3 Now we change the input file for checksum validation 35
 5.4 Loader 39
5.4.1 Initializing the programCounter 39
5.5 Disassembler 40
5.6 Display Memory , Register & Flag values 41
5.6.1 Display Memory value & Simulation of instruction 41
5.6.2 Display Register values & flag values & PSW value 43
5.6.3 Instruction not defined in the Reduced Instruction table 44
6 Conclusion 45