IEEE 1KANSACTIONS ON EDUCATION, VOL. 35, NO.

3, AUGUST 1992 247

Top-Down Design Process for Gate-Level

Combinational Logic Design
Richard S. Sandige, Senior Member, IEEE

Abstract-This paper describes a pedagogical process for de-

signing gate-level combinational logic circuits. The process can be Use logic descriptions to
used for either combinational logic circuits or the combinational Step 1 obtain Boolean functions or
logic sections of sequential logic circuits. Positive logic signals their complements in SOP
(active high signals) as well as negative logic signals (active low (Top level)
form. and write the functions in
signals) can be used in the design process. The top-down design
process allows the student to draw functional logic diagrams in design form (availible form).
a rather routine manner using the positive logic convention, or
the direct polarity convention. After obtaining functional logic 1
diagrams, realizable logic diagrams can be easily obtained using
any of the common off-the-shelf gate types including AND, OR, Obtain the signal lists
NAND, and NOR elements with appropriate inverter symbols. (choose the logic convention
Step 2
The advantage of the top-down design process is that students can for each availible signal to
very easily understand and implement gate-level combinational (Next level down 1
match its signal source or
logic functions. Examples are provided to illustrate the top-down signal destination).
design process in teaching combinational logic design.

I. INTRODUCTION

T HIS paper describes a rather unique design technique

for the design of combinational logic circuits. The top-
down design process for gate-level combinational logic design
Step 3
documentation ior the circuits
(document the layout steps

is a refinement of the “voltage symbolism” design technique

r - l
described by Rhyne [ 11. The voltage symbolism technique was
applauded and used extensively in industry since it provided
Obtain the functional logic
direct conversion from AND-OR-NOT expressions (either
Step -i diagrams.
sum-of-products form or product-of-sums form) to circuitry
that used NAND or NOR gates without losing the AND/OR
or OR/AND structure of the expressions. The top-down design
Obtain the realizable
process [2] is an improvement over the voltage symbolism Step 5
design technique. The steps involved in the top-down design
process are illustrated in the flowchart in Fig. 1. 1
The student can apply each design step in a relatively simple
manner, Obtaining logic diagrams to express the functionality
of a set of combination logic equations is the first step
towards understanding how to implement the equations. Once
Steo 0
aottom or im Iewi I
Obtain the aetailed
logic diagrams. I
Fig. 1. Flowchart for the top-down design process for gate-level combina-
the functional logic diagrams are obtained, these diagrams tional logic design.
can easily be converted into realizable logic diagrams using
preferred or readily available off-the-shelf gate-level logic
elements. form). The top-down design process works equally well for
functions expressed in canonical SOP or POS form or in
reduced SOP or POS form. Obtaining a circuit implementation
THE TOP-DOWN
11. TEACHING DESIGNPROCESS
with a minimum number of logic elements requires using
Beginning with Step 1 in the top-down design process, minimum functions, i.e., functions with a minimum number of
the student should first obtain the logic descriptions of the
literals. The designation of an input or an output signal in most
Boolean functions or their complements in either sum-of-
cases is expressed as a single variable such as X or as a more
products form (SOP form) or product-of-sums form (POS
meaningful signal name such as START. An input or output
Manuscript received October 1990; revised October 1991. signal can also be expressed as a complemented variable such
The author is with the Department of Electrical Engineering, University of
Wyoming, Laramie, WY 82071. as or STOP using an overbar €or the complement, or for
IEEE Log Number 9201007. in-line notation ANSI/IEEE Std 991-1986 [3] suggests the
0018-9359/92/0800-$03.00 0 1992 IEEE
248 IEEE TRANSACTIONS ON EDUCATION, VOL 35, NO. 3, AUGUST 1992

t I

ctrnit 9
Logic layout part (LLP)
Use the available form of
Step 3a the Boolean function to
write the Boolean function

m
clrcoit 4
using only the available
signals (remove the overbars).

?;I ?g
--
PL
PL
circuit 2

8
c
T 1
Avdable
conventlons signais
B,r

‘:.
I PL F1
1
Negation indication part (NIP)
Use the available form of the
Boolean function. For positive
Step 3b logic sign&, list 1 for each
Fig. 2. Representation of the signal logic conventions and available signals unbarred literal and 0 for each
for (1). barred literal. For negative
logic signals, list 0 for each
unbarred literal and 1 for
-
symbol 1 or can be used preceding the signal name and each barred literal.
results in the following examples for complemented variables:
-A, - A , T S T O P , “ S T O P . In this paper, when a signal is
accessible at an input or an output it will be referred to as Fig. 3. Design documentation procedure for diagrams using the positive
logic convention.
an available signal. An accessible or available signal can be
written as an uncomplemented variable or as a complemented
variable. For signal names that are complemented, we will Step 1 in design form (available form-in a form that uses
use the notation “VARIABLE. When a function is written the accessible signals required for the design).
using the accessible signals for the problem, we refer to the The next step, step 3, in the top-down design process is to
function as being written in design form (available form). obtain the design documentation for the circuit. The design
As an example, assume a student wants to implement the documentation procedure illustrated in Steps 3(a) and 3(b)
following reduced Boolean function for Circuit 3 shown in in Fig. 3 are used to accurately document the steps required
Fig. 2. to draw functional logic diagrams using the positive logic
convention. A summary of Steps 1 through 3 in the top-down
Fl= A.B.C+X.C. (1) design process is presented below for (1).

Fig. 2 illustrates that Circuit 3 is dependent on the available
signals coming from Circuit 1 and Circuit 2; that is, positive
logic (PL) signals A , B, and C. In addition, Circuit 3 is
required to supply the available signal required by Circuit 4;
that is, positive logic (PL) signal F1. Since the variables in
(1) are presently written in terms of the accessible or available
signals needed at the inputs and output of Circuit 3, we refer
to (1) as being written in design form (available form). This
completed Step 1 in the top-down design process.
Step 2 (the next level down) in the top-down design process
is used to document the available signals, i.e., the accessible
signals, in an organized list as
List of available signals: Fl, A , B, C
or Signal list: F1, A , B,C.
The available signals in the signal list are implied to
be positive logic signals unless otherwise stated. The vast
majority of designs in industry involve positive logic signals
as opposed to negative logic signals; however, the top-down
design process can be used when the signal list contains
all positive logic signals, all negative logic signals, or a
mixture of positive and negative logic signals that are either
complemented or uncomplemented. To accommodate such a
variety of available signals requires writing the functions for
Step 1: FI =A.B.C+A.C
Step 2: Signal list: F1, A , B . C
Step 3(a) : Logic Layout Part (LLP) :
F1= A . B . C +A.C
Step 3(b) : Negation Indication Part (NIP):
1 1 1 0 0 1
Obtaining the logic layout part (LLP), step 3(a), of the
design documentation just requires removing the overbars
above the available signals in (1) as illustrated above. Since
there are only positive logic signals in the signal list for
(l), a 1 is listed under each available signal in Step 3(a)
for each unbarred literal in (l), and a 0 is listed under each
available signal in Step 3(a) for each barred literal in (1).
This completes the negation indication part (NIP), step 3( b) of
the design documentation as shown above. Notice in Fig. 3,
step 3(b), that the design process for negative logic signals
is the complement of the design process for positive logic
signals. This should be quite evident since a positive logic
signal A can be obtained from a negative logic signal A by
simply adding an inverter (complementing the negative logic
signal) as illustrated in Fig. 4.
The functional logic diagram using the positive logic con-
vention for (l), step 4, can now be easily drawn and labeled
SANDIGE: TOP-DOWN DESIGN PROCESS 249

Negauve
logic
,
I
I
Postive
lopc
Device
names AND elenieni symbols OR elemenl symbols

convention I
I
I
convention

OUT= A
Positive lopic
4XD gales
a-=-
.4
I
I
-
A OUT
I
I
-
,
A = l = L
.4=O=H
1

I
I
A
-= O = L
A = l = H
A = I =H
A=O=L *==cr
Dc4lorg;in eauivaienr sjmaoir Dsrs book bvmbols

Fig. 4. Converting a negative logic signal .to a positive logic signal .-I
I

LLp:+NLp:
D m coo& s! inoois Dehlorgm equivnlenr symoois
A
B m
F1

Positive logic
convention (ac) Fig. 6. Equivalent AND and OR element symbols for normally available
devices.
Fig. 5. Functional logic diagram for (1) using the positive logic convention.

from the logic layout part (LLP) of the design documentation,

step 3(a), using simple AND and OR elements in the specified
SOP form as illustrated in Fig. 5. To complete the functional
logic diagram, a negation symbol “0” is added at each input
and output where a 0 appears in the negation indication part
(NIP) of the design documentation, step 3(b), as shown in
Fig. 5.
Step 5 in the top-down design process for gate-level com-
binational logic design is to obtain realizable logic circuit
diagrams. By realizable logic diagrams we mean obtaining
diagrams that use off-the-shelf IC devices. This step is easily
accomplished by using equivalent AND and OR element
symbols for available devices and equivalent signal lines.
Fig. 6 illustrates equivalent AND and OR element symbols
for normally available devices. The data book symbols are the
symbols used in manufacturer’s data books, while DeMorgan
equivalent symbols are the equivalent symbol representa-
tions. The Inverter and its equivalent are illustrated in Fig. 7,
which shows equivalent signal lines for inputs and outputs.
A functional logic diagram can be easily changed by the
student to a realizable logic diagram by making equivalent
signal line substitutions and using equivalent AND and OR
element symbols for the desired gate types, as illustrated in
Fig. 8(a)-(d) for the four types of realizable circuits resulting
from an SOP form of the function for (1). In a similar manner,
the student can easily obtain the four types of realizable
circuits resulting from a POS form of the function; namely the
OR/AND, NORINOR, ANDINOR, and NAND/AND forms
of circuits. The voltage symbolism technique required that
the student first choose the types of off-the-shelf devices to
be used in a design and then use these to obtain realizable
(c) (d)
Fig. 7 . Equivalent signal lines. (a), (b) for inputs; (c), (d) for outputs.
logic circuits. The top-down design process provides greater
flexibility by allowing the student to obtain functional logic
diagrams before choosing off-the-shelf devices. In addition,
the top-down design process allows the student to obtain logic
diagrams using either the positive logic convention or the
direct polarity convention, as will be illustrated in the design
example in the next section. The direct polarity convention
is also referred to as direct polarity indication and sometimes
mistakenly referred to as the mixed logic convention.
The last step, step 6, in the top-down design process is sim-
ply to obtain detailed logic diagrams from realizable logic dia-
grams. A detailed logic diagram is a logic diagram that depicts
the circuit as it is actually implemented; it may also include
information for manufacturing and maintenance. The final
detailed logic diagram is usually obtained using a schematic
capture program to speed up the design process. Detailed logic
diagrams usually include such items as: a) reference desig-
nators to identify each package; b) each part value or type:
c) pin numbers for input and output signals; and d) the pin
numbers for power and ground, in addition to other pertinent
items for manufacturing and maintenance. The student needs
to obtain a detailed logic diagram prior to wiring up a circuit
in the laboratory. The choice of whether to obtain detailed
logic diagrams using the positive logic convention or the
250 IEEE TRANSAC'I'IONS ON EDUCATION, VOL. 35. NO. 3, AUGUST 1992

TABLE I

A -B C -D F2

0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
PLC 0
0
0
1
1
0
1
0
0
1
0 1 0 1 1
0 1 1 0 0
AND/OR form 0 1 1 1 0
I 0 0 0 1
(a)
1 0 0 1 0
1 0 1 0 I
1 0 1 I O
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

,
--, -3

Fig. 9. Kdrnaugh map for design example.

have to e if these columns were complemented with B used

A
C PLC
NOWOR form
(d 1
Fig. 8. Realizable circuit implementations for an SOP form of (1).
direct polarity convention is a matter of preference. In the
next section, the top-down design process will be presented
using the direct polarity convention.
111. A DESIGNEXAMPLE
The student is requested in this example to obtain a com-
binational logic circuit implementation for the truth table
(Table I) listed below and to obtain a realizable logic circuit
diagram using the direct polarity convention.
The signal list, i.e., the list of accessible or available signals,
is F2, A , " B , C , and "D. Available signals " B and " D are
also used in the truth table description, but they would not
in place of available signal "I? and D used in place of available
signal "D. If these changes were made, students would still
have to write the equation in design form (available form-in
a form that uses the accessible signals required for the design)
for Step 1 in the top-down design process.
To minimize the function with pencil and paper (as opposed
to using a computer reduction program such as the Student
Version of PLDesigner [4]), the student needs to plot the
function on a Karnaugh map as shown in Fig. 9. From the
product terms p 1 through p 3 , the student writes the Boolean
function as indicated below to obtain the SOP form of the
function in design form with its accompanying signal list.
Since most engineers generally prefer to write a function in
SOP form, this is what we will use; however, if one prefers,
the function can be written in POS form and still follow the
top-down design process.
F 2 = Pl + P 2 + P3
= 3. + A . "B. + A . " B ."D (2)
Signal list: F2. A. -B, C, " D
This represents Steps 1 and 2 in the top-down design
process. Steps 3(a) and 3(b) in Fig. 10 illustrate the design
SANDIGE: TOP-DOWN DESIGN PROCESS 25 1

h g i c layout part (LLP)

Uee the available form of
Step 3a the Boolean function to
write the Fk“h c h
udng only the eveilsble
signals (remove the overban).

1 -E o r - Direct polarity
convention @PC)
Use the available form of the
Boolean h a l k m . For poeitive Fig. 11. Functional logic diagram for (2) using the direct polarity conven-
Step 3b logic signals, Est H for each tion.
unbarred literal and L for each
ImmdIIted. Fornegative
logic signah, Hst L for each
unbarred kmal and U for
each b a n d IiternL

Fig. 10. Design documentation procedure for diagrams using the direct
polarity convention.

documentation process for obtaining a functional logic

diagram using the direct polarity convention.
Following these simple steps, the student can write the
design documentation as follows. It should be noted that the
signal list contains only positive logic signals (active high
signals).
LLP: F 2 = N B . N D+ A . B . C+ A .
N N
PIP: H L L L H L H
To obtain the logic layout part (LLP), step 3(a), of the de-
sign documentation just requires removing the overbars above
the available signals in (2) as illustrated above. Remember
that positive logic signals in the positive logic convention
are equivalent to active high signals in the direct polarity
convention, and negative logic signals in the positive logic
convention are equivalent to active low signals in the direct
polarity convention. In ANSI/IEEE Std 991-1986, it is stated
“If all signal names on a diagram are true when high, the logic
level indication may be omitted from the names”. Therefore, it
is not unusual in data books [5], [6] and industrial schematics
to see positive logic signals used in place of active high signals
on diagrams using the direct polarity convention. Since the
signal list for (2) only specified positive logic signals (active
high signals) for the design, an H is listed under each available
signal in the LLP, step 3(a), for each unbarred literal in (2), and
an L is listed under each available signal in the LLP, step 3(a),
for each barred literal in (2). This completes the polarity
indication part (PIP), step 3( b), of the design documentation
as shown above.
The functional logic diagram using the direct polarity con-
vention for (2), step 4, can now be drawn and labeled from
the logic layout part (LLP) of the design documentation, using
simple AND and OR elements in the specified SOP form
as illustrated in Fig. 11. To complete the functional logic
diagram, a polarity symbol ‘‘A” is added at each input and
output where an L appears in the polarity indication part (PIP)
of the design documentation as shown in Fig. 11.
One possible realizable logic diagram, step 5 in the top-
down design process, is obtained as shown in Fig. 12
(NAND/NAND form) using the direct polarity convention.
This diagram was obtained using equivalent AND and OR
element symbols for the normally available devices shown in
DPC
Fig. 12. Realizable logic diagram for (2) using NAND gates and inverters
(NANDNAND form).
Fig. 6 and equivalent signal lines for inputs and outputs shown
B. N D in Fig. 7, with a small modification. The polarity symbol was
H H mentally substituted for the negation symbol in each of these
diagrams. This modification converts the diagrams in Figs. 6
and 7 from the positive logic convention to the direct polarity
convention.
Even though the majority of designs involve available
positive logic signals that may be either complemented or un-
complemented as illustrated by the design example presented
above, the top-down design process is versatile enough to
handle both positive and negative logic signals in the same
design. Negative logic signals that may occur in a design can
also be handled with ease using step 3(b) in Fig. 3 for the
positive logic convention or step 3( b) in Fig. 10 for the direct
polarity convention. Negative logic signals may be noted in a
signal list as X [ N L ]when using the positive logic convention,
while active low signals may be noted in the signal list as
X ( L ) when using the direct polarity convention. Since the
last step, step 6, in the top-down design process involves the
technology used for specific available gate types, this will not
be shown.
IV. CONCLUSIONS
The top-down design process can be used as an effec-
tive method for the design of gate-level combinational logic
circuits. There are several advantages to using this design
technique over the popular voltage symbolism technique. The
top-down design process divides the problem into easily man-
ageable steps to reduce student errors. After obtaining reduced
or minimum design equations and the required signal list, the
student obtains the design documentation for the type of circuit
diagram desired-either the positive logic convention or the
direct polarity convention. With the design documentation
description specifically written down, the student can simply
draw AND/OR or OR/AND type circuits and add the required
negation symbols or polarity symbols to obtain functional
252
logic diagrams. From these functional logic diagrams, the
student can use equivalent AND and OR element symbols and
substitute equivalent signal lines to obtain realizable circuits
for the desired gate types.
ACKNOWLEDGMENT
The author would like to thank A. Elken at McGraw-Hill
Publishing Company for his help in soliciting peer reviews
for the top-down design process during the time the text
Modern Digital Design was being written. He would also like
to thank the following reviewers for their helpful comments
and suggestions concerning the top-down design process:
S. W. Director, Carnegie-Mellon University; P. I. P. Boulton,
University of Toronto; T.-S. Chung, University of Kentucky;
J.D. Dixon, University of North Dakota; C. Druzgalski,
California State University-Long Beach; D. Ernie, University
of Minnesota; P. T. Hulina, Pennsylvania State University;
D. J. Johnson, University of Washington; E. C. Jones, Jr.,
Iowa State University; C. R. Kime, University of Wisconsin-
Madison; P. Noe, Texas A&M University; and P.D. Stigall,
University of Missouri-Rolla.
REFERENCES
[ 11 V. T. Rhyne, Fundamentals of Digital Systems Design. Englewood
Cliffs, NJ: Prentice-Hall, 1973.
[2] R. S. Sandige, Modern DigitalDesign. New York: McGraw-Hill, 1990.
[3] ANSIiIEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams.
New York: The Institute of Electrical and Electronic Engineers, 1986.
[4] PLDesigner Student Version (User’s Guide). Colorado Springs, CO:
Minc Inc., (licensed by McCraw-Hill), 1990.
IEEE TRANSACTIONS ON EDUCATION, VOL. 35, NO. 3, AUGUST 1992
High-speed CMOS Logic Data Book. Texas Instruments Inc., 1989.
ALSIAS Logic Data Book, Advanced Low-Power Schottky, Advanced
Schottky. Texas Instruments Inc., 1986.
S.H. Washburn, “An application of Boolean algebra to the design of
electronic switching circuits,” Trans. AIEE, p. 380, 1953.
S. P. Asija, “Instant logic conversions,” IEEE Spectrum, vol. 5, no. 12,
p. 77, 1968.
V. Ennis, “Positive and negative logic,” Comp. Design, vol. 9, no. 9,
p. 79, 1970.
P.M. Kintner, “A simple method of designing - - NOR logic,” Control
Eng., p. 77, 1963.
M. P. Marcus, Switching Circuits .for Engineers.
I Englewood Cliffs, NJ:
Prentice-Hall, 1962.
W. I. Fletcher, An Engineering Approach to Digital Design. Englewood
Cliffs, NJ: Prentice-Hall, 1980.
F. P. Prosser and D. E. Winkel, The Art of Digital Design. Englewood
Cliffs, NJ: Prentice-Hall, 1987.
Richard S. Sandige (S’63-M’64-SM’90) received
the B S.E E and M S E.E degrees from West Vir-
ginia University, Morgantown, in 1963 and 1969,
respectively, and the Ph D degree in electrical en-
gineering from Texas A&M University, College
Station, in 1978.
He is currently an Associate Professor in the
Depdrtment of Electrical Engineering, University
of Wyoming, Laramie Prior to joining the staff
dt the University of Wyoming, he worked for ten
years as a Member of the Technical Staff in the
Research and Development Laboratory dt Hewlett-Packard, Fort Collins, CO
His research interests include PLD’? and FPGA’s and their applications in
digital design and microprocessor systems He currently supports the research
dnd development activities of Minc Incorporated, a technology leader in
programmable logic synthesis tools He recently wrote a textbook entitled
Modern Digital Design (McGraw-Hill, 1990)