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ORDER NO.

MGCS010501G0

Technical Guide Digital Copier


DP-130/150

Please file and use this manual together with the service manual for Model No. DP-130/150, Order No.
MGCS010207C0.

© 2001 Matsushita Graphic Communication Systems, Inc.


All rights reserved. Unauthorized copying and distribution is
a violation of law.
Table of Contents

1 System Description .................................................................................................. 4


1.1. Electrical Circuit Explanation .................................................................................................. 4
1.2. Power On Initial Flow Chart .................................................................................................... 21

2 Schematic Diagram ................................................................................................. 26


2.1. General Circuit Diagram System Circuit ................................................................................. 26
2.2. CPU PC Board (V Model) ....................................................................................................... 27
2.3. CPU PC Board (P/A/PA/PP/FX Model) ................................................................................... 34
2.4. CCD PC Board ....................................................................................................................... 45
2.5. PNL PC Board (V/P Model) .................................................................................................... 48
2.6. PNL PC Board (A/PA Model) .................................................................................................. 49
2.7. PNL PC Board (FP/FX Model) ................................................................................................ 50
2.8. G3B PC Board. ....................................................................................................................... 51
2.9. LCE PC Board ........................................................................................................................ 56
2.10. LVPS PC Board (North America) ............................................................................................ 57
2.11. LVPS PC Board ...................................................................................................................... 59
(V Model except North America)
2.12. LVPS PC Board ...................................................................................................................... 61
(P/FP Model except North America)
2.13. LVPS PC Board (Taiwan) ........................................................................................................ 63

3 Electrical Circuit Diagram & Parts List ........................................................................... 65


3.1. Country Codes ........................................................................................................................ 65
3.2. Main CPU PC Board (FFPWB0665 for DP-150FX/FP) .......................................................... 66
Main CPU PC Board (FFPWB06651 for DP-150A)
Main CPU PC Board (FFPWB06652 for DP-130P/150P)
Main CPU PC Board (FFPWB06653 for DP-150PA)
3.3. Main CPU PC Board (FFPWB06641 for DP-150/130) ........................................................... 87
3.4. Control Panel PC Board (FFPWB0667 for DP-150/130) ........................................................ 96
Control Panel PC Board (FFPWB06671 for DP-150A/150P/150PA/130P)
3.5. Control Panel PC Board (FFPWB0668 for DP-150FP/FX) ................................................... 100
3.6. CCD PC Board (FFPWB0666) ............................................................................................. 104
3.7. LCE PC Board (DZEP000441) ............................................................................................. 107
3.8. Main LVPS PC Board (FFPWB06691 for North America) ..................................................... 109
3.9. Main LVPS PC Board (FFPWB06692, DP-150 except North America) ................................. 114
3.10. Main LVPS PC Board (FFPWB06694, DP-150A/P/FP except North America) ...................... 119
3.11. Main LVPS PC Board (FFPWB06695 for Taiwan) ................................................................ 124
3.12. G3B PC Board (FFPWB06711) ............................................................................................ 129

Note:
V model : DP-130/150 P model : DP-130P/150P A model : DP-150A
PA model : DP-150PA FP model : DP-150FP FX model : DP-150FX

3
1 System Description
1.1. Electrical Circuit Explanation
1.1.1. Block Diagram
Scanner Control Panel
5V2 12V -12V ADF
Lamp (for DP-150A/PA/FP/FX)
CCD

Amp

Inverter LCD RRSN PESN PFSN PFOSN


CCD PC Board

5V2 5V1

Control Panel AFOSN


LM
HPSN PCSN
Energy Saving SW SOL SOL SM

Printer
5V2 12V 24V 12V 5V2

ADC
5V2 3.3V
5VLD
GA1 5V2
LSU
Laser Safety
D/A
SW PM
5V2 LD

CODEC Drum
GA2 APC
PM2

SRAM
128KB 5V2 TESN
3.3V 3.3V Program HVPS Discharge
2MB FROM NDSN Lamp
DRAM8MB DRAM8MB
5V2
MM FM
Program
3.3V
2MB FROM
DRAM16MB 5V2
Sort SRAM
32KB SOL
DRAM BOARD RRSN PFSN PESN
5V2

SRAM SOL
32KB Paper Feed Unit HPESN
5V1 SOL
GA3 5V2
1284 IEEE1284 ADF
IF RST PFOSN FUOSN DOSN
Print
LVPS&ACD
5V2 5V1
5V1 • +5V1
CPU • +5V2
RST CPU
SH2 • 3.3V
TMP86CH06U
SH7041 TH • +12V
Processor
28 MHz TS • -12V
Fuser Lamp • +24V (SVP)
• +24V(PVP)

5V2 ADU (for DP-150FX)


FAX
FAX (for DP-150FP/FX) 5V2
SOL SOL
2MB FROM FAX Memory
2 or 4 FROM SOL
Program FAX MEMORY IF
512KB FROM

MODEM DSP 5V2 DXISN DXOSN


TR88017 MN195004
CODEC
SRAM MN86064 2nd Paper Feed Module
Analog 32KB

SP SOL
16Hz Detected
Transformer DP Signal PC
5V1 PFOSN
Telephone Line

NCU PESN PFSN

4
1.1.2. Image Data Circuit
The Image Data Circuit is independent of System circuit from Page Memory / Sort Memory circuit due
to high speed scanning and printing. As a result of this, all image data is managed by the Image Data
circuit and only coded data is transferred to the System Data BUS.

BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

IEEE1284 I/F

F-ROM
2 or 4 MB

5
1. Memory Control Gate Array
GA2 (IC30) is a Memory Controlling Gate Array.
• DMA Control
It is used to transfer data between the following devices.

Scanning Control LSI (GA1) Page Memory (S-DRAM) : Scanning Route


Page Memory (S-DRAM) CODEC (PM22) : Coding Route
CODEC (PM22) Page Memory (S-DRAM) : Decoding Route
Page Memory (S-DRAM) LSU Unit : Recording Route
System Memory (S-DRAM) Page Memory (S-DRAM) : Report Route

• Rotation Management
The rotation is carried out by the hardware when transferring the route.

• S-DRAM Control
It generates S-DRAM Control Signal for Page memory and Refresh Control when the power is ON.
It does not backup the Page Memory.

• Picture Quality Correction Circuit (Smoothing)


When the receiving data (8 dot/mm x 3.85, 7.7, 15.4 line/mm) is converted to 600 dpi x 600 dpi
resolution, the current printed data and 15 surrounding printed data are sent to the Smoothing ROM
through 16 bit line and the ROM sends smoothed dot data. As a result of this operation, the distorted
curved lines are smoothed.

• Gray-Level Enhancement
This control function allows expressing higher-level scales than using a recorded signal, by reducing
line density into 1/2 or 1/3 on the original after binary-to-multiple value conversion. This capability
increases reproduction of grayscale images such as photographs.

• Reduction / Enlargement Control Circuit


This circuit is used to process the received data so that it fits on the recording paper, according to
the Fax Parameter Settings.

• Synchronization Control Circuit


This circuit is used to synchronize the output of the recorded data with the horizontal synchronizing
output signal from the printer for each line. It controls the resolution of the printer as follows.
16 dot/mm x 15.4 line/mm : Report data
600 dpi x 600 dpi : Copy & Printer Interface

6
• FIFO/S-RAM Control
Picture Edit Coding Gate Array uses FIFO for Smoothing & Laser pulse width control, and S-RAM
for Smoothing Data and interface controls.

• S-DRAM Control
It generates S-DRAM Control Signal for SORT Memory and Refresh Control when the power is ON.
It does not backup the Page Memory.

2. Optional Memory for Image Side


The Optional Memories are:
• Memory PC Board (SODIMM) → DRAM Card (16 MB) for Sort memory
Install the DRAM Card for Sort memory to CN11 (FX/FP Model)/CN27 (A/PA Model) on the SORT
PCB.

7
1.1.3. Fax System Control Circuit
The System Control Block consists of the following IC that control the general Fax functions.

1. System CPU
The System CPU (SH7041) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and
DMA Control, Serial Communication Port, Timer Control, Interrupt Control, DRAM Control, and I/O
Port are integrated into 1 chip. Mask ROM (64k byte) is already installed and it controls the Monitor,
High Speed managing Task and Boot Programming.
• DMA Control
It has a 4ch DMA Control and is used to transfer data between the following devices.
Communication CODEC (PM22) ←→ Image Data Memory (DRAM)
• Serial Communication Port
It has a 2ch Serial Communication Port and is used to interface the following devices.
CPU ←→ Sub-CPU (Energy Saving Microprocessor)
• Timer Control
It is used to program the standard timer.
• Interrupt Control
It controls receipt & transfer to CPU the interrupt from Modem, LSI, Option, etc.
• DRAM Control
It generates DRAM Control Signal and Refresh Control when the power is ON.
• I/O Port
It is used to control lines and reset control around LSI.

2. System Memory
This system consists of the following memory.
• F-ROM (IC) → F-ROM (2MB) for programming
• F-ROM (IC) → F-ROM (2MB) for programming
The program is booted from F-ROM Card.
• F-ROM (IC) → Image Data Memory (2MB)
During a blackout, the image data is backed up.
• DRAM (IC) → Work RAM, buffer (8MB) for transfer and reception

3. Optional Memory for System Side


The Option Memories are:
• F-ROM Card (2/4MB) → Image Data Memory for expansion
During a blackout, the image data is backed up.
It is possible to rewrite the program by rebooting the main program from this card.

8
1.1.4. Scanning Circuit
1. Scanning LSI
GA1 (IC7) is a Scanning LSI and generates Shading Correction, MTF Correction, Reduction/
Enlargement, and Gray Scale Error Diffusion. The Image Signal is converted to binary signal and
transported.

2. TX Motor Drive Circuit


TX Motor Drive Circuit is controlled by SLA7032M and SCN PCB IC19, ADF PCB IC15.

1.1.5. Coding
Coding and decoding (MH/MR/MMR/JBIG conversion) is carried out by the hardware codec device.
There are 2 codecs, Image Codec and Communication Codec.
• PM-22 (IC32) : for Image Codec
It codes or decodes the data transferred from Sort memory. When copying, this codec codes from
the Image data to JBIG data. When communicating, this codec codes from Image data to MMR
data.

1.1.6. Sleep Mode


This function reduces the power consumption in standby mode. During Sleep Mode, power is supplied
only to the Energy Saver Lamp to keep it at a steady ON condition, to the circuit that monitors incoming
Ringing signals and to circuits that maintain Deferred communications. The power is recovered only
when an incoming Ringing signal is detected, the time to perform a Deferred communication has
lapsed or the Energy Saver key is pressed.

Recovers from Sleep Mode


No. Item Recovers from Remark
Sleep Mode
1 When Energy Saver key is pressed Yes
2 Deferred Communication time is lapsed Yes
3 Time for Deferred Communication Yes
4 Original Sensor is actuated Yes Not Document Sensor with Flatbed
5 Ringing signal detected Yes Not 1300Hz detection
6 Off-Hook (External telephone or Handset) Yes
7 When printing from a PC Yes

9
1.1.7. Signal Routing
1. Copy
BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

IEEE1284 I/F

2. Scan into Memory (FAX)


BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

IEEE1284 I/F

F-ROM
2 or 4 MB

10
3. File Print from Memory (FAX)
BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

IEEE1284 I/F

F-ROM
2 or 4 MB

4. Memory Transmission
BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

MODEM IEEE1284 I/F


NCU

F-ROM
2 or 4 MB

11
5. Memory Preception
BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


SDRAM (IC32)
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

NCU MODEM IEEE1284 I/F

6. Printing out
BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

IEEE1284 I/F

12
7. Scaner Input
BUF
ADC (IC11)
(IC20 ,21)
Amp
GA1 LSU
CCD (IC7)

Control &
SYSTEM DMA BUS

CODEC

Page Memory PM22/33


(IC32)
SDRAM
8MB GA2
(IC27) (IC30)
CPU

SH-2
(IC1)
CONECTER
SDRAM BUF (CN26)
8MB (IC35)
DRAM BORD (IC28)
8MB GA3
(CN27) Work Memory (IC34)

IEEE1284 I/F

F-ROM
2 or 4 MB

13
1.1.8. Modem and Peripheral Circuit (Optional FXB PCB)
This circuit consists of DSP, ROM, S-RAM, Analog Front End, Analog Master and peripheral circuitry.
This modem conforms to ITU-T, V.34, V.33, V.17, V.29, V.27ter, V.21 channel 2 (FSK), T.4, and T.30.
Macro order of DSP is sent from ROM to S-RAM and is outputted. DSP transfers/receives data from
Analog Front End and serial communication. Analog Front End communicates with the line through
Analog Master.

IC904
IC905 IC906
S-RAM
To Line IC901
Analog Modem
Analog
Front CPU
Master
To Speaker End
DSP
IC902
ROM

Modem
Program
System BUS

Modem Circuit Block Diagram


1. Receive Signal Control Circuit
This circuit consists of Operational Amplifier, Analog Master, and its peripheral circuit. On the received
signal from a line transformer (HYBSR), diffraction of signal transmission is attenuated using the
hybrid circuit, and the frequency of signal is limited to a certain band using a second LPF.
The signal is input to the analog front end via the analog SW for switching over between HYSIG and
the gain switching amplifier. 1300-Hz signal and remote signal are detected from HYSIG by switching
SW1.

2. Transmission Signal Control Circuit


This circuit consists of Operational Amplifier, Analog Master, and its peripheral circuit. On the signal
transmission from the analog front end, frequency of the signal is limited to a certain band using a
second LPF, and diffraction of the signal to a reception circuit is attenuated using the hybrid circuit.
The signal is sent out from the line transformer.

14
3.Line Monitor Circuit
The Line Monitor Circuit consists of an operational amplifier, analog master and its peripheral circuits.
Its function is to monitor the dial tone, DTMF tone, response signals, etc. over the speaker. It also
sounds the output of the key touch tones, alarm tones, etc. from the panel CPU over the speaker. The
received signal from the Ain (M) passes through an AGC circuit and is conditioned by the Analog Front-
End DSP and is then input to the Analog SW2 for volume control. The signal is then input to the
Speaker Amplifier, where it is amplified to a level sufficient to drive the speaker. The key touch tones
and Buzzer Signals from the panel are input to the Analog SW2 for volume control and then input to the
Speaker Amplifier. The monitor tone from the phone line and the buzzer tone from the panel can be
adjusted from the Control Panel.

HYSIG
Analog Master Analog Front-End DSP
RX signal Analog SW1
HYBSR Ain(M) IC906

Gain Switch
LPF Fc:7.8KHz
TX signal Amplifier
Aout(M) AGC
Hybrid Circuit
LPF Fc:4.5KHz
Analog SW2
Aout(V)

Amplifier Electronic Volume


Speaker
Buzzer Signal from Panel

15
1.1.9. Line Control Board
The following shows a block diagram of the Line Control Board.

HYBSR HYBSR

CML IC1 CML DC


PLS RL4 HOLD

Line GND Line AGND

CML MODEM CML MODEM


C5 C5
PC2 T2 PC1
Ring Ring
Telephone Detector Detector
for Auto Receive
PC1
+5V
Off-Hook
L : Off-Hook L : Off-Hook
Detector
H : On-Hook H : On-Hook

nHKOFF 9 nHKOFF 9
PC1

+5V +5V

nCTON nCTON
PC2

L : Ring In 10 L : Ring In 10

IC IC
+24V +24V

CML CML
H : FAX Side H : FAX Side
L : Telephone L : Telephone
CMLD 5 pCMLD 5
Q1

PLS RL4
H : Make H : Make
L : Break L : Break
PLSD 6 pPLSD 6
Q2

CN7
< LCU > < MDM > < LCE > < MDM >

[DZYNA1435*] [DZEP000441]

The Ring Detector consists of a photocoupler, PC2 (PC1 for LCE), and its peripheral circuits. The
ringing signal is a half-wave rectifier in the Ring Detector, and transferred through the nCTON signal
line to the IC on the SC PC Board. The IC observes the signal to distinguish from signals caused by
chattering.

The Off-Hook Detector (External Telephone) circuit consists of the photocoupler, PC1 (IC1 for LCE),
and its peripheral circuits. When PC1 detects loop current flow, it emits a Low active output signal
(nHKOF) to the IC which monitors it for a specified time. If the IC detects no change in the Low signal
level, it determines that the External Telephone is Off-Hook.

16
Dial Pulse Generator
The circuit consists of the CML relay, PLS relay and their peripheral circuits. This circuit generates
dial pulses. The CPU PC Board controls all dial pulse generation sequences. It turns relay CML and
PLS ON and OFF through the DZZSP58025. The status of the relays during dialing is shown below.
When the absence of the terminating message is confirmed by the Off-Hook detector, the CPU turns
CML relay ON to develop loop status (DC loop). After a few seconds, the CPU turns the PLS relay
On and Off to generate dial pulses, making and breaking the loop.

Dial Pulse

break
CML Relay
make

break
PLS Relay
make

Speech First Speech Second Speech


condition digit condition digit condition
Line release

break
Prepause Inter-digit
Line status pause

make

DTMF Tone Generator


The circuit is incorporated in the MODEM PC Board. The DTMF tone is conveyed to the telephone
line using the same route as the facsimile signal. The DTMF tone selection is controlled by the CPU.
The relay status during dialing is shown below.

DTMF Tone

break
PLS Relay
make

break
CML Relay
make

Speech First Speech Second Speech


condition digit condition digit condition
Line release

Inter-digit
Prepause pause
break DTMF signal
Line status

make

17
1.1.10. Laser Printer Motor Drive Circuit
1. System Description
It consists of 16 bit CPU TMP86CH06U, FROM for programming, peripheral I/O. The CPU controls
mechanism of Laser Printer, Fuser Lamp temperature, and Laser Unit.

5VLD
IC1 LSU
LD SW
CPU GA1
PM
SH2 IC7
SH7041 LD
Processor Drum
APC

IC24
MM
CPU Motor
TMP86CH06U

TH
FROM IC2,42 Fuser Lamp
TS

GA3 1284
IEEE1284 IF
LVPS
IC34 IC35

2. Printer Motor Drive Circuit


This Printer Motor is a Brushless DC Motor.

nMMCNT : When the signal level goes Low, the Printer Motor starts rotating.
nMMLCK : Rotation status signal for Printer Motor. When the Printer Motor reaches a constant
speed, nMMRDY signal level goes Low.

The Printer Motor is powered by +24 VDC supply. When the interlocks are open, the +24 VDC
supply is cut off and the Printer Motor stops rotating.
IC1
CN7
CPU
144 nMMCNT
SH2 2
DT6
SH7041
Processor 1

5V
nMMLCK
111
GA1
IC7

18
3. Fuser Lamp Drive Circuit
It consists of 1 Fuser Lamps and Fuser Lamp is controlled by two HTC PC Boards.
The Fuser Lamp is powered by 100 VAC. When the CN7, Pin 4 (HTCNT) on the LVPS PCB goes
LOW, the Fuser Lamp turns ON. This lights up the PC5 LED and activates the TR1 photo-triac, and
100 VAC is sent to the Fuser Lamp.

CN3
5V 1
AC1
to Fuser Lamp
CN7
2

to CPU
Board
L4

4 PC5 AC2
TR1

4. Interlock Safety Circuit


This safety circuit turns OFF the +24 VDC and +5 VDC supply voltages when the Printer Cover is
opened. When the Printer Cover is opened, the microswitch(es) on the LVPS Board are de-actu-
ated, turning OFF +24 VDC to the Printer Motor Drive Circuit, the HVPS, the Paper Feed Solenoid
Circuits, the Clutch Drive Circuit, and the Laser Driver Circuit on the Laser Unit.

SW2 CN5
LVPS
1
24V

to CPU PC board

SW3 SW4 CN6

1
5V
to CPU PC board

19
5. LSU Control Circuit
The laser control signals are described below.
Actual data is sent from CPU PCB to LSU.

nVIDEO : Actual data is outputted by these 2 signals.


ADJUST : Laser Power Sample/Hold Timing Signal.
nHSYNC : This horizontal synchronization signal transmitted from the Beam Detection Sensor
sets the horizontal position of the laser beam as it crosses the OPC Drum.
ENABLE : The LSU is activated when this output signal is LOW. If an error occurs, the nLDON
output signal level goes High and the LSU is deactivated.
PMCLK : This is the Polygon Motor Drive Clock.
nPMLCK : When the Polygon Motor speed is constant, the nPMRDY is at a Low output signal
level.
nPMCNT : This is the Polygon Motor Control Signal. The Polygon Motor rotates when the nPMON
output signal level is LOW.

IC1 CN4

CPU
SH2 143 nPMCNT
DT5 11
SH7041
Processor

90 PMCLK
DT22 13

5V

113 nPMLCK
12

IC11

ENABLE
GA1 5

IC7
nVIDEO
6

ADJUST
7

IC13 nHSYNC
4

20
1.2. Power On Initial Flow Chart
1.2.1. Fax

* Check outside view of SC PCB before checking signal.


0 Initial Flow Especially check whether CN903 (FROM Card) pins
short or not.
XTAL
3.5V
Power ON 0V

<Check Output : If Signal is not correct, each IC


might be defective >
Hardware Reset
Power CN13(12,13)5V -> CPU
Master 7.16Hz -> (94)IC1CPU( 107)28.3MHz
Boot Program in CPU Start Clock -> BL108
Reset ResetIC5(8) -> -> (173)
-> ->(108)IC1CPU

Y Is Update Memory Card


Installed IC2(14) is Low ?
<Check Output : If Signal is not correct, each IC
might be defective >
Is program date API IC2(14) : Low / High
Same? Y N IC1CPU(50) -> IC7(150)
CPU(CS0)
-> (2) IC2(14)
N IC1CPU(43) -> IC5
CPU (RD)
-> IC2(54)
Update Program (A0~20)IC7(7~39) -> MSC(14,
CPU(A1-3)
16,17) -> IC2(4~32)
CPU(D0-16) IC1CPU(D0-16) -> IC2(33,35,38-)

CPU I/O Port Set

I/O Device Reset

I/O Device Port Set

System Program (FROM) Start

DRAM Working Area Clear

Panel Initial

21
1 Initial Flow 2

Y FROM IC1
In case of replaced FROM on FXB PCB
formated ?

N
FROM (Image area) initial It may take 15 - 20 sec. During formatting.

PRINTER initial

Task Initialize Task initialize for Software.

Y Back up data
PARITY ERROR ? Back up data in SRAM Parameter, Journal,...

Shipment set N
System data save to F-ROM
F-ROM image area format

Image memory Confirmation of FROM Memory Card size.


(F- ROM Card) Check
0

Y Memory size
change? Optional FROM Memory Card

F-ROM image area format N


(New size)

0 2

22
2 Initial Flow 3

JOB Recover, if need Confirmation of timer, Power OFF/ON,…..

SCANNER initial

Y APR-22-2000 10:00
PRINTER error ?
00%

N
CHECK PRINTER
EX. E04
Y
SCANNER error ?
DOCUMENT JAM
EX.
J31
N
DISPLAY ERROR DISPLAY DATE & TIME ADF COVER OPEN
EX.
J61

Initial Flow 4

SCANNER initial

Y ADF Door
OPEN ?
N

EJECT START

Error Set
Info. Code 061 N
B Point OFF ?

Y Jam Length N
Over ?

Error (Jam) Set


Info. Code 031

END

23
1.2.2. Printer Initial Flow Chart

SC Initial End

Hard Reset

Start Watching I/O Port

IC7 Y Right Cover Open STOP


Pin109
N

IC7 L Regist Sensor ON STOP


Pin115

IC1 L Exit Sensor ON STOP


Pin54

IC1(53) 2nd Paper Pass Sensor ON


L STOP
Feed Cover Open
When the optional
H 2nd Feed Module
is installed.
2nd Paper Detecting Sensor ON
IC1(52) H STOP
2nd Paper Tray Open
L

24
B

Main Motor On H: ON
IC1(144) L: OFF

Main Motor Service STOP


IC7(111) H Error
Rotation Defect

Internal Process of
High Voltage ON
IC7-Pin85, 89

Fuser Heat-up
(Lamps ON)
IC7(83)

IC1(118) Service
Y Thermistor Open Error STOP
Vin < 0.016V

IC1(118)
Vin increase Service STOP
Y Abnormal Temperature Error
under 0.016V
(Watching during Initial Operation)
N

Main Motor On L: Stop


IC1 Pin144 H: High Speed

IC7 Service STOP


Pin112 H Fan not Ready Error

Internal Process of
High Voltage OFF

Motor OFF

Fuser Idle
(Lamps OFF)

Fan Motor OFF

Stand-by

25
B
A

D
C
2
2.1.

Control Panel PCB

1
7

3
4
6

2
5
8
9
CN401

11
12
13
14

10
.....DC5V Line
.....DC24V Line

5
6
8
7

2
1
3
4
9
11
10
12

VL
GND

LCLK
CPLD
KCLK

CPWR

CPDAT
CPKEY
CPLAT
EPKEY 13
EPLED 14
Optics Drive Motor CN2 Flat
CN6 CN12 Cable CN 801
.....AC120V/220–240V Line

11 1 LMBB AGND 20 1

1
1

9 2 SVP VOUTE 19 2
7 3 LMB AGND 18 3
M 5 4 LMAB
Pulse VOUTO 17 4
3 5 SVP AGND 16 5
1 6 LMA CCDADT 15 6
CCDACLK 14 7
CCDALD 13 8
CN5 GND 12 9
For DP-150A/PA/FP/FX, DP-130FP 7 SH 11 10

Platen/ADF 1 6 VL FCK 10 11
PCSN 2 5 PCSN 5 0 SCK 9 12
Open/Close Sensor 3 RS1
4 GND 8 13
3 RS2 7
THE PARTS WITH

1 VL 14
Lamp Unit Home HPSN 2 2 HPSN 5 0 GND 6 15
Position Sensor 3 1 GND VL 5 16
GND 4 17

CCD PCB
CN3 +12V 3 18
IMPORTANT FOR SAFETY

10 AGND 2 19
9 PVP -12V 1 20
1
Bypass Solenoid 2 8 HFSOL 24 0
MARK OF THE SCHEMATIC.

1 7 PVP
Pick-up Solenoid 2 6 PUSOL

1 5 PVP
Registration
2 4 RRSOL 24 0
Solenoid 3 EXFM
1
FM 2 2 EXFL Inverter PCB
Exhust Fan Motor 3 1 PGND
IMPORTANT SAFETY NOTICE

CN16 Flat Cable


CN2 1
PGND 1 4
DIAGRAM INCORPORATE SPECIAL FEATURES

PGND 2 3 2
Bypass Paper Size
Schematic Diagram

WHEN SERVICING IT IS ESSENTIAL THAT ONLY

LPCNT 3 2 3
Detecting Switch 24 0
MARK ON THIS SCHEMATIC

CN17 1 4
SVP 4
THE CRITICAL COMPONENTS IN THE PARTS WITH

1 HFPS1 Detect 5
MANUFACTURE'S SPECIFIED PARTS BE USED FOR

1 MS 2 GND CN15 CN1


3 HFPS2 Detect Exposure Lamp
2 VL 1
MS 4 GND TXD1OUT 2
RXD1IN 3
GND 4

CN8
TREF 1 10
HVTCNT 2 9
CN4 GREF 3 8
1 VL_LSU BREF 4 7 AC1 1
8

CN701
7 2 GND HVCNT 5 6 AC2 3
CN 8

6 3 GND HVLKC 6 5
5 4 HSYNC VREF 7 4

HVPS
4 5 ENABLE 5 0 HVBCNT 8 3
6 2

CN LS
3 VIDEO PGND 9
2 7 ADJUST PVP 10 1

LSU
1 8 GND 11
14
5 9 PVP S1

2
2

4 10 PGND
Polygon 3 11 PMCNT
Motor M 2 12 PMLCK ON
Main

CN LSM
1 13 PMCLK
15
16
Motor
CN7
24 0 MMLCK 1 5 Power Switch
MMCNT 2 4
General Circuit Diagram System Circuit

For DP-150A/PA/FP/FX 3
3
CN 1

GND 2
CN18
4
M
CNAFSC PVP 5 1
ADF 1 1 GND

2 2 AFOSIZ2

3 3 VL CN 1
Paper Size 3 4 4 GND GND 1
Interlock Switch
AFO 5 AFOSIZ1
Detecting 2 5 5 0 2
SIZ1 1
Sensor 6 6 VL VL 3 Close
10 Paper S2 24V
3 1 GND GND 4
3
Cover Open/ AFO 2 2 11 AFOSN 5 0 5 0 PFOSN 5 PFO Exit
2
SN SN Sensor
Close Sensor 1 3 12 VL VL 6 1
3 4 13 GND GND 7
Paper AFPE 3 Regist- S3 Laser Close
2 5 14 APESN 5 0 5 0 RRSN 8 RR
Detecting SN 2 ration
1 SN
6 15 VL VL 9 1
Sensor CNAFC Sensor
3 7 GND GND 10 LP 2 1 Choke Only for
3 Paper
Registration AFRR 2
8 AFRRSN 5 0 5 0 PESN 11 PE AC 2 2
2
CN4

SN SN Detecting S4 Laser Close Fuser Europ


Sensor 1 9 VL VL 12 1

26
Registration 2 18 AFRRCL 24 0 Sensor
1 19 SVP
Clutch
2 20 AFPSOL 24 0 Mian Metal Frame
Paper Feed 1 21 SVP E Only for Europe
Solenoid 11 22 ADMBB
(Green/ inret
9 23 SVP
Yellow)
ADF Drive 7 24 ADMB F3
5
Pulse (Brown)
Motor M 25 ADMAB
F1 L
3 26 SVP (Blue)
E4 1 ADMA F2 N
E3 27
ADF
Metal
2 2
28
LVPS CN1
L (Black)
Frame Stamp 16 STPSOL 24 0 AC1
1 1
17 SVP Only for North America
Solenoid
CNTS CNSTC
Mian Metal Frame

CN2 N
N (White)
2nd Paper Feed AC2

Module (Option) E (Green or Green/Yellow)


CNPF CN22 Mian Metal Frame
3 1 1 GND
Registration SCR 2 2
2 SCRSN 5 0 Fuser Unit
Sensor SN 1 3 3 VL
4 4 GND Thermostat x 2
3
Paper Detecting SCPE 5 5 SCPESN 5 0

3
3

2 CN3 Mark (R)


Sensor SN 1 6 (Red)
6 VL
AC1 1
2 7 7 SCPSOL 24 0
Paper Feed LP1 2
1 8 PVP
(White)
8
Solenoid
9 Fuser Lamp
E1
E2 2nd Cassette Module
Metal Frame CN5 CN7 CN6
2
4
4
5
5

1
3
1
3
1
4
6
7
8
9

2
3

Mian Metal Frame


10
11
12
13
14
15

For DP-150FX
CN19 Thermistor
1 GND
2 ADPSN2
CNAD1C 3 VL
ADU 3 1 4 GND
Paper Pass ADF 2 2 5 ADPSN1 5 0
Sensor SN1 1 3 6 VL
2 7 ADPFSOL 24 0
Paper Exit Solenoid 1
2
4
2

1
3
3
9
8
7
6
5
3
2
1

8 PVP
11
12
10

13
14

PVP
SVP
VLC

AGND 4

PGND
ZCRS
VL
GND

VL_LSU 15
+12V

PGND
VL
GND
3.3V
-12V

3.3V
GND

HTTR
GND
GND

PVCNT 5
SVCNT 4
EPCNT 1
CN13

CN9

CN14

CN21
0

2 24 0 CN10 Toner Level Sensor


2 ADSBSOL2
ADU Solenoid 2 1 GND 1 1
5

1 PVP CPU PCB 2 2


TE
5 0 TESN
24 0

VL 3 3
SN Discharge Lamp
CN20 72Pin 2MB PVP 4 1 1
CNEL
24 0 24 0 ELP 5 2 EL
2 2 ADSBSOL1 2
ADU Solenoid 1 1 1
SDRAM TH1 6 CNTH 1
PVP
TH2 7 2
VL 8 1 1
2
ND Drum Virgin
CN11 for DP-150FP/FX 5 0 NDSN 9 2
CN24 10 3 3 SN Detecting Sensor
CN27 for DP-150A/PA, DP-130A GND
For DP-150FP/FX 60P CNNDC
36P
GND
-12V

CN23 CN26
8 VLC

5 GND
4 VL
2

7 PGND
6 SVP
1

3 +12V

CN902
2
3

1
4
6
7
8

Speaker CNSP CN905 CN904 Printer Connector


CN901 (Option)
1 1 SPKOT
2 2
68Pin 2MB
GND
Fax PCB (IEE1284)
GND
+5V
+24V
CMLD
PLSD
TURS
HSDT

FAX Memory
4

1 (HOK2)
3
5
6
7
8
9 HKOF

2
10 CTON
11 HYBSR
12 AGND
13 HYSIG
14 TCKD
15 EAKD

Except DP-130/150V/A
CN903
4

1
3
5
6
7
8
9

2
10
11
12
13
14
15

CNP25
NCU PCB
Model

CNJ23 CNJ20 CNJ21


4
3

CNJ24
DP-130/150

4
4

LINE
4
3

Hand Set
General Circuit
Drawing Name

Diagram System Circuit


B
A

D
C
2.2. CPU PC Board (V Model)
1 2 3 4

CPUBLK
CPUBLK.Sch INPUT
D[0..15] A[0..21] INPUT.Sch
D[0..15] A[0..21]
nZC SYSCK nPESN nPESNIN CCDIF
nZC SYSCK nPESN nPESNIN
nINT1 nCS0 nHPSN nHPSNIN CCDIF.sch
nINT1 nCS0 nHPSN nHPSNIN
nINT2 nCS1 nRRSN nRRSNIN OGSET SVDATAA[0..7]
nINT2 nCS1 nRRSN nRRSNIN OGSET SVDATAA[0..7]
nINT3 nRD ZCRS nZC ADCLK2 SVDATAB[0..7]
nINT3 nRD ZCRS nZC ADCLK2 SVDATAB[0..7]
A nSRAMCS
nPFOSNIN
nSRAMCS nWRH
nWRH
nWRL
pHTCNT
TH1
pHTCNT nHTTR
nHTTR
nID0I
EGSET
ADCLK1
EGSET A
nPFOSNIN nWRL TH1 nID0I ADCLK1
nHVLKCIN nHFSOLI TH2 nID1I VOUTE
nHVLKCIN nHFSOLI TH2 nID1I VOUTE
nWR nELPI NID0 nID2I VOUTO
nWR nELPI NID0 nID2I VOUTO
nROMCS nPUSOLI NID1 nCDI
nROMCS nPUSOLI NID1 nCDI
nPCSNIN nSVCNT NID2 EPALED
nPCSNIN nSVCNT NID2 EPALED
nNDSNIN nPVCNT nCD nMMLCKIN
nNDSNIN nPVCNT nCD nMMLCKIN
HTSNIN nPMCNT nMMLCK nDOPSNIN
HTSNIN nPMCNT nMMLCK nDOPSNIN
TESNIN nMMCNT nDOPSN nPCSNIN
TESNIN nMMCNT nDOPSN nPCSNIN
PVPEM LMPDWN nPFOSN nNDSNIN
PVPEM LMPDWN nPFOSN nNDSNIN
SVPEM TXD1 nEXFL PVPEM
SVPEM TXD1 nEXFL PVPEM
nWAIT EPLDCNT nPMLCK TESNIN
nWAIT EPLDCNT nPMLCK TESNIN
RXD1 EPACNTIN nHVLKC HTSNIN
RXD1 EPACNTIN nHVLKC HTSNIN
nSRAMCS2 nRST0 nPCSN SVPEM
nSRAMCS2 nRST0 nPCSN SVPEM
EPAKEYIN nRST1 nNDSN CPKEYIN
EPAKEYIN nRST1 nNDSN CPKEYIN
TESN nEPCNT CONNECTOR
TESN nEPCNT
CPKEY nPFOSNIN CONNECTOR.Sch
CPKEY nPFOSNIN
EPAKEY nEXFLIN CPDAT nDOPSN
EPAKEY nEXFLIN CPDAT nDOPSN
nRST1 nPMLCKIN LCLK nPFOSN
nRST1 nPMLCKIN LCLK nPFOSN
EPACNTIN nHVLKCIN KCLK nRRSN
EPACNTIN nHVLKCIN KCLK nRRSN
EPLDCNT nHFPS1IN pCPLAT nPESN
EPLDCNT nHFPS1IN pCPLAT nPESN
nHFPS1 nHFPS2IN pCPLD CPKEY
nHFPS1 nHFPS2IN pCPLD CPKEY
nHFPS2 EPAKEYIN pEXFM nEXFL
nHFPS2 EPAKEYIN pEXFM nEXFL
nRRSOL nHSYNC
nRRSOL nHSYNC
nPUSOL nPMLCK
nPUSOL nPMLCK
nHFSOL nHPSN
nHFSOL nHPSN
ENABLE nPCSN
ENABLE nPCSN
nVIDEO nMMLCK
B ADJUST
nPMCNT
nVIDEO
ADJUST
nMMLCK
VREF
VREF
nHVLKC
B
nPMCNT nHVLKC
PMCLK ZCRS
PMCLK ZCRS
nMMCNT TESN
nMMCNT TESN
TREF TH1
TREF TH1
GREF TH2
GREF TH2
BREF nNDSN
BREF nNDSN
nHVTCNT nWRH
nHVTCNT nWRH
nHVCNT VOUTE
nHVCNT VOUTE
GABLK nHVBCNT VOUTO
nHVBCNT VOUTO
GABLK.Sch nSVCNT nCD
nSVCNT nCD
D[0..15] nWAIT nPVCNT nID0
D[0..15] nWAIT nPVCNT nID0
A[0..21] nINT3 nHTTR nID1
A[0..21] nINT3 nHTTR nID1
nCS0 nWR nELP nID2
nCS0 nWR nELP nID2
nCS1 nINT1 nRD EPAKEY
nCS1 nINT1 nRD EPAKEY
nRD nINT2 nWRL RXD1IN
nRD nINT2 nWRL RXD1IN
nWRH nSRAMCS nRST1 nHFPS1
nWRH nSRAMCS nRST1 nHFPS1
nWRL nROMCS OUTPUT nLPCNT nHFPS2
nWRL nROMCS nLPCNT nHFPS2
nRST0 nFAXROMCS OUTPUT.Sch CCDADT
nRST0 nFAXROMCS CCDADT
SYSCK nLMAI nRRSOLI nRRSOL CCDACLK
SYSCK nLMAI nRRSOLI nRRSOL CCDACLK
nID0I nLMABI nHFSOLI nHFSOL CCDALD
nID0I nLMABI nHFSOLI nHFSOL CCDALD
nID1I nLMBI nPUSOLI nPUSOL nSH
nID1I nLMBI nPUSOLI nPUSOL nSH
nID2I nLMBBI nELPI nELP nFCK
nID2I nLMBBI nELPI nELP nFCK
nCDI nLMENB nLMAI nLMA nSCK
nCDI nLMENB nLMAI nLMA nSCK
CPKEYIN nEXFMI nLMABI nLMAB nRS1
CPKEYIN nEXFMI nLMABI nLMAB nRS1
nPESNIN pHTCNT nLMBI nLMB nRS2
nPESNIN pHTCNT nLMBI nLMB nRS2
nDOPSNIN nRRSOLI nLMBBI nLMBB nEPCNT
nDOPSNIN nRRSOLI nLMBBI nLMBB nEPCNT
nZC ADCLK1 nLMENB pEXFM nFAXROMCS
C nMMLCKIN
nZC
nMMLCKIN
ADCLK1
ADCLK2
ADCLK2 nEXFMI
nLMENB
nEXFMI
pEXFM
RXD1
RXD1 A[1..20]
nFAXROMCS
A[1..20]
C
nEXFLIN nLPCNT LMPDWN TXD1OUT D[0..15]
nEXFLIN nLPCNT LMPDWN TXD1OUT D[0..15]
nPMLCKIN nHVCNT TXD1 EPALED
nPMLCKIN nHVCNT TXD1 EPALED
nHPSNIN nHVBCNT RXD1IN TXD1OUT
nHPSNIN nHVBCNT RXD1IN TXD1OUT
nRRSNIN nHVTCNT nLMA
nRRSNIN nHVTCNT nLMA
SVDATAA[0..7] PMCLK nLMAB
SVDATAA[0..7] PMCLK nLMAB
SVDATAB[0..7] CPDAT nLMB
SVDATAB[0..7] CPDAT nLMB
VREF LCLK nLMBB
VREF LCLK nLMBB
nHSYNC KCLK
nHSYNC KCLK
nHFPS1IN pCPLAT
nHFPS1IN pCPLAT
nHFPS2IN pCPLD
nHFPS2IN pCPLD
nRST1 GREF
nRST1 GREF
BREF
BREF
TREF
TREF
OGSET
OGSET
EGSET
EGSET
CCDADT
CCDADT
CCDACLK
CCDACLK
CCDALD
CCDALD
nSH
nSH
nFCK
nFCK
nSCK
nSCK
nRS1
nRS1
nRS2
nRS2
ADJUST
ADJUST
nVIDEO
nVIDEO
ENABLE
ENABLE
D nSRAMCS2
nSRAMCS2 D

Model Drawing Name


FFPWB06641
For DP-130/150 LCNROOT.PRJ (1/7)
1 2 3 4

27
1 2 3 4

A [3:E1] [7:D5]
A[0..21]
A[0..21] A[0..21]

RA5 MNR14EABJ103 VL
A

A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
7 8
D[0..15] D[0..15] 5 6
D[0..15]
[3:F1] [7:C5] 3 4
1 2

RA6 MNR14EABJ103
7 8
5 6
VL C148 3 4
IC2 ECJ1VF1C104Z 1 2
A1 25 29 D0
A0 D0
A2 24 31 D1 RA7 MNR14EABJ103
A1 D1
A3 23 33 D2 7 8
A2 D2
A4 22 35 D3 5 6
A3 D3
A5 21 38 D4 R146 3 4
A4 D4
A6 20 40 D5 ERJ3GSY0R00V R145 1 2
A5 D5
A7 19 42 D6 ERJ3GSY0R00V
A6 D6
A8 18 44 D7 RA8 MNR14EABJ103
A7 D7
A9 8 30 D8 7 8
A8 D8
A10 7 32 D9 5 6
A9 D9 C4
A11 6 34 D10 3 4
A10 D10 ECJ1VF1C104Z
A12 5 36 D11 1 2
A11 D11 RA2 RA4 C3
A13 4 39 D12
A12 D12 MNR14EABJ103 MNR14EABJ103 C2 ECJ1VF1C104Z C5
A14 3 41 D13 RA9 MNR14EABJ103
A13 D13 RA1 RA3 ECJ1VF1C104Z ECJ1VF1C104Z
A15 2 43 D14 7 8
A14 D14 MNR14EABJ103 MNR14EABJ103 ECJ1VF1C104Z
A16 1 45 D15 5 6
A15 D15
A17 48 VL 3 4
A16 C1
A18 17 9 1 2
A17 N.C TL72
10 VL
N.C TL73

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8
nWR 11 15 VL R1 ERJ3GSYJ103V
[3:D1] nWR WE N.C TL74 ERJ3GSYJ103V
nRST0 12 16 VL C63
RP N.C TL108

2
4
6
8
13 VL
VPP R2
nWP 14 37 R4
WP VCC
nROMCS 26 ERJ3GSYJ103V
[3:D1] nROMCS CE

135
112

128
127
nRD 28 27 C11 R3 ECEA1CKA100B RA10 R5

99
85
77
63
40
26
12

41
39
38
37
27
25
24
23
22
21
20
19
18
17
16
15
13
11
10
OE GND

9
8
7
VL 47 46 ECJ1VF1C104Z MNR14EABJ103 ERJ3GSYJ103V
BYTE GND

A[20]/PB8/nIRQ6/nWAIT
A[19]/PB7/nIRQ5/nBREQ
A[18]/PB6/nIRQ4/nBACK
A[21]/PB9/nIRQ7/nADTRG
IC1

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

A[17]/P81
A[16]/P80
A[15]/PC15
A[14]/PC14
A[13]/PC13
A[12]/PC12
A[11]/PC11
A[10]/PC10
A[9]/PC9
A[8]/PC8
A[7]/PC7
A[6]/PC6
A[5]/PC5
A[4]/PC4
A[3]/PC3
A[2]/PC2
A[1]/PC1
A[0]/PC0
AVref
ERJ3GSYJ103V

Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc

AVcc
LHF40VZ3 D0 92

1
3
5
7
D[0]/PD0
D1 91
D[1]/PD1
VL D2 90 50 nCS0
D[2]/PD2 *CS0/PA10 nCS0 [3:D1]
D3 89 49 nCS1
DT20 D[3]/PD3 *CS1/PA11 nCS1 [3:D1]
D4 88 57
D[4]/PD4 *CS2/D[28]/PD28 TL103
DTA114EKA146 D5 86 56
D[5]/PD5 *CS3/D[29]/PD29 TL102
nVPPCNT D6 84 43 nRD

B B
D[6]/PD6 *RD/PA14 nRD [3:D1] [7:B5]
D7 83 47 nWRH
D[7]/PD7 *WRH/PA13 nWRH [3:D1] [7:B5]
D8 82 48 nWRL
D[8]/PD8 *WRL/PA12 nWRL [3:D1] [7:B5]
IC3 D9 81 101 nWAIT
D[9]/PD9 *WAIT/PA17 nWAIT [3:D1]
A1 10 11 D0 D10 80 31 nPCSNIN
R30 A0 I/O1 D[10]/PD10 *RAS/PB2/*IRQ0/*POE0 nPCSNIN [4:E3]
A2 9 12 D1 D11 78 34 nCTSIN
ERJ3GSYJ103V A1 I/O2 D[11]/PD11 *CASH/PB4/*IRQ2/POE2 nCTSIN [4:D3] 1
A3 8 13 D2 D12 76 32
A2 I/O3 D[12]/PD12 *CASL/PB3/*IRQ1/*POE1 TL100
A4 7 15 D3 D13 75 36
A3 I/04 D[13]/PD13 RDWR/PB5/*IRQ3/*POE3 TL99
A5 6 16 D4 D14 74 100 nNDSNIN
A4 I/O5 D[14]/PD14 *AH/PA16 nNDSNIN [4:E3]
A6 5 17 D5 D15 73
A5 I/O6 D[15]/PD15
A7 4 18 D6 62
A6 I/O7 *DREQ0/D[24]/PD24 TL98
A8 3 19 D7 98 60
A7 I/O8 NMI *DREQ1/D[25]/PD25 TL97
59
DACK0/D[26]/PD26 TL96
A9 25 nZC 72 58
A8 [3:B1] [4:A2]nZC *IRQ0/D[16]/PD16 DACK1/D[27]/PD27 TL95
A10 24 nINT1 70 110
A9 [3:D1] nINT1 *IRQ1/D[17]/PD17 DRAK0/PE1/TIOC0B TL94
A11 21 nINT2 69 113
A10 [3:D1] nINT2 *IRQ2/D[18]/PD18 DRAK1/PE3/TIOC0D TL93
A12 23 nINT3 68
A11 [3:D1] nINT3 *IRQ3/D[19]/PD19
A13 2 67
A12 C7 C81 TL75 *IRQ4/D[20]/PD20
A14 26 66
A13 ECJ1VF1C104Z C78 ECJ1VB1H102K TL76 *IRQ5/D[21]/PD21
A15 1 65 131 EPACNTIN
A14 ECJ1VB1H102K TL77 *IRQ6/D[22]/PD22 TXD0/PA1 EPACNTIN [4:A2]
28 64 130 EPLDCNT
VCC C79 C80 TL78 *IRQ7/D[23]/PD23 RXD0/PA0 EPLDCNT [4:D5]
nRD 22 VL 46 134 TXD1
OE ECJ1VB1H102K ECJ1VB1H102K TL79 *IRQOUT/D[30]/PD30 TXD1/PA4 TXD1 [5:E4]
nWRL 27 14 133 RXD1
WE GND RXD1/PA3 RXD1 [5:E4]
20 HTSNIN 118 132
CE1 [4:B2] HTSNIN PF0/AN0 SCK0/nIRQ0/PA2/nDREQ0 TL92
R53 TESNIN 119 136
W24258S-70LL [4:B2] TESNIN PVPEM 120
PF1/AN1 SCK1/nIRQ1/PA5/nDREQ1 TL4
ERJ3GSYJ103V [4:B2] PVPEM PF2/AN2
IC4 SVPEM 121
[4:B2] SVPEM PF3/AN3
A1 10 11 D8 122
A0 I/O1 PF4/AN4
A2 9 12 D9 123 109 nHFSOLI
A1 I/O2 PF5/AN5 PE0/nDREQ0/TIOC0A nHFSOLI [5:D1]
A3 8 13 D10 125 111 nPUSOLI
A2 I/O3 R143 PF6/AN6 PE2/nDREQ1/TIOC0C nPUSOLI [5:D1]
A4 7 15 D11 +12V SYSCK 126 114 nELPI
A3 I/04 SYSCK PF7/AN7 PE4/TIOC1A nELPI [5:D1]
A5 6 16 D12 ERJ3GSYJ100V 115
A4 I/O5 [3:D1] PE5/TIOC1B TL87
A6 5 17 D13 108 116
A5 I/O6 R44 *RES PE6/TIOC2A TL88
A7 4 18 D14 44 137
A6 I/O7 ERJ3GSYJ683V DT7 C77 TL80 *WDTOVF PE7/TIOC2B TL89
A8 3 19 D15 33 138
A7 I/O8 DTC114EKA146 ECJ1VB1H102K *BREQ/PA18/DRAK0 PE8/TIOC3A TL90
30 139
TL82 *BACK/PA19/DRAK1 PE9/TIOC3B TL91
A9 25 140 pSVCNT
A8 PE10/TIOC3C
A10 24 107 142 pPVCNT
A9 CK/PA15 PE11/TIOC3D
A11 21 EPAKEYIN 143 pPMCNT

PD3/D[31]/nADTRG

PA8/nIREQ2/TCLKC
PA9/nIREQ3/TCLKD
A10 EPAKEYIN PE12/TIOC4A
A12 23 (NOT MOUNT) 94 144 pMMCNT
A11 XTAL PE13/nMRES/TIOC4B

PA6/nCS2/TCLKA
PA7/nCS3/TCLKB
A13 2 VL [4:D4] 2
A12 C8 R13 PE14/nDACK0/TIOC4C/nAH TL106
A14 26 R6 96 5 LMPDWN

PA20/nCASHL
PA21/nCASHH
A13 EXTAL PE15/nDACK1/TIOC4D/nIRQOUT LMPDWN [5:E1]

PA22/nWRHL
PA23/nWRHH
A15 1 ECJ1VF1C104Z VL ERJ3GSYJ103V
A14 R40 ERJ3GSYJ201V
VL 28
VCC ERJ3GSYJ102V R34

PLLCAP

PLLVcc

PLLVss
nRD 22
OE
E

AVss
nWRH 27 14 ERJ3GSYJ103V
WE GND

Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss

MD0
MD1
MD2
MD3
R33 20 nSVCNT
ERJ3GSYJ152V CE1 R32 nSVCNT [7:E2]
B
W24258S-70LL Q1 XL1 HD6437041F28 DT3

C C
ERJ3GSYJ102V
2SB709ATX HC49US7.15MT pSVCNT DTC114EKA146

105

104

106

141
129
117

124

103
102
93
87
79
71
61
55
42
35
28
14

45
54
53
52
51
29

97
95
6

4
3
1
C

D2
nSRAMCS D1 R47 VL
[3:D1] nSRAMCS R49

TL83
TL84
TL85
MA152KTX
DT1 ERJ3GSYJ302V
MA152KTX IC25 C10 ECJ1VF1C104Z ERJ3GSYJ103V
A1 10 11 D0 DTC114EKA146 C76 VL nPVCNT
A0 I/O1 ECUV1H220JCV C9 R7 R50 nPVCNT [7:E2]
A2 9 12 D1
A1 I/O2 C75 DT4
A3 8 13 D2 ERJ3GSYJ103V
A2 I/O3 ECUV1H220JCV ECUV1H471JCV DTC114EKA146
A4 7 15 D3 VL pPVCNT
A3 I/04 R51
A5 6 16 D4 ERJ3GSYJ201V
A4 I/O5
A6 5 17 D5 ERJ3GSYJ103V
A5 I/O6
A7 4 18 D6 R10 TL109
A6 I/O7 R52
A8 3 19 D7
A7 I/O8 ERJ3GSYJ152V
VL VL ERJ3GSYJ103V
A9 25 nPMCNT
A8 nPMCNT [7:D1]
A10 24
A9 DT5
A11 21
A10 BT1 DTC114EKA146
A12 23 IC5 R8 pPMCNT
A11 CR2330-1HH D7
A13 2 3 5 ERJ3GSYJ102V nVPPCNT
A12 CK VCC 1
A14 26 VL 2 6
A13 R VR TL105
A15 1 1 7 nCTI
A14 CT VS TL104 nCTI [5:C1]
28 MA152KTX 4 8 nRST0
VCC C102 GND R nRST0 [3:D1]
nRD 22 nWP
OE ECJ1VF1C104Z C104 C64 MB3773TR
nWRL 27 14 nMMCNT
WE GND ECQV1H155JL3 R48 nMMCNT [7:B1]
20
CE1 C6 DT6
ERJ3GSYJ103V
W24258S-70LL VL VL nPFOSNIN pMMCNT DTC114EKA146
nPFOSNIN [4:E3]
IC26 nHVLKCIN
ECEA1CKA100B ECJ1VF1C104Z nHVLKCIN [4:F2]
A1 10 11 D8
A0 I/O1
A2 9 12 D9
A1 I/O2
A3 8 13 D10 R139 R140
A2 I/O3
A4 7 15 D11 ERJ3GSYJ102V ERJ3GSYJ102V
A3 I/04
A5 6 16 D12 IC11F
A4 I/O5
A6 5 17 D13 13 12 nRST1
A5 I/O6 nRST1 [3:B4] [4:B2] [7:B5]
A7 4 18 D14
A6 I/O7 DT18 TC74VHC05FEL
A8 3 19 D15
A7 I/O8 DTC114EKA146
A9 25
A8
A10 24
A9
A11 21
A10
A12 23
A11
A13 2
A12
A14 26 VL
A13
A15 1
A14 C97
28
VCC ECJ1VF1C104Z
nRD 22
OE
nWRH 27 14

D [3:D1] nSRAMCS2
nSRAMCS2 20
WE
CE1
GND

W24258S-70LL
D

Model Drawing Name


FFPWB06641
For DP-130/150 CPUBLK.SCH (2/7)
1 2 3 4

28
1 2 3 4

A 3.3V
R75
A
ECJ1VF1C104Z ERJ3GSY0R00V
ECJ1VF1C104Z

C20 C24 XL2


ECJ1VF1C104Z C22 ECJ1VF1C104Z C117 TL61 1 4
C23 INH VCC
C19 C21 ECJ1VB1H103K BL1
2 3 CCDCLK
ECJ1VF1C104ZVL GND OSC
ECJ1VF1C104Z BLM11B221SDT (CK 26M)
VL KCO736S27P38

119
154

122
155

156
163
178

157
164
179
21

20
52

18
40
47
53
94

19
41
48
54
95
D[0..15] IC7 nLPCNT
D[0..15] nLPCNT [7:B2]
FFPAV0009 SVDATAA[0..7] IC10 CPDAT
[2:F1] [7:C5] SVDATAA[0..7] [6:D5] DT8 CPDAT [7:E1]
CCDADTI 2 18 CCDADT

VSSI5V
VSSI5V
VSSI5V
VSSI5V
[7:F5]

VDDI5V
VDDI5V
VDDI5V
1A1 1Y1 CCDADT

VSSO5V
VSSO5V
VSSO5V
VSSO5V
VSSO5V
VSSO5V
VSSO5V
VSSO5V
VDDO5V
VDDO5V
VDDO5V
VDDO5V
VDDO5V
VDDO5V
VDDO5V
VDDO5V
CCDACLKI 4 16 CCDACLK pLPCNTI DTC114EKA146 DT23
1A2 1Y2 CCDACLK [7:F5] DTC143EKA146
D0 158 22 SVDATAA0 CCDALDI 6 14 CCDALD CPDATI
D1 159
DATA0 SVDATAA0
23 SVDATAA1 nSHI R132ERJ3GSYJ100V 8
1A3 1Y3
12 nSH
CCDALD [7:F5]
DATA1 SVDATAA1 1A4 1Y4 nSH [7:E5]
D2 160 24 SVDATAA2
D3 161
DATA2 SVDATAA2
25 SVDATAA3 nFCKI R133ERJ3GSYJ100V 11 9 nFCK
DATA3 SVDATAA3 2A1 2Y1 nFCK [7:E5]
D4 162 26 SVDATAA4 13 7 nSCK
D5 167
DATA4 SVDATAA4
27 SVDATAA5 nSCKI R134ERJ3GSYJ100V 15
2A2 2Y2
5 nRS1
nSCK [7:E5] nHVCNT
DATA5 SVDATAA5 2A3 2Y3 nRS1 [7:E5] nHVCNT [7:F2]
D6 168 28 SVDATAA6 SVDATAB[0..7] 17 3 nRS2 LCLK
D7 169
DATA6 SVDATAA6
29 SVDATAA7
SVDATAB[0..7] [6:B5]nRS1I R135ERJ3GSYJ100V 2A4 2Y4
BLM11P600SPT
nRS2 [7:E5] DT9 LCLK [7:E1]
DATA7 SVDATAA7 DTC114EKA146 DT24
D8 170 30 SVDATAB0 1 20 3.3V pHVCNTI
D9 171
DATA8 SVDATAA8
31 SVDATAB1 nRS2I R136ERJ3GSYJ100V 19
1G VL
10 LCLKI DTC143EKA146
DATA9 SVDATAA9 2G GND
D10 172 32 SVDATAB2 BL67
DATA10 SVDATAA10 C29 C150
D11 173 33 SVDATAB3 T74VHC244FEL
DATA11 SVDATAA11 ECJ1VF1C104Z ECJ1VF1C104Z
D12 174 34 SVDATAB4
DATA12 SVDATAA12
D13 175 35 SVDATAB5
DATA13 SVDATAA13
D14 176 36 SVDATAB6 nHVBCNT
DATA14 SVDATAA14 nHVBCNT [7:F2]
A[0..21] D15 177 37 SVDATAB7 BLM11P600SPT KCLK
A[0..21] DATA15 SVDATAA15 DT10 KCLK [7:E1]
BL68 VL (NOT MOUNT)
[2:F1] [7:D5] A0 125 3 CCDCLK pHVBCNTI DTC114EKA146 DT25
AD0 CCDCLK R141 DTC143EKA146
A1 126 6 CCDACLKI
AD1 DACLK
A2 127 7 CCDADTI ERJ3GSY0R00V
AD2 DADATA C151 C152
A3 128 8 CCDALDI

14
AD3 DALD ECJ1VF1C104Z ECJ1VF1C104Z R142
A4 129 9 nSHI KCLKI
AD4 SH
A5 130 10 nRS1I IC11A ERJ3GSY0R00V
AD5 RS1
A6 131 11 nRS2I ADJUSTI 1 2 ADJUST nHVTCNT
AD6 RS2 ADJUST [7:D1] nHVTCNT [7:F2]
A7 132 12 nSCKI pCPLAT
AD7 SCK TC74VHC05FEL DT11 pCPLAT [7:E1]
A8 133 15 nFCKI
AD8 FCK DTC114EKA146 DT26
A9 134 16 ADCLK1 pHVTCNTI

7
AD9 ADCLK1 ADCLK1 [6:C4] DTC143EKA146
A10 135 17 ADCLK2 CPLATI
AD10 ADCLK2 ADCLK2 [6:A4]
A11 136 IC11B
AD11 BL65
A12 137 42 VIDEOI VIDEOI 3 4 nVIDEO

B A13
A14
A15
138
139
140
AD12
AD13
AD14
AD15
VIDEO
CKSEL
TRG
ENABLE
43
44
45
TRGI TL60
ENABLEI
BLM11B221SDT
1 IC11C
TC74VHC05FEL
nVIDEO [7:D1]

PMCLK
PMCLK [7:C1]
B
A16 143 46 ADJUSTI ENABLEI 5 6 ENABLE pCPLD
AD16 ADJUST ENABLE [7:D1] DT22 pCPLD [7:E1]
A17 144 49 LLSYNCI
AD17 LLSYNC TC74VHC05FEL DTC143EKA146 DT27
A18 145 50 LLSYNCDI PMCLKI
AD18 LLSYNCD DTC143EKA146
A19 146 51 PVCLKI CPLDI
AD19 PVCLK
A20 147
AD20
A21 148 2 GACLK VL
AD21 CLK R76
nWRL 124 229 XL3 ERJ3GSY0R00V
[2:D6] [7:B5]nWRL nWRH 103
WRL BIDATA0
230 C118 TL62 1 4
[2:D6] [7:B5]nWRH WRH BIDATA1 INH VCC
nRD 149 231 IC12
[2:D6] [7:B5]nRD RD BIDATA2 ECJ1VB1H103K BL2 (CK 34M) 1
nCS0 150 232 3.3V 2 3 13 TRGI
[2:D6] nCS0 nCS1 151
CSA0 BIDATA3
233
GND OSC
2
CLK IN TR
11 PVCLKI
[2:D6] nCS1 CSA1 BIDATA4 BLM11B221SDT TL63 TEST1 CKO
nWAIT 152 234 KCO766S17P43 3 10
[2:D6] nWAIT WAIT BIDATA5 TL64 TEST2 CKO TL68
nINT3 153 235 4 BL63
[2:D3] nINT3 INTA BIDATA6 R9 TL65 PULSE BLM11B121SDT
nRST0 123 236 6
[2:B4] nRST0 RESET BIDATA7 TL66 CKO/2
SYSCK 104 221 ERJ3GSYJ103V BL70 7
[2:C4] SYSCK SYSCLK BILEN TL59 TL67 CKO/2
222 VL BLM11P600SPT 16
BIVEN TL58 VCC
nWR 55 223 12 9
[2:E1] nWR WR BIRDY VCC CNTCK TL69
nINT1 56 224 5 15
[2:D3] nINT1 INT1 BIRD TL57 GND TEST3 TL70
nINT2 57 C66 8 14
[2:D3] nINT2 INT2 C30 C31 GND GND
nSRAMCS 58 198
[2:B1] nSRAMCS nROMCS 59
SRAMCS BRDATA0
199 TL56 ECEA1CKA100B ECJ1VF1C104Z M66235FPT2
[2:E1] nROMCS nFAXROMCS 62
ROMCS BRDATA1
200 TL55 ECJ1VF1C104Z
[7:B5] nFAXROMCS FAXROMCS BRDATA2
201 TL54
BRDATA3 TL53
nID0I 96 202
[4:E3] nID0I NID0 BRDATA4 TL52
nID1I 97 203 VL VL
[4:D3] nID1I NID1 BRDATA5 TL51
nID2I 98 204
[4:D3] nID2I NID2 BRDATA6 TL50 R54
nCDI 99 205
[4:D3] nCDI NCD BRDATA7 TL49
nSRAMCS2 100 206 ERJ3GSYJ103V
[2:A1] nSRAMCS2 SRAMCS2 BRLEN TL48 C32 ECJ1VF1C104Z
207
BRVEN TL47 IC13A
nLMAI 63 208
[5:F2] nLMAI LMAI BRSTB TL46
nLMABI 64 nHSYNC 1 2 LLSYNCI
[5:F2] nLMABI LMABI [7:D1] nHSYNC
nLMBI 65 182
[5:E2] nLMBI LMBI TVDATA0 TL45
nLMBBI 66 183
[5:E2] nLMBBI LMBBI TVDATA1 TL44 TC74VHC14FEL
nLMENB 67 184
[5:E2] nLMENB LMENB TVDATA2 TL43
68 185
TL23 ADMAI TVDATA3 TL42 IC13B ERJ3EKF3601V IC13C
69 186
TL24 ADMABI TVDATA4 TL41 R129 R84
70 187 3 4 5 6 LLSYNCDI
TL25 ADMBI TVDATA5 TL40
71 188 ERJ3GSYJ103V
TL26 ADMBBI TVDATA6 TL39
72 189
TL27 ADMENB TVDATA7 TL38 TC74VHC14FEL TC74VHC14FEL

0
DADATA 73 190 3.3V C122
CPUDADATA TLEN TL37 ECUV1H101JCV IC9C
DACLK 74 191
CPUDACLK TVEN TL36 R41
DALD 75 192 10 (ANALOG)
CPUDALD TCLK TL35 +
CPDATI 76 193 8 GREF
CPDAT TLSYNC TL34 R130 GREF [7:F2]
LCLKI 77 3.3V 9

C C
LCLK ERJ3GSYJ103V R77 -
KCLKI 78 211 ERJ3GSYJ103V
KCLK TP0 TL33
CPLATI 79 212 XL4 ERJ3GSY0R00V BA10324FT2
CPLAT TP1 TL32 TL71 1 C25
CPLDI 80 213 C119 4

0
CPLD TP2 TL31 INH VCC ECJ1VF1C104Z
81 214
TL28 CPWR TP3 ECJ1VB1H103K BL3
[5:B1] nEXFMI nEXFMI 82 215 2 3 GACLK
EXFMI TP4 GND OSC

0
pHTCNT 83 216
[4:F4] pHTCNT HTCNT TP5 BLM11B221SDT IC9B
pLPCNTI 84 217 KCO736S21P00
LPCNT TP6
pHVCNTI 85 218 5 (ANALOG)
HVCNT TP7 R57 +
pHVBCNTI 88 237 7 BREF
HVBCNT XTEST R55 BREF [7:F2]
pHVTCNTI 89 238 ERJ3GSYJ103V 6
HVTCNT MTEST -
PMCLKI 90 239 ERJ3GSYJ103V
PMCLK TPIN C26
nRRSOLI 91 BA10324FT2
[5:D1] nRRSOLI RRSOLI ECJ1VF1C104Z
92

0
TL29 AFRRSOLI R131 R56
93
TL30 SCPSOLI
CPKEYIN 105 ERJ3GSYJ103V ERJ3GSYJ103V IC8
[4:C2] CPKEYIN CPKEY
106 nRST1 DADATA 3 12 (ANALOG)
ADPSNIN1 nRST1
[2:A4] [4:B2] [7:B5] DI AO1
107 3.3V DACLK 2 13 (ANALOG)
ADPSNIN2 C153 CLK AO2
[4:F2] nPESNIN nPESNIN 108 DALD 1 14 (ANALOG)
PESNIN ECJ1VB1H103K LD AO3
[4:F2] nDOPSNIN nDOPSNIN 109 18 15 (ANALOG) +12V
DOPSNIN R AO4
nZC 110 VL 4 (ANALOG) EGSET
[2:D3] [4:A2]nZC ZC AO5 EGSET [6:D2]
nMMLCKIN 111 17 5 (ANALOG) OGSET
[4:F2] nMMLCKIN MMLCKIN VDD AO6 OGSET [6:B2]

4
nEXFLIN 112 VREFIN (ANALOG) 11 6
[4:F2] nEXFLIN EXFLIN VREFU1 AO7 IC9A
nPMLCKIN 113 (ANALOG) 10 7
[4:F2] nPMLCKIN nHPSNIN 114
PMLCKIN VREFU2 AO8
16 3 (ANALOG)
[4:F2] nHPSNIN nRRSNIN 115
HPSNIN
+12V R74 ECJ1VF1C104Z DO +
1 TREF
[4:F2] nRRSNIN RRSNIN TREF [7:F2]
116 ERJ3GSYJ122V 8 2
AFRRSNIN C106 GND -
nHFPS1IN 117 9
[4:D3] nHFPS1IN ENCODER0 VREFL
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V
VDDI3V

VDDO3V
VDDO3V
VDDO3V
VDDO3V
VDDO3V
VDDO3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V
VSSI3V

VSSO3V
VSSO3V
VSSO3V
VSSO3V
VSSO3V
VSSO3V

nHFPS2IN 118 BA10324FT2 C27


[4:D3] nHFPS2IN ENCODER1 ECJ1VF1C104Z
M62356P

11
C65 C108

0
3.3V ECEA1CKA100B ECJ2VF1H104Z
101
121
141
165
180
194
225

102
120
142
166
181
195
226
240

196
209
219
227

197
210
220
228
39
60
86

38
61
87

13

14
1

D4 IC9D
3.3V MA717TX VREF 12 (ANALOG)
[7:F2] VREF (ANALOG)
+
14 VREFIN
C12 C16 C149 13
C18 ECJ1VF1C104Z -
ECJ1VF1C104Z ECJ1VF1C104Z ECJ1VF1C104Z BA10324FT2 C28
C17 ZD1 ECJ1VF1C104Z

0
C15 C107
ECJ1VF1C104Z ECJ1VF1C104Z
C13 C14 MA3051MTX
ECJ1VF1C104Z ECJ1VF1C104Z 1
ECJ1VF1C104Z

D D

Model Drawing Name


FFPWB06641
For DP-130/150 GABLK.SCH (3/7)
1 2 3 4

29
1 2 3 4

ERJ3GSYJ152V
ERJ3GSYJ152V
ERJ3GSYJ152V ERJ3GSYJ152V
ERJ3GSYJ152V ERJ3GSYJ152V
VL VL pHTCNT
[3:C1] pHTCNT

D3 VL
ERJ3GSYJ152V MA152KTX

A ERJ3GSYJ152V
R58 A

R14

R15

R16

R17

R18

R19

R20

R21
nHPSN R92 nHPSNIN
[7:C1] nHPSN ERJ3GSYJ101V nHPSNIN [3:B1] ERJ3GSYJ103V
VL
nRRSN R93 nRRSNIN VL R85 nHTTR
[7:F1] nRRSN ERJ3GSYJ101V nRRSNIN [3:B1] nHTTR [7:E2]
R94 ERJ3EKF8201V

8
nPESN ERJ3GSYJ101V nPESNIN
[7:F1] nPESN nPESNIN [3:B1] R86 IC14A
nDOPSN R95 nDOPSNIN TH1 R37 3
[7:F1] nDOPSN ERJ3GSYJ101V nDOPSNIN [3:B1] ERJ3EKF8201V [7:E2] TH1 +
ERJ3GSYJ102V 1 DT12
nMMLCK R96 nMMLCKIN 2 DTC114EKA146
[7:B1] nMMLCK ERJ3GSYJ101V nMMLCKIN [3:B1] -
nEXFL R97 nEXFLIN BA10393FT2
[7:D1] nEXFL ERJ3GSYJ101V nEXFLIN [3:B1] R87 C33

4
nPMLCK R98 nPMLCKIN ECJ1VF1C104Z
[7:D1] nPMLCK ERJ3GSYJ101V nPMLCKIN [3:B1] ERJ3EKF3901V VL
nHVLKC R99 nHVLKCIN
[7:F2] nHVLKC ERJ3GSYJ101V nHVLKCIN [2:A5]
R88

0
C
C93 ERJ3GSYJ334V IC14B
C82 ECJ1VB1H102K 5
ECJ1VB1H102K Q3 +
B 7
TL8

C
2SC2412KT146 6
C87 C90 -
ERJ3GSYJ152V ECJ1VB1H102K ECJ1VB1H102K TH2 R90 B Q4 BA10393FT2

E
ERJ3GSYJ152V C88 C91 [7:E2] TH2 2SC2412KT146

AK

0
ERJ3GSYJ101V
ERJ3GSYJ152V ERJ3GSYJ152V ECJ1VB1H102K ECJ1VB1H102K DA1
ERJ3GSYJ152V ERJ3GSYJ152V ERJ3GSYJ152V C89 C92 MA153ATX

E
VL ERJ3GSYJ152VERJ3GSYJ152V ECJ1VB1H102K ECJ1VB1H102K C120
ECJ1VB1H103K
VL R89

R122

R123

R339
R22

R23

R24

R26

R27

R28

R29

ERJ3GSYJ334V
ERJ3GSYJ152V

K
nPFOSN R100 nPFOSNIN
[7:F1] nPFOSN ERJ3GSYJ101V nPFOSNIN [2:A2]
nPCSN R101 nPCSNIN
[7:C1] nPCSN ERJ3GSYJ101V nPCSNIN [2:D6]
nNDSN R102 nNDSNIN
[7:E2] nNDSN ERJ3GSYJ101V nNDSNIN [2:D6]

NID0 R104 nID0I


[7:B5] NID0 ERJ3GSYJ101V nID0I [3:D1]
NID1 R105 nID1I
[7:B5] NID1 ERJ3GSYJ101V nID1I [3:D1]
NID2 R106 nID2I

B B
[7:B5] NID2 ERJ3GSYJ101V nID2I [3:D1]
nCD R107 nCDI
[7:B5] nCD ERJ3GSYJ101V nCDI [3:D1]
(NOT MOUNT)

nHFPS1 R126 nHFPS1IN


[7:B2] nHFPS1 ERJ3GSYJ101V nHFPS1IN [3:B1]
nHFPS2 R127 nHFPS2IN
[7:B2] nHFPS2 ERJ3GSYJ101V nHFPS2IN [3:B1]
nCTS R338 nCTSIN
[5:C3] nCTS ERJ3GSYJ101V nCTSIN [2:D6] VL

R147
ERJ3GSYJ103V 1

EPAKEYIN
EPAKEYIN [2:C4]
C100 DT30

C101

C142

C143

C244
DTC114EKA146 VLC
C94

C95

C96

C98

C99

ECJ1VB1H102K ECJ1VB1H102K
DT21
EPLDCNT DTA114EKA146
ECJ1VB1H102K ECJ1VB1H102K ECJ1VB1H102KECJ1VB1H102K [2:C6] EPLDCNT
VLC
ECJ1VB1H102K ECJ1VB1H102K VLC VLC

ECJ1VB1H102K ECJ1VB1H102K VLC


VLC C67 ECJ1VF1C104Z
C46 ECJ1VF1C104Z C140 C35 ECJ1VF1C104Z
ECJ1VB1H102K
VLC C83 ECJ1VF1C104Z VLC
VLCRST

10
IC17B
R35 4

10
IC17A IC17C

4
ERJ3GSYJ103V 1 6 9 IC16B DT28
IC6A DTA114EKA146
VL IC15A IC15B IC16A 3 5 8 11 9

SD
R124 J Q
EPAKEY 1 2 2 5 12 9 3 5 2 10

SD

SD

SD
[7:E1] EPAKEY D Q D Q J Q TC74VHC08FEL
ERJ3GSYJ102V 13
TC74VHC08FEL TC74VHC08FEL CLK
3 11 1 EPALED
R31 C116 TC74VHC14FEL VLC CLK CLK CLK EPALED [7:E1]
12 7

CD
ERJ3GSYJ152V ECJ1VB1H103K TL1 K Q TL3
VLC 6 8 2 6

CD

CD

CD
IC13D TC74VHC14FEL Q Q K Q TL2
CPKEY R109 9 8 CPKEYIN VLC T74VHC112FEL

14
[7:E1] CPKEY ERJ3GSYJ101V CPKEYIN [3:B1] TC74VHC74FEL TC74VHC74FEL T74VHC112FEL

13

15
1
R59 VLCRST nEPCNT

C C103
ECJ1VB1H102K
ERJ3GSYJ103V

R125 3
IC6B
4 5
IC6C
6
C34 ECJ1VF1C104Z DT17
nEPCNT [7:F2]
C
VL ERJ3GSYJ102V
4

DT2 C135TC74VHC14FEL VLC TC74VHC14FEL VLC C141


DA2 ZCRS DTC114EKA146 ECJ1VB1H103K ECJ1VB1H102K DTC114EKA146
MA128TX

RA11
TH1 8 7 HTSNIN
2
3
5
6

ECJ1VB1H102K TESNIN HTSNIN [2:C4]


TESN 6 5
[7:E2] TESN TESNIN [2:C4]
4 3 PVPEM
PVPEM [2:C4]
R45 2 1 SVPEM
SVPEM [2:C4]
2
3
5
6

ERJ3GSYJ683V
PVP SVP MNR14EABJ101 C84
DA3 C121 C85 C86
MA127TX ECJ1VB1H103K IC24 VLC C139
R46
ERJ3GSYJ683V ECJ1VB1H102K 3 5 ECJ1VB1H102K
TL6 OUTC VCC
ECJ1VB1H102K VLC 2 6
VSC VSB/RESIN
1 7
CT VSA TL5
VLC 4 8 VLC
C147 GND RESET
PVPERR
4

R60 ECQV1H224JL3 MB3771TR C105


SVPERR ERJ3GSYJ103V R138
R111 ERJ3GSYJ103V
ERJ3GSYJ103V ECJ1VF1C104Z
IC17D
12 VLCRST
R62 11
13 TL110
ERJ3GSYJ103V
DT13 DT14
DTC114EKA146 TC74VHC08FEL
nRST1
nRST1
[2:A4] [3:B4] [7:B5]
VL
IC6D
R61
ERJ3GSYJ103V DTC114EKA146 9 8
TL111
R11
ERJ3GSYJ152V VLC
TC74VHC14FEL VLC
VLC
nZC 1
nZC [2:D3] [3:B1] IC6E
R12 R42 R91 11 10
TL112
C

ERJ3GSYJ472V ERJ3GSYJ103V
ERJ3GSYJ152V
R36 Q2 TC74VHC14FEL VLC
[7:E2] ZCRS ZCRS B
2SC2412KT146 IC6F

D ERJ3GSYJ102V
C123
13 12
TL7 D
E

ECQV1H104JL3 R43 DT15 DT16


DTC114EKA146 DTC114EKA146 TC74VHC14FEL VLC
ERJ3GSYJ472V EPACNTIN
[2:C6] EPACNTIN

Model Drawing Name


FFPWB06641
For DP-130/150 INPUT.SCH (4/7)
1 2 3 4

30
1 2 3 4

SVP

R64
ERJ3GSYJ103V R65 ZD2
VL 1ZB51TPA3
A R63
ERJ3GSYJ103V

R66
D11
1DL42TPA3
D12
1DL42TPA3
A
ERJ3GSYJ103V ERJ3GSYJ103V (1A)

D10
1DL42TPA3
IC19 D13 VL
nLMAI 6 7 1DL42TPA3
[3:C1] nLMAI INA VSA
nLMABI 5 1 (1A) nLMA R113
[3:C1] nLMABI INA OUTA nLMA [7:B1]
nLMBI 17 8 (1A) nLMAB ERJ3GSYJ103V
[3:C1] nLMBI INB OUTA nLMAB [7:B1]
nLMBBI 16
[3:C1] nLMBBI INB IC13E
12 IC11D
VSB (1A)
11 nLMB TXD1 11 10 9 8 TXD1OUT
OUTB nLMB [7:B1] [2:C6] TXD1 TXD1OUT [7:A3]
VL 4 18 (1A) nLMBB
GNDA OUTB nLMBB [7:C1] TC74VHC05FEL
(1A) 9
RSA TC74VHC14FEL
nLMENB 2
[3:C1] nLMENB 3
SYNCA
R116 REFA
VL VL
ERJ3EKF3900V 15
GNDB C124
(1A) 10 R112 R121
R110 RSB C109 ECA1VM101B
13 ERJ3GSYJ103V ERJ3GSYJ103V
SYNCB ECJ2VF1H104Z
ERJ3EKF1000V R115 R114 14
DT29 REFB IC13F
ERX2SJ1R0E ERX2SJ1R0E IC11E
LMPDWN DTC114EKA146 R117 SLA7032M RXD1 10 11 12 13 R128 RXD1IN
[2:C6] LMPDWN [2:C6] RXD1 ERJ3GSYJ101V RXD1IN [7:A3]
ERJ3EKF1000V TC74VHC05FEL C146
C145 C144 TC74VHC14FEL ECJ1VB1H102K
ECJ1VB1H102K ECJ1VB1H102K

B B

R68 D6
ERJ3GSYJ103V R69 1SR139400T32
VL ERJ3GSYJ103V PVP

R67 R70
ERJ3GSYJ103V ERJ3GSYJ103V D5 D8
1SR139400T32 1SR139400T32
VL

IC18
nRRSOLI 3 2 (0.4A)nRRSOL
[3:C1] nRRSOLI I O nRRSOL [7:D1]
nHFSOLI 6 7 (0.4A)nHFSOL
[2:C6] nHFSOLI I O nHFSOL [7:D1]
nELPI 11 10 (0.4A) nELP
[2:C6] nELPI I O nELP [7:E2]
nPUSOLI 14 15 (0.4A)nPUSOL
[2:C6] nPUSOLI I O nPUSOL [7:D1]
1 4
VCC PGND
8 5
VCC PGND
9 12
COM PGND
16 13
COM PGND

TD62308BP-1

C36 ECJ1VF1C104Z

PVP

C VL
D31
1SR139400T32
C
VL R340
ERJ3GSYJ103V nCT
nCT [7:E4]
R341 Q19 nCTS
nCTS [4:D1]
ERJ3GSYJ103V
DT48 2SD1994ATA DT49
1 nCTI DTC114EKA146 DTC114EKA146
[2:B5] nCTI

VL

R38 PVP
R71
ERJ3GSYJ472V
E

ERJ3GSYJ103V
R118
C

B Q5
ERJ6GEYJ472V 2SA1674TA
nEXFMI B Q7 (0.2A) pEXFM
[3:C1] nEXFMI 2SC2412KT146 pEXFM [7:D1]
C
E

D9
R39 1SR139400T32
ERJ3GSYJ472V

D D

Model Drawing Name


FFPWB06641
For DP-130/150 OUTPUT.SCH (5/7)
1 2 3 4

31
1 2 3 4

+12V
(NOT MOUNT)

BL84
BLM11B121SDT

A C136
A
ECJ1VF1E104Z

8
IC22A (NOT MOUNT)
VOUTE (ANALOG) 3
[7:F5] VOUTE + R119
1 (ANALOG) R78
2 ERJ3GSYJ750V
- ERJ3GSY0R00V
C59 LM6172IM
ECJ1VF1C104Z DA4 R79 VL

4
1SS396
ERJ3GSY0R00V
(NOT MOUNT) R80
BL57
ERJ3GSY0R00V
VL BLM11B221SDT

C137
ECEA1CKA100B ECJ1VF1C104Z
ECJ1VF1E104Z
ECJ1VF1C104Z C73 C58 C74
BL85 C57 ECEA1CKA100B
BLM11B121SDT

-12V

(ANALOG) SVDATAA[0..7]
SVDATAA[0..7] [3:F3]
IC21
+12V ECJ1VF1C104Z 20 1 SVDATAA0
-PD DB0
19 2 SVDATAA1
C56 DVDD DB1
18 3 SVDATAA2
AVDD DB2
17 4 SVDATAA3
BIAS DB3

8
(ANALOG) 16 5 SVDATAA4
IC23A Ain DB4
15 6 SVDATAA5
B [3:B5] EGSET
EGSET (ANALOG) 3
+
1
BL59
ECJ1VF1C104Z 14
(ANALOG) 13
AVSS DB5
1/2Vref
DB6
Vref+ DB7
7
8
SVDATAA6
SVDATAA7
B
2 12 9
- BLM11B221SDT C54 Vref- OVF TL9
11 10
C61 C138 C72 DVSS CK
BA10358FT2
ECJ1VF1C104Z ECJ1VF1E104Z ECEA1CKA100B TC35071F

4
C55
ECJ1VF1C104Z

BL58
BLM11B221SDT

NF14
NFM839470101
ADCLK1 1 3
[3:E3] ADCLK1

2
1

VL
(NOT MOUNT)
0

BL62
(NOT MOUNT) BLM11B221SDT
VOUTO (ANALOG) 5 IC22B
[7:F5] VOUTO + R120
7 (ANALOG) R81

C C60
6
-
LM6172IM
ERJ3GSYJ750V ERJ3GSY0R00V
ECJ1VF1C104Z
ECEA1CKA100B

C70
ECJ1VF1C104Z

C53 C71
C
ECJ1VF1C104Z DA5 R82 C52 ECEA1CKA100B
0

1SS396
ERJ3GSY0R00V
(NOT MOUNT) R83
ERJ3GSY0R00V
VL

SVDATAB[0..7]
SVDATAB[0..7] [3:E3]
IC20
ECJ1VF1C104Z 20 1 SVDATAB0
-PD DB0
19 2 SVDATAB1
C51 DVDD DB1
18 3 SVDATAB2
AVDD DB2
17 4 SVDATAB3
BIAS DB3
0

(ANALOG) 16 5 SVDATAB4
IC23B Ain DB4
15 6 SVDATAB5
ECJ1VF1C104Z AVSS DB5
OGSET (ANALOG) 5 14 7 SVDATAB6
[3:B5] OGSET + BL60 1/2Vref
DB6
7 (ANALOG) 13 8 SVDATAB7
Vref+ DB7
6 12 9
- BLM11B221SDT C49 Vref- OVF TL10
11 10
C62 C69 DVSS CK
BA10358FT2
ECJ1VF1C104Z ECEA1CKA100B TC35071F
0

C50
ECJ1VF1C104Z

BL61
BLM11B221SDT
1

NF15
NFM839470101
ADCLK2 1 3
[3:E3] ADCLK2
D D

2
Model Drawing Name
FFPWB06641
For DP-130/150 CCDIF.SCH (6/7)
1 2 3 4

32
1 2 3 4

C43 ECJ1VF1C104Z

VL

A A
BL64
BL28 BLM11B221SDT
CN1 TREF PVP
BLM11P600SPT [3:B6] TREF
PVP
BL4 BLM11B221SDT 1 BL29 BLM11B221SDT
nDOPSN nHVTCNT CN8
[4:F1] nDOPSN 2 [3:E5] nHVTCNT
CN14
3 BL30 BLM11B221SDT 1
GREF SVP
BL5 BLM11B221SDT 4 [3:C6] GREF 2 1
nPFOSN
[4:E1] nPFOSN 5 BL31 BLM11B221SDT 3 2
BREF
6 [3:C6] BREF 4 3
BL6 BLM11B221SDT 7 BL32 BLM11B221SDT 5 4
nRRSN nHVCNT
[4:F1] nRRSN 8 [3:E5] nHVCNT 6 C113 C127 B4PVH
9 BL33 BLM11B221SDT 7 ECA1VM101B
nHVLKC
BL7 BLM11B221SDT 10 [4:F1] nHVLKC 8 ECJ2VF1H104Z
nPESN CN12
[4:F1] nPESN 11 BL34 BLM11B221SDT 9 C112
VREF
12 [3:B5] VREF 10 ECJ2VF1H104Z C128 BL46 ERJ3GSY0R00V 20
VOUTE
BL35 BLM11B221SDT 11 ECA1VM101B [6:E1] VOUTE 19
nHVBCNT
[3:E5] nHVBCNT BL47 ERJ3GSY0R00V 18
DF311P2DSA VOUTO
[6:C1] VOUTO 17
DF1112DP2DSA
BL48 BLM11B221SDT 16
CCDADT
[3:F5] CCDADT 15
BL49 BLM11B221SDT 14
VL C44 ECJ1VF1C104Z CCDACLK
BL66 BLM11P600SPT [3:F5] CCDACLK 13
BL36 BLM11B221SDT BL50 BLM11B221SDT 12
nEPCNT CCDALD
BL8 BLM11B221SDT [4:C6] nEPCNT [3:F5] CCDALD 11
CPDAT CN9 PVP
[3:F6] CPDAT BL37 BLM11B221SDT BL51 BLM11B221SDT 10
nHTTR CN29 nSH
BL9 BLM11B221SDT [4:F4] nHTTR 1 [3:F5] nSH 9
[4:C1] CPKEY NF5
CPKEY BL38 BLM11B221SDT 2 1 8
ZCRS nCT NFM839470101
BL10BLM11B221SDT C243 [4:A1] ZCRS 3 [5:C3] nCT 2 7
LCLK nFCK 1 3
[3:E6] LCLK ECUV1H101JCV 1 BL39 BLM11B221SDT 4 [3:F5] nFCK 6
CN2 nSVCNT DF32P2DSA
BL11 BLM11B221SDT [2:C6] nSVCNT 5 5
pCPLD
[3:E6] pCPLD 1 BL40 BLM11B221SDT 4
nPVCNT DF35P2DSA 1 NF6

2
2 [2:B6] nPVCNT 3
NFM839470101
BL12 BLM11B221SDT 3 2
pCPLAT nSCK 1 3
[3:E6] pCPLAT 4 [3:F5] nSCK 1
5
20FE-BT-VK-N
6
NF7

2
BL14 BLM11B221SDT 7
KCLK VL C47 ECJ1VF1C104Z 1 NFM839470101
[3:E6] KCLK 8 BL72 BLM11P600SPT
nRS1 1 3
9 [3:F5] nRS1
10
PVP
BL15 BLM11B221SDT 11
EPAKEY CN10 NF8

2
[4:C2] EPAKEY 12
NFM839470101
BL16BLM11B221SDT 13 BL41 BLM11B221SDT 1
EPALED TESN nRS2 1 3
[3:C6] EPALED 14 [4:B1] TESN 2 [3:E5] nRS2
BL42 BLM11B221SDT 3
DF1114DP2DSA nELP
[5:D3] nELP 4

2
BL43 BLM11B221SDT 5
TH1
[4:F3] TH1 6
VL

B B
BL44 BLM11B221SDT 7 BL74 BLM11P600SPT
PVP TH2
[4:E3] TH2 8
CN3 +12V
BL45 BLM11B221SDT 9 BL75 BLM11P600SPT
nNDSN
1 [4:E1] nNDSN 10
nEXFL -12V
[4:F1] nEXFL pEXFM
2
DF310P2DSA
BL76 BLM11P600SPT
[5:B3] pEXFM nRRSOL
3
[5:D3] nRRSOL 4
5 C133
nPUSOL
[5:D3] nPUSOL 6
7 C115 C114
nHFSOL
[5:D3] nHFSOL 8 ECEA1VKA100B
9 ECJ1VF1E104ZECJ1VF1E104Z
10 C134 C68
DF1110DP2DSA ECEA1VKA100B
C48
PVP C245 ECJ1VF1C104Z ECJ1VF1C104Z
BL82 BLM21P600SGT ECEA1CKA100B
VL_LSU
C131 ECJ1VF1C104Z
R137 CN4 1 VLC C41 ECEA1CKA101B
BL79 BLM11P300SPT
ERJ3GSYJ201V (1A)
1
-12V VL
BL17 BLM11B221SDT 2 ECA1VM101B
[3:C4]nHSYNC nHSYNC
3
BL18 BLM11B221SDT 4 C126
ENABLE CN11
[3:E5] ENABLE 5 ECJ2VF1H104Z C111 A[1..20] 17
BL19 BLM11B221SDT 6 A[1..20]
[2:F1] [3:E1] VCC
nVIDEO CN13 51
[3:E5] nVIDEO 7 TL11 18
VCC
BL20 BLM11B221SDT 8 C125 1 VPP1
ADJUST A1 29
[3:E5] ADJUST 9
+12V ECJ2VF1H104Z C110
2
A2 28
A0
BL21 BLM11B221SDT 10 3 A1
nPMCNT A3 27
[2:B6] nPMCNT 11 ECA1VM101B 4 A2
A4 26
BL22 BLM11B221SDT 12 5 A3
nPMLCK A5 25
[4:F1] nPMLCK 13 C130 6 A4
A6 24
BL23 BLM11B221SDT 14 7 A5
PMCLK 3.3V C39 C40 ECEA1CKA101B A7 23
[3:E5] PMCLK 15 8 A6
A8 22
16 ECJ1VF1C104Z ECJ1VF1C104Z 9 A7
A9 12
10 A8
DF1116DP2DSA A10 11
C129 11 A9
A11 8
C37 C38 ECEA1CKA101B 12 A10
VL A12 10
13 A11
VL C45 ECJ1VF1C104Z A13 21
BL69 BLM11P600SPT 14 A12
A14 13
ECJ1VF1C104Z 15 A13
CN5 A15 14
ECJ1VF1C104Z NF1 A14
DF315P2DSA A16 20
BL24 BLM11B221SDT 1 A15
[4:F1] nHPSN nHPSN DSS30691F103 A17 19
2 A16
VL_LSU 1 3 A18 46
3 A17
A19 47
BL25 BLM11B221SDT 4 C132 A18
[4:E1] nPCSN D[0..15] A20 48
nPCSN 5 C42 [2:F1] [3:F1]D[0..15] A19
49
2

C 6
7
175487-7
ECJ1VF1C104Z
ECEA1CKA101B
D0
50
53
30
A20
A21
A22
D0
C
D1 31
D1
D2 32
D2
D3 2
D3
D4 3
D4
D5 4
D5
SVP SVP D6 5
D6
CN6 D7 6
D7
nLMBB (1A) D8 64
[5:E3] nLMBB 1 D8
CN16 D9 65
2 D9
nLMB (1A) D10 66
[5:E3] nLMB nLMAB (1A)
3 1
D11 37
D10
[5:E3] nLMAB 4
nLPCNT
BL13 BLM11B221SDT 2
D12 38
D11
5 [3:F5] nLPCNT 3 D12
nLMA (1A) D13 39
[5:F3] nLMA 6 4
D14 40
D13
D14
175487-6 04FEBTVKN VL D15 41
D15
nID0 67
[4:E1] nID0 ID0
nID1 63
[4:D1] nID1 ID1
nID2 62
[4:D1] nID2 ID2
nWRL 15
[3:D1] [2:D6]nWRL nWRH 33
WEL
[3:D1] [2:D6]nWRH WEH
PVP CN17 7
BL56 BLM11B221SDT CE1
nHFPS1 nFAXROMCS 42
BLM11B221SDT [4:D1] nHFPS1 1 [3:D1] nFAXROMCS CE2
CN7 R73 16
BL26 BL71 2 RDY/BSY
nMMLCK nHFPS2 ERJ3GSYJ103V nRDTL107 9
[4:F1] nMMLCK 1 [4:D1] nHFPS2 3 [3:D1] [2:D6]nRD OE
nCD 36
BL27 2 BLM11B221SDT 4 [4:D1] nCD CD
nMMCNT 59
[2:B6] nMMCNT 3 TL12 MB4
175487-4 44
BLM11B221SDT 4 TL13 RFU
45
5 TL14 RFU
57
TL15 RFU
175487-5 60
TL16 RFU
43
TL17 N.C.
52
TL18 N.C.
VL 54
TL19 N.C.
55
TL20 N.C.
56
TL21 N.C.
CN15 nRST1 58
[2:A4] [3:B4] [4:B2]
nRST1 N.C.
61
1 TL22 N.C.
TXD1OUT 1
[5:E5] TXD1OUT 2 GND
RXD1IN 34
[5:E6] RXD1IN 3 GND
35
4 GND
68
GND
DF34P2DSA

ICM-C68H-S112-400N1

D PCMCIA CON.
D

Model Drawing Name


FFPWB06641
For DP-130/150 CONNECTOR.SCH (7/7)
1 2 3 4

33
2.3. CPU PC Board (P/A/PA/PP/FX Model)
1 2 3 4
CPUBLK
CPUBLK.Sch Ga2blk
D[0..15] A[0..21] Ga2blk.sch OUTPUT
D[0..15] A[0..21]
nZC SYSCK BRDATA[0..7] BIDATA[0..7] OUTPUT.Sch IEEE1284
nZC SYSCK BRDATA[0..7] BIDATA[0..7]
nINT1 nCS0 BRLEN BIRDY nLMAI nLMA IEEE1284.sch CONNECTOR
nINT1 nCS0 BRLEN BIRDY nLMAI nLMA
nGCPDRQ0 nCS1 BRVEN nGA2INT nLMABI nLMAB A[1..5] nINTPREPA CONNECTOR.Sch
nGCPDRQ0 nCS1 BRVEN nGA2INT nLMABI nLMAB A[1..5] nINTPREPA
nINT3 nRD BRSTB nDREQ0 nLMBI nLMB nCSPR nDREQPRR nADSBSOL2 nPFOSN
nINT3 nRD BRSTB nDREQ0 nLMBI nLMB nCSPR nDREQPRR nADSBSOL2 nPFOSN
nSRAMCS nWRH BILEN nDREQ1 nLMBBI nLMBB nRD nDREQPRS nADSBSOL1 nRRSN
nSRAMCS nWRH BILEN nDREQ1 nLMBBI nLMBB nRD nDREQPRS nADSBSOL1 nRRSN
nPFOSNIN nWRL BIVEN CS_CO1 nLMENB RXD1 nWRL nINTPR nADPFSOL nPESN
nPFOSNIN nWRL BIVEN CS_CO1 nLMENB RXD1 nWRL nINTPR nADPFSOL nPESN
nHVLKCIN nHFSOLI BIRD FAX_A0 LMPDWN TXD1OUT PRRST CPDAT nADPSN2
nHVLKCIN nHFSOLI BIRD FAX_A0 LMPDWN TXD1OUT PRRST CPDAT nADPSN2
nWR nELPI A[0..21] FAX_A1 TXD1 nADMA nDRAKPRR LCLK nADPSN1
nWR nELPI A[0..21] FAX_A1 TXD1 nADMA nDRAKPRR LCLK nADPSN1
nROM0CS nPUSOLI D[0..15] IDBACK RXD1IN nADMAB nWRH KCLK CPKEY
nROM0CS nPUSOLI D[0..15] IDBACK RXD1IN nADMAB nWRH KCLK CPKEY
nPCSNIN nSVCNT nWRL IDACK AMPDWN nADMB D[0..15] pCPLAT nEXFL
nPCSNIN nSVCNT nWRL IDACK AMPDWN nADMB D[0..15] pCPLAT nEXFL
nNDSNIN nPVCNT nWRH OBACK nADMAI nADMBB EPARSTPR pCPLD nHSYNC
A HTSNIN
TESNIN
nNDSNIN
HTSNIN
nPVCNT
nPMCNT
nPMCNT
nMMCNT
nRD
nCS0
nWRH
nRD
OBACK
ODACK
ODACK
I_D
nADMABI
nADMBI
nADMAI
nADMABI
nADMBB
nRRSOL
nRRSOL
nHFSOL
nDRAKPRS
pRST1
EPARSTPR
nDRAKPRS
pCPWR
pEXFM
pCPLD
pCPWR
nHSYNC
nPMLCK
nPMLCK
nHPSN
A
TESNIN nMMCNT nCS0 I_D nADMBI nHFSOL pRST1 pEXFM nHPSN
PVPEM LMPDWN nCS2 SMATSD[0..12] nADMBBI nPUSOL nRST1 nRRSOL nPCSN
PVPEM LMPDWN nCS2 SMATSD[0..12] nADMBBI nPUSOL nRST1 nRRSOL nPCSN
SVPEM TXD1 nCS3 BASD0 nADMENB nELP nPUSOL nSCRSN
SVPEM TXD1 nCS3 BASD0 nADMENB nELP nPUSOL nSCRSN
nWAIT nRST0 nRST0 BASD1 nRRSOLI nSCPSOL nHFSOL nSCPESN
nWAIT nRST0 nRST0 BASD1 nRRSOLI nSCPSOL nHFSOL nSCPESN
RXD1 nRST1 pDRAK0 WESD nHFSOLI nAFRRCL ENABLE nAFOSIZ1
RXD1 nRST1 pDRAK0 WESD nHFSOLI nAFRRCL ENABLE nAFOSIZ1
nAFOSIZ1IN nCS2 pDRAK1 CKSD nPUSOLI nSTPSOL nVIDEO nAFRRSN
nAFOSIZ1IN nCS2 pDRAK1 CKSD nPUSOLI nSTPSOL nVIDEO nAFRRSN
nAFOSNIN nCS3 nDPACK CASSD nELPI nAFPSOL ADJUST nAFOSN
nAFOSNIN nCS3 nDPACK CASSD nELPI nAFPSOL ADJUST nAFOSN
nDREQ0 pDACK0 IOD[0..15] RASSD nSCPSOLI nADPFSOL nPMCNT nAPESN
nDREQ0 pDACK0 IOD[0..15] RASSD nSCPSOLI nADPFSOL nPMCNT nAPESN
nDREQ1 nADPFSOLI IDREQ DQMLSD nAFRRSOLI nADSBSOL1 PMCLK EPAKEY
nDREQ1 nADPFSOLI IDREQ DQMLSD nAFRRSOLI nADSBSOL1 PMCLK EPAKEY
nAPESNEPA nAFPSOLI ODREQ DQMUSD nAFPSOLI nADSBSOL2 nLMA nDPACK
nAPESNEPA nAFPSOLI ODREQ DQMUSD nAFPSOLI nADSBSOL2 nLMA nDPACK
nSCRSNIN nSTPSOLI INTCO nWAIT nSTPSOLI pEXFM nLMAB nDIRQ1
nSCRSNIN nSTPSOLI INTCO nWAIT nSTPSOLI pEXFM nLMAB nDIRQ1
nSCPESNIN nADSBSOL1I SDATSD[0..15] nDRAKPRR nADPFSOLI nLMB nDIRQ2
nSCPESNIN nADSBSOL1I SDATSD[0..15] nDRAKPRR nADPFSOLI nLMB nDIRQ2
nINT4 nADSBSOL2I pDACK0 nDRAKPRS nADSBSOL1I nLMBB nCTONP
nINT4 nADSBSOL2I pDACK0 nDRAKPRS nADSBSOL1I nLMBB nCTONP
nGCPDRQ1 AMPDWN nWAITG1 nSDCSE[0..3] nADSBSOL2I EPACPU nSCPSOL nMMLCK
nGCPDRQ1 AMPDWN nWAITG1 nSDCSE[0..3] nADSBSOL2I nSCPSOL nMMLCK
nDIRQ2 pRST1 nDREQPRR nMODEMCS nEXFMI EPACPU.Sch nSTPSOL VREF
nDIRQ2 pRST1 nDREQPRR nMODEMCS nEXFMI nSTPSOL VREF
nINTPR pDRAK0 nDREQPRS nFAXCDCS EPTXD EPRXD nAFRRCL nHVLKC
nINTPR pDRAK0 nDREQPRS nFAXCDCS EPTXD EPRXD nAFRRCL nHVLKC
EPRXD pDRAK1 SYSCK nFAXROMCS nINTPREPA EPALED nAFPSOL ZCRS
EPRXD pDRAK1 SYSCK nFAXROMCS nINTPREPA EPALED nAFPSOL ZCRS
MB4 EPARST nCSPR nCTONP EPARSTPR nADMA TESN
MB4 EPARST nCSPR nCTONP EPARSTPR nADMA TESN
EPAKEYIN nMDRST EPAKEY nAPESNEPA nADMAB TH1
EPAKEYIN nMDRST EPAKEY nAPESNEPA nADMAB TH1
nCTONPIN EPTXD nEPCNT EPAKEYIN nADMB TH2
nCTONPIN EPTXD nEPCNT EPAKEYIN nADMB TH2
nROM1CS PRRST nHSDTP nCTONPIN nADMBB nNDSN
nROM1CS PRRST nHSDTP nCTONPIN nADMBB nNDSN
nCPLATGD nAPESNIN EPALED VOUTE
nCPLATGD nAPESNIN EPALED VOUTE
EPARST D[0..15] VOUTO
EPARST D[0..15] VOUTO
pBZCK A[0..20] RXD1IN
pBZCK A[0..20] RXD1IN
nWRL nHFPS1
nWRL nHFPS1
nWRH nHFPS2
nWRH nHFPS2
nRD SMEMID[0..3]
nRD SMEMID[0..3]
nMODEMCS nCD
nMODEMCS nCD
SYSCKFX nDOPSN
SYSCKFX nDOPSN
nMDRST MB4
nMDRST MB4
pBZCK nID0
pBZCK nID0
nMMCNT nID1
B GABLK
TREF
GREF
nMMCNT
TREF
nID1
nID2
nID2
nGCPINT
B
GREF nGCPINT
GABLK.Sch CCDIF BREF nHSDTP
BREF nHSDTP
D[0..15] nWAITG1 INPUT CCDIF.sch nHVTCNT
D[0..15] nWAITG1 nHVTCNT
A[0..21] nWR INPUT.Sch OGSET SVDATAA[0..7] nHVCNT
A[0..21] nWR OGSET SVDATAA[0..7] nHVCNT
nCS0 nSRAMCS nPESN nPESNIN ADCLK2 SVDATAB[0..7] nHVBCNT
nCS0 nSRAMCS nPESN nPESNIN ADCLK2 SVDATAB[0..7] nHVBCNT
nCS1 nROM0CS nHPSN nHPSNIN EGSET nSVCNT
nCS1 nROM0CS nHPSN nHPSNIN EGSET nSVCNT
nRD nLMAI nRRSN nRRSNIN ADCLK1 nPVCNT
nRD nLMAI nRRSN nRRSNIN ADCLK1 nPVCNT
nWRH nLMABI ZCRS nZC VOUTE Pm22blk nHTTR
nWRH nLMABI ZCRS nZC VOUTE nHTTR
nWRL nLMBI pHTCNT nHTTR VOUTO Pm22blk.sch nEPCNT
nWRL nLMBI pHTCNT nHTTR VOUTO nEPCNT
nRST0 nLMBBI TH1 nID0I D[0..15] OBACK nELP
nRST0 nLMBBI TH1 nID0I D[0..15] OBACK nELP
nID0I nLMENB TH2 nID1I I_D ODACK CCDADT
nID0I nLMENB TH2 nID1I I_D ODACK CCDADT
nID1I nEXFMI nCD nID2I NWRL INTCO CCDACLK
nID1I nEXFMI nCD nID2I NWRL INTCO CCDACLK
nID2I pHTCNT nMMLCK nCDI nRD IDREQ CCDALD
nID2I pHTCNT nMMLCK nCDI nRD IDREQ CCDALD
nCDI nRRSOLI nPFOSN nMMLCKIN ODREQ nSH
nCDI nRRSOLI nPFOSN nMMLCKIN ODREQ nSH
CPKEYIN ADCLK1 nEXFL nPCSNIN CS_CO1 nFCK
CPKEYIN ADCLK1 nEXFL nPCSNIN CS_CO1 nFCK
nPESNIN ADCLK2 nPMLCK nNDSNIN IDACK nSCK
nPESNIN ADCLK2 nPMLCK nNDSNIN IDACK nSCK
nZC nLPCNT nHVLKC CPKEYIN nRST0 nRS1
nZC nLPCNT nHVLKC CPKEYIN nRST0 nRS1
nMMLCKIN nHVCNT nPCSN nPFOSNIN IOD[0..15] nRS2
nMMLCKIN nHVCNT nPCSN nPFOSNIN IOD[0..15] nRS2
nEXFLIN nHVBCNT nNDSN nEXFLIN IDBACK TXD1OUT
nEXFLIN nHVBCNT nNDSN nEXFLIN IDBACK TXD1OUT
nPMLCKIN nHVTCNT CPKEY nPMLCKIN SYSCK nLPCNT
nPMLCKIN nHVTCNT CPKEY nPMLCKIN SYSCK nLPCNT
nHPSNIN PMCLK nAPESN nHVLKCIN FAX_A0
nHPSNIN PMCLK nAPESN nHVLKCIN FAX_A0
nRRSNIN CPDAT nHFPS1 nHFPS1IN FAX_A1
nRRSNIN CPDAT nHFPS1 nHFPS1IN FAX_A1
SVDATAA[0..7] LCLK nHFPS2 nHFPS2IN nSDCSE[0..3]
SVDATAA[0..7] LCLK nHFPS2 nHFPS2IN nSDCSE[0..3]
SVDATAB[0..7] KCLK nAFOSIZ1 nAPESNIN SMATSD[0..12]
SVDATAB[0..7] KCLK nAFOSIZ1 nAPESNIN SMATSD[0..12]
VREF pCPLAT nAFOSN nAFOSIZ1IN SDATSD[0..15]
VREF pCPLAT nAFOSN nAFOSIZ1IN SDATSD[0..15]
nHSYNC pCPLD nAFRRSN nAFOSNIN DQMLSD
nHSYNC pCPLD nAFRRSN nAFOSNIN DQMLSD
nHFPS1IN GREF nSCPESN nAFRRSNIN DQMUSD
nHFPS1IN GREF nSCPESN nAFRRSNIN DQMUSD
nHFPS2IN BREF nSCRSN nSCPESNIN BASD0
nHFPS2IN BREF nSCRSN nSCPESNIN BASD0
nRST1 TREF nADPSN1 nSCRSNIN BASD1
nRST1 TREF nADPSN1 nSCRSNIN BASD1
nADPSN1IN OGSET nADPSN2 nADPSN1IN WESD
nADPSN1IN OGSET nADPSN2 nADPSN1IN WESD
nADPSN2IN EGSET TESN nADPSN2IN CKSD
nADPSN2IN EGSET TESN nADPSN2IN CKSD
nAFRRSNIN CCDADT nDOPSN PVPEM CASSD
C BIDATA[0..7]
BIRDY
nAFRRSNIN CCDADT
BIDATA[0..7] CCDACLK
CCDACLK
CCDALD
nID0
nID1
nDOPSN
nID0
PVPEM
TESNIN
TESNIN
HTSNIN
RASSD
nFAXCDCS
CASSD
RASSD C
BIRDY CCDALD nID1 HTSNIN nFAXCDCS
nDOPSNIN nSH nID2 SVPEM nFAXROMCS
nDOPSNIN nSH nID2 SVPEM nFAXROMCS
nGA2INT nFCK MB4 nDOPSNIN nRST1
nGA2INT nFCK MB4 nDOPSNIN nRST1
nGCPINT nSCK MB4I nGCPCS
nGCPINT nSCK MB4I nGCPCS
nDIRQ1 nRS1 nGCPDRQ0
nDIRQ1 nRS1 nGCPDRQ0
nCPLATGD nRS2 nGCPDRQ1
nCPLATGD nRS2 nGCPDRQ1
ADJUST
ADJUST
nVIDEO
nVIDEO
ENABLE
ENABLE
nADMAI
nADMAI
nADMABI
nADMABI
nADMBI
nADMBI
nADMBBI
nADMBBI
nADMENB
nADMENB
pCPWR
pCPWR
nAFRRSOLI
nAFRRSOLI
nSCPSOLI
nSCPSOLI
BILEN
BILEN
BIVEN
BIVEN
BIRD
BIRD
BRDATA[0..7]
BRDATA[0..7]
BRLEN
BRLEN
BRVEN
BRVEN
BRSTB
BRSTB
SMEMID[0..3]
SMEMID[0..3]
nROM1CS
nROM1CS
nINT1
nINT1
nGCPCS
nGCPCS
SYSCK
SYSCKGA2
nINT3
nINT3
nINT4
nINT4
SYSCKFX
D SYSCKFX
D
Model Drawing Name
FFPWB0665 For DP-150FX/FP
FFPWB06651 For DP-150A
FFPWB06652 For DP-130P/150P MAINROOT (1/11)
FFPWB06653 For DP-150PA
1 2 3 4

34
1 2 3 4

[3:F1] [4:B3] [8:E1] [10:E2] [11:D5]


D[0..15] D[0..15]
D[0..15]
A[0..21] A[0..21]
A[0..21]
[3:E1] [4:C3] [8:D1] [11:C5]

A A0
A1
A2
32
28
27
IC41
A0
A1
D0
D1
33
35
38
D0
D1
D2
A
A2 D2
A3 26 40 D3
A3 D3
A4 25 44 D4
A4 D4
A5 24 46 D5
A5 D5
A6 23 49 D6
A6 D6
A7 22 51 D7
A7 D7
A8 20 34 D8
A8 D8
A9 19 36 D9
A9 D9
A10 18 39 D10 RA5 MNR14EABJ103 VL

A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A10 D10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A11 17 41 D11 7 8
A11 D11
A12 13 45 D12 5 6
A12 D12
A13 12 47 D13 3 4
A13 D13
A14 11 50 D14 1 2
A14 D14
A15 10 52 D15
A15 D15
A16 8 RA6 MNR14EABJ103
A16
A17 7 3 7 8
A17 N.C. TL24
A18 6 1 5 6
A18 N.C. TL25 2
A19 5 29 R152 3 4
A19 N.C. TL43
A20 4 30 VL VL_CPU ERJ3GSY0R00V 1 2
A20 N.C. TL45
NF16 (NOT MOUNT)
VL nRST0 16 53 1 3 VL_CPU RA7 MNR14EABJ103
RP STS TL57 C35
31 7 8
BYTE 1 ECJ1VF1C104Z
9 NFM60R30T222 5 6
VCC
nROM1CS 14 37 VL 3 4

2
[3:D1] nROM1CS CE0 VCC
2 43 1 2
CE1 VCC
nRD 54
OE C248
nWR 55 21 R316 RA8 MNR14EABJ103
WE GND ECJ1VF1C104Z
VL_GA1 nWP1 56 42 ERJ3GSY0R00V 7 8
WP GND
15 48 5 6
DT13 VPP GND
3 4
DTB114EKT146 LHF16K57 1 2
nVPPCNT1 RA2 RA4 C4
MNR14EABJ103 MNR14EABJ103 ECJ1VF1C104Z RA9 MNR14EABJ103
RA1 RA3 C3 7 8
IC2 MNR14EABJ103 MNR14EABJ103 C2 ECJ1VF1C104Z C5 5 6
A0 32 33 D0 VL ECJ1VF1C104Z ECJ1VF1C104Z 3 4
A0 D0
R5 A1 28 35 D1 1 2
A1 D1
A2 27 38 D2 VL
ERJ3GSYJ103V A2 D2

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8
A3 26 40 D3 C1 R1
A3 D3 ERJ3GSYJ103V
A4 25 44 D4 VL ECJ1VF1C104Z
A4 D4

2
4
6
8

2