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Current and voltage parameters Fan-Out Propagation delays Power requirements Noise immunity Invalid voltage levels Current-sourcing and current-sinking action IC Packages
Common IC packages
(Courtesy of Texas Instruments)
VIH(min): high-level input voltage VIL(max): low-level input voltage VOH(min): high-level output voltage VOL(max): low-level output voltage
IIH(min): high-level input current, the current that flows into an
input when a specified high-level voltage is applied to that input.
IIL(max): low-level input current IOH(min): high-level output current IOL(max): low-level output current
Every IC needs a certain amount of electrical power to operate. Vcc (TTL) VDD(MOS) Power dissipation determined by Icc and Vcc. Average Icc(avg)= (ICCH + ICCL)/2 PD(avg) = Icc(avg) x Vcc
Power Dissipation :Power dissipation is the amount of heat (in milliwatts) that the IC dissipates in the form of heat.
ICCH and ICCL
ICCL – current from supply when all outputs are low
ICCH – current from supply when all outputs are high
Propagation delays Measured between 50% points on inputs and outputs .
.DC noise margins Noise margins – amount of “noise” a signal can tolerate going from an outp an input.
Currents and voltages in the two logic states O – output I – input H – high L .low .
Comparison of current-sourcing and current-sinking actions .
IIL : Integrated injection logic. • • • • • .Logic Families • RTL : Resistor transistor logic DTL : Diode transistor Logic TTL: Transistor-transistor logic ECL: Emitter-coupled logic. MOS ICs: Metal-oxide-semiconductor ICs.
Diode Logic (DL) • In Diode logic. Diodes also cannot work for multiple stages. o o . • • Diodes can also be used as a logical switch o The disadvantage of Diodes is that they tend to degrade the signals quickly. The diodes also cannot perform the NOT operation which limits their functionality. all the logic is implemented with the use of resistors and diodes The purpose of the diodes is to perform OR and AND operations. only one stage at a time.
The drawback in using RTL gates is that they draw a great amount of current from the power supply. ü . ü ü RTL gates can be used as amplifiers as well to amplify small signals. ü They are used in slower applications. all the logic is implemented with the use of transistors and resistors ü Resistor-Transistor gates are not very expensive and are very simple to construct. but cannot be used in today's computers as they cannot switch at high speeds.Resistor-Transistor Logic (RTL) In resistor-transistor logic.
If any input is high the corresponding transistor is driven into saturation This causes output as low If all input are low at 0.2v all transistors are cutoff because 2. 3.1. .
Ø Ø DTL was used in early vacuum tube computers. .Diode Transistor Logic (DTL) In Diode-transistor logic. As the diodes can perform AND and OR operations but along with a transistor the output signal can be amplified Ø The switching speed of the transistor is limited due to the input resistor to transistor. all the logic is implemented with the use of diodes and transistors. Ø DTL has some advantages over DL and RTL.
Y=(A. .C)’ If all the inputs are high the transistor is driven into saturation region The voltage at Y equal to VBE plus the two diode drops across D4 & D5.B.
.8-2 The Transistor-Transistor-Logic (TTL) Logic Family The NAND gate is a basic TTL circuit.
8-2 The TTL Logic Family TTL circuits have a similar structure The input will be the cathode of a PN junction A HIGH input will turn off the junction and only a leakage current is generated in Q1 (Q2 and Q4 turn on). A LOW input turns on the junction and a relatively large current is generated through Q1 (Q2 and Q4 turn off). Most TTL circuits have some type of totem-pole output configuration .
TTL NAND gate in its two output states .
TTL NAND gate with output low .
TTL NAND gate with output high .
Flow of Current in TTL Output State Figure 8-9 (a) When the TTL output is in the LOW state. providing current to the load gate. (b) In the output HIGH state. Q4 acts as a current sink. . Q3 acts as a current source. deriving its current from the load.
wise. and Q6 if off. Q3 and Q4 are off. if A or B is high.TTL NOR gate circuit Q2 and Q4 added to TTL inverter is high only when A and B are low. . Q6 is on and output is low. case both Q1 and Q2 are on.
and output is low . Q4 and Q6 is on. and output is low hen B is high.TTL NOR gate circuit Q2 and Q4 added to TTL inverter hen A is high. Q3 and Q6 is on.
and Q6 is off. Q3 and Q4 are off.TTL NOR gate circuit Q2 and Q4 added to TTL inverter ut is high only when A and B are low. s case both Q1 and Q2 are on. .
and recommended operating conditions. switching characteristics. SN7402. S7402 all perform the same function Data sheets contain electrical characteristics. prefix indicates manufacturer SN – Texas Instruments DM – National Semiconductor S – Signetics DM7402. .8-3 TTL Data Sheets First line of TTL ICs was the 54/74 series 54 series operates over a wider temperature range Same numbering system.
v The logic levels for ECL are normally -0.Emitter Coupled Logic (ECL) v This logic is used in applications with high speed environment.6 for low logic. The design of ECL consists of termination resistors which allows the signals to v propagate with very low reflection.9V for high logic and -1. v ECL is considered to be one of the best because there is a very low propagation delay. .
Data sheet for the 74ALS00 NAND gate IC (Courtesy of Texas Instruments) .
74 series Schottky TTL. 74LS series (LS-TTL) Advanced Schottky TTL. Columbus. 10e Copyright ©2007 by Pearson Education. . 74ALS series 74F fast TTL Refer to Table 8-6 for a comparison between the series characteristics Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications. Inc. 74S series Low power Schottky TTL. 74AS series (AS-TTL) Advanced low power Schottky TTL.8-4 TTL Series Characteristics Standard 74 series TTL has evolved into other series: Standard TTL. OH 43235 All rights reserved..
.Schottky-clamped Transistor (a) (b) (c) (d) (e) Schottky-clamped transistor. basic NAND gate in S-TTL series Schottky diode has a smaller junction voltage than the transistor currently will be shunted from the transistor when it goes into reverse bias preventing the transistor from going into saturation fewer carriers will be present in the transistor and it will switch faster.
OH 43235 All rights reserved. .. Inc.8-5 TTL Loading and Fan Out Fan out refers to the load drive capability of an IC output A TTL output has a limit on how much current it can sink in the LOW state A TTL output has a limit on how much current it can source in the HIGH state. Columbus. 10e Copyright ©2007 by Pearson Education. Exceeding these currents will result in output voltage levels outside specified ranges Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications.
The sum must be less than the output IOL specification.. Add the IIL for all inputs connected to an output. . OH 43235 All rights reserved. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications.8-5 TTL Loading and Fan Out Determining fan out Add the IIH for all inputs connected to an output. Columbus. 10e Copyright ©2007 by Pearson Education. The sum must be less than the output IOH specification. Inc.
Currents when a TTL output is driving several inputs .
. 10e Copyright ©2007 by Pearson Education. Inc.. Columbus.8-6 Other TTL Characteristics Unconnected (floating) inputs Unused inputs Tied together inputs Biasing TTL inputs low Current transients Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications. OH 43235 All rights reserved.
Three ways to handle unused logic inputs .
•Gate 4 uses a • . Leakage currents. Each input • Gates 2 and 3 have one input transistor. and IIL = 0. the 74LS devices have IIH = 20uA.4mA.Determining TTL Loads Determine the load that gate 1 is driving.
6 mA = -8.Calculating fan-out • (max fan-out low). •Maximum sink (implies low output) current = fan-out x IL = 5 x -1. 5 in this case.6mA| = 5 .0mA.4mA| / 40uA = 10(max fan-out high) •Maximum fan-out is limited by lowest fan-out. •Max fan-out of LS to standard TTL (high) = IOH(max) / IIH(max) = |-. Max fan-out of LS to standard TTL (low) = IOL(max) / IIL(max) = 8mA / |-1.
Max fan-out when low = IOL(max) / IIL(max) . •Maximum fan-out is limited by lowest fan-out.4mA| / 20uA = 20 (max fan-out high for 74AS devices.4mA| = 20 (max fan-out low for 74AS devices. •Max fan-out when high = IOH(max) / IIH(max) = |-0.• = 8mA/|-.
Magnitude of current needed by load should be less than magnitude of max sink or source current. • Max sink current for LS device in low state. • . . fan-out x IIL = 20 x -0.4mA = Max supply current for LS device in high state.4mA = -8mA. fan-out x IOH = 20 x -0.Driving Different Families ermine max currents that can be supplied and sunk ermine current needed • -8mA.
Calculating Propagation Delay Time .Figure 8-56 Problems 8-11 and 8-13.
TTL Characteristic When Switching from LOW to HIGH • When a totem pole TTL output goes from LOW to HIGH. . a high amplitude current spike is drawn from the VCC supply (because Q4 and Q3 are both on for a short time).
8-7 MOS Technology Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Simple and cheap to fabricate Consume very little power More circuit elements are possible Susceptible to static electricity damage .
.8-7 MOS Technology Schematic symbols for P and N channel enhancement MOSFETs.
(c) N-MOS inverter operation. . (b) circuit model.8-7 MOS Technology: N-channel MOSFET N-channel MOSFET used as a switch: (a) symbol.
(b) circuit model for OFF and ON. (c) P-MOS inverter circuit. .P-channel MOSFET P-channel MOSFET used as a switch: (a) symbol.
8-8 Complementary MOS Logic The CMOS family uses both P and N channel MOSFETs Faster Consumes less power More complex fabrication CMOS Inverter (Figure 8-22) CMOS NAND gate (Figure 8-23) CMOS NOR gate (Figure 8-24) .
CMOS INVERTER .
CMOS NAND gate .
CMOS NOR gate .
8-9 CMOS Series Characteristics CMOS devices compete directly with TTL Pin compatible Functionally equivalent Electrically compatible 4000/1400 series 74C series 74HC/HCT (high-speed CMOS) 74AC/ACT (advanced CMOS) 74AHC/AHCT (advanced high-speed CMOS) BiCMOS 5-volt logic Fan out Switching speed Unused inputs .
Loads Act Like Capacitors Figure 8-26 Each CMOS input adds to the total load capacitance seen by the driving gate’s output. .
Current spikes when switching (charging a capacitive load) Figure 8-25 Current spikes are drawn from the VDD supply each time the output switches from LOW to HIGH. This is due mainly to the charging current of the load capacitance. .
8-10 Low Voltage Technology CMOS family: 74LVC (low voltage CMOS) 74ALVC (advanced low voltage CMOS) 74LV (low voltage) 74AVC (advanced very low voltage CMOS) 74AUC (advanced ultra-low voltage CMOS) 74AUP (advanced ultra-low power) 74CBT (cross bar technology) 74CBTLV (cross bar technology low voltage) 74GTLP (gunning transceiver logic plus) 74SSTV (stub series terminated logic) 74TVC (translation voltage clamp) .
8-10 Low Voltage Technology BiCMOS family: 74LVT (low voltage BiCMOS technology) 74ALVT (advanced low voltage BiCMOS technology) 74ALB (advanced low voltage BiCMOS) 74VME (VERSA Module Eurocard) .
Voltage-level comparison .
8-11 Open Collector/Open Drain Outputs Conventional CMOS outputs and TTL totem pole outputs should never be connected to the same point. Open-collector/open-drain outputs Open-collector/open-drain buffer/drivers IEEE/ANSI symbols for open collector/drain outputs .
.Open collector gates – no internal load Figure 8-30 (a) Opencollector TTL circuit. (b) with external pull-up resistor.
Cannot Connect Outputs of Typical Gates Together Figure 8-29 Totem-pole outputs tied together can produce harmful current through Q4. .
.Open-collector gates are useful for driving high-current loads Figure 8-32 An opencollector buffer/driver drives a high-current. high-voltage load.
Can connect open-collector to form an AND gate Figure 8-31 Wired-AND operation using open-collector gates. .
and high impedance.8-12 Tristate (Three-State) Logic Outputs Three states are possible: HIGH. LOW. Advantages of tristate devices Tristate buffers Tristate ICs IEEE/ANSI symbol for tristate outputs .
Hi-Z state is an open circuit Figure 8-35 Three output conditions of tristate. .
.Tri-state operation Figure 8-37 (a) Tristate buffers used to connect several signals to a common bus. (b) conditions for transmitting B to the bus.
Problem 8-31. Bidirectional transceiver .
8-15 CMOS Transmission Gate (Bilateral Switch) Acts as a single pole. . single throw switch Controlled by an input logic level Passes signals in both directions Signals applied to the input can be analog or digital Input must be between 0 and VDD volts.
CMOS bilateral switch (transmission gate) Both devices on or both off .
Figure 8-45 Example 8-12: 74HC4016 bilateral switches used to switch an analog signal to two different outputs. .
Determine the waveform at X assuming Ron = 200Ω .Problem 8-37.
Problem 8-14 Figure 8-57 Problem 8-14. Resistor R is used to hold MR LOW while the switch is open. The master reset is active-high and is activated by a push-button switch. (a) What is the maximum value that can be used for R? (b) Repeat if using a 74ALS193 Make this voltage < VIL(max) to remain a logic 0 .
The amplitude is less than VIL.tw(H)min or 33. so the answer is no.3ns. Therefore. However. 8. tw(L)min = Tmin .3ns. tw(L) (actual) is less than tw(L)min.3ns – 20ns = 13. No. . Tmin = 1/fmax = 33. fmax (from data sheet) is given as 30MHz. Tp of 10ns is less than tw(H) = 20ns minimum (from data sheet) tw(L) not given.b.16 Will each clock waveform below reliably trigger a 74LS112 flip (a) (b) (c) No.
yes – greater packing density Lower PD (below 1Mhz). 8. no – MOS rout~1000ohms Simpler fabrication structure. yes – MOS devices are smaller Higher speed. no Greater fan-out. yes – inputs to gates are capacitors Lower output impedance. no – input structure is a capacitor .19 Which of the following are advantages that CMOS generally h ? (a) (b) (c) (d) (e) (f) (g) (h) (i) Greater packing density.. yes Lower input capacitance. yes.MOS essentially an open circuit when off Transistors as only circuit element. yes More suited to VLSI. .
increase in f.20 Which of the following operating conditions will probably result st average PD for a CMOS logic system? (a) (b) (c) VDD = 5V.. switching frequency = 1MHz VDD = 5V. increase in I (current spike) . switching frequency = 10kHz Power drain generally increases with. increase in V. (b) is probably has the lowest average PD. switching frequency = 10kHz VDD = 10V. decrease in R (of capacitive load). therefore. 8. P = VI. increase in P I = V/R. an increase in VDD and frequency.
9V .Prob.8V – 0. Noise margins: VNL = VIL – VOL. VNH = VOH – VIH VNL = VIL(LS) – VOL(HC) = 0.1V = 0. 8.7V VNH = VOH(HC) – VIH(LS) = 4.9V – 2.22 Calculate the Noise Margins when a 74HC gate drives a standard 74LS input.0V = 2.
23 What will cause latch-up in a CMOS IC? Latch-up can be triggered by high-voltage spikes or ringing at the device inputs and outputs. CMOS cross-section . or a regulated power supply.Prob. a larger current flows and may damage the device. 8. When latch-up occurs. Clamping diodes can be used externally.
27 Determine the logic expression for output X. Output of wired-AND is (AB)’ (CD)’ (EF)’ X = ((AB)’ (CD)’ (EF)’)’ . 8.Prob.
(a) Tying the output to 5V (b) Tying the output to ground (c) Applying an input of 7V (d) Tying the output to another TTL output . 8.28 Which of the following would be most likely to destroy a TTL while it is switching from HIGH to LOW?.Prob.
4 = 2.4 – 0.29 (a) What will be the voltage of the 7406 output when Q = 0? (b) Find Rs if Vf = 2. (a) .2V. Voltage across Rs = 5V – Vf – VOL = 5 – 2.Prob. 8. (a) 5V since the 7406 has an open collector and Q4 is off.4V at If = 20mA for the diode.
NMOS Circuits Outputs obtained by using the inputs to either “pull-up” the network to VDD. Oklobdzija . or “pulldown” Y. G. D. Fabrication. in Digital Design and E. CRC Press 2008. eBook ISBN: 978-0-8493-8604-6. Markovic. CMOS Circuits. Yamashita. . andto ground. Ed. S. V. Kado. John.
Complex functions can be implemented with a • .ass Transistor/Transmission Gate Lo Inputs as well as VDD and ground are steered to the output. • • Simple and fast.
• • CMOS transmission gate operates as a bi-directional . • Using NMOS and PMOS in parallel allows both logic levels to pass well.ass Transistor/Transmission Gate Lo Simple pass transistor only passes one logic level well.
Similarly for other conditions. For a XOR gate. when both A and B are low. • . output is A (0).ass Transistor/Transmission Gate Lo • Can be used to realize logic gates and functions. the top TG in on and bottom is off.
Sequential CMOS Logic Circuits uential circuits depend on current and previous values of the put is stored as a state variable. . uit consists of combinational logic and memory.
• Operates as a latch when CLK = 1.Sequential CMOS Logic Circuits When CLK = 0. output remains the same due to feedback loop. and the data is accepted continually. • Positive-level sensing D-latch using transmission gates and inverters . positive-level sensing. • When CLK = 1. Q = D.
the negative latch holds the value of D at • Positive edge-triggered D flip-flo . The positive latch (rightmost latch) holds the previous value and the negative latch follows the input. • When CLK transitions to 1. the latches are isolated from each other. • When CLK = 0.Sequential CMOS Logic Circuits Positive and negative sensing latches can be combined to form an edge-triggered flip-flop.
Sequential CMOS Logic Circuits MOS implementation of the positive-edge triggered D flip-flop (18 transisto .
increase speed. Dynamic logic gates are used to decrease complexity. • Basic design eliminates one of the switch networks from the CMOS logic circuits (almost 50% reduction). • • Output decays with time unless it is periodically refreshed. and lower power dissipation. • .Dynamic Logic Circuits Use the capacitive input of the MOSFET to store a charge and remember the value for later use.
• When CLK = 0. • No conducting path between between VDD and ground for this precharge phase eliminates a static current. The PMOS is off and NMOS is on. PMOS is on and NMOS is off and the load capacitance is charged to VDD. a precharge and evaluation phase. • Evaluation phase starts when CLK = 1.Dynamic Logic Circuits Dynamic logic circuits have two-phase operation. • .
(b) discharges when A + B = 1.Dynamic Logic Circuits When CLK = 0. • . • When CLK = 1. PMOS is on and NMOS is off and the load capacitance is charged to VDD. (a) discharges when AB = 1. and (c) discharges when ABC + D = 1.
Low-Voltage Design Four sources of power dissipation in CMOS VLSI design .
• • Copper line and low-permittivity layer between wiring layers. and operation on low supply voltage.Silicon on Insulator Suited for low-parasitic capacitance.. .
Silicon on Insulator MOS transistor • SOI MOS transistor Improved SOI MOS transistor A MOSFET is formed on a thin SOI layer over a buried oxide (BOX) layer. • • . • The entire MOSFET is enclosed in a silicon oxide layer. The process technology is similar to conventional CMOS technology. Low capacitance near source/drain leads to high-speed operation.
the drain junction capacitance consists of a capacitance between the drain and the substrate. the capacitance between drain and substrate consists of a series capacitance. • . The BOX capacitance has a dielectric constant 1/3 smaller than Si. • In SOI structures.Silicon on Insulator In a conventional device.
Silicon on Insulator The threshold voltage of the MOSFET is a function of the sourcesubstrate voltage – body effect. • . the body is floating so there is no body effect. • In SOI structures (unlike the conventional case).
BiCMOS CMOS is limited by speed ECL is 2 to 5 times faster than CMOS but ECL has high power consumption which makes VLSI difficult BiCMOS combines the high-density integration of MOS logic with the current-driving capabilities of bipolar transistors .
BiCMOS Inverter Similar to a CMOS gate with a current amplifier as an output stage • When input is HIGH. M2 is on causing Q2 to conduct. The results is a LOW output. • . The results is a HIGH output. M1 is on causing Q1 to conduct. while M1 and Q1 are off. • When input is LOW. while M2 and Q2 are off.
BiCMOS Inverter When input is HIGH (output is LOW). current in M2 is multiplied by β in Q2 resulting in more current at the output and faster operation than CMOS. • Similar to CMOS but better capacitance-driving capabilities. • Has substantial speed advantage over CMOS gates when driving large • .
CMOS is better for driving small loads because of the added complexity of BiCMOS. BiCMOS probably not used with supply voltages under 3V. which limits the range of supply voltages The non-scalability of built-in voltages is one of the most important deficiencies of bipolar technology. • Built-in voltages like VBE(on) do not scale. • • that can be used. • .BiCMOS • Similar to CMOS but better capacitance-driving capabilities. • The use of BiCMOS in ICs like ALUs is not likely because of the complexity of BiCMOS. BiCMOS is better for driving large capacitive loads such as gate arrays and memories.
7 V logic 0 Noise margins approximately 150 mV Output complement is produced. eliminating need for inverters Typical fan out is 25 Typical power dissipation is 25 mW Current flow remains constant. -1. Basic ECL circuit ECL OR/NOR gate ECL characteristics n n n n n n n Very fast switching.8-14 The ECL Digital IC Family o o o o Emitter coupled logic – increased switching speed.8 V logic 1. eliminating noise spikes . typical propagation delay is 360 ps -0.
Current amplifiers . Chen . eBook ISBN: 978-0-20301015-0. in Logic Design Ed. W. (b) with addition of emitter followers.ECL Circuitry ECL Inverter Current switches from one side to the other S.1201/9780203010150.. Muroga. DOI: 10.-K. Emitter-Coupled Logic.ch13 Figure 8-41 (a) Basic ECL circuit. CRC Press 2003.
and can often be eliminated • • • . • Current flows to -4V through the transistor with the base grounded or one of the input transistors.Emitter-Coupled Logic (ECL) F = (X + Y + Z)’ F=X+Y+Z • . Current is amplified by emitter-follower amplifiers. The basic gate is the NOR/OR gate.The basis of the gate is a differential amplifier. 50Ω resistors only used for protecting transistors from large current.
Current will not flow through Tr and its collector will be high. and therefore one output of the gate low. it turns on the corresponding transistor. • When all input voltages are low. Current flows through Tr and its • . or Z. Currently flows through it making its collector have a low voltage.Emitter-Coupled Logic (ECL) .When a high voltage is applied to an input X. as well as its corresponding output. Y. the corresponding transistors are off and the corresponding output is high.
Emitter-Coupled Logic (ECL)
When the emitter circuits are connected together they may form a wired-OR circuit; also called emitter-dotting.
If both transistors T1 and T2 are off, the output is low; otherwise, the output is high.
Emitter-Coupled Logic (ECL)
An OR gate can be eliminated simply by connecting two outputs.
Once an output has been connected to another emitter, it does not retain its original logic function.
Emitter-Coupled Logic (ECL)
If an emitter follower circuit is repeated, then the corresponding outputs can be connected independently.
Reduce the number of input connections to each gate by providing Wired-Ors. • • Repeat for the OR network and choose the “best” one. . or by using OR-outputs of other gates.Emitter-Coupled Logic (ECL) Design of a logic network with ECL Procedure: •Design a network for given logic function and its complement using NOR gates without considering fan-in or fan-out restrictions. Use a minimum number of NOR gates.
Emitter-Coupled Logic (ECL) The use of OR outputs and wired-Ors generally reduces the number of connections or fan-ins (input transistors). and connections lengths. OR network NOR network . thus saving chip area.
Emitter-Coupled Logic (ECL) Series gating (a) (b) (c) x’ at collector when x is at base consider two transistors: one with x and one with y at base series gating results in OR function: x’ + y’ = (xy)’ .
Emitter-Coupled Logic (ECL) Series gating create a structure where the complement of minterms are available at collec .
Emitter-Coupled Logic (ECL) Logic functions in ECL can often be made with fewer transistors than CMOS Full-adder using series gating. and wired-OR connections in ECL .
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