Bipolar transistors theory and applications

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The bipolar transistors, theory and basic applications
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Module 5
THE BIPOLAR TRANSISTOR
1. Construction
The invention of transistor by Barden, Brattain and Shockley in 1948 has started the
real electronic era. The bipolar transistor consists of a semiconductor crystal in which a very
thin n-type (p-type) layer is sandwiched by two p-type (n-type) layers, as shown
schematically in Fig. 1. The emitter layer is normally highly doped than the base layer. The
doping concentration of the collector layer is normally different from that of the emitter and
base layers. The three layers are supplied with ohmic metallic contacts in order to be able to
bias the transistor. The three terminals are denoted by the emitter E, the base B and the
collector C. This type of transistor is called (pnp), (npn) transistor. We shall study in detail
the electrical behavior of pnp transistor. The results obtained hold equally well for npn
transistor. We shall see that for a good transistor, the base width must be much smaller than
the diffusion length of the minority charge carriers in the base region. With the last
condition satisfied, the transistor can function as an amplifier. It can be used also as a
controlled switch.
Figure 1. The schematic construction of bipolar transistors.
2. Qualitative Description Of The Transistor Action
It is clear from Fig. 1 , that a transistor has two pn junctions, the emitter-base junction
EJ and the collector-base junction CJ, with a common n-layer. Because any of them has two
states according to the polarity of the applied voltage on it, the forward and the reverse state,
there are four different possibilities to bias the transistor as indicated in table 1 & Fig. 2.
Consequently, four operation modes of a transistor will result. When the two junctions are
reverse biased very small current will pass through the transistor. Consequently, the
transistor can be considered as an open switch. In contrary if the two junctions are forward
biased, the transistor will be low ohmic and it can be simulated with a closed switch. In case
2 and 3 it will be in its active mode of operation.
1
When we apply a bias on the transistor, currents will pass in the emitter, in the
collector, and in the base. These currents will be denoted by IE, IC and IB respectively. We
shall assume that all currents flow in the different electrodes as shown in Fig. 3. The actual
directions of the currents can be the assumed directions or the opposite of them. It is clear
that there is a relation between the three currents. From the first Kirchhoff's law the sum of
the three currents is equal to zero, that is,
IE +IC+IB = 0 (1)
Thus, knowing two of these currents, the third can be determined from eqn (1).
EJ CJ state of transistor
1 reverse biased reverse biased switch off
VEB < 0 VCB < 0
2 forward biased reverse biased forward active, or normal active.
VEB > 0 VCB < 0
3 reverse biased forward biased Inverse active
VEB < 0 VCB > 0
4 forward biased forward biased saturation condition, switch on
VEB > 0 VCB > 0
Table 1. Different possibilities to bias the transistor and the corresponding modes of operation.
Figure 2. Different possibilities to bias a transistor.
Also, if the potential differences between two pairs of terminals are known, the third
can be determined from the second Kirchhoff's law,
VCE =VCB+VBE = VCB - VEB (2)

Thus we can determine the terminal currents and voltages completely by knowing two
currents and two voltages of the transistor.
2
3. The Forward Active Operation:
In this mode of operation, the transistor must be capable of amplifying signals. This
means that a small electric power supplied to the input circuit, here the emitter-base
junction, must cause a much larger power consumption from the collector supply VCB in the
output collector circuit. We can simply say we want to control the output power with small
input power.
In the transistor circuit shown in Fig. 3 , the controlling input power can be expressed
by:
Pin = VEB IE
This power will be consumed in the EJ. Since the EJ is forward biased, then VEB is of
the order of 0.6 Volt. The controlled output power, which is the power, supplied by the
battery VCB can be written in the form.
Pout = VCB IC
Because the CJ is reverse biased, VCB can have values, which are much greater than
0.6 V but must be smaller than the breakdown voltage of the collector junction.
Figure 3. Common base connection of the transistor.
For effective control and amplification the ratio Pout/pin must be as high as possible.
We can write
Pout  VCB   I C 
=  . 
Pin  VEB   I E 
Since IE = -(IC +IB) , then

 
Pout VCB  IC  VCB  −1 
=  =  
 −( I C + I B )  VEB
(3)
Pin VEB  1+ IB 
 IC 
3
Figure 4. The different current components in a pnp transistor in active operation mode.
The symbols in the figure have the following meanings:
fixed acceptor ions in the transition region.
fixed donor ions in the transition region.
holes.
free electrons.
Recombination of an electron and hole pair.
IPE The injected hole current from the emitter into the base.
InE The injected electron current from the base into emitter.
IVR The recombination current in the neutral base region.
IPC The hole current reaching the collector junction.
ICO The reverse saturation current of the reverse biased collector junction provided
that VCB<- 3 VT.
For fixed value of VCB/VEB, the ratio Pout/pin will increase if (IB/IC) decreases. The
maximum value of Pout/pin will be reached if IB/IC goes to zero.
Thus for a good transistor, the following condition must be satisfied
IB
<< l (4)
IC
i.e. the base current must be much smaller than the collector current and consequently the
collector current will approach the emitter current.
How can we design the transistor to fulfill this requirement? In order to answer this
question, we must determine the relation between the transistor currents and the physical
parameters of the transistor, such as the doping concentration of different layers, the
minority carrier lifetime in each layer, and the width of the base layer. Therefore, we must
study the motion of the mobile charge carriers in each region as we have done in the diode.
4
before developing an exact theory for the transistor, it is worthy to answer the above
question qualitatively making use of the principles previously developed in pn junction. We
shall assume that the drift currents of the minority charges are negligible and low injection
conditions are satisfied.
As the emitter junction is forward biased, holes will be injected from the emitter into
the base. The rate of injection of these holes across the emitter junction is the injection hole
current Ipe. Our study of the pn junction has showed us that when the junction is forward
biased the concentration of the minority carriers, here holes in the base, decreases as the
distance from the transition region edge increases (see Fig. 5). Neglecting the hole drift
current, which is well satisfied at low injection, the injected holes from the emitter move
toward the collector junction by diffusion due to the presence of a concentration gradient.
On their way to the collector junction, some of them recombine with electrons supplied by
the base current as shown in Fig. 4 . The rate of recombination represents the current
component IVr .The rest of the injected holes, which succeed to reach the collector junction
will be swept by the electric field in the collector base transition region, i.e., they will be
collected by the collector junction as the electric field is in the direction so as to aid their
motion to the neutral collector body. The rate of arrival of the injected holes from the emitter
to the collector transition region constitutes the current component Ipc.
As the collector junction is reverse biased with a voltage greater than 3VT, an
additional collector current component which is very small and equal to the reverse
saturation current ICO the collector junction will flow across the collector junction.
The collector current IC is the algebraic sum of the hole current, Ipc, and the reverse
saturation current of collector junction, thus
- IC = Ipc +ICO (5)
We must return now to the emitter junction. Since it is forward biased, an electron
current will be injected also from the base to the emitter. This current component is denoted
by Ine in Fig. 4 .This injected electron current must be supplied by the base current.
We can now express the emitter current as follows,
IE = Ipe + I ne (6)
The base current IB can be written as follows
-IB = (Ivr + Ine) -ICO (7)
4. Definition of Some New Parameters:
Let us now introduce some physical parameters associated with the transistor
operation:
(1) The emitter injection efficiency γ : it is the ratio of the injected current from the
emitter to the total emitter current, i.e.,
5
I pe
γ=
I pe + I ne
1
= (8)
I
1 + ne
I pe
The emitter injection efficiency γ is always smal ler than one. It increases as the ratio
Ine/Ipe decreases. It approaches one when the back injected current from the base Ine is
much smaller than that injected from the emitter into the base Ipe.
(2) The transport factor αT: it is defined as the ratio of the hole current that can reach
the collector or the collected hole current Ipc to the injected hole current from the
emitter Ipe, that is,
I pc I pc
αT = =
I pe I pc + IVr
1 (9)
=
I
1 + vr
I pc
αT increases as the ratio of the lost hole current by recombination, Ivr, to the collected
hole current, Ipc, decreases. αT approaches one when Ivr<< Ipc.
(3) The current amplification factor in common base circuit α: it is defined as the ratio
of the collected hole current Ipc to the total emitter current IE, i.e.,
I pc − I c − I CO
α = = (10)
IE IE
If the collector junction is short circuited, its own current will be zero. Thus (10) reduces
to
− IC
α =
IE VCB = 0
Therefore α is also called the short circuit current amplification factor in common base
circuit.
Equation (10) can be rewritten in the form

 I pe  I pc
α =  . = γ .α T (11)
 I E  I pe
6
Figure 5. Minority & majority carrier distribution in an active pnp transistor.
Notice that we have used a log scale.
The symbols in the figure have the following meanings:
peo & neo are the majority and minority carrier concentrations in the emitter at
thermal equilibrium respectively.
pco & nco are the equilibrium carrier density in the collector.
nbo & pbo are that of the base.
pb(o) & pb(w) is the non-equilibrium minority carrier concentration at the base edges of
the EJ & CJ respectively.
Hence, the current amplification factor α is equal to the emitter efficiency, γ , times the
transport factor, α T .
It has been previously mentioned that for good transistor, IC must approach IE. From
equation (10), this is possible only when α approaches one. From eqn. (11), α approaches
one when both the injection efficiency γ and the transport factor αT approach one. This
means that the back injected electron current from the base into emitter and the hole
recombination current in the neutral base region must be much smaller than the injected hole
current from the emitter. This is also clear from Fig. 4 . How can we make Ipe>> Ine? From
the diode theory we can write
I pe
∝ =
(
pb ( o) pbo e EB T − 1
V V
)=
pbo ni2 N b N e
= =
I ne (
ne (o) neo eVEB VT − 1) neo ni2 N e N b
The meanings of the new symbols are given in the inset of figures 4 and 5 .
7
In summary we can conclude that for γ ≅ 1 we must make Ne >> N b. That is why the
emitter doping concentration must be much higher than the base concentration for practical
transistors.
The order of magnitudes of the doping concentration in the emitter and base
respectively are Ne = 1018 to 1021 /cm3 and Nb = l0l5 to 10l7 /cm3 .
We have also learnt from the PN junction study that the injected carriers from one
side to the other side of the junction diffuse on the average a distance equal to the mean
diffusion length before they recombine. Applying this fact on the holes injected from the
emitter of a transistor, in order to make the recombination current in the neutral base region
very small, the injected holes from the emitter must diffuse a much smaller distance than the
diffusion length to arrive the collector junction. As a result the neutral base width wb must
be smaller than the diffusion length Lp of the holes in the base region, that is,
Wb << Lp = Dp τ p . (12)
Wb ranges from ½ µm to 100 µm and the diffusion length Lp ranges from 10 µm to 500 µm.
The smaller values for Wb and Lp are for high frequency transistors while the upper values
hold for low frequency power transistors. The diffusion length can be adjusted by
controlling the minority carrier life time τ p.
5. Minority Carrier Distribution in the Base and Approximate expressions for γ ,α

αT and α
According to the law of the junction, the concentrations at the edges (i.e. at x = 0 & x
= wb) of the base region are determined completely by the voltages applied on the emitter
and collector junctions. If recombination of minority charges in the base region is negligible
during their diffusion towards the CJ, the hole current at any point in the base does not
change. Because the minority carriers flow mainly by diffusion at low injection (pb(o) <<
nbo), the slope of the hole distribution must consequently be independent of x. Hence the
hole concentration in the base can be described by a straight line joining the concentrations
at the edges of the base as shown in Fig. 5 . In practical transistors, there is a small
recombination in the base, consequently, the hole concentration at any point is slightly
smaller than that of the straight line, as shown in Fig. 5 . however, a straight line distribution
of the minority carriers in the base is quite adequate to describe the behavior of all practical
types of transistors.
Since the EJ is forward biased then pb(o)>> pbo, and since the CJ is reverse biased,
then pb(w) << pbo. The hole concentration decreases continuously from pb(o) to pb(w) as
shown in Fig. 5 . It decreases linearly from pb(o) to pb(w) if the recombination is negligible.
Notice that we have assumed that neutrality holds at every point outside the transition region
After some mathematical analysis one can prove that the injected hole current in the
base
 q Dp pbo q wb pbo  V V
J pe = 
 w
+
2τ 
( )
 e EB T − 1 (13)
b p
8
This means that the collector hole current is controlled completely by the emitter base
voltage in this case also. In fact this is the transistor effect.
An expression for αT can also be proven to be
αT = 1 for wb << LP (14)

w2
1 + b2
2 Lp
Substituting wb = 3 µm and LP=30 µm in eqn (14) we get a value of 0.995 for the transport
factor. It must be remembered that (14) holds only when the base width is much smaller than
the diffusion length of the minority carriers in the base region.
In order to obtain an expression for the emitter efficiency γ , we must determine
firstly the injected electron current from the base Jne into the emitter. This can be found to be
qDn ∆ ne (0 ) qDn neo VEB VT
J ne =
Lne
=
Lne
e( −1 ) (15)
Substituting eqns (13) and (15) in (8) we get

1
γ = (16)
Dn wb N b
1+ . .
Dp Lne N e
With Dn = 3 Dp = 20 cm2/s, wb = 3 µm Lne = 10 µm, Nb = 1016/cm3 and Ne = 5 × 1018/cm for

a practical transistor, the emitter efficiency amounts to 0.988.
In conclusion the transport factor increases as the ratio of the base width to the
diffusion length of the minority charge carriers in the base is reduced. Also we can easily see
from the expression of γ , that the injection efficiency can be increased appreciably when the
doping concentration in the emitter is made higher than the doping concentration in the base.
The amplification factor α can be found by multiplying αT and γ:
 
  
  
1 1
α = γ .α T =  
2
(17)
 Dn wb N b     
 1 + D . L . N   1 + 1 2  wb  
 e 
p n
  Lp  
For this highly idealized theory, the current amplification factor is independent of the
transistor currents. practically, the current amplification factor depends on the transistor
current. The maximum measured amplification factor coincides with the value calculated
from eqn. (17).
A typical shape of measured α as a function of the collector current is shown in Fig. 6
. At low collector currents α is smaller than αmax due to the recombination in the emitter
transition region. At high collector currents, the low injection condition does not hold. As a
consequence, α will decrease with the collector current. The excess majority carriers
increase due to the injection of minority carriers at high currents because the neutrality
9
condition must be satisfied. Majority carriers increase resulting from injection has the same
effect of raising the doping concentration in the base. It follows from eqn.(16) that the
current amplification factor will be reduced as shown in Fig. 6 at high current.
Figure 6. Typical curve of α as a function. of Ic.
6. Shockley Theory
Exact Expressions for γ, αT and α
If Wb is not much smaller than the diffusion length of the minority carriers in the
base, we must solve the diffusion equation with the boundary conditions at x = 0 & x = wb.
It must be said that the following assumptions must hold:
(i) low injection condition.
(ii) the minority carriers flow mainly by diffusion.
(iii) Recombination and generation in the space charge regions are negligible
(iv) One-dimensional model with we ,wC > Lne ,Lnc respectively.
Taking these assumption one can determine the exact expression for the transport
factor αT given by
1
αT = (18)
w
cosh b
Lp
If wb < Lp, which is the case for practical transistors, eqn (18) reduces to
1
αT = 2
1w 
1+  b 
2  Lp 
This expression coincides with equation (14).
10
A more general expression for the injection efficiency γ can also be derived to give
1 1
γ = = (19)
I ne w
1+ L p tanh b
I pe D Lp N b
1+ n . .
Dp Ln Ne
Wb
Instead of wb, in eqn (16) we have the term Lp tanh in this expression for γ. For practical
Lp
transistors, where wb < Lp, eqn (19) reduces to eqn (16), since Lp.tanh(wb/Lp) ≅ Lp . (wb/Lp) =
wb , if wb < Lp.
7. The Ebers-Moll Model
In order to develop the Ebers-Moll model let us

determine:
(A) The terminal currents for VCB = 0
and VEB ≠ 0 and
(B) The terminal currents for VCB ≠ 0
and VEB = 0
(A) VEB ≠ 0. The emitter current can be

determined under these biasing
conditions to give
JE = Jpe + Jne
 
 
=  q Dn neo qDp pbo  VEB VT
 Ln
+
L p tanh wb 
e −1 ( )
 L p 

The above relation is normally written in the
reduced form Figure 8. Minority carrier distribution
( )
to develop the Ebers -Moll model
J E( A ) = J ES eVEB VT − 1 (20)
where JES is the reverse saturation current of the emitter junction with short circuited CJ.
The collector current is caused by the collected hole current only i.e.
( )
− J C( A ) = the collector current = J pc = α F J E (21)
where αF is the forward current amplification factor.

The base current can be determined from eqn (20) and eqn (21)
− J B( A) = (1 − α F ) J E( A) (22)
If VEB and the internal physical parameters are known, all currents can be determined.
11
(B) What is the situation when we apply voltage on the collector junction while
keeping the emitter junction short circuited?
The collector will function as an emitter and the emitter will function as a collector,
i.e. the functions of emitter and collector are reversed. Hence this mode of operation is
called the inverse mode as shown in Fig. 8 case B.
As the CJ is forward biased VCB > 0 and the EJ is short circuit VEB = 0,by analogy to
case A we can write the following expressions for the transistor currents:
The collector current = J C( B ) = J CS (eV CB VT
)
−1 (23)
where JCS is the reverse saturation current of the CJ with VEB = 0, The collected emitter
current
− J E( B ) = α I J C( B ) = α I J CS ( eV V − 1)
EB T
(24)
where α I is the inverse current amplification factor with VEB = 0, and
( )
The base current = − J B( B ) = (1 − α I ) J CB (25)
The General Case : VCB ≠ 0 & VEB ≠ 0

If we superpose the voltages and currents in both cases A & B, we get the relation
between the terminal voltages as the independent parameters and the terminal currents as the
dependent parameters.
Figure 9. Ebers-Moll circuit model of a pnp transistor.( two-diode model)

DE is the emitter pn junction.
DC is the collector pn junction.
IDE and IDC are the currents in DE and DC respectively.
It follows that the total collector current

JC = Injected current density + collected current density
( )
JC = J C( B ) + − J C( A ) = J CS (eVCB VT
−1 ) (
−α F J ES eVCB VT − 1 ) (26)
12
The total emitter current
( ) ( )
J E = J E( A ) injected + J C( B ) collected = J ES eVCB VT − 1 − α I J CS eVCB VT − 1 (27)
and the base current ( − J B ) = J C + J E

These two important equations (26) and (27) are called the Ebers and Moll model
They describe totally the I-V characteristics of ideal or intrinsic transistors. Any special case
can be derived easily from these two equations. They can be represented by the electric
circuit shown in Fig. 9.
Figure 9a. Circuit symbols of the bipolar transistors.
8. Graphical Representation of I-V Characteristics of a pnp Transistor

The circuit symbols of the npn and pnp transistor are shown in Fig. 9 As the transistor
is a three electrode device, we can use any of the three electrodes as a common terminal for
the applied sources and measuring voltmeters.
Therefore, there are three possible circuit configurations, the common base, the
common emitter and the common collector, as shown in Figs. 10 , 11 and 12 respectively.
Figure 10. Common base circuit

IC = f(VCB,IE)
In order to compare the three connections, let us introduce and calculate the power control
ratio pout /pin for each connection.
Common Base Circuit
pin = VEB . I E
pout = VCB . I C
pout  VCB  I C
= .
pin  VEB  I E
13
When the CJ is reverse biased VCB >> VEB ,
and for good transistors IC ≅ IE ,then
pout VCB VCB
= = >> 1 ,
pin VEB VEB
Hence voltage amplification only exists.
Figure 11. Common

emitter circuit,
IC = f(VEC,IB)
Common Emitter Circuit

pout VCE I C VCB + VBE IC
= . = .
pin VEB I B VBE I E − IC
V   α   VCB 
=  CB + 1   =  .( β )
 VBE   1 − α   VBE 
α
With β = >> 1 and VCE >> VBE , then both voltage and current gain exist.
1−α
Figure 12. Common collector

circuit IE = f(VEC, IB)
Common Collector Circuit

pout VEC . I E
=
pin VEB . I B
VEC ≅ VBC as VBE << VBC
14
 IC + I B   I 
  =  1 + C  = 1 + β >> 1
 IB   IB 
pout
= 1+ β ,
pin
Hence only current gain exist.

The most used circuit configuration for the amplification and switching is the
common emitter circuit, since it produces the highest power control ratio among all possible
circuit connections of the transistor, these are given in figures 10 , 11 and 12 . The common
base circuit can amplify voltages only while the common collector amplifies current only.
8.1. Static Characteristics of the Transistor in Common Base Circuit

For the sake of an easier circuit analysis, the most interest lies on the output or
collector characteristics for different discrete values of the controlling emitter current. That
is
 
I C = fC  VCB , IE 
 { { 
 Continuous parameter Varied in steps 
In order to get the functional relationship between IC and VCB for certain IE, we must
eliminate VEB from the Ebers and Moll equations, (26) & (27). This gives
J C = −α F J E + J CBO  e − 1

V
CB / VT
(28)
with J CBO = (1 − α I α F ) J CS
Equation (28) describes the static characteristics of a pnp transistor in common-base circuit
shown in Fig. 13.
It is clear from the characteristic equation. that the (I-V) collector characteristic of the
transistor is the I-V characteristic of the CJ (the term JCBO ( eV V − 1 )) superimposed on the
CB T
collected hole current from the emitter junction (the term - α F JE)
If JE = 0, i.e. open circuited emitter the collector current is just the current of the
collector junction. Therefore, when VCB < 0 and equal to -3VT, JC = JCBO = JCO ,that is the
current which passes through the collector is only the reverse saturation current of this
junction JCO. As this current is very small (in the order of nA), the collector circuit can be
considered as an off switch and the region under the curve IE = 0 and VCB < 0 is called the
off region .At any positive emitter current, say 3 IEl, the transistor will be capable of
amplification so long as the collector junction is reverse biased i.e. VCB < 0. Thus this
region is called the active region If VCB is made positive, the collector junction will be
forward biased and the collector current begins to decrease, the transistor is not capable of
amplification. This state is called the saturated state of the transistor as the base region is
flooded with minority carriers as shown in the bottom of Fig. 8 .
Notice that if the transistor is saturated,
15
pout VCB J C
= . , VCB ≤ VEB and J C < J E .
pin VEB J E
Thus the output power is smaller than the input power. This means no amplification.
Figure 13. Current voltage characteristics of a transistor in the common base connection.
8.2. I-V Characteristic of a Transistor in a Common Emitter Circuit

This characteristic is normally given in the data sheets of the transistors We are now
interested to relate the collector current IC with collector to emitter voltage VCE and the base
current IB. That is
 
I C = f  VCE , I{B 
 { 
 Continuous in steps 
Although the Ebers-Moll eqns. are derived for the common base configuration, We can get
from them
J C = β F J B + J CEO ( eV V . e −V V − 1) ,
CB T
(29)
BE T
αF  J 
with β= >> 1, and J CEO =  CO  > J CO .
1−αF 1−αF 
16
The new parameter βF is called the current amplification factor in the emitter circuit.
It is much greater than unity. JCBO is the collector to emitter current with open base JB = 0 as
it is clear form eqn (29) By representing eqn. (29) graphically we get the collector
characteristics in common emitter circuit shown in fig. 14 .
Figure 14. Collector I-V characteristics of a transistor in the common emitter configuration.
Now, we shall explain the shape of the current-voltage characteristic shown in fig.
14. for constant base current, say 3 IBl, and large negative values of VCE, the emitter junction
will be forward biased while the CJ is reverse biased, hence
J C = β F ( − J B ) − I CEO
The minus sign is introduced because the base current is forced to flow out of the
base lead . JC is independent of VCE, so long as VCB < -3 VT. Reducing VCE more, the CJ
voltage VCB will attain the value zero, consequently,
J C = + β F ( − J B ) , for VCB = 0 , (VCE = VBE )
This is the boundary between the active and saturation region, which is represented
by the dashed curve in Fig. 14 . If we decrease VCE further, the CJ will be forward biased. It
begins to inject holes in the base. Consequently, the net collector current will decrease and
reaches ultimately to zero. In this case
1424 3 1442443
( )
J C = β F (− J B ) + J CEO e VCB VT − 1 < β F J B
− Ve . value + Ve . value
It is observed experimentally that the collector current depends slightly on VCE in the
active region as shown in Fig. 14 by the solid lines. This can be explained easily as follows:
When VCE increases, VCB increases also, and consequently, the neutral base width
decreases because of the widening of collector transition region as demonstrated in Fig. 15 .
In consequence the hole gradient increases and consequently the fraction of the holes which
reach the collector. This effect is called "The Early effect".
17
Figure 15. The collector
current increases due to
the increase in the reverse
bias voltage of the
CJ.(Early Effect).
8.3. The Input Characteristic

(i) Common Base Connection
It is required to determine the functional relationship
IE = f (VBE, VCB)
It is clear that eqn (27) describes this characteristic. We can deduce easily that for a
fixed value of VCB, the emitter current increases exponentially with VBE. It is more or less a
diode characteristic as shown in fig. 16. At high emitter current, the curves flatten and
deviate from that of ideal transistor because of the ohmic voltage drops on the neutral
regions of the transistor. The different body resistances of a real transistor is shown in fig.
16a . Expressed in an other way, the terminal voltages will be dropped partly on the junction
and on the ohmic resistances of the neutral regions of the transistor. these resistances must
be taken into consideration in the Ebers -Moll model as shown in Fig. 9a . On the other side,
the slight increase of the emitter current with increasing reverse bias of the CJ is due to
"Early effect".
Figure 16. Input characteristic for common-base.
18
Fig. 16a Construction of a real transistor RE, RB and RC are the emitter, the base
and the collector body resistances respectively.
Figure. 9a. Ebers-Moll model for a real transistor.
(ii) Common Emitter Connection

By adding eqns (26),and (27), the input characteristic of the transistor in the common
emitter configuration can be obtained i.e.,
(
− J B = (1 − α F ) J ES e −VBE VT
) (
− 1 +(1 − α I ) J CS eVCE VT
e −VBE VT
)
−1
This characteristic is represented in Fig. 17 for different values of collector to emitter

voltage such that the collector junction is reverse biased. The effects of the ohmic voltage
drops and the widening of the collector space charge region are also shown in the figure .As
VCE increases and the base current becomes smaller.
19
Figure. 17. Input
characteristic for
common emitter
with VCEl > VCE2
9. Voltage Ratings of the Transistor

If we increase the reverse bias voltage of the CJ, the transition region spreads in the
base. If the base width is small, the edge of the transition region of the CJ can reach the edge
of the emitter transition region before the avalanche breakdown condition in the CJ is
fulfilled. This situation is shown in Fig. 18a.
The voltage at which this happens is called the punch-through voltage, Vpt. Under
this condition the neutral base width goes to zero and the hole concentration gradient
becomes very big. As a result a big hole current flows from the emitter to the collector as
shown in Fig. 18b. This current must be limited by the external circuit otherwise the electric
power dissipated in the transistor will damage it. Now a simple relation can be derived easily
for the punch-through voltage as follows:
Figure 18a. Punch-through condition in a transistor.

The collector transition region reaches the emitter junction .
20
qN D w`b
Emax = ,
εw
1
V pt = E max w`b
2
and it follows that
qN D `
V pt = 1 wb
ε
2
where W`b is the metallurgical width of the base

Figure 18b. At punch-through the collector
region.
current increases abruptly.
On the other side, an avalanche breakdown of the collector junction can occur before
punch-through, if the breakdown voltage is smaller than the punch-through voltage. It has
been previously proved that
ε
VBr = 1
2 E cr2
qN D
10. Transit Time

The transit time of the minority charge carriers in the base sets an upper limit for
usefulness of the transistor as an amplifier and also for its switching speed. Let us now
derive an expression for this time. assume that the base width wb is much smaller than the
diffusion length of the minority carriers in the base region. This condition is well satisfied
practically for all types of transistors as explained in Sec. 3 .One can easily deduce that the
transit time of the minority charge carriers is given by
wb2
T= (30)
2 Dp
It is clear from this equation that the transit time of the minority carriers in the neutral
base region can be decreased appreciably by reducing the base width. As a result the high
frequency and switching transistors must have the smallest base width among the different
types of transistors. We can deduce easily from eqn.(30) that upon reducing the transit time
of the transistor, its voltage ratings will be made smaller. Thus it is impossible to realize a
high power transistor for very high frequency applications. This problem could be partially
solved by the invention of drift transistors in which the minority carriers move mainly under
the influence of an electric field in the base region. Also materials with much higher
mobilities such as GAS are also used for the fabrication of very high frequency transistor.
21
11. The Transistor As A Circuit Element
The transistor is an important component in electronic circuits because, as we saw in

the preceding sections it can perform the two basic functions of amplification and switching.
In order to perform these functions, the transistor must be correctly biased at certain
dc operating conditions. So, in this section we shall pay attention to transistor biasing and
how we can determine the dc operating conditions of a transistor in dc circuits. There are
three possible circuit configurations of the transistor:
I. Common base.
II. Common emitter.
III. Common collector.
The most used transistor configuration is the common emitter as it leads to the most
efficient control of the transistor. Basically the transistor is biased with two different voltage
sources as shown in Fig. 19. The BE junction is forward biased while the CB junction is
reverse biased.
The transistor is in its active state. The resistors, RB and RC are used to limit the base
and collector currents IB and IC respectively. The designation for the two power supplies, for
the base VBB, and for the collector VCC are according to the IEEE nomenclature.
It is required now to analyze this circuit to determine the currents IB, IC and the
voltages VCE and VBE.
In principle, the Kirchhoff voltage and current laws are used together with the
terminal properties of the device in the circuit.
IC
The procedure is to write down the loop RC
equations for the input loop 1 passing through the RB
VCC
emitter junction, and the output loop 2 passing IB

2
through the collector to emitter as shown in Fig.
VCE
19. Therefore, we get: VBB 1 VBE
VBB = I B RB + VBE (31)

VCC = I C RC + VCE (32) Figure 19. Two battery transistor biasing.
According to the circuit theory, other loops do not give any new equations. As we
have four unknowns, we need two other independent equations. These are the terminal
relationships of the device that can be expressed in the functional form as follows:
I B = FB ( V BE , VCE ) (33)
which represents the input characteristics of the transistor, and
I C = FC ( I B , VCE ) (34)
Which represents the collector characteristics of the transistor. We know that Eq. 33
and Eq. 34 are nonlinear. Therefore, there are different methods to solve these equations:
22
I. The numerical method by using digital VCE > 0.6V
computers.
IB
II. The graphical solution.
III. Approximate analytical methods. (a) (b)
IV. Combining (II) and (III).
VBE
In the approximate analytical method the VBEO VBEa
nonlinear terminal I-V characteristics are peicewise
linearized resulting in the so-called linear model of the Figure 20. The input characteristics
device. piece wise linearized.
The actual input characteristics IB=FB(VBE,VCE) of the transistor are approximated by
the broken line (a) as shown in Fig. 20.
The equivalent circuit represented by this broken line is VBEγγ rBE
IB
shown in Fig. 21 where the cut in voltage VBEγ required to
B E
enter the forward biased junction into conduction, rBE the large
signal dynamic resistance of the base emitter junction. The Figure 21. Equivalent circuit
of the EJ.
resistor rBE is in series with the back battery VBEγ.
It must be mentioned that this peicewise linear model of the i/p bas-emitter junction
is similar to that of a p-n junction. A more approximate model for the base characteristics is
that corresponding to the vertical line b in Fig. 18 with rBE = 0 and VBEγγ = VBEa . This means
that a forward biased B-E junction can be substituted by a nearly constant drop VBEa.
VBEa depends on the semiconductor material of the transistor. It amounts to about

0.6V for Silicon transistor. When the transistor is in the saturation it needs more base
current, and hence its BE voltage VBES, becomes larger than VBEa. VBES amounts to about
0.7V for Si transistors and 0.4V for Ge transistors.
IC III II IB5
For any other transistor type you can find the
IB4
parameters of the linear model using the same procedure.
IB3
The collector characteristics IC = fC (IB ,VCE) can be
IB2
also piecewise linearized as shown in Fig. 22 to get the
linear circuit model representing the transistor between IB1
the collector and emitter terminals. In the active mode of
operation the collector current can be expressed as VCE
a linear function of IB and VCE as follows: Figure 22. The output

characteristics with piece wise
IC = βIB + rCEa VCE + ICBO (35)
linearization.
Where β is the common emitter current gain and
rCEa is the inverse of the slope of the straight line in the active region. ICBO is the collector-
emitter current with the base open circuit. For many transistor circuits this current is much
smaller than β IB and can be neglected. Also gCEa VCE can be neglected compared toβ β IB.
Therefore Eq. 5 approximates to a more approximate linear model:
23
IC ≅ β IB (36)
According to Eq. 36 the transistor between C and E can be modeled with a pure
dependent current source β IB as shown in Fig. 23.
In the saturation mode of operation the collector characteristics can be approximated
by the straight line II; whose equation can be written as:
VCE = VCE sat + I C rCE sat
VCE sat is the intercept of line II with the VCE axes, and rCE sat is the inverse slope of
the same line. The above equation is represented by the equivalent circuit shown in Fig. 23.
But for the sake of more approximate analysis, one can consider that the voltage drop
between the collector and the emitter VCEsat is about 0.1 to 0.3V for Si transistors which
means that line II is substituted by suitable vertical line III.
In summary to analyze transistor dc circuits quickly we can use the following
approximate relationships. For active transistors:
VBE = VBEa = fixed voltage = 0.6 - 0.7 for Si and IC = β IB. C
VCESat rCESat
E
And for saturated transistors: IC
VCE sat = 0.1 - 0.3V and Equivalent circuit of

collector to emitter at
VBE sat = 0.7 - 0.8V for Si.
saturation.
Example:
Calculate IC and VCE for the Si transistor circuit shown in Fig. 19 given that
Ω, β = 100 and VCC = 10V, for RC = 1k and RC = 20k.
VBB = 1.5V, RB = 100kΩ
Solution:
C
Assuming active transistor: ICBO
VBB − VBE 15
. − 0.6 βIB
IB = = = 9 µΑ rCEa
RB 100
β IB = 900 µ A
IC =β E
if RC = 1k, then Figure 23. The active equivalent

circuit from collector to emitter.
VCE = VCC − IC RC = 10 − 0.9 × 1k = 9.1V
Since VCE > 0.1V , then the transistor is active.
Ω , then
If RC = 20 kΩ
VCE = 10 −18 = − 8V.
Negative VCE means that the transistor is saturated, and the collector current becomes:
VCC − VCESat 10 − 0 .1
IC = = = 0 .495 mA
RC 20
24
Graphical Solutions
To solve the basic transistor circuit in Fig. 19 graphically, the input and output
collector characteristics must be given in
graphical form as shown in Fig. 24. V CC
Firstly we determine IB and VBE by RE

drawing line I representing Eq. 31 on the input II IB5
characteristics. Qi is the required solution. Then IB4
IB3
we draw the load line II representing Eq. 32 on Qt Q IB2
the output collector characteristics. Plot the IB IB1
dynamic transfer current characteristics which VBB VCE VCC VCE
RB
represents the collector current as a function of I
the base current for all points of the load line.
Qi VBB
Since the base current is known form Qi, the VBE
collector current can be determined from the
Figure 24. Graphical solution of the
dynamic transfer characteristics and consequently
transistor operating point.
VCE from the load line. This can be done easily
by drawing vertical line from Qi, the input operating point, to meet the dynamic transfer
curve in Qt followed by a horizontal line meeting the load line in output operating point Q as
shown in Fig. 24 by the dashed line. “Graphical solution” methods have limited applications
for more complicated transistor circuits and numerical solution methods are preferred.
Combined Piecewise Linear Model And Graphical Solution:

If the input characteristic is not given, one can determine the base current using
piecewise linear model Eq. 33 where the forward biased input junction is replaced by
a resistance in series with a back battery equals the cut in voltage VBEa. After drawing the
load line on the collector characteristics, one can locate the operating point, since IB in now
known.
The Universal Biasing Circuit Of A Transistor Amplifier:

The universal biasing circuit of a transistor is shown Fig. 25. A single power supply
is used instead of two power supplies in the basic circuit of Fig. 19. In order to forward bias
the emitter junction, the potential divider R2 and R1 is used.
The emitter self bias resistance RE is used to make the collector current less sensitive
to temperature variations. It is said that RE stabilizes the operating point. One can
understand the effect of RE as follows:
25
If IC is increased because of a temperature rise the emitter
+VCC
current increases accordingly. For hard potential divider such that VB
is nearly constant VBE will be reduced because of the higher emitter RC
R2
potential. As VBE decreases, the collector current will be reduced
IC
returning again to its initial value before the rise in the temperature VB IB
has been occurred.
Using Thevinen’s theorem one can reduce this circuit to a IE
R1
circuit similar to the basic circuit in Fig. 19. But with: RE
VCC R1 R1 R2
V BB = and R B =
R1 + R2 R1 + R2
Figure 25. The
The input loop equation can be written as: universal biasing circuit
of the transistor.
V BB = I B R B + I E RE (37)
Substituting IE=IC+IB in Eq. 37 and
considering that VBEa ≅ constant one gets: +VCC
'
V BB = V BB − V BEa = I B ( R B + RE ) + I C RE (38) R2 RC
C2
The output loop equation is: I0
C1
Ii
VCC = VCE + IC ( RE + RC ) + IB RE (39)
RS
Normally IBRE is negligible in comparison R1 RE
RL V0
Vi
to the other terms; hence: CE
vS
VCC = VCE + IC ( RE + RC ) (40)
Which is the load line equation for
Figure 27. The common emitter transistor circuit.
self bias transistor circuit. The load line has
VCC
the slope 1/( RE + RC ) instead of 1/RC for V'BB
IC
RC + R E
the basic circuit. Representing Eq. 40 RE
Ia
results in the load line IIa in Fig. 26 while Qt
Eq. 38 results in the bias curve Ia on the Q
output collector characteristics. The IB IIa

operating point Q is the interception point '
V BB VCC VCE
of the load line with the bias curve. As RB + R E
shown in Fig. 26, the bias line can also be
Qi VBE
represented on the transfer characteristics
which is easier to draw than the bias curve Figure 26. Graphical solution of the
in the output characteristics. One can check universal biasing circuit.
the value of VBEa by projecting the
operating point Qt on the input characteristics as shown in Fig. 26. VBEa must be found
around 0.65V.
The analytical solution of this circuit can be carried out by solving eqns 38 and 40
together with the piece wise linear equations of the transistor output characteristics.
26
The Transistor Amplifier Circuit:
The common emitter amplifier circuit is shown in Fig. 27. The signal to be amplified
is applied to the input of the amplifier via a coupling capacitor C1 which prevents the direct
current from the signal source VS. The useful load RL is connected between the collector and
ground through an another dc blocking condenser C2.
A universal biasing circuit is utilized to adjust the dc operating point of the transistor.
It is required to determine the amplifier characteristics. These are the voltage gain AV, the
current gain Ai, the power gain AP, the input impedance Zi and the output impedance Z0.
They are defined by:
V0
The voltage gain AV =
VS (41)
I
The current gain Ai = 0
Ii (42)
P0
The power gain AP =
Pi (43)
Vi
The input impedance Z i =
Ii (44)
V0
The output impedance Z 0 = vs = 0 (45)
I0
where Vi is the input voltage, V0 the output voltage, Ii the input current and I0 the output
current of the signal.
Before starting our analysis of the amplifier circuit let us classify the amplifiers. The
first classification is based on the signal level in the amplifier where one differentiate
between the small signal and large signal amplifiers. The second classification is according
to the dc operating point. One recognizes three classes:
• Class A where the operating point lies in the middle of the load line.
• Class B where the operating point lies on the edge of transistor cutoff.
• Class C where the operating point lies in the cutoff region of the transistor
characteristic field.
Class B and C are large signal amplifiers. Amplifiers also are classified according to
their operating frequencies. There are audio, video and radio frequency amplifiers. There are
also linear and nonlinear amplifiers.
We shall confine our study to the class A, linear amplifier with small signal. There
are different methods to analyze the amplifier circuit:
(i) The graphical solution.
(ii) The small signal equivalent circuits, and
(iii)The numerical method using digital computer.
27
(I) The Graphical Analysis:
The dc operating point is IC
determined in the previous section. ac dynamic transfer curve
Assume that RC, RE, R2 and R1 are VCC

dc dynamic transfer curve R +R
selected such that the operating point C E
lies midway on the dc load line as Icm

Q Q
shown in Fig. 28. t
Since the ac resistance of the

output loop is different from the dc IB VCC VCE
resistance, the ac load line will not Vbem
coincide with the dc load line. The Vcem
t Q t
emitter bias resistance RE will be by- Vsm
passed by CE, and C2 will be short t
circuit. Therefore, the total ac resistance input ac load line
slope =1/RS Ibm
Rac between the collector and emitter t VS
can be written as: Figure 28. The dc operating point on the output, the
RC . RL transfer and input characteristics. The different
Rac = ≡ R'L (46) voltage and current waveforms.
RC + RL
The ac load line has a resistance R'L and must pass through the dc operating point Q
as shown in Fig. 28.
The ac load line of the input has an ac resistance approximately equals RS according
to the reduced input circuits of Fig. 29 where C1 and CE are short circuit while R1 in parallel
with R2 is shunted by the practically much lower ac resistance of the base emitter junction.
The input ac load line is drawn RS C1 B
on the input characteristics in Fig. 28.
RS
Assuming that VS changes sinusoidally
R2 R1 CE
as shown in Fig. 28 the ac load line RE
VS VS
swings back and forth without changing
slope such that the maximum excursion
at the VBE’ axis amounts to Vsm. The Figure 29. The ac input circuit.
intersection points with the VBE curve
are the required base currents and base emitter voltages at different time instants of the input
signal. Consequently, one gets the collector current ic(t) waveform by directly projecting the
input points on the ac dynamic transfer curve ic= f (it) at the ac load line. Then one
determines vCE(t) shown in Fig. 28 by further projecting the transfer points on the ac load
line. The resulting current and voltage waveforms are nearly sinusoidal thanks to small VS
and the linearity of the different characteristic curves in the neighborhood of the operating
point.
Now one can calculate the different quantities characterizing the amplifier by
substituting
28
RC
VS ≡ Vsm , V0 ≡ Vcem , I 0 = I cm , Ii ≡ Ibm and Vi = Vbem.
RC + R L
It is important to notice that the input and output voltage are antiphase. This is
because as the input voltage increases the collector current increases the voltage drop on RL
and decreases the voltage on the transistor for fixed VCC.
Because of the nonlinear input and transfer characteristics, as Vsm is raised the
distortion in the current and voltage waveforms increases. Ultimately, by inspecting the ac
load line and the transfer curve one can see that the positive output voltage half wave will be
clipped first if Icm ≥ Ic while the negative half will be clipped if I cm ≥ (I ∗C − I C ) . The positive
trough clipping is due to that the transistor gets off at that portion of time while the transistor
becomes saturated during the negative trough clipping.
As special cases, one can assume that RS = 0 where the input signal source is a pure
voltage source or RS = ∞ , where the signal source is a pure current source. In case of
constant voltage source the input ac load line will be vertical while it will be horizontal for
the current source.
(Ii) The Small Signal Equivalent Circuit:

It is clear from the foregoing study that the graphical solution method is suitable for
low frequency small and large signals. If the signal is small, one can use the small signal
models of the active device. The small signal models are simply the small signal equivalent
circuits of the device containing conventional circuit elements. The circuit elements are
termed the parameters of the equivalent circuit.
Since the transistor input characteristics is rb’c
that of a diode, one can apply the small signal
rb’b
equivalent circuit of the diode developed B B’
previously on the base- emitter junction of the Cb’c
transistor as shown in Fig 30. rb’e
Vb’e Cb’e rce
-
the resistance rb b is the base spreading Ib’e gmVb’e
resistance, rb’e is the dynamic resistance of the
base- emitter junction and Cb’e is its capacitance. E
Figure 30. The hybrid −π equivalent circuit of

Since I c = f ( I B ,VCE ) (47) a bipolar transistor.
Then a total change in IC can be obtained
by differentiating Eq. 47 partially:
∂ IC ∂ IC
dI c = dI B + dVCE
∂ IB ∂ VCE (48)
∂ IC ∂ IC 1
Substituting for small signal operation dIc=ic, dIB = ib-e , dVCE =Vce, β = and =
∂ IB ∂ VCE rce
one gets:
29
Vce
ic = β ibe +
rce (49)
Where β is the small signal emitter current amplification factor and rce is the small
signal collector emitter resistance with base ac open circuit.
The definition of β and rce drives directly from Eqns. 48 and 49 can be represented by
the equivalent circuit shown in Fig. 30. The current source accounts for the transistor effect.
One has to include the equivalent circuit of the collector base junction between the terminal
B’ and C in Fig. 30. As any diode equivalent circuit it comprises a resistance r b’c and
a capacitance Cb’c. With reference to Fig. 30:
Vb− e = rb− e . ib− e
(50)
Then the current source:
β ib− e = β Vb − e / rb− e = gmVb− e
(51)
β
with gm = (52)
rb' e
where gm is the transfer conductance which is basically defined by:

∂ IC
gm = (53)
∂ V BE
The small signal equivalent circuit of Fig. 30 is termed the hybrid−π model of the
bipolar transistor. The parameters of this model depends on the dc operating condition of the
transistor. They are to large extent independent of frequency.
V BE
Since I C ≅ α F I ES e VT
(54)
for active transistor, it follows that gm after Eq. 53 is given by:
IC
gm =
VT (55)
where VT is the thermal voltage. The other parameters follow directly those of diode
discussed previously, and therefore no need to discuss their dependence on the operating
conditions again.
Lead inductances and neutral collector and emitter region resistances can be added to
the above circuit to make it suitable for very high frequency applications.
This equivalent circuit is based on physical reasoning. There are circuit models which
formally describes the electrical performance of the device. In this black box representation
of the active device one considers it a general 2 port network. The power of this approach
lies on the complete measurability of circuit parameters in contrary to the physical model.
According to the four terminal notations, one can use the h-, z-, y- and the s- parameters.
The operating frequency gives priority to certain parameters groups. At low frequency
applications the h-parameter are commonly used.
30
The transistor and its small signal Ib IC
hfeIb
equivalent h-model is shown in Fig. 31. The C C
transistor signal currents and voltages are hie 1/hoe B
related by: Vbe Vce
hreVce E E
Vbe = hie I b + hreVce (56)
E
I c = hfe I b + hoeVce
(57) Figure 31. The transistor and its small signal h-
parameters model.
Eq. 56 and Eq. 57 are the definition
equations of the h-parameters:
Vbe
hie = input impedance ≡ Vce = 0 (58)
Ib
Vbe
hre = inverse voltage feed back factor ≡ Ib = 0 (59)
Vce
IC
h fe = the forward current amplification factor ≡ Vce = 0
Ib (60)
IC
hoe = the output admitance ≡ Ib = 0
Vce (61)
These parameters as they defined are directly measurable from the terminals. From
the circuit analysis point of view the hybrid−π model is completely equivalent to the h-
model and their parameters can be interrelated to each others. For practical transistor
operating in the active mode hre is normally very small and can be neglected.
In analyzing our low frequency RS rb′′b Io
B C
small signal amplifier of Fig. 27 we
Ii Ib
use the hybrid−π model neglecting gmVb′′e
all capacitors and rb’c because the VS Vi Vo
collector junction is reverse biased. Vb′′e rce
RB rb′′e RC RL
The final circuit to be analyzed is
shown in Fig. 32.
E
For practical amplifier circuits Figure 32. The small signal low frequency circuit of the CE
RB >> (rb’b + rb’e) and it follows amplifier circuit.
that:
VS
Ib = , and
R S + rb' b + rb' e
(62)
V S rb' e
Vb' e = I b . rb' e =
R S + rb' b + rb' e
(63)
The output voltage V0 can be expressed by:
31
V0 = − gm ( rce RC R L ) Vb' e
R'L rce
= − gm ' V'
R L + rce b e
(64)
where
RL′ = RC RL
Normally RL′ 〈〈 rce and Eq. 64 reduces to:
V0 = − g m R'L Vb' e
(65)
Substituting Eq. 63 in Eq. 65 one gets:
V0 − gm R'L rb' e
AV = =
VS R S + rb' b + rb' e
(66)
The voltage gain is proportional to the transconductance gm and the effective load
resistance R’L.
V0
The output current = I 0 = (67)
RL
I0
The current gain Ai ≡ can be written as:
Ib
Ai ≡
( )
g m . R'L Vb' e rb' e
R L .Vb' e
(68)
=
( )
g m R'L rb' e
RL
Vi
The input impedance = Z i = ≅ rb′b + rb′e (69)
Ii
V0
The output impedance = Z 0 = = rce R C ≈ R C (70)
I0
In order to determine Z0 the input voltage source must be short circuit.
32
Numerical example:
For a transistor amplifier having IC = 10mA, IB = 0.1 mA, β = 100, r b’b = 10Ω
Ω,
I C 10 mA
gm = = = 0 .4 A / V
VT 25 mV ,
VT 25 mV
rb' e = = = 250Ω
Ω
I B 0 .1mA ,
Ω, RC = 1kΩ
and for rce = 500kΩ Ω, RL = 250Ω
Ω, and RS = 50Ω
Ω, one calculates from the above
equations:
0 .4 × 200( 250 ) 0 .4 × 200 × 250
AV = = = 64
50 + ( 10 + 250 ) 310
0 .4 × 200( 260 )
Ai = = 83 .2
250
Z i ≈ 260Ω
Z 0 = 500k 1000 ≈ 1000 Ω
The other basic transistor amplifier circuits, the common base and the common
collector can be treated in the same way and they are left as an exercise for the reader.
33
Amplifiers
The Characteristics Of An Amplifier:
The amplifier is an electronic circuit used to raise the signal level, the
voltage, the current and the power.
The block diagram of an amplifier is shown in Fig.1.1
Fig. 1.1
The amplifier converts the dc power into the ac power. It is generally

characterized by :
• a voltage gain Av = Vo/Vi

• a current gain AI = Io/Ii
Vi
• an input impedance Z i =
Ii
V
• an output impedance Z o = o Vs = o
Io
• A power supply : single power supply, bipolar power supply, regulation and
ripple
(S / N) input
• Noise figure NF = 〉1
(S / N) output
= (S i / N i ) / ( (S o / (N o + N a ))
S No + Na
= i -
So Ni
1  Na 
= • A + 
A  Ni 
 Na   N ai 
NF =  1 +  ≡ 1 + 
 A Ni   Ni 
34
where Nai : the equivalent noise input of the amplifier.
• The dynamic range of the amplifier:
The input voltage range at which the output voltage varies linearly with the
input
• The noise sets as lower limit to the input signal that can be amplified.
Vna : the equivalent input noise voltage of the amplifier.
Vo
Vi
Vna
• The nonlinear distortion of the amplifier

V
HD = H = VRMS 2
− VF2 / VF
VF
2
 VRMS 
HD =   - 1
 VF 
VF : the fundamental voltage, VH : the harmonics voltage.
Po 3rd order intercept point

1-dB compression point
Third Order Po
Minimum input
power is limited
by the equivalent
noise input power Pi
35
• The triple point (the third order intercept)
(f1 , f2) are input to the amplifier, non-linearities cause : second-order
products such as 2 f1 , 2 f2 . f1 + f2 , f1 - f2 and third order products
2 f1 - f 2 2 f 2 - f1
2 fi + f2 , , 2 f 2 + f1 ,
↑ ↑
May fall in the amplifier band width
* Third-order output
(Noise floor) Minimum input power is limited by the equivalent noise input
power
• An amplifier is characterized by a frequency response :
- Audio , Video , rf , IF , microwave
There is no amplifier which can amply all frequencies equally
Audio : 20 c/s - 20k c/s , video 30 → 6 k c/s
rf … IF … ≡ fall in the radio frequency bands
• linear or pulse amplifier
• small signal or power amplifier
• coupling : dc , ac RC
transformer coupled
• dc operating point : A, B, AB, C
• Differential input, differential output, single ended input, differential
• Operational amplifier, transconductance , transimpedance
• Multistage or single stage amplifier
• discrete or inteated
• Bipolar or MOS amplifier, BICMOS
I. The Single Stage Basic Amplifier (Discrete)
• An amplifier must contain an amplifying device :

- Bipolar transistors npn
pnp
- MOS transistors p
n
- JFET’s p
n
- * Varactor diodes (parameteric amplifier)
* MESFETs
* HEMT
* Junn diode
* Impatt diode
* Microwave tubes
* Tunnel diode
36
The Basic Amplifier Circuits
CE CB CC
CS CG CD
Voltage and Voltage Current

current amplifiers amplifiers amplifiers
1. The CE class A , small signal
The biasing:
IC
I1
IB
I2 IE
IC Pmax
VCC
RC + RE
Class A
ICQ Operating
Point
IB VCE Q VCC VCE
37
DC Analysis : graphical , analytical , simulators
VCC = I C R C + I E R E + VCE (1)
I 2 ≈ 10 I B , R 1 & R 2 builds a hard
VCC R 1
p. divider : VB ≈ = VBE + I E R E (2)
R1 + R 2
from eqn.(2) we get IE since VBE = 0.7 V for Si Tr.
RE : is taken such that VE 10% of VCC = 0.1 VCC

 B + 1
IE =   I we can get IC , substitute in (1) to get VCE = VCEQ is
 B  C
normally put in the middle of the loadline
Normally we take VBE = 0.6 V, IC = β IB for active transistor
AC Analysis
The AC analysis can be carried out :
(i) SPICE
(ii) Analytical h, y, z, s parameters
physical models
The Physical Parameters

are suitable for all frequencies
The h-parameters
Vbe = hie Ib + hre Vce (1)
I2 = hfe Ib + hoe VCE (2)
38
The Y-parameters
Ib = yie Vbe + yre VCE (1)
Ic = yfe Vbe + yoe VCE (2)
The Small Signal Equivalent Circuit
The hybrid - π parameters :
Define the hybrid - π parameters and their dependence on the operating point.
n VT 1
rbe = , τ β = C b'e . rb'e =
IB ωβ
rb’e = is the collector junction resistance = ∞
C b’c = the junction cap. Of the collector
I 
g vn =  C 
 V1 
 ∂ VCE  V 
rce =   =  AF 
 ∂ IC   IC 
39
IC
VCE
VAF
An important property of an amplifying device is the unity gain frequency fT. It

is a Figure of merit of an amplifying device.
fT = low frequency gain & B.W, BW : the bandwidth
It is related to the transit time of carriers in the device
1
ωT T = 1 2 π fT T = 1 , fT =
2πT
fT is given in data sheets
From the hybrid - π equivalent circuit with output short circuit we have :
Vb 'e = I b (Z b'e )
I C = g m Z b'e I b
Ic
=
( g m rb'e ) ≡ β o
Ib 1 + jw rb'e ( C b'e + C b'c )
Ic βo
=
Ib 1 + (ω rb'e ( C b'e + C b'c ))
2
βo
f
fβ
For (IC/Ib) = 0.7 βo ,
ω β rb'e ( C b'e + C b'c ) = 1
40
And for (IC/Ib) = 1
βo . fB
fT = = gain x bandwidth
given in data if given we can get fβ and calculate Cb’e .

sheets
The hybrid - π equivalent circuit can be simplified further by using the Miller
Theorm
IM Cb’c
Vb’e Vce Cb’c (1-Vb’c/Vce)

Cb’c (1-Vce/Vb’e)
The Miller Theorem
A general equivalent circuit of any amplifying device
41
The SSEC of the CE with signal source υs & load RL :
Vo
The voltage gain
Vi
Vo Ao
=
Vi  f   1   f   f 
1 +  1 + j   1 - j CL2   1 - j CL2 
 f ch1   f ch2   f   f 
the high freq. cut-off , the low freq. cut-off
Ao is the gain it medium frequency
2π f CL1 . C1 (ri + R s ) = 1
(
2π f CL2 - C 2 R L + R 'C = 1 ) , R 'C = R C ro ≈ R C
 r • Rs 
2π f ch1 . C i  i  = 1
 ri + R S 
2π fch2 - Co ( R L rc ro ) = 1
log (A)
6 dB/decade 6 dB/decade
12 dB/decade Ao 12 dB/decade
log (f)
fcL2 fcL1 fch1 fch2
ri
A o = g m R 'L
ri + R S
The mid frequency gain is proportional to gm and R 'L
Rs decreases the gain of the amplifier
42
f ch1 〈〈 f ch2 and limits the frequency response of the amplifier
Amplifier with current source ←

The input impedance Z i = Ci ri
The output impedance Z o = Co ro Rc
The phase shift

f
CL12 f
φ = θ 1 + θ 2 - θ 3 - θ 4 , where : θ 1
2 = tan -1
θ 34 = tan -1
f f
ch 34
2. The Common-Base Circuit
The biasing circuit is the universal biasing one
I 1 = 10 I B , I 2 = 11 I B , VE = 0.1 VCE or 1V
For class A operation the op lies midway on the load line

1
VCE = ( VCC - VC )
2
C1 & C2 , CB are coupling and by pass capacitors.
The CB is characterized by :
(i) voltage gain Av low input impedance Zi in comparison to the CE
(ii) no current gain output impedance as the CE
(iii) No miller capacitance effect, larger BW
(iv) higher drive current
43
IC
VCC
RC + RE
ICQ
VCE Q VCC VCE
The solution is by means of the equivalent circuit
E C
vs
αF Ie
βo
• c eb = c be αF =
1 + βo
rbe
• reb =
= 1 / gm
βo
The definition of the small signal parameters of the CB configuration. αF is the
low frequency value of the common base current gain
RE >> reb , Rc // RL = Rc’ effective load resistance
Vo = α F . R 'L I e
I e ≅ Vs / ( R s + reb )
Vo L α F R 'L
A vo = = αF RL
'
= = g m R L / (1 + R s g m )
Vs R s + reb R s + reb
 α F R 'L 
for R s = 0 , A vm =  
 reb 
44
The Frequency Response
A vo
Av =
 f   f   f   f CL2 
1 - j  1 + j   1 - j CL1  1 - j 
 f ch1   f ch2   f   f 
Av
Avo
BW
log (f)
fcL2 fcL1 fch1 fch2
ω ch2 . C eb . reb ≈ 1 (1)
where ωch2 = fT 2 π
ω ch2 . C jc . R 'L = 1 (2)
ω ch1 . C 1 ( R s + reb RE ) = 1 (3)
ω ch2 . C 2 (R 'L ) = 1 (4)
The input impedance
Zi = RE reb = 1 / g m
The output impedance = RC
45
3. The Emitter Follower
The emitter follower = CE, with RC = 0 and the output is taken from the emitter
with CE = 0. The operating point is set in the middle of the load line
IC Pmax
ac loadline
VCC
RE
ICQ
VCE Q VCC VCE
1 1
VCE = VCC , VE = VCC
2 2
RE normally must satisfy the matching condition at the input.
* Input impedance is high
* Output impedance low
* current gain only
* voltage gain 〈 1
DC Analysis
VCC = VCE + I E R E (1)
46
VCC R L
VBB = = TE R E + 0.7 V (2)
R1 + R 2
IB = I E / (1 + β) (3)
From (1), (2) and (3) we get IB , IC and VCE.
AC analysis by means of the equivalent circuit
gm vbe
vbe
The CC amplifier has externally high band width. Therefore we make mid band
analysis only with Rs = 0
Vs = Vbe + Vo (1)
Vo V  1  1
= g m Vbe + be =  g m +  Vbe =  1 +  = g m Vbe (2)
RE rbe  rbe   β
Substitute (1) in (2)
Vo = g m R E ( Vs - Vo )
Vo 1
∴ (1 + g m R E ) Vo = Vs , = A vo ≡ 〈1
Vs 1 + gm RE
The input resistance
Z i = rbe + (1 + β o ) R E (3)
The output impedance
Zo ≅ 1 / gm (4)
• Note it is assumed that R 1 R 2 〉〉 Z i
47
II. Multi-Stage Amplifiers
High gain amplifiers are constructed by connecting two or more stages
in series or cascade. The signal voltage at the output of one stage is fed to the
input of the following stage. The interstage coupling is different according to
the amplifier application. The coupling can be classified to : (i) dc coupling for
dc and low frequency amplifiers as well as integrated circuit amplifier, (ii) ac
coupling which comporise either a capacitive coupling or transformer coupling.
The capacitve coupling is used in audio and video amplifiers while the
transformer coupling is used in power amplifiers as well as rf amplifiers.
1- The Two Stage RC Coupling Amplifiers
Stage 2
Stage 1
vo2
vo1
Fig. 1
Fig.1 shows the two stage RC coupled amplifier. It consists of two

common emitter amplifies. The presence of Cc isolates the dc of the two stages
so that the dc operating point will remain constant. However, the input of stage
2 loads the output of the first stage.
V
The gain of stage 1 = o1 = A vo1
Vs
V
The gain of stage 2 = o2 = A vo 2
V01
V
The gain of the amplifier = o2 = A vo1 . A vo2
Vs
Therefor the problem is reduced to the analysis of a single stage CE amplifier
treated before, Hence,
A vo1 = g m1 R 'L1 , where R 'L 1 is the effective load of Q 1
48
R 'L 1 = R C1 / /rbe2 , with R 3 , R 4 〉〉 R c1 and rbe2
rbe2 is the base to emitter resistance of Q1.
The gain of the second stage Avo2 = gm2 RL
R 'L = R C2 / / R L
The input impedance of the amplifier
Z i ≅ rbe1 , and
Z o ≅ R c2
The Frequency Response Of The Amplifier

The freq. response of such on amplifier has the form shown in Fig.2.
Av
6 dB/oct 6 dB/oct
12 dB/oct 12 dB/oct
Av1
18 dB/oct 18 dB/oct
ω cL3 ω cL2 ω cL1 ω ch1 ω ch2 ω ch3 f
Fig. 2
Because we have 3 coupling capacitors Av has 3 corner frequencies. The

amplifier will have also three high freq. corners. These corner frequencies can
be determined by using the reduced equivalent circuit of the transistor as shown
in Fig.3 .
vbe1 vo1
Fig. 3
ω CL1 C1 . (r1 / /R 2 / /R 3 ) = 1 (1)

ω CL2 . C c . ( ro / /R c1 + R 3 / /R 4 / /r12 ) = 1 (2)
ω CL3 C o ( ro2 / /R c2 + R L ) = 1 (3)
ω ch1 C i1 ( R s / /R c / /R 1 / /ri1 ) = 1 (4)
ω ch2 ( C o1 + C r2 ) ( ro1 / /R c1 / /R 3 / /R 4 / /r12 ) = 1 (5)
49
ω ch3 ( C o2 ) ( ro2 / /R c2 / / RL ) = 1 (6)
- It must be mentioned that one calculates the smallest one for the high
frequency cut-off value and the largest value for ωCL . The bandwidth of the
amplifier =
ω ch smallest - ω CL largest
- Also one has to take into consideration any parasitic and load capacitances
into considerations by simply adding them to the shunt capacitances as they
affect only the high frequency corners.
- The emitter by-poss capacitor must be chosen high enough to cause a low
freq. corner 〈 ωCL largest.
- The input signal must be kept sufficiently small not to over drive the
amplifier causing clipping distortion.
2- The Transformer Coupled Amplifier

Transformer coupling is used for matching one amplifier stage to its following
one or to mach its load. In case of extreme load mismatch to the output
resistance of the RC coupled amplifier, it gain will be practically small.
Fig.4 shows a transformer coupled amplifier
vo
Fig. 4. Transformer Coupled Amplifier
2
 np 
The ac collector load R '
=   RL
L
 ns 
50
R′L is made to mach the output impedance of the transistor ro , i.e.,
R 'L = ro
IC
VCC/ RE
2 ICQ
ICQ
ac loadline
VCE
V’CC VCC 2V’CC
Fig. 5
This amplifier is a class A amplifier such that the operating point lies mid way
of the ac load line as shown in Fig.5.
Q p is adjusted by R 1 , R 2 an R E
The dc voltage drop on RE limits the output voltage swing. But it is necessary
for thermal stability of the operating point. From Fig.5 the maximum voltage
swing = 2 Vcc when the dc operating point is set at the middle of the ac load
line.
Assuming ideal transformer one can express the gain directly. The amplifier is
still of a CE configuration, hence,
2
 np 
A voc = g m R L at the collector = g m . R L   , and
'
 ns 
V np
A vo = o = g m R L
Vi ns
The operating point and the load lines must remain within the safe operating
area of the device.
Because of nonidealities in the transformer, this amplifier has a pass-band

characteristics like the RC coupled amplifier shown in Fig.6. The shape of the
response can be explained by the transformer equivalent circuit shown in Fig.7.
51
Av
f
fcL fcH
Fig. 6
Fig. 7. Equivalent circuit of the transformer
M: is the mutual inductance,

Lp : the primary inductance
Ls : the secondary inductance
Rp : the primary resistance
Rs : the secondary resistance
At low frequencies the effect of the series elements is negligible while the
current gm Vi will be divided by M & R′L . A reduction of the gain occurs
relative to the midband when M gets uneffective and ωCL can be expressed by
ω CL = R 'L / M
At high frequency the opposite is true and
(ω ch ) -1 ( ) (
= L p + L s - 2 M / R p + R s + R 'L )
• We have to notice here that Vo can be made inphase or antiphase reversing
the load convection to the transformer. While in the RC-CE circuit the output
is always anti phase of the input.
52
3- Direct Coupled Amplifiers
In case of amplifying dc and low frequency signals, or in IC amplifier
one has to use direct coupling. Fig.8 shows a 3-stage direct coupled amplifiers.
One important notice is that there is no need for the base biasing potential
divides since the base is directly biased from the collector of the previous stage.
Here their is dc interaction between the stages and this must be taken into
consideration in setting the operating of Q1 , Q2 and Q3 .
Fig. 8
For this circuit it is difficult to set the desired Q-point and required gain
simultaneously. In addition there is an increasing dc collector level from Q1 to
Q3 . This is clear from the practical two stage dc amplifier shown in Fig.9.
= 20V
20 kΩ
100 kΩ
15 kΩ
3.5 V 8.8 V
β = 50 vo
10 kΩ
5 kΩ
1 kΩ
Fig. 9
To solve the problem of increasing collector bias one uses complementary

transistor as shown in Fig.10 .
53
= 20V
15 kΩ 5 kΩ 500 Ω
1.3V 14V 5.3V
1 kΩ 5 kΩ
500 Ω
Fig. 10. Two-stage dc using complementary transistors
These dc amplifier types suffer from any fluctuations in the dc operating

conditions of the transistors. Any temperature variations and dc power supply
variations will be interpreted as an output dc signal.
4- The Differential Amplifier

The differential amplifiers of Fig.11 does not suffer from the above cited
problem. It is the amplifier with much superior performance for direct coupling.
IC1 IC2
VC VC
VEE
Fig. 11
For the cannot made signals, from symmetry Vo = 0

The E point is E virtual ground .
Vi Vi
i c1 = g m , i c2 = - g m
2 2
54
Vi
Vo1 = - g m R L
2
Vi
Vo2 - g m R L
2
( Vo2 - Vo1 )= g m R L Vid = Vod
V
Ao = od = g m R L ⇔
Vid
gain = CE emitter gain ⇔ with an input = Vi
VEE
Fig. 12
The practical differential amplifier has a small common mode output because of
slight unsymmtries in the real circuits. Therefore one defines the so called
common mode gain
V
A cm = ocm ,
Vicm
In addition to the common mode rejection ratio CMRR which is defined by

Ad
CMRR =
A cm
As, the CMRR increases the differential amplifier behaves better near dc.
The common mode rejection ration increases as REE increases. This can be
practically achieved by using current source biasing IEE instread of REE as
shown in Fig. 12.
55
5- The Darlington Configuration
One can combine two transistors to get composite transistor with superior
properties. The darlington configuration is shown in Fig.13 . In active mode of
operation, the current relations are such that IC ≈ β2 IB , since β 〉〉 1 . That is a
transistor with much higher current gain. Therefore it needs very small base
current to drive much larger collector currents. Also the input impedance is
large, ri = hie1 + (1 + β) hiez .
β(β+1)IB
assumed
IB β1 = β2 = β
(β+1)IB
(β+1)2IB
Fig. 13
6- The Composite PNP Transistor

One of the useful combined transistor pairs is the composite pnp transistor
shown in Fig.14.
IB
(β2+1)β1IB
β1IB
Fig. 14
IC = β1 (β2 + 1) IB
For β1 = β2 = β
56
I = β2 IB . , the current amplification factor is also here β2. Q1 acts as a driver
for Q2 and the whole acts as an equivalent pnp transistor.
7- The Cascode Amplifier

In the cascode configuration one sums the merits of the CE & the CB
configurations, to build a high frequency amplifier with relatively, high input
resistance as in the CE, configuration. The cascode configuration is shown in
Fig.15 .
Fig. 15
The dc voltage levels are adjusted as shown in Fig.15 by R3 , R2 , R1 & RE .

CB by - passes the base to the ground.
Vo
The gain A v = = g m R 'L
Vi
The output resistance = rbe

The input resistance = RC
and the frequency response is that of CB because there is no Miller capacitance
between Vo & Vi .
57
Power Amplifiers
Introduction
In many electronic systems a substantial amount of signal power must be delivered to
an output device which service as the load for the electronic circuit. The load may take
several forms, such as a loudspeaker for audio sound reproduction, an ac motor to
drive a pen or stylus for a chart recorders, a servomotor for an automatic control
system, or an electromechanical device in an industrial application.
It is the function of the power amplifier to deliver signal power to the load with a
minimum of distortion and with high efficiency. The efficiency of the power amplifier
depends on the circuit configuration and can, to a certain extent, be controlled by the
circuit designer. The distortion, generated within the power amplifier, is a function of
circuit components and circuit design, and can be held within acceptable limits by
correct design procedure.
We recognize various kinds of distortion. Frequency distortion is defined as the

variation in amplifier gain as a function of the frequency of the input signal. Modern
components and correct design can produce an amplifier with a linear gain response
(within 1 dB) over a very wide frequency band. This is achieved mainly by omitting all
frequency-conscious components (such as coupling capacitors) from the circuit and
using direct-coupled amplifier stages wherever possible.
Another reason for avoiding capacitors is that they may cause phase distortion. Phase
distortion results from unequal phase shifts in signals of different frequencies. To
preserve the phase relationship of all frequency components in a complex waveform,
the phase angle between output and input signal voltages should be independent of
frequency. Phase distortion is generally of minor importance, especially in audio
circuits, where it is not perceptible to the ear. It can be objectionable in systems which
depend in their operation on exact preservation of waveform characteristics, such as
television or pulse circuits. The use of capacitors then should be restricted and, where
capacitors must be high-quality components.
The most objectionable form of distortion is nonlinear distortion. This may be of two
kinds : harmonic or amplitude distortion, and intermodulation distortion. Harmonic
distortion is developed by nonlinearity in the transistor characteristics or by nonlinear
circuit components. Overdriving a transistor, so that distortion is the result of
interaction of two or more signal frequencies within an amplifier stage. The output
signal of the stage then contains frequency components consisting of the sum and
difference of the original input signal frequencies.
58
Special circuit configurations are used to obtain large output power at high efficiency
and low distortion. In this chapter we examine the characteristics of several commonly
used power amplifier circuits, in both audio and radiofrequency applications.
Classification of Amplifiers
Depending on the bias conditions in the circuit, power amplifiers are classified in three
basic categories : class A, class B, and class C.
In a class A amplifier, the bias conditions are such that the operating point (Q point) of
the transistor is located well within the linear part of the collector characteristics. The
applied signal never drives the transistor into cutoff or into saturation. The optimum
bias is such that the Q point is approximately halfway between cutoff and saturation,
as in Fig. 6-1.
Signal excursion is limited to the active region and avoids cutoff (point A) and
saturation (point B). As indicated in Fig. 6-1, the quiescent collector voltage VC is
approximately one-half the supply voltage VCC . The quiescent collector current IC
causes quiescent collector dissipation and this is wasteful in the sense that it does not
contribute to ac load power.
Fig. 6-1
The class A amplifier is the least efficient circuit of the three basic categories.
59
In a class B amplifier, the transistor is biased at cutoff, with the Q point located on the
VC axis, as in Fig. 6-2. In the case of a sinusoidal input signal, ac collector current
flows only during one-half of the cycle (180 degrees), and is zero for the other half of
the input cycle. The quiescent collector current is zero and hence the quiescent power
dissipation is zero. Because of zero power dissipation in the absence of an input
signal, a class B amplifier is more efficient than a class A amplifier. Since only one-
half of the input signal is subject to amplification, the class B amplifier is generally
connected in a push-pull configuration, when two transistors alternately amplify one-
half of the input signal (Section 6-4).
Fig. 6-2
A class AB amplifier operates between the two conditions described for class A and
Class B, with the Q point somewhere between cutoff and the center of the collector
characteristics. Hence, some quiescent collector current flows and some dc collector
dissipation is present. With an applied input signal, the transistor is driven into cutoff
for less than half of the signal cycle and the collector current is therefore zero for less
than half of the input signal cycle. Class AB amplifiers are also connected in push-pull
configurations and tend to reduce crossover distortion (Section 6-5).
In a class C amplifier, the transistor is biased well beyond cutoff and the collector
current is zero for more than one-half of the input signal cycle. Collector current tends
to flow in short-duration pulses, only when the transistor is driven out of its cutoff
condition into conduction. The class C amplifier has the highest efficiency, and is
used primarily in tuned radiofrequency power amplifiers.
Because of its relatively high current and power gain, the CE transistor configuration
is generally used in power amplifiers.
60
Class A Power Amplifier
Figure 6-3 shows the circuit diagram of a transformer-coupled class A power
amplifier, Resistors RA and RB supply bias to power transistor Q1 while emitter resistor
RE provides the necessary dc circuit stabilization (Section 3-5). RE is usually bypassed
with a fairly large emitter capacitor CE to improve the stage gain. Load resistor RL is
transformer-coupled to the collector and is reflected into the collector circuit as
2
N 
R '
=  1  RL
 N2 
L
Fig. 6-3
There are several advantages in using a transformer to couple the load to the collector,
First, with transformer coupling there is no direct current would degrade the
performance of the output device. Second, it the resistance of the transformer primary
is neglected, the collector voltage VC equals the supply voltage VCC, and hence a
smaller supply voltage can be used. Third, the transformer provides impedance
transformation and allows a low-impedance load, such as a loudspeaker to be reflected
as a higher impedance collector load necessary for correct operation of the power
transistor. On the other hand, a transformer is relatively heavy and occupies valuable
space.
61
Fig. 6-4
Figure 6-4 represents a simplified circuit of the class A power amplifier of Fig.6-3. In
this equivalent circuit, the collector supply voltage is represented by VCC′ = VCC - VE.
The base bias circuit is replaced by its Thevenin equivalent battery VBB in series with
resistor Rb , where
RB
VBB = VCC (6-2)
RA + RB
and
RA RB
Rb = (6-3)
RA + RB
The total collector current iC consists of two components : a dc component IC

(quiescent collector current) and an ac component ic (load current), so
IC = IC + ic (6-4)
The primary of the output transformer, represented by inductor L2 acts as a short

circuit to the dc voltage drop across RL . The ac voltage drop across RL is the output
voltage
υ o = i C R 'L (6-5)
In the circuit of Fig. 6-4, the instantaneous collector-emitter voltage equals
υ CE = VCC' + υ o = VCC' + i c R 'L (6-6)
Equation (6-6) is the expression for the ac loadline, plotted on the hypothetical
collector characteristics of Fig. 6-5. The quiescent collector-to-emitter voltage equals
VCC’ and the quiescent collector current equals IC. Since in a class A amplifier the
operating point makes equal excusions on each side of the Q point, the ac collector
voltage can reach a peak value Vm = VCC’ and the total collector voltage swing can
62
therefore extend from 0 to 2 VCC’ . To avoid nonlinearlty and distortion, however, the
signal excursion is generally kept well below this possible peak value.
Fig. 6-5
When the input voltage υs is sinusoidal, the average or dc value of the ac collector
signal current is zero. Only quiescent collector current contributes to the power drawn
from the battery, and this power equals
PCC = VCC' I C (6-7)
Hence, in a class A power amplifier, the power drawn from the dc supply is constant
and depends only on collector voltage V CC’ and quiescent collector current IC .
The ac power delivered to the load equals
PL = R 'L ( I rms )
2
(6-8)
Where Irms is the value of the ac load current in the transformer primary. The total
power drawn from the collector supply equals the power delivered to the load plus the
power dissipated in the transistor as collector dissipation, so we can write.
PCC = PL + PC (6-9)
63
where PC represents the collector dissipation. Under quiescent conditions, when there
is no input signal, PL = 0 and hence PCC = PC = VCC’ IC. This indicates that the
collector dissipation is maximum when there is no input signal.
The maximum power that can delivered to the load equals the product of the
maximum ac collector voltage and the corresponding maximum ac collector current,
so
PL(max) = Vrms(max) I rms(max) = 0.5 VCC ' I C (6-10)
The maximum theoretical efficiency (sometimes called “conversion efficiency”) of the

class A power amplifier then equals
PL(max) 0.5 VCC' I C
η = = = 0.5 or 50% (6-11)
PCC VCC ' I C
Equation (6-11) indicates that maximum ac load power is obtained only when the
amplifier is designed for maximum quiescent collector dissipation. In practice, 50
percent efficiency is not reached, since the transistor would then operate in the
nonlinear part of its characteristics and unacceptable distortion would be introduced.
The amount of power the transistor itself can dissipate is limited by the maximum
ratings of collector voltage, current, and power. These maximum permissible ratings
are indicated by the closed region bounded by IC(max) , Vc(max) , and PC(max) in Fig. 6-5.
When the power to be delivered to the load PL is specified (with a given input signal
waveform), the maximum collector dissipation [PC(max)]can be determined. For a
sinusoidal input signal,
PL = PC(max) = 0.5 VCC' I C (6-12)
based on these parameters, a suitable power transistor with permissible collector

dissipation at least as great as PC(max) , and suitable current and voltage ratings, can be
selected.
Example 6-1
A silicon power transistor, operating in the class A configuration of fig. 6-3, has the
following maximum ratings: IC= 4 A , VCE = 45 V, PC = 15 W, VBE = 1 V, and β > 30.
A 4-Ω loudspeaker is transformer-coupled to the collector circuit. The transistor is to
operate within its ratings and is to deliver maximum power to the 4-Ω load. Specify
reasonable operating conditions.
Solution
The maximum ratings determine the maximum allowable values for quiescent
collector voltage and current. These are IC(max) = 4 A/2 = 2 A and VCC′ = 45 V/2 =
64
22.5 V. At these Q-point values, the collector dissipation is PC(max) = I C(max) x VCC′ =
2 A x 22.5 V = 45 W, which far exceeds the rated dissipated of 15 W. Hence, the
actual quiescent current and/or voltage must be reduced suppose that we select a
power supply voltage of VCC = 15 V and assume that the emitter voltage VE is 10
percent of the supply voltage (an average value). In that case, VE = 1.5 V and VCC =
VCC - VE = 13.5 V. The Q-point collector voltage is therefore 13.5 V and the
maximum Q-point collector current which may be allowed without exceeding the rated
dissipation is IC(max) = 15 W/13.5 V = 1.1 A. To assume operation below this limit, we
select quiescent operation with IC = 1 A. To give the ac loading the correct slope, the
load resistance reflected into the primary of the output transformer is RL′ = VCC′/IC =
13.5 V/1 A = 13. Ω. This establishes the required turns ratio of the transformer. The
quiescent power dissipation equals PC = VCC′ IC = 13.5 V x 1 A = 13.5 W. With a
sinusoidal input signal applied, the maximum signal power the amplifier can deliver to
the load equals PL = 0.5 VCC′ IC = 6.75 w. The total power drawn from the battery
under these conditions is PCC = PC + PL = 13.5 W + 6.75 W = 20.25 W.
Class B Push-Pall Power Amplifier

In the class B mode of operation, the transistor is biased at cutoff, as was indicated in
Fig.6-2. If the power amplifier of Fig. 6-3 were biased at cutoff, the transistor would
respond only to the positive portions of the input signal, when it should be forced into
conduction. During the negative portions of the input signal the transistor would
remain cut off and no collector current would flow. Clearly, if a class B amplifier is to
response the entire signal waveform, a different circuit configuration must be
considered. One such configuration, called a transformer-coupled push-pull amplifier,
is shown in Fig. 6-6.
Fig. 6-6
Input signal υs is coupled by a center-tapped input transformer to a pair of identical

npn transistors. The input or driver transformer provides two input signals in
antiphase, which is evident from the polarity dots on the transformer windings.
65
The load, represented by load resistor RL, is coupled to the collector circuits of the
power transistors by a center-tapped output transformer. The use of transformers in
this circuit has definite disadvantages in terms of distortion, frequency response,
efficiency, and power bandwidth, on the other hand, it provides for impedance
transformation and matches the load to the collector circuit.
Fig. 6-7
It is clear that in the absence of an input signal (quiescent conditions), the base and
emitter of each transistor are at ground potential and hence both transistors are cut off
(class B operation). When input signal υs goes positive, transistor Q1 becomes
forward-biased and conducts, while transistor Q2 becomes reverse-biased and is
driven deeper into cutoff. When Q1 conducts, it products a collector current iC1
through the upper half of the output transformer with a direction as indicated in Fig
6-6. When the input signal υs negative, Q2 conducts and Q1 is driven into cutoff.
Collector current IC2 flows through the lower half of the output transformer with a
direction as indicated Fig.6-6. Hence Q1 amplifies the positive portions of the input
signal and Q2 amplifies the negative portions. The two transistors operate as switches
66
delivering output current to the transformer-coupled load on alternate half-cycles.
Figure 6-7 illustrates the action of the circuit with a sinusoidal input signal υs .
It is instructive to investigate the conditions under which maximum collector

dissipation occurs and to find the maximum theoretical efficiency of the circuit.
Under quiescent conditions, when the input signal is zero, both transistors are cut off
and do not supply any collector current. Hence, the quiescent power dissipation is
zero. With input signal υs applied, the current drawn from the power supply VCC is
represented by Fig. 6-7(d), where
i CC = I C1 + I C2 (6-13)
If Im represents the peak value of collector currents iC1 and iC2, the rms value of the
total current waveform of Fig. 6-7(d) is
2
I rms = Im (6-14)
π
and the power delivered by VCC is

2
PCC = VCC I m (6-15)
π
or
2
2 VCC
PCC = (6-16)
π R 'L
Since Im represents the peak value of the collector current or the primary load current,
the power delivered to the load equals.
PL = R 'L I 2rms = 0.5 R 'L I 2m (6-17)
The collector-to-emitter voltages of Q1 and Q2 can be expressed as
υ CE1 = VCC - υ 1 = VCC - i C1 R 'L (6-18)

and
υ CE 2 = VCC - υ 2 = VCC - i C2 R 'L (6-19)
It follows from eqs. (6-18) and (6-19) that the peak value of the transformer primary
voltages υ1 and υ2 can reach a maximum of VCC. Hence, the maximum power which
can be delivered to the load equals.
67
2
0.5 VCC
PL = = 0.5 VCC I m (6-20)
R 'L
The maximum theoretical efficiency of the class B power amplifier therefore equals
2
PL 0.5VCC / R 'L
η = = = 0.785 or 78.5 % (6-21)
PCC (2 / π )(VCC 2
/ R 'L
The maximum output which can be delivered by the class B amplifier is limited by the
maximum rated collector current and voltage of the transistor or, in some cases, by the
rated collector dissipation of the transistors. Let us consider the two cases separately.
The maximum collector-to-emitter voltage VCE(max) and the maximum collector current
IC(max) are listed as maximum ratings in the transistor data sheet. Referring to Fig. 6-6,
we observe that when Q1 conducts its collector current IC1 through the upper half of
the output transformer induces a voltage - υ2 in the lower half of the output
transformer. Since υ1 = - υ2 may reach a peak value of VCC, the transistors must be
able to withstand a maximum collector-to-emitter voltage VCE(max) equal to twice the
supply voltage VCC. Entering this condition into eq. (6-20) we obtain .
1
PL = 0.5 VCC I m = VCE(max ) I C(max) (6-22)
4
Equation (6-22) represents the maximum output power the class B amplifier can
deliver without exceeding the maximum transistor current and voltage ratings.
In the second case the output power may be limited by the maximum collector
dissipation of the tansistors. In the class B amplifier the collector dissipation of each
transistor is zero under quiescent conditions (iC1 = iC2 = 0). Hence, the maximum
collector dissipation must occur when signal is applied. The instantaneous collector
dissipation equals.
PC = υce iC (6-23)
As the operating point moves along the ac loadine (Fig. 6-8), from the Q point at
VCE = VCC and IC = 0 to the other extreme on the IC axis, where VCE = 0 and IC = I, the
instantaneous values of υce , and PC all change from point to point along this path. The
maximum value of PC occurs when the ac loadline is tangent to the hyperbola of
maximum permissible collector dissipation. The point of tangency is located at
VCE = VCC/2 and IC = 1/2. This reasoning holds for Q1 on positive signal excursions
and for Q2 on negative signal excursions. Thus we find that the maximum
instantaneous collector dissipation for each transistor equals.
2
VCC 1 VCC
PC(max) = = (6-24)
2 2 4 R 'L
68
Fig. 6-8
Hence, from eq. (6-20), the output power the amplifier can deliver without exceeding
the maximum instantaneous collector dissipation equals
2
0.5 VCC
PL = = 2 PC(max) (6-25)
R 'L
If the instantaneous maximum collector dissipation is indeed equal to the maximum

permissible collector dissipation (as is the case when the ac loadline is tangent to the
hyperbola of maximum collector dissipation), the output power under maximum
signal conditions can be expressed as
PL = 2 PC(max) (6-26)
Comparing this result with the maximum output power available from a class A
amplifier, we find that in class B operation the output power for a sinusoidal input
signal is twice as great for class A operation.
The objective of a class B push-pull amplifier is to deliver a specified amount of

output power to a given load with a specific (usually sinusoidal) input sign. With
transformer coupling of the load, the reflected load resistance can be adjusted to suit
the requirements of the transistor collector circuit and suitable power transistors can
then be selected. With the load power PL specified, and RL′ determined, the collector
supply voltage VCC can be determined from eq. (6-20). The peak collector current can
be found by realizing that VCC = RL′ I. The maximum instantaneous collector
dissipation is determined from eq. (6-24) and this then allows the selection of
transistors having suitable voltage, current, and power ratings.
69
The procedure is illustrated in the following example.
Example 6-2
The push-pull amplifier of Fig. 6-6 is required to deliver to W of output power to a 4-
Ω loudspeaker which is transformer-coupled to the collector circuit. The available
collector supply voltage VCC = 30 V. Determine the required turns ratio of the output
transformer and the minimum voltage, current, and power ratings of the power
transistors.
Solution
With PL = 10 W and VCC = 30 V, eq. (6-20) yields the required reflected load
resistance RL′ since
2
0.5 VCC
PL =
R 'L
and RL′ = 0.5 (30)2/10 = 45 Ω .

Since
2
N 
R '
=  1  RL
 N2 
L
45
then turns ratio of the output transformer equals a = ≅ 3.35
4
Since
PL = 2 PC(max)
The maximum instantaneous collector dissipation equals

PL
PC(max) = = 5W
2
Hence, each transistor should have a maximum collector dissipation of at least 5 W.
The maximum collector current IC(max) is determined from
VCC 30 V 2
I C (max) = = = A
RL'
45 Ω 3
Under maximum signal conditions, each transistor must be able to withstand a

collector-to-emitter voltage equal to at least twice the supply voltage. This condition
yields.
VCE (max) = 2 VCC = 60 V
Using the maximum voltage and current ratings of the transistor to calculate the
maximum load power which can be delivered and using eq. (6-22), we obtain
70
1
PL = VCE(max) I C(max)
4
or
1 2
PL = x 60 V x A = 10 W
4 3
Summarizing, the transistor ratings should be
VCE (max) 〉 60 V
2
I C(max) 〉 A
3
PC(max) 〉5W
Crossover Distortion In Push-Pull Amplifiers

The input circuit of the class B amplifier of Fig. 6-6 can be represented as Fig. 6-9.
Each half of the input transformer is replaced by its equivalent circuit consisting of
voltage source υs and internal resistance R s . Base currents ib1 into Q1 and ib2 into Q2
obviously depend on the magnitude of input voltage υs and input resistance R s and
also on the forward-bias characteristics of the base-emitter junctions of Q1 and Q2.
The base current into the device is practically zero until the base-emitter voltage
reaches a value of a few tenths of a volt (approximately 0.3 V for germanium and
0.7 V for silicon). This characteristic has a detrimental effect on the performance of
the class B push-pull amplifier in terms of its waveform reproduction.
Fig. 6-9
Consider the composite volt-ampere characteristics of the input circuit of Fig. 6-9, as
shown in Fig. 6-10. The input characteristics of Q1 and Q2 are shown “back to back”
and it is assumed that the base-emitter voltages of Q1 and Q2 are equal to the source
voltage υs (neglect Rs). Base current ib1 does not have an appreciable value until
source voltage υs has reached a positive value of a few tenths of a volt. Similarly, base
71
current ib2 does not have an appreciable value until υs has reached a negative value of
a few tends of a volt. The area between the knees of the back-to-back characteristics
thus represents a region in which the base currents are not directly proportional to the
source voltage υs , and this introduces a form of distortion called crossover distortion.
Fig. 6-10
If the source voltage υs is sinusoidal, as in Fig.6-11 (a), base currents ib1 and ib2 will
have waveforms as indicated in Fig. 6-11 (b). The composite collector current, ot load
current, will then also be nonlinear, with a waveform as in Fig. 6-11 (c). The
nonlinearity is introduced when the action of the circuit transfers or “crosses over”
from one transistor to the other.
If the exact waveform of the input signal must be preserved in the output circuit of the
amplifier, as in audio signal reproduction, the cause of crossover distortion must be
eliminated or at least sharply reduced. In a practical circuit, this is often achieved by
applying a small forward bias to the base-emitter junctions of Q1 and Q2, thereby
placing both transistors at the threshold of strong conduction. The back-to-back input
characteristics of Q1 and Q2 will then be shifted along the voltage axis in the manner
indicated in Fig. 6-12. Notice that in this case the composite volt-ampere characteristic
more nearly approaches a straight line. A commonly used bias circuit is shown in Fig.
6-13, where diode D provides just sufficient bias to place both Q1 and Q2 at the knee
of their input volt-ampere characteristic. This circuit arrangement is popular because
diode D stabilized the Q points of the transistors against temperature variations.
A resistive bias network can also be used, simply by replacing the diode by a resistor
of suitable value. The advantage of q point stabilization, however, is then sacrificed.
72
Fig. 6-11
In addition to the problems of crossover distortion, another difficult with the push-pull
amplifier is that it requires two transistors of the same polarity and with almost
identical characteristics. If the two transistors are not equal, nonlinear distortion
results. Most manufacturers supply transistors in “matched pairs”, either npn or pnp.
A matched pair consists of two transistors whose characteristics are very similar and
they are specially supplied for use in push-pull amplifiers. In addition push-pull
amplifiers generally use a liberal amount of negative feedback to reduce distortion.
73
Fig. 6-12
Fig. 6-13
Complementary Symmetry Amplifier

The conventional transformer-coupled push-pull output stage of Fig. 6-6 with
transistors of the same polarity, requires two input signals of opposite phase. In Fig.
6-6 this phase-splitting function is performed by the input transformer with its center-
tapped secondary. The disadvantages of using a transformer for phase splitting many,
particularly in terms of frequency response and distortion. In the audio spectrum, the
upper end of the frequency band is affected by the stray inductance and capacitance of
the transformer, the lower end of the frequency band is affected by the primary self-
inductance. Nonlinear behavior of the magnetic core material of the transformer
introduces distortion. These remarks also apply to the output transformer. The use of
both input and output transformer therefore tends to degrade the performance of the
circuit even further.
74
The most economical solution to eliminate transformers altogether is found in the
complementary symmetry circuit, which used an npn and a pnp transistor in the
configuration of Fig. 6-14. For the sake of simplicity, the components required for dc
adjustment have been omitted from the circuit.
Fig. 6-14
The transistors are assumed to operate in class B. Note that in this simplified circuit
two separate collector supplies are used, instead of the single supply in the normal
push-pull circuit. Input signal source υs delivers signal current i s to transistors Q1
and Q2.
On the positive half-cycle of the input voltage, npn transistor Q1 becomes forward-
biased and conducts, while pnp transistor Q2 is driven into cutoff. Collector current
iC1 flows through the load resistor RL in the direction indicated in Fig. 6-14. On the
negative half-cycle of the input voltage, Q2 conducts and Q1 is cutoff, so that
collector current iC2 flows through the load in the opposite direction. Hence,
Q1 amplifies the positive of the input signal and Q2 amplifies the negative portions.
The two transistors act as emitter followers, alternately delivering as output current to
the load.
The analysis of the complementary symmetry circuit to the load, to that of the
conventional push-pull circuit and need not be repeated here. A little though convinces
us that all the voltage, current, and power relations derived for the push-pull circuit of
Fig. 6-6 apply equally to the complementary symmetry circuit of Fig. 6-14 if RL′ in
those relations RL is replaced by . Hence, the delivered output power to the load
equals twice the maximum collector dissipation per transistor and
PL = 2 PC(max) (6-27)
The maximum theoretical efficiency of the complementary symmetry amplifier is

equal to that of the push-pull amplifier and
75
η = 78.5 % (6-28)
the basic circuit of fig. 6-14 is not very practical, since it uses two power supplies and
does not contain the required components for biasing and stabilization. Figure 6-15
shows a practical arrangement of the complementary symmetry amplifier using a
single power source. The circuit includes a driver stage and the necessary components
for biasing and feedback.
Fig. 6-15
Load impedance RL is ac-coupled by capacitor C3 to the complementary output

transistor C3 to the complementary output transistors Q2 and Q3. Emitter resistors R6
and R7 stabilize the output stage Q2-Q3 against temperature variations. In addition,
resistor R1 stabilizes driver transistor Q1 against temperature variations by applying
feedback from the emitters of the output transistors to the base Q1. The dc voltage at
the midpoint between the emitters of Q2 and Q3 is approximately one-half supply
voltage - VCC .
76
to minimize crossover distortion, the output transistors must be biased to a quiescent
emitter current of a few milliampers. If both transistor. If both transistors had the same
polarity, this quiescent current could be obtained by applying a small negative base
voltage with respect to the emitter voltage, in the manner suggested in Fig. 6-13. Since
the output transistors have opposite polarity, the base of Q2 requires a negative bias
with respect to its emitter and the base of Q3 requires a positive bias with respect to
its emitter. These bias voltages are supplied by resistor R4 in Fig. 6-15, which is
inserted in the collector circuit of driver transistor Q1. This introduces some
asymmetry in the circuit and hence R4 should have a small resistance. R4 is usually a
preset potentiometer to allow exact adjustment of the operating points of the output
transistors and to prevent clipping of the output signal at maximum signal excursion.
Also R4 is sometimes paralleled by a thermistor to compensate for temperature
dependence of the quiescent currents.
The operation of the circuit is similar to that described for the basic circuit of Fig. 6-
14. During the positive half-cycles of the input voltage, applied to the base of driver
transistor Q1, output transistor q3 conducts and lowers the dc voltage at point A (the
midpoint between the emitters of the output transistors). During the negative half-
cycles of the input voltage, output transistor Q2 conducts and raises the dc voltage at
point A. The variations in the dc voltage at point A are transferred to the load via
capacitor C3.
An example of an economical 1-W stereo pickup amplifier, with a complementary

output stage, is shown in Fig. 6-16. The design uses an absolute minimum of
components. The simple power supply, designed for an output voltage of 9 V, consists
of a 6.3 V A-V secondary winding with a single rectifier diode and a large storage
capacitor. The circuits for the input transistors of each channel are decoupled by a
common RC filter (33 kΩ and 80 µF). The complementary output stage is almost
identical to the one described in Fig. 6-15. Since is a low-cost circuit, no temperature
compensating emitter resistors are used in the output stage. Ganged tone controls and
separate or dual-concentric volume controls for each channel are recommended.
In each case may be of the linear type. Feedback is used to achieve a high input
impedance, and a good low-frequency response is obtained with a capacitive source
such as a ceramic pickup.
The performance specifications per channel are
nominal power output 900 mW into 8-Ω load

sensitivity (1000 Hz) for Po = 9000 mw 600 mW
from 1000-pH source
frequency response (- 3 dB) 110 to 11,500 Hz
tone control - 12 dB at 10,000 Hz
nominal supply voltage 9V
current consumption at Po =900 mW 160 mW
77
Fig. 6-16
QUASI Complementary Amplifier

The complementary symmetry output stage of Fig. 6-15 requires transistors with
practically identical characteristics. For large power outputs (say, in excess of 10 W) it
is rather difficult to manufacture complementary symmetry pairs economically. To
retain the advantages of the complementary circuit (single-ended input and no output
transformer), complementary transistors are often used in the driver stage of the high-
power amplifier and are then followed in the output stage by two power transistors of
the same polarity in a push-pull configuration. This circuit arrangement is known as a
quasi-complementary amplifier and is shown in fig. 6-17. Notice that the again two
separate power supplied are used and that the load is connects for feedback and circuit
stabilization are omitted for the sake of simplicity.
Input transistor Q1 is biased in the conventional manner by R1. The collector load of
Q1 consists of R2 and R3, with R2 providing the correct bias voltage for the
complementary transistors Q2 and Q3. This bias arrangement ensures that Q2 and Q3
draw a small quiescent current to avoid crossover distortion. The complementary pair
Q2-Q3 provides the phase splitting function required for the class B push-pull output
stage Q4-Q5. The current requirements, and hence the power dissipation, in the
complementary pair are relatively small since the only power required is that used to
provide the base drive for the power transistors. The complementary pair need not be
closely matched because their Q-points can be set adequately by making R2 variable.
78
Fig. 6-17
A qualitative analysis of the circuit of Fig.6-17 proceeds as follows : When the input
signal goes positive, Q1 collector current decreases, forcing Q2 into heavier
conduction and Q3 into cutoff. Hence, the base current into power transistor Q4
increases while the base current into q5 decreases or becomes zero. When the input
signal goes negative, the reverse action takes place. Hence, the output current
delivered to the load is supplied alternately by each power transistor in a standard
push-pull action. Transistor combination Q2-Q4 can be regarded as a Darlington pair,
while transistor combination Q3-Q5 is connected as a complementary Dalrlington pair.
Fig. 6-18
79
The circuit is not very practical since it requires two power supplies and a “floating”
load. A practical circuit arrangement, using a single power source, is shown in Fig.
6-18. The load RL is capacitively coupled to the midpoint of the output stage in
manner identical to that described for the complementary circuit of Fig. 6-15. Emitter
resistors R4 and R5 provide stabilization of the output stage against temperature
variations. Bias resistor R2 is usually shunted by a thermistor Rt to stabilize the
complementary pair Q2-Q3. The operation of the circuit is virtually identical to that of
the basic circuit of Fig. 6-16 and requires no further elaboration.
Questions
1- For each class of amplifier operation (A, B, and C) indicate the position of the dc
operating point on the IC-VC collector characteristics. Breifly explain how the
collector current in each case varies in response to the input signal.
2- In what circuit configurations is a class B amplifier generally used ?
3- state the theoretical maximum efficiency of a class A amplifier and a class B
amplifier.
4- what is the quiescent power dissipation(at zero input signal)of a class B amplifier?
5- Assume that a load resistor is transformer-coupled to a class A output stage. What
can happen to the transistor if the load resistor is disconnected ?
6- Name the advantages and the disadvantages of transformer coupling.
7- Name the various types of distortion that can be present in a power amplifier and
in each case explain how this distortion is generated.
8- What is meant by crossover distortion ? How can crossover distortion be
minimized ?
9- Draw the circuit diagram of a transistors produce the push-pull stage and explain
how the two class B transistors produce the output signal.
10- Why is it necessary to use a pair of matched transistors in a push-pull stage ?
11- What are some of the advantages of a complementary symmetry amplifier over a
conventional push-pull amplifier ?
12- Explain the function of each component in the 1-W stereo amplifier of Fig. 6-16.
13- What is the major advantage of a quasi-complementary pair over the
complementary symmetry pair.
80
Heatsink Evaluation
Introduction
One of the important ratings of semiconductor power devices is the maximum
permissible junction temperature, Tj . The life expectancy and reliability of the device
depend on the junction temperature and it is therefore important that this temperature
be kept as low as space and economic considerations permit.
Figure 7-22 shows a diagramatic representation of a semiconductor device. The with

its heat-generating junction is in close thermal contact with its metal encapsulation or
case. Most of the heat generated inside the device is transferred to the relatively heavy
mounting base, from which it is dissipated-to the surrounding environment. In power
devices such as rectifier diodes, the mounting base is not large enough to dissipate the
generated heat adequately and the surface area of the case can then be extended by
attaching the device to a thermally conductive metal plate, called a heatsink.
Fig. 7-22
The heatsink may be a simple flat piece of aluminum or steel. In many cases the
surface area of the heatsink is increased by folding or by finned extrusions.
Thermal Resistance
With the semiconductor mounted on a heatsink, the flow of heat takes place from the
heat-generating junction via the mounting base of the case to the heatsink, and then by
conduction, convection, and radiation to the surrounding environment. We recognize
three distinct parts in the heat-flow system, each exhibiting a certain resistance to the
flow of heat. The total resistance to heat flow is called the thermal resistance, Rth,
which is related to the power dissipation of the device, and to the difference in
temperature between the heat-generating junction and the operating environment
81
(ambience). This relation is expressed in the form of a thermal law, similar to Ohm’s
law for electric circuits, which states that
∆T = P R th(j-a) (7-37)
where
∆ Tj = Tj - Ta (junction temperature minus ambient temperature), in
°C
P = maximum power dissipation of the device, in watts
Rth(j-a) = thermal resistance from junction to ambience, in °C /W
In eq. (7-37), ∆ Tj is know, since Tj is stated in the device, and Ta is the ambient
temperature which can be measured. P represents the actual maximum power
dissipation of the device and is known from its circuit configuration. The total thermal
resistance can then readily be calculated.
In an actual case Rth(j-a) consists of the thermal resistances from junction to ambience,
so that
R th ( j− a ) = R th(j-c) + R th(c-s) + R th(s-a) (7-38)
Fig. 7-23
where
Rth(j-c) = thermal resistance from junction to case
Rth(c-s) = thermal resistance from case to heatsink
Rth(s-a) = thermal resistance from heatsink to ambience
82
The situation is illustrated graphically in Fig.7-23. By rearranging Fig. (7-38) we can
calculate the thermal resistance of the heatsink.
Example 7-6
A 2N4347 power transistor is used a series regulator in a power supply. The
maximum power dissipation of the devices is 10 W and the ambient temperature is
not expected to exceed 50°C. Calculate the required thermal resistance of the heatsink.
Solution
From the diode manual we find the maximum permissible junction temperature of the
2N4347 is Tj = 200°C. The thermal resistance from junction to case is listed as Rth(j-
c) = 1.5°C /W. The thermal resistance from case to heatsink is not given in the
transistor manual, but experience indicates that = 0.5°C /W is a reasonable value.
Using the thermal law, we find the total thermal resistance from junction to ambience :
∆ Tj 200o C
R th ( j− a ) = = = 15o C / W
P 10 W
Subtracting the known parts of the thermal resistance path, the thermal resistance of
the heatsink is
R th ( s− a ) = 15o C / W - 2 o C / W = 13o C / W
Example 7-6 indicates that it is a fairly simple procedure to calculate the required
thermal resistance of a heatsink, using the device ratings and external circuit
conditions.
The next step is, of course, to find the correct material ofwhich the heatsink is made
and to calculate the required size of the heatsink in order to dissipate the generated
heat adequately.
Physical Characteristics
Various heatsink metals have different thermal conductivity properties.
Copper has a very high thermal conductivity and is used for heatsink requiring low
thermal resistance with maximum surface area.
Aluminum also has a high thermal conductivity and has the advantage of light weight
and low cost. Aluminum is the obvious choice for most applications.
Steel has a moderate thermal conductivity, but is very low in cost compared to copper
and aluminum. The most common application of steel heatsink is where the device is
mounted directly onto the equipment chassis, with the chassis serving as the heatsink.
83
The surface of the heatsink has an effect on its emissivity. Bright or polished metal
surfaces have poor emission properties, while matte black painted or black anodized
surface have the best emission properties. A matte paint finish of any color is
considerably better than a bright surface.
The mounting attitude of the heatsink is also of importance. For the best transfer of
heat, vertical mounting with both sides of the heatsink exposed to convection is best.
Frequently the space available to mount the heatsink is limited, and the total surface
area may then be extended by folding or the use of multiple fins.
In some cases, natural convection cooling is not sufficient, especially for thermal
resistances below 2°C/W, and forced air cooling a then required.
Fig. 7-24
84
Calculation of Heatsink Dimensions
The total thermal resistance of the heatsink consists of two parts, namely a part
responsible for conduction of heat within the metal itself, and a part responsible for
radiation from the metal surface into the environment.
The conduction properties of the heatsink on the physical characteristics of the metal,
such as thickness and type of material. Table 7-3 lists the thermal conduction
properties for various metals of different thickness.
Gage (SWS) 24 22 20 18 16 14 12
Thickness inches 0.022 0.028 0.036 0.048 0.064 0.080 0.104
mm 0.56 0.71 0.92 1.22 1.63 2.04 2.54
Copper 2.04 1.81 1.59 1.38 1.20 1.07 0.94

Aluminum 2.74 2.43 2.14 1.86 1.61 1.44 1.26
Steel 5.87 5.19 4.80 3.97 3.44 3.08 2.70
The table shows that the thermal resistance of steel is approximately twice that of
aluminum. The radiation properties of the metals listed in Table 7-3 depend on several
factors such as the total surface area of the heatsink, the surface finish, and the
position (horizontally or vertically placed). Figure 7-24 relates these parameters in a
nomogram. Its use is best demonstrated by an example.
Example 7-7
A heatsink with a thermal resistance Rth(s-a) = 13°C/W is required to dissipate the heat
generated by a 2N4347 power transistor, operated at 10-W dissipation (see also
Ex. 7-6). A flat piece of 70-gage aluminum is available, which will be mounted
vertically to allow radiation from both sides. Calculate the size of this heatsink.
Solution
From Table 7-3 we determine the thermal resistance of 20-gage aluminum, and we
find that Rth(conduction) = 2.14°C/W. This indicates that the heatsink should have
radiation properties corresponding to
R th ( radiation ) = 13o C / W - 2.14 o C / W = 10.86o C / W
Use the nomogram of Fig. 7-24. Align a straightedge from the point k = 0.85 (vertical
mounting of bright aluminum) on the k scale to the point Rth(radiation) = 10 10.86°C/W
on the Rth scale. The A scale then indicates the required area and we read that A = 51.5
cm2. Since the most effective shape of a heatsink is approximately square, the
dimensions of the bright aluminum sheet should be approximately 7 by 8 cm. If the
surface of the aluminum sheet is blackened, the required area is only 27 cm2 .
85
For heatssinks of finned construction, appropriate nomograms are available from the
manufactures but the procedure for calculating type and size of heatsink is essentially
the same. Also forced-air cooling considerably reduces the required heatsink area and
again nomograms are available which related the size of the heatsink to the total power
dissipation and the velocity of the forced air.
86
EXPERIMENTS ON THE BIPOLAR JUNCTION TRANSISTORS
AND APPLICATIONS
Experiment 1 : The Static I.V Characteristics Of The Bipolar

Transistors
A. The objectives of this experiment are :

1- To measure the input characteristic and the output collector
characteristics.
2- To calculate the current amplification factors.
3- To determine the operating regions of the transistor.
4- To measure the leakage currents of the transistor ICEO and ICBO .
5- To determine the piece wise linear parameter model of the bipolar
transistor .
6- To define the safe operating area of the transistor .
B. Instruments and Components:

Two variable voltage power supplies 0-20 V / 100 mA, three digital
multimeters, Two channel oscilloscope with x-capability, A function
generator, the components of the circuit in Fig. 1.
Notice : If a curve tracer is available, then you don’t need any other
measuring instruments.
C. Procedure:
1- Connect the measuring circuit of the transistor as shown in Fig. 1 using
the experimental bread board.
IC VC
IB
VCE
VB
RB = 100 kΩ, RC = 0.5 kΩ

Fig. 1: The measuring circuit of the output collector characteristic
87
The voltmeters VB and VC are used to measure the voltage drops on RB and
RC respectively. One can calculate IB and IC from VB and VC using the ohm s
low, i.e.,
VB VC
IB = and IC =
RB RC
2- It is now required to measure a transistor curve, this can be accomplished

by keeping IB = IB1 = 10 µA for example and varying VCC from 0V up to
15V in steps while reading the corresponding VC and calculating IC. The
same procedure is followed for another transistor curve or a required IB
value IB2 = 20 µA and ISO on.
3- Tabulate your results as in the following table
Table of the I-V Characteristics “Output Characteristics”

VCE (V) 0.1 0.2 0.3 0.4 0.6 0.7 0.8 1 2 3 4 6 8 10
IC at 1 µ A
IC of IB = 10A
IC = 20 µ A
4- Now it is required to measure the input I-V characteristics :

This can be carried out as follows :
(i) Make RC = 0 , and adjust VCC = VCE as the desired value for an input
curve, the desired values are VCE = 0 VCE = 0.5 and VCE = 3V , This
characteristic is basically a diode characteristics.
IB
10 kΩ
VB
VBE
Fig. 2: Measuring circuit for the input characteristics
(ii) Connect a voltmeter across the base & emitter as shown in Fig. 2.
Vary VBB from 0 up to 10V and read VBE & IB = 100 VB µA.
88
(iii) Tabulate your results as shown in table 2
Table 2. The Input I-V C/cs
VBE (V) 0.1 0.2 0.3 0.4 0.5 0,6 0.7 0.8
IB at VCE = 0
VCE = 0.5
VCE = 3V
5- Plot on a millimeter paper the output and input c/cs of tables 1 and 2 on a
separate charts.
After finishing the plotting of the I-V curves perform the following :
a- Compare the input and the output characteristics with theoretical
transistor curves given in the lectures.
b-Determine the on, the off regions of the transistor and the active region.
c- determine the piece wise linear model of the transistor in the three
regions.
d- Calculate β dc and hfe , the ac β, from your curves. Why are they
different ?
e- Calculate the output collector resistance rce at IC = 5 mA and VCE = 5V .
f- Calculate the input resistance rbe at IB = 50 A and VCE = 1V .
g- Compare rce and rbe . Why are they different ?
6- The leakage currents of the transistor is very important for operating the
transistor as an electronic switch in the off-state. An ideal switch must
have zero leakage currents when it is off. Therefore, the measurement of
them is of prime importance. Now let us turn our attention to the
measurement of ICEO and ICBO. Two measure them use the measuring
circuits in Fig.3 .
VC VC
1 MΩ 1 MΩ
ICEO ICBO
ICEO = VC / 1MΩ = VC in µA ICBO =VC in µA
Fig. 3 Measuring Circuits of ICEO & ICBO
89
Notice that in order to be able to measure ICEO & ICBO because of there
extremely small values we used a large resistance in series with the
transistor to obtain measurable voltage drops.
Put the results in the form
VCE = 10V , ICBO = , ICEO =
Explain why ICEO is greater than ICBO .
7- From the transistor data sheet read

BVCEO =
BVCBO =
Pmax at room temp =
IC max =
Draw the boundary of the safe operating area of your transistor on the
output characteristics.
8- The transistor β of the transistor varies with the collector current. A fact
which must be taken into consideration when we design transistor circuits.
It is required to measure β as a function of the collector current and given
VCE say VCE = 1V.
IC
10 kΩ TUT
IB
VCE = 1 V
Fig. 4: Measuring circuit for β
- The procedure is straight forward, vary IB by charging VBB & measure the
corresponding IC as indicated in the measuring circuit of Fig.4 .
- Tabulate your results in a table like table 3.
Table 4. β versus IC at VCE = 1V
IB 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

IC
IC
β=
IB
- Then plot β versus IC.

- Explain the shape of the curve.
90
9- Curve tracing:
Curve tracing is a very useful technique by which one can display the
whole family of the device curves on a CRO screen. It saves time and
effort compared to the tedious point by point measurement. There are very
advanced carve tracer in the market with digital processing capabilities of
the acquired curves. In this experiment we shall demonstrate the curve
tracing concept using the conventional laboratory instrument, the
oscilloscope 9 the function generator, and a stair case generator.
To trace the transistor curves on the screen of a CRO we construct the set
up shown in Fig. 5.
To X of the
oscilloscope
DUT
Function
generator
Stair-case
generator
To Y of the
oscilloscope
Fig. 5: A curve trace is composed of a function generator, a stair case generator and an
oscilloscope
In order to trace a transistor curve the function generator must produce a

saw tooth of a period T as shown in Fig. 5. Therefore νCE will be
increased linearly in the time interval T. At the same time the stair case
generator must produce one of its stairs to keep the base current IB of the
transistor constant while sweeping the collector to emitter voltage by the
function generator. Therefore, the saw tooth must be also synchronized
with the stair case to obtain a stable display on the screen. Since the static
characteristics are required the time T must be sufficiently large for steady
state response of the device. On the other side , T must be sufficiently
small to avoid flickering of the displayed curves. A very suitable time T =
10 m seconds with a frequency of the sawtooth of 100 HZ.
Use the available function generator, the stair case generator and setting
RC = 1 kΩ and RB = 1== kΩ , trace the collector family of curves of the
transistor BC107 on the screen of the oscilloscope. Compare your
transistor curves with those measured point by point.
91
AND APPLICATIONS
Experiment 2 : The Small Signal Characteristics Of The Bipolar

Transistor
The small signal characteristics of the transistor is required when it is
used as a small signal amplifier where it is biased at certain dc operating point
in the active part of it I-V characteristics. The small signal response of the
transistor can be equivalently the h-parameters or the hybrid-π equivalent
circuit. The hybrid parameters are directly measurable while the hybrid-π
equivalent circuit parameters or internal physical parameters which could be
partly calculated and indirectly measured. The objectives of this experiment are:
- To set a suitable dc operating point of the transistor.
- To measure the h-parameters, hie, hfe , hre and hoe .
- To measure the transistor fT , the maximum operating frequency of the
transistor.
- To measure the junction capacitance of the collector.
- To check the equivalence of the two descriptions using the circuit simulator
SPICE.
Laboratory Instruments Required
- One power supply 0-20V/100 mA, one capacitance meter, a function
generator standard , an oscilloscope, a wide band ac voltmeter, Resistors,
the transistor under test, a digital multimeter, potentiometers.
The Experimental Procedure:

- Connect the measuring circuit as shown in Fig. 1
10 V
50 kΩ
10 kΩ
3
Pot. 1
1 10 µF
ib
10 kΩ 2 50 Ω
4
vb
Function
Generator
50 Ω
Fig. 1 : Measuring circuit for the h-parameters.
92
- Adjust the operating point such that VCE = 5V and IC = 1 mA , use pot. 1 to a
chive this
- Measurement hie by connecting the 50 Ω between point 3 and ground.
υ Vb
- By definition h ie = 'b = υ ce = 0 with short circuit between 3 &
db Ib
ground.
- Set the sin wave oscillator at f = 10 kHz and the amplitude is sufficiently
large so that νbe = 10 mV. One has to be sure that the small signal condition
prevails.
- Use the ac voltmeter to measure V1 and V2
V2
h ie = .Rs , Rs = 10 kΩ
V1 - V2
- To measure hre , remove the 50 Ω short circuit and insert instead the sine
wave oscillator. Adjust the oscillator at f = 10 kHz and output voltage of
10V. Then measure V2 using the ac voltmeter.
V
Calculate h re = 2
V3
- To measure hoe , the output conductance insert a current sensing resistance in
the emitter Re = 50Ω. For the same function generator connection and
settings as above Measure the ac voltage drop across the 50 Ω emitter
resistance.
 V4 
Calculate h oe =  
 R e V3 
- To measure hfe
The settings are as the measurement of hie with V3 must be also measured.
V3 x 10k
Calculate h fe =
50 Ω x ( V1 - V2 )
- To measure fT , measure hfe as described above as a function of freq. and

tabulate your results as in table 1.
Table 6. hfe versus f
hfe
f
The a plot hfe versus f and determine the freq. fβ at which hfe drops to 0.707
0f its value at low frequency hfeo .
By definition fT = hfeo . fβ .
- Compare your results with that given in the data sheet of the transistor.
93
- Now measure Ccb by using the RLC meter and the circuit shown in Fig. 2.
This value is measured at zero junction voltage
C cbo (measured value)
Calculate C cb (VCB ) =
1 + 2 VCB
RLC meter
Fig. 2. Measuring circuit for Ccb
- Now start calculating the hybrid-π parameters as follows :

IC 1 mA
gm = = = 0.04
VT 25 mV
VT h
rb 'e = = feo = 25 h feo
IB gm
rb 'b = h ie - rb'e
1
(C cb + ε b'e ) =
(2 π f β ) rb'e
rce = 1 / h oe
C cb = C cbo / 1 + 2 VCB
- Then compare the two equivalent circuits using the SPICE simulator.
- You may repeat for other operating points and frequencies.
94
AND APPLICATIONS
Experiment 3 : Bipolar Transistor As A Switch
1. Introduction
Transistors are now universally applied in switching circuits. They are
used in digital computers, communication systems and automatic control.
Any switch has the function to open and close current paths in an electric
circuit in a controlled way. Thus, the switch has two states, an off-state and an
on-state. According to the operating principles of various switches, they can be
classified into 1) mechanical, 2) electromechanical, 3) thermomechanical,
4) thermoelectronic, 5) optoelectronic and 6) electronic switches.
A switch which operates ideally has an infinite resistance when open and
zero resistance when closed, consumes no control power and changes state in
no time. In practice, there is no ideal switch. However, all efforts in the field of
switches are directed to approach some of these ideal switching characteristics.
Which properties most approach the ideal ones, it depends on the application
field of these switches.
2. Characteristics Of The Ideal Transistor Switch
2.1 The On-State

Fig. 1 shows the practical volt-ampere characteristic curve of a common
emitter junction transistor. Area I represents the saturation region of operation.
In this region the emitter-base (EJ) and the collector-base (CJ) junctions are
forward biased. Area II represents the active region operation of the transistor.
The emitter-base junction is forward biased while the base-collector junction is
reverse biased. Area III represents the off-region of operation, where the two
junctions are reverse biased. It is clear from the Fig. (1.b and 1.c) that for
certain load line the state of the transistor is completely defined by the base
current. If we draw on the same figures the characteristics of ideal switch, we
can easily see that, if IB ≥ IBS , the transistor approaches the on-state of the ideal
switch. The minimum collector to emitter voltage is called the saturation
voltage VCE sat. This voltage is a function of the collector current and it can be
expressed by
VCE Sat = VJE - VJC + I C max R C = f (I C max ) (2.1)
where VJE , VJC are the emitter and collector junction voltages, and RC is the
collector body resistance. This function is given in transistor data sheets. A
typical curve is shown in Fig. 1.d. At low collector currents, the ohmic drop
95
has no effect, however, as IC max increases the influence of the ohmic
component become appreciable.
The absolute maximum collector current, that the transistor can

withstand without failure is not limited by allowable power dissipation but it is
limited by other failure mechanisms.
2.2 Off-State
When Vin < 0, the transistor is in the off state, but a leakage current
passes through the transistor. If IB = 0 , i.e. the EJ is open circuit, the current is
very small and equal to ICEO . When EJ is short circuit the collector current IC =
ICS . For reverse biased EJ the collector current will be equal to the reverse
saturation current of the collector junction ICBO = ICO . A typical curve of ICO as
a function of temperature is shown in Fig. 1.e . From the two diode model of
the transistor shown in Fig. 2, we can derive the relation.
I CEO = (β + 1) I CO ,
Also we can prove that
ICO = (1 - αF αI) ICS .
Where α is the dc current amplification factor in common emitter circuit,

αF and α1 are the current amplification factors in the forward and reverse active
mode. Since α <1, ICEO > ICO. This means, it is better for loss leakage current
to reverse bias the EJ. The maximum collector to emitter voltage, which the
transistor can withstand in this off-state is limited by the collector junction
breakdown voltage.
3. Switching Times
3.1 Transition From Off To On-State Or Turn-On Time
In order to measure the switching times of a transistor, we drive it with
an input pulse as shown in Fig.3. At t < 0 the transistor is in the off-state (state
B on the I-V characteristic). At t = 0, although the pulse generator voltage ein
changes abruptly and hence the base current (IBF = ein/RB), the collector current
as shown in Fig.3 increases firstly slowly with time, then rapidly and finally
reaches a steady state value IC max , which corresponds to state A. The turn-on
time ton can be divided in two parts, the delay time td and the rise time tr. The
delay time is by convention the time taken by the collector current to reach 10%
of its steady state value (IC max). The rise time is the time required for the
collector to change from 10% to 90% of its steady state value.
3.2 Transition Time From The Off-To The On-State Turn-Off Time
At t = τ1 the input voltage changes its polarity and magnitude
instantaneously as shown in Fig.3. The collector current does not fall abruptly
to its off value, see Fig.3. Instead, it continues to flow with its on-value IC max
96
for certain period, then falls rapidly with increasing time and it reaches finally
its off-value.
The turn-off time can be divided also into two parts. The storage delay
time (simply storage time), ts and the fall time. Storage time ts is the time from
input voltage reversal till the collector current falls to 90% of it’s on value IC
max , while the fall time tf is the time required for the collector current to fall
from 90% to 10% of IC max .
3.3 Switching Times As A Function Of Transistor Currents And Internal

Physical Parameter-Theory
In order to determine the dependence of the collector current on time and
consequently the switching times for an applied control pulse, there are
different methods depending on the degree of approximation. In order to
complete the picture, these methods are :
i) Exact solution of the time dependent continuity, Poisson and current
equations for given initial and boundary conditions.
ii) Using approximate models for transistor, such as charge control model and
modified Ebers-Moll two diode model.
In this study we shall use a simplified charge control model. The first
assumption is that the emitter and the collector injection efficiencies are equal
to one. This means that we shall neglect the recombination current in the
highly doped emitter and collector regions. The consequence of this
assumption is that the base current supplies or extracts majority charge carriers
to or from the base region only. A fraction of these charges can be stored, or
extracted and the other fraction recombines with minority charge carries
injected in the base region. In steady state, where there is no change of charge
density with time, the base current has to supply the recombination losses only.
From the law of conservation of electric charges, we can now write :
 d Q B (t)  Q B (t)
i B (t) =   + (3.1)
 dt  τB
where iB is the base current, QB(t) is the excess minority charge carries in the
base region, dQB/d t is the rate of change of stored base charge with time. QB/τB
is the recombination rate, or the charge recombined per unit time. τB is the
lifetime of the minority charge carriers in the base region.
3.3.1 The Turn-On Time ton

Fig.4 shows the minority charge carrier distributions in the base region
for the off-state B and for the on-state A without and with saturation (VCB = 0
& VCB < 0). We shall assume that the magnitude of the base current step IB1 is ≥
IBS. In order to bring the transistor from state B to state AI, the base current has
to charge the space charge region of the Ej and to build up the charge QF. If IB >
97
IBS, the transistor goes to state A2, where an additional saturation charge QS will
build up, but the collector current reaches approximately its steady state value
IC max , once QF is stored, (See Figs. 1.b & 1.c).
Solving equation. 3.1 with the initial conditions QB(0) = 0 and taking into
consideration that IB(t) = IB1 (0 ≤ t ≤ τ1). We get for QB(t) the expression :
(
Q B ( t ) = I B1 τ B 1 - e
-t / τ
B
) (3.2)
The second assumption in the charge control model is that the collector current
ic(t) at any time t is proportional to QB(t) . Hence
Q B (t)
i C (t) = (3.3)
TC
where TC is called the collector time constant. It is equal to the transit time of
the minority charge carries predominately by diffusion in the base region. It
can be expressed by TC = WB2 / 2 D , where WB is the neutral base thickness
and D is diffusion constant of the minority charge carriers.
Substituting equation (3.3) in (3.2), we can write
(
i C ( t ) = β I B1 1 - e
-t / τ B
) (3.4)
with β = τB/TC is the current amplification factor of the CE circuit.
Substituting iC(ton) = 0.9 IC max in equation. (3.4) and rearranging, we get an

expression for the on-time
 
 
1
t on = τ 1n   (3.5)
 0.9 I C max 
1 - 
 β I B1 
β I B1
The ratio β I B1 / I C max ≡ = m , , is the called overdrive factor. As a
β I BS
result, (3.5) reduces to
 
 1 
t on = τ 1n   (3.6)
 1 - 0.9 
 m
For m >> 1, equation. (3.5) can be rewritten as
98
 0.9 
t on ≈   (3.7)
 m 
which means that the turn-on time is inversely proportional to the overdrive
factor m.
3.3.2 The Saturation Charge QS

The total base charge QB = QF + QS in the on-steady state can be expressed by
Q F + Q S = I B1 τ B (3.8)
d Q B (t)
which follows from equation. (3.1) with = 0 & i B (∞ ) = I B1
dt
Since QF = τ IBS , then
Q S = τ B (I B1 - I BS ) = τ B I BS (m - 1) (3.9)
3.3.3 The Turn-Off Time

The turn-off is the inverse process of turn-on. The excess charges in the
neutral base region must vanish during the turn-off phase. It is clear from the
continuity equation (3.1) that by making IB zero or by reversing it d QB(t)/d t
will be negative, this means that the charge stored in the base can be removed
by a negative base current and by the recombination process. The rate of
removal of this charge will be greater if the reverse base current is increased.
This means that the turn-off time decreases with increasing the reverse base
current IB2 .
During the whole turn-off phase, the reverse base current is

approximately constant and equal to I B2 . Therefore, solving equation. (3.1)
with the initial condition QB(t) = QF + QS = IB1 τB we obtain QB(t) .
Q B (t ) = τ B (I B1 + I B2 ) e -t / τ B - I B2 τ B (3.10)
At t = tS , Q B(t) = QF = I BS τB .This means that the saturation charge will be

removed during the storage delay time. Hence, it follows from equation.(3.10)
that
 m + n
t s = τ B 1n  
 1 + n
with
I B1 I
m = and n = B2 ≡ the reverse overdrive factor.
I BS I BS
If n > m >1, then, the above equation reduces to
99
τ B (m - 1)
ts ≡ (3.11)
n
The turn-off transients ends when the excess charge is reduced to zero,
therefore from equation. (3.10) we get
 m m
t off = τ B 1n  1 +  ≅ τ (3.12)
 n n
from n > m > 1 and (IB2 > IB1 > IBS), the fall time
tf = toff - ts = τB/n (3.13)
It is clear from equation. (3.12) that the turn off time will be reduced by
increasing the reverse base current. But it increases with increasing the
overdrive factor m. This means that if we increase the overdrive factor to
decrease the turn-on time the turn-off time increases because of the increase in
the saturation charge QS .
4. Experiment
4.1 Objectives
The aim of this experiment is to analyze the basic switching
characteristics of the transistor and to investigate some of the methods of
improving its transient responses.
4.2 Test Circuit

The test circuit is shown in Fig. 5. It consists of the transistor under test t
in common emitter circuit. The collector is connected in series with a load
resistance RL, a dc collector power supply and 47Ω current measuring
resistance. A resistance RB is inserted in series with the base lead in order to
limit the base current. At the same time the base current can be determined by
measuring the voltage drop across RB, connectors. The 47Ω resistances are
used to match the coaxial cables.
4.3 Instruments Required

- Pulse generator.
- Power supply 10-15 volt variable.
- Dual channel oscilloscope.
4.4 Procedure
(a) Connect the measuring circuit as shown on Fig. 5.
(b) Observe and record the shape of the waveforms of the input voltage ein, the
base current iB(t), the collector current iC(t) and the collector to emitter
voltage VCE(t) at different values of forward base current IB1. Hence,
100
determine the transfer characteristics shown in Figs. (1.c) and 1.d).
determine the value of the large signal current amplification factor β from
the relation β = IC max /IBS. IBS is the value of the base current at VCB = 0 (i.e.
IB1 = IBS at VBE = VCE).
(c) Measure the on-time ton at I B2 = 0 and I B1 = IBS … 10 IBS
(d) Measure the storage time tS and the fall time tf at I B2 = 0 and I B1 = IBS …
10 IBS
(e) Measure the storage time tS with I B2 = 2 IBS and I B1 = 2 IBS
(f) Plot the measured values in (c), … to (e) on log-log papers.
(g) Determine the standard switching times td, tr, ts and tf at
IB1 = - IB2 = IC max /10 .
(h) Compare the experimental results with theoretical. Determine the lifetime
τB of the minority charge carriers in the base from the experimental curves.
Then calculate the neutral base width WB from the relation
WB = 2 D n τ B / β , given that Dn = 50 cm2/sec.
(i) Connect the given condensers in parallel with RB. Observe and record the
collector and base current wave-forms without and with the condensers at
IB1 = IBS. Explain the reduction of the switching times by the condensers.
101
IC
IB
Fig. 1a: Transfer characteristic measuring circuit
The static transfer characteristic
α ICEO
B ICO
E ICEO C
Fig. 2 : Transistor equivalent circuit with open base

102
Fig. 3 : Switching times
Fig. 4: The electron distribution in the base region at

a) off-state
b) on-state AI - edge of saturation region
c) on-state AII - heavy saturation
vce(t)
To Y1 of the
To Y1 of the To Y2 of the oscilloscope
oscilloscope oscilloscope
Ω
10kΩ
ic(t)
Pulse To Y2 of the
Generator oscilloscope
Rm =
97 Ω
Fig. 5: The measuring circuit of the transistor switch
103
AND APPLICATIONS
Experiment 4 : The Basic BJT Amplifier Circuits
Introduction :
There are three basic BJT amplifier circuits, the common emitter, the
common base and the common collector or the emitter follower. Any linear
amplifier is characterized by its voltage gain AV, current gain AI and hence its
power gain in addition to its input and output impedance. The frequency and
phase response is also of interest objectives.
- Measuring the characteristics of the three configurations
- Comparing the three configurations.
- A dc power supply 20 V/1A, multimeter, function generator and a two
channel oscilloscope.
A- The CE Amplifier
Procedure :
1- Connect the measuring circuit as shown in Fig. 1
To Y2 of the
oscilloscope
10 µF
2
1
10 µF 10 kΩ
10 kΩ
Function
Generator 10 kΩ 100 Ω
10 µF
To Y1 of the
oscilloscope
Fig. 1
2- Set the operating point such that VCE = 5V by varying R1

3- Disconnect RL and measure the voltage gain of the amplifier at 1 kHz. This
is accomplished by inserting a small input voltage Vbe ≈ 20 mV - 50 mV
and measuring Vce. Both Vbe & Vce will be observed and measured by an
oscilloscope. calculate the gain of the amplifier Av
104
Vce
Av =
Vbe
4- Now measure the ac base current by meaning the ac voltage drop on RB
calculate the current gain by
i υ / Rc
A t = c = ce
ib υb / RB
5- calculate the input resistance
υ
γ i = be
ib
6- Measure the output resistance by applying the signal generator to the output
between point (2) & ground and shorting the input between 3 and ground
as shown in Fig. 2
10 µF Pot. 2
10 µF
10 kΩ
10 kΩ 100 Ω
10 µF Function
Generator
Fig. 2 : Circuit to measure ro
First make the resistance of potentiometer 2 = 0 and measure υce by the

oscilloscope : Then increase gradually the pot 2 resistance till υce becomes one
half its original value. Then connect the function generator and measure the
resistance of the potentiometer 2 using an ohmmeter. This value will be the
output resistance of the amplifier . These measurements must be carried out at
the freq. range where the amplifier characteristics are independent of frequency.
Be sure of that by sweeping the freq. and observing oscilloscope waveforms.
• Now let us study the effect of loading by connecting a pot 3 across the
output in Fig. 1. Observe the waveforms of the input y1 and the output y2 by
decreasing RL and comment on your results.
• Now disconnect RL and increase the input voltage observe the waveforms
of y1 & y2 and comment on your results. This is to study the effect of large
input signal on the waveforms of the amplifier.
• Calculate Av, AI, ri , and ro using the small signal equivalent circuit and
compare with your measured values.
105
B- The CB Amplifier
Procedure :
1- Connect the measuring circuit as shown in Fig.3
To Y2 of the
oscilloscope
10 µF
10 µF
10 µF 10 kΩ
10 µF 100 Ω
10 kΩ
10 µF
Function
Generator
To Y1 of the
oscilloscope
Fig. 3
This circuit is basically as the CE in Fig. 1 with some modifications. Now

the base is ac by passed to the ground to achieve the common base
configuration. The input signal is inserted at the emitter and the output is
taken from the collector.
2- Adjust the operating point at VCE = 5B as in the CE case by varying [pt 2
and monitoring VCE by the digital multimeter.
3- Measure the voltage gain by
- Setting the freq. of the signal generator to f = 1 kHz.
- Setting υeb = 10-20 mV by adjusting the amplitude of the function
generator and pot 1.
- Observe the wave forms of y1 & y2 corresponding to υeb & υce
respectively and measure their peak values and hence calculate
V
A v = cem = ………..
Vebm
- Measure the current gain by measuring the voltage drop across the pot 1
and browning its resistance value. Then calculate
ic Vpot 1 / R pot 1 Vcem / R c
AI = =
ie Vpot 1 m / R pot 1
- Measure the output resistance in the same manner as carried out for the
CE amplifier.
- Measure the input resistance by
106
Vebm Vebm
γi ==
I em Vpot 1 m / R pot 1
- Study the effect of RL on the input and output waveforms and the
voltage gain of the amplifier by changing the value o RL, pot 3: comment
on your results.
- Study of effect of increasing the input voltage on the input and output
waveforms here it is required to observe the distortion of the output. The
output waveform becomes clipped at relatively large input voltage.
Record some oscillograms showing this clipping.
- Calculate the amplifier parameters using the equivalent circuit and
compare with the experimental results.
C- The Common Collector Amplifier

Procedure :
1- Connect the measuring circuit a shown in Fig.4
10 µF
100Ω
47 kΩ
vb
10 µF
100 kΩ
To Y2 of the
10 kΩ 10 µF oscilloscope
RE =
Function 1 kHz
To Y1 of the 1 kΩ 10 kΩ
Generator
oscilloscope
Fig. 4. Common Collector Amplifier Circuit
2- Adjust the dc operating point as before at VCE = 5V.

3- Measure the voltage gain of the amplifier by
- setting the freq. of the function generator to 1 kHz.
- the input voltage at y1 at one volt peak to peak
- observe the output voltage waveform at y2 and measure the peak to peak
value.
- calculate the voltage gain
Vepp
Av =
Vbpp
4- Measure the current gain by measuring the ac voltage drop at pot 1 and its
resistance R pot 1 then calculate
107
ie Vem / R E
AI = =
ib Vpot 1 m / R pot 1
5- Measure the output resistance in the some manner as the CE circuit but here
use a 100 ohmmeter potentiometer in series with the function generator
connected to the output.
6- Study the effect of loading on the gain and the waveforms of the amplifier
as due previously.
7- Study the distortion of the waveforms when driving the amplifier with
increased input signal.
8- Calculate the amplifier parameters using the equivalent circuit & compare
with the measured values.
9- Make a comparison table for the three configurations.
108
AND APPLICATIONS
Experiment 5 : AC Coupled Amplifiers
Purpose
1- To demonstrate resistive-capacitive coupling.
2- To evaluate the advantages and disadvantages of resistive-capacitive.
3- To demonstrate some of the applications requiring reactive coupling.
Introduction
During this experiment you will examine two types of coupling. One has
a wide range of applications, the other is used less often because of its unique
characteristics. Similar to the previous experiment, you will connect two
amplifier stages using each of the coupling methods. Your will then consider
the advantages of each.
You will first consider the RC coupling method. Resistive-Capacitive
coupling is the most commonly used method of linking amplifier stages
together. Using this type of coupling, the transistor’s output load is a resistance.
Two common emitter amplifiers will be tied together through a capacitor. Keep
in mind during this portion of the experiment that the output signal from the
first stage must pass through the coupling capacitor to reach the second stage.
Later in this experiment, you will observe the operation of transformer
coupling. As the name implies, the first stage is coupled to the second stage
through transformer action. This method of coupling is sometimes used as an
impedance matching device between amplifier stages. It can also be used to
step up or step down a signal between stages. It also provides isolation
between stages because there is no physical connection between the first and
second stages. The signal transfer is caused by electromagnetic induction.
Procedure
1- Connect the measuring circuit as shown in Fig. 1 the circuit is composed of
a CE npn- and pnp amplifiers coupled with 10 µF capacitor.
Set the freq. of the function generator to 1 kHz.
2- Set the generator at a frequency of 1000 Hz.
3- Center potentiometers R103 and R106. Turn your trainer on.
4- Connect channel 1 scope probe of your oscilloscope to TP100.
Adjust the input signal’s amplitude to 0.2 volts peak-to-peak.
5- Look at Figure 1 and list the coupling component in this circuit.
109
Function
Generator
Fig. 1
6- Connect channel 2 of your oscilloscope to monitor the output waveform at

TP107.
Adjust R103 and R106 until a sine wave is present at TP107.
7- Move channel 2 scope from TP107 to TP102.
What is the peak-to-peak amplitude of the waveform at TP102 ?
______ volts peak-to-peak
8- Momentarily turn SW101 off.
Position 8 opens the signal path between the two amplifier stages. Again
measure the peak-to-peak amplitude of the voltage at TP102.
9- Turn SW101 on.
Did the waveform amplitude change in steps 6 or 7.
___________________________________________________
Why did this change in amplitude occur ?
___________________________________________________
10- Continue to monitor TP102, the output of the first stage, on channel 2 of
your oscilloscope. Move channel 1’s scope probe to TP105, the input of the
second stage.
Is there any difference in the amplitude of these two signals (TP105 and
TP102) ?
Measure the DC voltage at TP102 and TP105.
TP102 _____ VDC TP105 _____ VDC
Explain your answer.
___________________________________________________
11- Move the scope probe from TP105 to the output of the second stage
(TP107).
Change the amplitude of the input signal to the first stage (Q101), by
adjusting R808.
What happened to the output at TP107 and why ?
___________________________________________________
12- Move the scope probe from TP102 to TP100.
Readjust the input voltage to 0.2 volts peak-to-peak.
110
Now, vary the input frequency from its minimum to maximum value.
What can you say about the frequency response of this circuit ?
___________________________________________________
f (Hz) 10 30 100 300 1k 3k 10k 30k

V
Gain = o
V
i
Implement the transformer coupled circuit shown in Figure 2 :
Function
Generator Jumper
Wire
Fig. 2
.
13- Set the Generator frequency to approximately 20 kHz.
14- View the output of the first stage by touching your oscilloscope probe to
TP102. Record the amplitude of this waveform below.
15- Momentarily remove the output lead of this first stage by removing the
jumper wire from TP810.
Again view the output of the first stage at TP102.
Record the amplitude of this waveform below.
16- What happened to the amplitude of the sine wave at TP102 when the
jumper lead was removed from TP810 ?
Increased/decreased/stayed the same
Why do you think this occurs ?
___________________________________________________
17- Reverse the jumper wires to TP810 and TP811.

What affect did this have on the input and output signals ?
___________________________________________________
18- Turn your trainer off and read the following summary.
111
Summary
During steps 1 through 11 of this experiment, you observed the
operation of an NPN common emitter amplifier. RC coupled to a PNP common
emitter amplifier. This type of coupling is one of the most widely employed
methods of coupling. When NPN and PNP transistors are used in pairs they are
said to be a complementary pair.
You should have measured an approximate 1.75 volt peak-to-peak sine
wave at TP102. You then momentarily turned SW101 position 8 off to isolate
the first stage from the second. With an open between stages, the output from
the first stage increased to approximately 2 volts. This increase is due to the
removal of the AC loading of the second stage. This circuit used capacitive
coupling. There is no DC loading because capacitors block DC.
The input to the second stage at TP105 is approximately the same as the
output at TP102. Capacitor C102 couples the entire signal. There is very little
AC loss across coupling capacitors.
When you adjusted the 100 k ohm potentiometer (R808) during step 1,
the output distorted as you increased the input voltage. With no input, Q101 is
operating near the midpoint of its operating range. As the input is increased,
Q102 is driven alternately into saturation and cutoff. This causes both the
positive and negative peaks of the output waveform to be clipped.
As the input frequency was varied in step 11, there was little if any
changes in either the amplitude or the shape of the output waveform. Capacitive
coupling can be used for a wide range of frequencies. However, at the lower
frequencies a large valued coupling capacitor is required. The lower limit is a
few Hz for this type of coupling. The upper frequency limit is set by the
characteristics of the transistor used in the amplifier.
During steps 12 through 16 you investigated transformer coupling.
Transformer coupling is used to couple a high impedance output to a few
impedance input ideally, this is done by adjusting the turns ratio of the
transformer's input and output windings. However, an exact match is virtually
impossible because of component tolerances. Transformer coupling has the
advantage of being able to step-up or step-down signal voltages. It also
provides isolation between stages because the same current is not flowing in
both stage.
In step 11, the first stage output was found to be about 1.9 volts peak-to-
peak. You then removed the first stage from the second stage and found little
change in the output at TP102. The second stage does not load the first stage to
any great extent as it did in the first part of this experiment.
Other problems encountered when using transformer are that it can not
couple DC signals and that it is relatively expensive when compared to resistive
or RC coupling.
When you reversed the leads (TP810 and TP811), you reversed the
polarity of the output signal. Thus with transformer coupling you can also
couple a signal in-or out-of-phase.
112
AND APPLICATIONS
Experiment 6 : Direct and Resistance Coupling
Purpose
1- To demonstrate direct and resistive coupling.
2- To evaluate the advantage and disadvantages of direct and capacitive
coupling.
3- To demonstrate type of circuits that normally utilize direct and purely
resistive coupling.
Introduction
In many applications it is necessary to interconnect, or couple, two or
more amplifier stages together. It is important that the signal is not altered from
the output of the first stage, to the input of the second stage, by the coupling
circuits.
There are a variety of ways to couple amplifier stages. In many

instances, coupling methods are suited to some application but not others. In
this experiment, you will utilize direct and resistive coupling to connect two
amplifier stages. You will observe the advantages and disadvantages of each
method and an example of the type of circuit that utilizes types of coupling.
Procedure
1- Connect a jumper wires from TP102 to TP105. Refer to Figure 1, is the
first stage of this circuit configured as a common emitter, base, or collector
circuit ?
___________________________________________________
What is the circuit configuration of the second stage ?

___________________________________________________
Function
Generator
Fig. 1
113
2- Which adjustment (R808, R103, or R106) now has the most effect on both
the input and output waveforms ?
___________________________________________________
Explain why ?
___________________________________________________
Which adjustment (R808, R103, or R106) now has the least effect on both
the input and output waveforms ?
___________________________________________________
Explain why ?
___________________________________________________
3- Move channel 2 scope probe from TP106 to TP107.

Is there an output waveform at TP107 ?
___________________________________________________
Explain the cause of the condition of the output waveform at TP107.
___________________________________________________
4- Remove the jumper wire between TP107 and TP108.

When the output is taken from the collector of Q102 (TP107) and with
R109 in the circuit as shown in Figure 3, is the second stage of this circuit
configured as a common emitter, common base, or common collector ?
common ________________
5- Turn your trainer off. Remove the jumper wire between TP102 and TP105.
Place jumper wires between the following points :
TP102 and TP832.
TP105 and TP831.
Figure 2 shows the revised circuit.
Notice that the two amplifier stages are now coupling through a variable
resistor (R809).
Function
Generator
Fig. 2
6- Adjust the generator frequency to 1000 Hz.
114
7- Turn R809 fully counterclockwise. In this position there is little or no
resistance offered by R809. The circuit is effectively direct coupled.
Turn the trainer on and again monitor the output at TP107 with channel two
of your oscilloscope.
8- Measure the DC voltage level at TP105. Record the voltage below.
_______________ VDC
9- Slowly turn R809 clockwise until a sine wave output is obtained. If you
cannot obtain a full sine wave output, readjust R106 and R103. Measure
the DC voltage level TP105. Record the voltage below.
_______________ VDC
10- Compare the polarity of the voltage levels measured in steps 8 and 9. Did
the polarity change ?
___________________________________________________
11- How does this polarity changes affect Q102 ?
___________________________________________________
12- Slowly increase the resistance between the stages by turning R809
clockwise.
What happens to the output at TP107 as the resistance of R809 is
increased?
___________________________________________________
13- Explain the result you obtained in step 22.

___________________________________________________
___________________________________________________
14- Vary the frequency from 200 Hz to 20 kHz.

What affect does this have on the output signal’s amplitude, frequency, and
phase.
___________________________________________________
15- What is the phase relationship between the input signal at TP100 and the
output signal at TP107 ?
___________________________________________________
16- What is the approximate gain of the first stage ?

___________________________________________________
17- What is the approximate gain of the second stage ?

___________________________________________________
Turn the trainer off and read the following summary.
115
Summary
During steps 1 through 2 you referred to Figure 2 and noted that the first
stage of this circuit was configured as a common emitter amplifier. You also
noticed that the second stage was configured in the common collector
configuration. You then changed the second stage of the circuit to a common
emitter circuit by removing the jumper wire between TP107 and TP108 and
taking the output at TP107. When you opened SW101 position 4, the output of
the first stage increased because you opened the signal line to Q102 which
decreased the load on Q101.
In step 3 you placed a variable resistor between the two stages. This type
of coupling is commonly referred to as resistive coupling. In this type of
coupling, a resistor is placed in series with the signal path. R809 is the series
resistance in this part of the experiment. R809 allowed you to control the
resistance between the stages as well as the DC voltage at the base of Q102.
When R809 was set to its minimum value, the DC voltage level at TP105 was
approximately 5.7 volts which caused Q102 to cutoff.
You then increased the resistance of R809 until a negative voltage was
applied to TP105. You again measured the DC voltage level at TP105 and
found it to be between -0.4 and -2.4 volts DC. This polarity change allowed
Q102 to conduct in its linear region.
As you continued to increase the resistance between the two stages the
amplitude of the output began to decrease as the current flow between the
circuits was limited. Thus, the output from Q101 increased slightly or remained
unchanged while the output from Q102 decreased as you increased R809’s
resistance.
In both direct and resistive coupled circuits, the biasing is critical. The
entire circuit is extremely sensitive to changes in the output current of Q101. As
you proved, the operating point of Q102 is determined by the value of R104
and the coupling resistance R809.
When you changed the frequency from 200 Hz to 20 kHz you probably
noticed that it has little if any effect on the input or output signals. You should
have also seen that the input and output signals were in phase (double
inversion). The first sage (Q101) has a gain of approximately 8 and Q102 has a
gain of approximately 5. However, the over all gain is (0.3 volts at TP100 to
204 volts at TP107) 8 instead of the (5 x 8) 40 that you may have expected.
This is because the signal is passed through R809 (the coupling resistor).
Resistive and direct coupling are normally used in low frequency or DC circuits
where gain is not as important as accuracy.
116
AND APPLICATIONS
Experiment 7 : Multi-transistor Amplifier
A- The Darlington Amplifier

In this experiment it is required to measure the characteristics of the Darlington
amplifier.
Instruments Required
- Power supply 0-∞ V/1A
- Multimeter
- Function generator
- Oscilloscope
Procedure
- Connect the measuring circuit as shown in Fig. 1
470 kΩ 10 µF
10 µF
Function
Generator 10 kΩ
Pot. 1 50 kΩ 10 µF
Pot. 2 100 Ω
Fig. 1
- Set the operating point at IC = 5 mA by adjusting potentiometer 2.
- Now measure the transistor currents of Q1 & Q2. Q1 is the driver of Q2. Then
calculate
I I
β1 = C , β 2 = C2
I B1 I B2
and the overall current gain of the Darlington
I
β = C
I B1
- Measure the amplifier parameters as you exactly did for measuring single
transistor CE stage. The required parameters are :ri , ro , Ai and AV
ri = ___________,
ro = ___________,
117
Ai = __________,
AV = __________.
- Compare with the single transistor CE amplitude stage.
B- The Composite pnp-transistor

Instead of driving an output npn transistor with another npn-transistor in
a Darlington pair, one can drive it with an pnp transistor. The whole
configuration works an a pnp-transistor.
In this experiment it is required to measure the characteristics of this

composite pair by an amplifier stage.
Procedure
- Connect the measuring circuit as shown
Pot. 2 100 Ω 10 µF
50 kΩ
10 µF
Q1
Q2
Function 470 kΩ
10 kΩ
Generator 10 µF
1 kΩ
Fig. 2
- Set the operating point of IE2 = 5 mA by adjusting pot 2.
- Measure the transistor currents of Q1 & Q2. Then

I I I E2
Calculate β 1 = C1 , β 2 = C2 & = β the over all current gain.
I B1 I B2 IB
β1 = _________________ , β2 = ____________________,
β = __________
Check that β = B1 (B2 + 1)
- Measure the amplifier parameters

ri = ___________,
ro = ___________,
Ai = __________,
AV = __________.
- Compare with the single common emitter stage.
118
C - The Differential Amplifier
The differential amplifier amplifies the difference between two signals.

In is characterized by direct coupling and hence it is one of the basic building
blocks of the analog integrated circuit. In this experiment it is required to
measure the performance parameter of this amplifier.
Procedure
- Connect the measuring circuit as shown in Fig. 3.
4.7 kΩ 4.7 kΩ
10 kΩ VBE1 VBE2
Function 200 Ω 10 kΩ
Generator 33 kΩ
47 kΩ
2.2 kΩ
Fig. 3. Measuring circuit of the differential amplifier
- Adjust the power supply at ± 5V.
- Adjust the voltage of the test point TP7 at 2.9V.
- Balance the circuit by connecting a dc voltmeter between TP3 and TP4 and
adjusting pot 2 for zero voltage between the two collector.
- Now measure the voltages at all test points, then calculate the current in each
resistance compare the operating conditions of each transmitter.
- Connect TP1 and TP2 together and apply a relatively large signal ≈ 1V at the
input from the function generator will a frequency of 1 kHz. Measure the ac
voltage difference between TP1 and TP2 using the two channel oscilloscope
or and an ac voltmeter. Then calculate the common mode gain Ac
Ac = Vo/Vi = ________________
- Now measure the difference mode gain by applying the function generator
to test point 1 while grounding TP2. Adjust the amplitude of the function
generator to about 50 mV and f = 1 KHz. Observe the waveforms at TP3 and
TP4 and measure Vo . The different gain
V
A d = o = ________________ .
Vi
119
- Calculate the common-mode rejection ratio
Ad
CMRR = = _________________
Ac
- Calculate the dc input offset voltage Vos

Vi os = VTP1 - VTP2 = ___________________
- Measure the frequency response of the amplifier.
- Calculate these parameters and compare with the measured parameters.
D- The Cascode Amplifier

The cascode circuit sums the merits of the CE and the CB such that it
can amplify signal at high frequency. In this experiment it is required to
experimentally study this circuit.
Procedure
1 kΩ
10 kΩ
10 µF 10 µF
2.7 kΩ
10 kΩ 10 µF
Function
Generator vi 4.7 kΩ 10 µF
100 Ω
Fig. 4
- Adjust the dc operating conditions as follows :

IC = 5 mA , VCE1 = VCE2 = 2.25V
- Measure the frequency response of the amplifier by adjusting Vi = 20 mV

and measuring Vo at frequencies starting from 10, 30, 100, 300 Hz ….. up to
the highest possible frequency. Use in the measurement either the
oscilloscope or a wide band, ac voltmeter.
- Compare with the common emitter only.
120
AND APPLICATIONS
Experiment 8 : Push-Pull Amplifier

1. Objective
To study the operating principles of the push-pull amplifier and the fault
finding in the two stage amplifier circuits.
2. Theory
2.1 Classification of Amplifiers
Amplifiers are described in many ways, according to their frequency
range, the method of operating, the ultimate use, the type of load, the method of
interstage coupling, etc. The position of the quiescent point and extent of the
C/Cs that is being determine the method of operation.
A. Class A
A class a amplifier is one in which the operating and the input signal are
such that the current in the output circuit (in the collector electrode) flows at all
times.
B. Class B
A class B amplifier is one in which the operating point is at the an
extreme end of its C/Cs, so that the quiescent power is very small. Hence either
the quiescent current or the quiescent voltage is approximately zero. If the
signal voltage is sinusoidal, amplification takes place for only one-half a cycle.
C. Class AB
A class AB amplifier is operating between the two extremes defined for
Class A and class B. Hence the output signal is zero for part but than one-half
of an input sinusoidal signal cycle.
D. Class C
A class C amplifier is one which the operating point is chosen so that the
output current (or voltage) is zero for more than one-half of an input sinusoidal
signal cycle.
2.2 Push-Pull Output Stage

In the class B amplifier, the dc collector current is less than the peak AC
current. Thus less collector dissipation results, and the efficiency increases. The
relation of power and efficiency are as follows .
121
Fig. 1
The AC load line has a slope of :

ic I
=
VCE RL
The maximum value of both ic1 and ic2 is:
V
I cm = CE
RL
The maximum supplied power is :
2 Vce2
Pccm =
π RL
The maximum power transferred to load :
Vce2
PLm =
2 RL
The maximum power dissipated in each collector is :
1 Vce2
Pcm = 3
π RL
The maximum efficiency is :
π
ηm = ≈ 78.5 %
4
2.2.1. Amplifier Using Complementary Symmetry

Fig. 2 illustrates a type of push-pull class B amplifier which employs one
pnp and one npn transistor and requires no transformers. This type of amplifiers
uses complementary symmetry.
Its operation can be explained by referring to the figure. When the signal
voltage is positive, the npn transistors conducts, while the pnp transistor is cut
off. When the signal voltage is negative the operation is reversed.
The advantage of the configuration is that it is transformerless, and the

disadvantage of is the need for both positive and negative supply voltages and
122
the problem of obtaining pairs of transistors matched closely enough to achieve
low distortion.
The load-line and output-circuit power relation for this amplifier for this
same as for the conventional class B amplifier.
Fig. 2
3. Required Components and Equipment

2 Transistor DC140
1 Transistor BD136
1 Transistor BD138
2 Diode IN4007
2 Resistor 10 Ω
1 Resistor 100 Ω
1 Resistor 5.6 kΩ
1 Resistor 27 kΩ
1 Resistor 330 kΩ
1 Resistor 150 kΩ
1 Resistor 470 kΩ
1 Resistor 1.5 kΩ
1 Resistor 4.7 kΩ
1 Resistor 10 kΩ
1 Resistor 330 kΩ
1 Capacitor 47 kΩ
1 capacitor 0.47 µF
2 capacitor 1 µF
1 Pot. 4.7 kΩ
1 Pot 100 kΩ
1 Two-Channel Oscilloscope
1 Multimeter
1 Power Supply +/- 7.5 V/3A
1 Function Generator
123
4- Procedure
4.1. Setting of the Complementary output Stage
1- Assemble the circuit as shown in Fig. 3 and leave the bases of the
complementary transistors open.
2- Apply the operating voltage and set the collector potential of V2 to approx.
-0.7 using R2.
3- Connect the output stage transistor as in Fig. 3 (still without load resistor
RL).
4- Set the potential at point A to 0V with R5 .
Fig. 3
4.2. Determination of the Voltage Gain

1- Apply a peak to peak value of UEPP =30 mV at the input with the function
generator, if necessary use a voltage divider.
2- Using the oscilloscope measure the output voltage and calculate the voltage
gain.
3- Connect the load resistor RL = 100Ω between point A and ground and
determine UAPP and the voltage gain Vu again.
4.3. Power and Efficiency Calculations

1- Connect the circuit as in Fig. 3.
2- Connect the function generator to the input of the circuit and adjust the
frequency to 10 kHz.
124
3- Measure the voltage waveform UA , V(R6) and V(R7) and find the peak
value of the collector current Icm .
4- Calculate the load power PL supplied power Pcc , collector power
dissipation Pc and efficiency η1 for the push-pull pair.
5- Change the amplitude of the input voltage and repeat steps 3 and 4.
6- Plot PL , Pcc , Pc and η vs. Icm .
4.4. Representation of Nonlinear Distortion by Shifting the Working Points

1- Raise the input voltage UE and adjust R2 until the output voltage shows
clear distortions (RL connected).
2- Assumption R2 is set. To 0Ω. Describe the shift in the working point and
the effect on the output voltage.
3- Additionally, distortions can occur from adjusting R5 or from increasing the
input voltage. Display, for each, the distorted output voltage on the
oscilloscope and explain the curve shapes.
Fig. 4
125
4.5. Fault Finding in the Two-Stage Amplifier
4.5.1 Incorrect Working Point
1- Assemble the circuit as in Fig. 4, and set UCE1 to UB/2 and UCE2 to UB/4 .
2- Apply an AC input voltage and observe the circuit response, explain your
observations.
3- Now set the working point of V1 unsymmetrically and that of V2
symmetrically. Observe the transmission response of the circuit (with
identical input signal) changing, explain your observation.
4.5.2 Fault Resulting from a defect in the Coupling Capacitor

1- For the coupling capacitor C2 simulate the following defects.
a. C2 is bridged. b. C2 shows a dry soldering joint.
2- In each of the previous defects observe the circuit response, explain your
observations.
4.5.3 Fault Resulting from Defective Transistor
1- Simulate each of the following defects and observe the circuit response and
explain the results.
2- All the paths from V2 are continuously conductive.
3- The collector-emitter path of V2 is interrupted.
4- The base-emitter path is interrupted and how are the DC voltage potentials
shifted.
5. Reference
Shilling and Belove, “Electronic Circuits Discrete and Integrated Circuits”,
McGraw Hill.
126
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The bipolar transistors, theory and basic applications

Book · January 2000

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Figure 1. The schematic construction of bipolar transistors.

2. Qualitative Description Of The Transistor Action

Figure 2. Different possibilities to bias a transistor.

VCE =VCB+VBE = VCB - VEB (2)

Figure 3. Common base connection of the transistor.

Since IE = -(IC +IB) , then

-IB = (Ivr + Ine) -ICO (7)

4. Definition of Some New Parameters:

Equation (10) can be rewritten in the form

5. Minority Carrier Distribution in the Base and Approximate expressions for γ ,α

αT = 1 for wb << LP (14)

Substituting eqns (13) and (15) in (8) we get

With Dn = 3 Dp = 20 cm2/s, wb = 3 µm Lne = 10 µm, Nb = 1016/cm3 and Ne = 5 × 1018/cm for

Figure 6. Typical curve of α as a function. of Ic.

This expression coincides with equation (14).

7. The Ebers-Moll Model

In order to develop the Ebers-Moll model let us

(A) VEB ≠ 0. The emitter current can be

where αF is the forward current amplification factor.

where α I is the inverse current amplification factor with VEB = 0, and

The General Case : VCB ≠ 0 & VEB ≠ 0

Figure 9. Ebers-Moll circuit model of a pnp transistor.( two-diode model)

It follows that the total collector current

and the base current ( − J B ) = J C + J E

Figure 9a. Circuit symbols of the bipolar transistors.

8. Graphical Representation of I-V Characteristics of a pnp Transistor

Figure 10. Common base circuit

Hence voltage amplification only exists.

Figure 11. Common

Common Emitter Circuit

Figure 12. Common collector

Common Collector Circuit

VEC ≅ VBC as VBE << VBC

Hence only current gain exist.

8.1. Static Characteristics of the Transistor in Common Base Circuit

J C = −α F J E + J CBO  e − 1

8.2. I-V Characteristic of a Transistor in a Common Emitter Circuit

8.3. The Input Characteristic

Figure 16. Input characteristic for common-base.

Figure. 9a. Ebers-Moll model for a real transistor.

(ii) Common Emitter Connection

This characteristic is represented in Fig. 17 for different values of collector to emitter

9. Voltage Ratings of the Transistor

Figure 18a. Punch-through condition in a transistor.

where W`b is the metallurgical width of the base

10. Transit Time

The transistor is an important component in electronic circuits because, as we saw in

emitter junction, and the output loop 2 passing IB

VBB = I B RB + VBE (31)

VBEa depends on the semiconductor material of the transistor. It amounts to about

a linear function of IB and VCE as follows: Figure 22. The output

VCE sat = 0.1 - 0.3V and Equivalent circuit of

if RC = 1k, then Figure 23. The active equivalent

Firstly we determine IB and VBE by RE

Combined Piecewise Linear Model And Graphical Solution:

The Universal Biasing Circuit Of A Transistor Amplifier:

output collector characteristics. The IB IIa