Instruction Set Reference (By Allen-Bradley) PDF

Allen-Bradley
PLC-5
Programmable
Instruction
Controllers Set Reference
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PLC-5 Instruction Set Alphabetical Listing

For this For this For this For this
See Page: See Page: See Page: See Page:
Instruction: Instruction: Instruction: Instruction:
ABL 17-51 CMP 3-3 JSR 13-12 RES 2-25
ACB 17-71 COP 9-20 LBL 13-5 RET 13-12
ACI 17-91 COS 4-211 LEQ 3-9 RTO 2-13
ACN 17-101 CPT 4-5 LES 3-10 SBR 13-12
ACS 4-131 CTD 2-20 LFL 11-51 SDS 18-2
ADD 4-14 CTU 2-18 LFU 11-51 SFR 13-231
AEX 17-111 DDT 10-2 LIM 3-11 SIN 4-271
AFI 13-19 DEG 6-51 LN 4-231 SQI 12-2

1
AHL 17-12 DFA 18-3 LOG 4-241 SQL 12-2
AIC 17-141 DIV 4-22 MCR 13-3 SQO 12-2
AND 5-2 DTR 10-8 MEQ 3-13 SQR 4-28
ARD 17-151 EOT 13-24 MOV 7-4 SRT 4-291
ARL 17-181 EQU 3-6 MSG 16-2 STD 4-311
ASC 17-211 FAL 9-2 MUL 4-25 SUB 4-34
ASN 4-151 FBC 10-2 MVM 7-5 TAN 4-351
ASR 17-221 FFL 11-5 NEG 4-26 TND 13-19
ATN 4-161 FFU 11-5 NEQ 3-15 TOD 6-3
AVE 4-171 FLL 9-21 NOT 5-4 TOF 2-9
AWA 17-231 FOR 13-8 NXT 13-8 TON 2-5
AWT 17-261 FRD 6-4 ONS 13-20 UID 13-251
BRK 13-8 FSC 9-15 OR 5-6 UIE 13-261
BSL 11-2 GEQ 3-7 OSF 13-221 XIC 1-3
BSR 11-2 GRT 3-8 OSR 13-211 XIO 1-4
BTD 7-2 IDI 1-102 OTE 1-5 XOR 5-8

2
BTR 15-4 IDO 1-11 OTL 1-6 XPY 4-361
1
BTW 15-4 IIN 1-8 OTU 1-7 Enhanced PLC -5 processors
only.
CIO 15-252 IOT 1-9 PID NO TAG 2
6200 programming software
with ControlNet PLC-5
CLR 4-20 JMP 13-5 RAD 6-61 processors only
1785-6.1 November 1998

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Table A
Choosing an Instruction Category
If You Want to Perform Use this Instruction Category:

this Operation:
examine, check or control 2-state device or condition bit level

multiple 2-state devices or conditions multi-bit
move, copy, change, analog values, codes element level

compute, compare multiple sets of values file instructions
convert conversion instructions
time or delay timer
count counter
shift or track bit shift
sequence sequencer
PID PID
message sending/receiving message
transfer data to/from modules block transfer or ControlNet transfer
diagnostics, fault handling diagnostics
control the flow of your program program control
Table B
Example Operations
If Your Application Calls for Operations such as: Use:
detecting when a limit switch closes bit level
changing the temperature preset element level
transfer analog data block transfer
turn on a motor 10 seconds after a pump is activated timing
move 1 of 3 recipes into a work area multi-element
keep track of parts as they move from station to station shifting
keep track of total parts in a bin counting
1785-6.1 November 1998

Summary of Changes
Summary of Changes
New Information Added to 7KHOLVWEHORZVXPPDUL]HVWKHFKDQJHVWKDWKDYHEHHQPDGHWRWKLV
this Manual PDQXDOVLQFHWKHODVWSULQWLQJ
For this Update Information: See Chapter:
Converting non-decimal numbers with the FRD instruction 6
How non-existing, indirect addresses affect the COP and 9

FLL instructions
How the .POS value operates in sequencer instructions 12
Using a RET instruction 13
Using the PID bias term 14
Using the no zero crossing (.NOZC) and no back calculation 14

(.NOBC) features in the PD control block
Clarification to error code 89 for MSG instruction 16
Ethernet PLC-5 processors now support SLC Typed Read and 16

SLC Typed Write MSG instructions
Configuring a multihop MSG instruction over Ethernet or 16

over ControlNet
Monitoring the status of the .EN bit in a continuous 16

MSG instruction
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1785-6.1 November 1998

Summary of Changes
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1785-6.1 November 1998

Preface
Preface
Conventions 7KLVPDQXDOXVHVWKHIROORZLQJFRQYHQWLRQV
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References to: Include these Allen-Bradley Processors:
Classic PLC-5 processors PLC-5/10™, -5/12™, -5/15™, -5/25™, and -5/VME™ processors.
Enhanced PLC-5 processors PLC-5/11™, -5/20™, -5/30™, -5/40™, -5/40L™, -5/60™,

-5/60L™, and -5/80™ processors.
Note: Unless otherwise specified, Enhanced PLC-5 processors include
Ethernet PLC-5, ControlNet PLC-5, Protected PLC-5 and VME PLC-5
processors.
Ethernet PLC-5 processors PLC-5/20E™, -5/40E™, and -5/80E™ processors.
ControlNet PLC-5 processors PLC-5/20C™, -5/40C™, -5/46C™, and -5/80C™ processors.
Protected PLC-5 processors 1 PLC-5/26™, -5/46™, and -5/86™ processors.
VME PLC-5 processors PLC-5/V30™, -5/V40™, -5/V40L™, and -5/V80™ processors. See the
PLC-5/VME VMEbus Programmable Controllers User Manual for more
information.

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1785-6.1 November 1998

Preface
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1785-6.1 November 1998

Table of Contents
Relay-Type Instructions Chapter 1

XIC, XIO, OTE, OTL, OTU, IIN, IOT, Using Relay-Type Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IDI, IDO I/O Image Files in Data Storage . . . . . . . . . . . . . . . . . . . . . 1-2
Rung Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Examine On (XIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Examine Off (XIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Energize (OTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Latch (OTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Unlatch (OTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Immediate Input (IIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Immediate Output (IOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Immediate Data Input (IDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Immediate Data Output (IDO) . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Using IDI and IDO Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Timer Instructions TON, TOF, Chapter 2

RTO Counter Instructions CTU, Using Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CTD Reset RES Using Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Timer Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Timer On Delay (TON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Timer Off Delay (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Retentive Timer On (RTO) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Using Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Count Up (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Count Down (CTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timer and Counter Reset (RES). . . . . . . . . . . . . . . . . . . . . . 2-20
1785-6.1 November 1998

toc–2 Table of Contents
Compare Instructions Chapter 3

CMP, EQU, GEQ, GRT, LEQ, LES, LIM, Using Compare Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
MEQ, NEQ Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Compare (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Entering the CMP Expression. . . . . . . . . . . . . . . . . . . . . . . 3-2
Determining the Length of an Expression. . . . . . . . . . . . . . 3-3
Equal to (EQU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Greater than or Equal to (GEQ). . . . . . . . . . . . . . . . . . . . . . . . 3-5
Greater than (GRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Less than or Equal to (LEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Less than (LES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Limit Test (LIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Mask Compare Equal to (MEQ) . . . . . . . . . . . . . . . . . . . . . . . 3-9
Not Equal to (NEQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Compute Instructions Chapter 4

CPT, ACS, ADD, ASN, ATN, AVE, Using Compute Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
CLR, COS, DIV, LN, LOG, MUL, NEG, Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Data Types and the Compute Instruction . . . . . . . . . . . . . . . . 4-3
SIN, SRT, SQR, STD, SUB, TAN, XPY Using Floating Point Data Types . . . . . . . . . . . . . . . . . . . . . . 4-4
Compute (CPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Entering the CPT Expression . . . . . . . . . . . . . . . . . . . . . . . 4-5
Determining the Length of an Expression. . . . . . . . . . . . . . 4-7
Determining the Order of Operation . . . . . . . . . . . . . . . . . . 4-8
Expression Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Entering the Destination . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Using CPT Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Arc Cosine (ACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Addition (ADD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Arc Sine (ASN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Arc Tangent (ATN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Average File (AVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Clear (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Cosine (COS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Divide (DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Natural Log (LN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Log to the Base 10 (LOG). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Multiply (MUL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Negate (NEG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Sine (SIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Square Root (SQR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
1785-6.1 November 1998

Table of Contents toc–3
Sort File (SRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Standard Deviation (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Subtract (SUB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Tangent (TAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
X to the Power of Y (XPY). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
Logical Instructions Chapter 5

AND, NOT, OR, XOR Using Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . 5-1
AND Operation (AND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
NOT Operation (NOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
OR Operation (OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Exclusive OR Operation (XOR) . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Conversion Instructions Chapter 6

FRD and TOD, DEG and RAD Using the Conversion Instructions . . . . . . . . . . . . . . . . . . . . . 6-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . 6-1
Convert to BCD (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Convert from BCD (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Degree (DEG)
(Enhanced PLC-5 Processors Only) . . . . . . . . . . . . . . . . . . . . 6-3
Radian (RAD)
(Enhanced PLC-5 Processors Only) . . . . . . . . . . . . . . . . . . . . 6-4
Bit Modify and Move Instructions Chapter 7

BTD, MOV, MVM Using Bit Modify and Move Instructions . . . . . . . . . . . . . . . . . 7-1
Bit Distribute (BTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Move (MOV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Masked Move (MVM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
File Instruction Concepts Chapter 8

Concepts of File Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Using the Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Manipulating File Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Choosing Modes of Block Operation . . . . . . . . . . . . . . . . . . . 8-5
All Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Numerical Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Incremental Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Special Case, Numerical Mode with Words Per Scan = 1. . 8-8
1785-6.1 November 1998

File Instructions Chapter 9

FAL, FSC, COP, FLL Using File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
File Arithmetic and Logic (FAL) . . . . . . . . . . . . . . . . . . . . . . . 9-2
FAL Copy Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
FAL Arithmetic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Upper and Lower Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
FAL Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
FAL Convert Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
File Search and Compare (FSC) . . . . . . . . . . . . . . . . . . . . . . 9-14
FSC Search and Compare Operations . . . . . . . . . . . . . . . . . 9-17
Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
File Search Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
File Copy (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
File Fill (FLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Diagnostic Instructions Chapter 10

FBC, DDT, DTR Using Diagnostic Instructions . . . . . . . . . . . . . . . . . . . . . . . 10-1
File Bit Comparison (FBC) and Diagnostic Detect (DDT) . . . . 10-2
Selecting the Search Mode . . . . . . . . . . . . . . . . . . . . . . . 10-2
One Mismatch at a Time . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
All Per Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Data Transitional (DTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Shift Register Instructions Chapter 11

BSL, BSR, FFL, FFU, LFL, LFU Applying Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Using Bit Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Using FIFO and LIFO Instructions . . . . . . . . . . . . . . . . . . . . . 11-5
Sequencer Instructions Chapter 12

SQO, SQI, SQL Applying Sequencers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Using Sequencer Instructions . . . . . . . . . . . . . . . . . . . . . . . 12-2
Resetting the Position of SQO . . . . . . . . . . . . . . . . . . . . . 12-6
Using SQI Without SQO . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
1785-6.1 November 1998

Program Control Instructions MCR, Chapter 13

JMP, LBL, FOR, NXT, BRK, JSR, Selecting Program Flow Instructions . . . . . . . . . . . . . . . . . . 13-1
SBR, RET, TND, AFI, ONS, OSR, OSF, Master Control Reset (MCR) . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Jump (JMP) and Label (LBL) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
SFR, EOT, UIE, UID Using JMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Using LBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
For Next Loop (FOR, NXT), Break (BRK) . . . . . . . . . . . . . . . . 13-5
Using FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Using BRK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Using NXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Jump to Subroutine (JSR), Subroutine (SBR),
and Return (RET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Passing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Nesting Subroutine Files . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Using JSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Using SBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Using RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
Temporary End (TND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Always False (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
One Shot (ONS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
One Shot Rising (OSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
One Shot Falling (OSF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Sequential Function Chart Reset (SFR). . . . . . . . . . . . . . . . 13-17
End of Transition (EOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
User Interrupt Disable (UID) . . . . . . . . . . . . . . . . . . . . . . . . 13-19
User Interrupt Enable (UIE). . . . . . . . . . . . . . . . . . . . . . . . . 13-20
Process Control Instruction PID Chapter 14

Using PID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
PID Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Using PID Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Conversion of Gain Constants . . . . . . . . . . . . . . . . . . . . . 14-3
Integral Term Implementation . . . . . . . . . . . . . . . . . . . . . 14-3
Derivative Term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Setting Input/Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Implementing Scaling to Engineering Units . . . . . . . . . . . . . 14-5
Setting the Dead Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Using Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Using No Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Selecting the Derivative Term (Acts on PV or Error) . . . . . . . 14-7
1785-6.1 November 1998

Setting Output Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Using Output Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Anti-Reset Windup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Using a Manual Mode Operation (Bumpless Transfer) . . . 14-8
Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Feedforward or Output Biasing . . . . . . . . . . . . . . . . . . . . . . 14-9
Resume Last State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
PID Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Using No Back Calculation. . . . . . . . . . . . . . . . . . . . . . . 14-11
Operational Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Integer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
PD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
Using an Integer Data File Type for the Control Block. . . . . 14-14
Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-16
Using a PD File Type for the Control Block . . . . . . . . . . . . . 14-18
Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-23
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . 14-25
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Transferring Data to the PID Instruction . . . . . . . . . . . . . 14-25
Loop Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Number of PID Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Loop Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Descaling Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
PID Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Integer Block (N) Examples . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
PD Block Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Ladder Logic Simulation of a Manual Control Station . . . 14-37
Cascading Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Ratio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Process Variable Tracking . . . . . . . . . . . . . . . . . . . . . . . 14-39
PID Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
1785-6.1 November 1998

Block-Transfer Instructions Chapter 15

BTR and BTW and ControlNet I/O Using Block Transfer and ControlNet I/O
Transfer Instruction CIO Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Using Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . 15-1
Block-Transfer Read (BTR) and Block-Transfer Write (BTW). 15-3
Block-Transfer Request Queue . . . . . . . . . . . . . . . . . . . . 15-3
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Requested Word Count (.RLEN) . . . . . . . . . . . . . . . . . . . . 15-8
Transmitted Word Count (.DLEN) . . . . . . . . . . . . . . . . . . . 15-8
File Number (.FILE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Element Number (.ELEM). . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 15-10
Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 15-12
Block Transfer Timing – Classic PLC-5 Processors . . . . . . 15-13
Instruction Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Waiting Time in the Queue. . . . . . . . . . . . . . . . . . . . . . . 15-13
Transfer Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Block Transfer Timing – Enhanced PLC-5 Processors . . . . 15-14
Instruction Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Waiting Time in the Holding Area . . . . . . . . . . . . . . . . . . 15-14
Transfer Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Example Bidirectional Alternating Block-Transfer. . . . . . 15-16
Example Bidirectional Alternating Repeating
Block-Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Example Bidirectional Continuous Block-Transfer . . . . . 15-18
Example Directional Non-Continuous Block-Transfer . . . 15-19
Example Directional Repeating Block Transfer . . . . . . . . 15-19
Example Directional Continuous Block-Transfer . . . . . . . 15-20
Example Buffering Block Transfer-Data . . . . . . . . . . . . . 15-21
ControlNet I/O Transfer (CIO) Instruction . . . . . . . . . . . . . . 15-22
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Using the CIO Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
Using the CT Control Block . . . . . . . . . . . . . . . . . . . . . . 15-25
1785-6.1 November 1998

Message Instruction MSG Chapter 16

Using the Message Instruction. . . . . . . . . . . . . . . . . . . . . . . 16-1
Message (MSG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
MSG Data Entry Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Using the Message Instruction for Ethernet
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Using the Message Instruction for PLC-5 Ethernet Interface
Module Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Configuring an Ethernet Multihop MSG Instruction. . . . . . . . 16-9
Using the Message Instruction for ControlNet
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Configuring a ControlNet Multihop MSG Instruction . . . . . . 16-11
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Error Code (.ERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Requested Length (.RLEN) . . . . . . . . . . . . . . . . . . . . . . . 16-13
Transmitted Length (.DLEN) . . . . . . . . . . . . . . . . . . . . . . 16-13
Communication Command . . . . . . . . . . . . . . . . . . . . . . 16-14
External Data Table Addresses. . . . . . . . . . . . . . . . . . . . 16-15
PLC-2 to PLC-5 Compatibility Files . . . . . . . . . . . . . . . . 16-15
Sending SLC Typed Logical Read and Typed Logical
Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
Monitoring a Message Instruction . . . . . . . . . . . . . . . . . . . 16-17
Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 16-18
Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 16-19
MSG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
1785-6.1 November 1998

ASCII Instructions Chapter 17

ABL, ACB, ACI, ACN, AEX, AIC, AHL, Using ASCII Instructions
ARD, ARL, ASC, ASR, AWA, AWT Enhanced PLC-5 Processors Only . . . . . . . . . . . . . . . . . . . . 17-1
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Length (.LEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Position (.POS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Using Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Test Buffer for Line (ABL) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Number of Characters in Buffer (ACB) . . . . . . . . . . . . . . . . . 17-5
ASCII String to Integer (ACI) . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
ASCII String Concatenate (ACN) . . . . . . . . . . . . . . . . . . . . . . 17-7
ASCII String Extract (AEX) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
ASCII Set or Reset Handshake Lines (AHL). . . . . . . . . . . . . . 17-8
ASCII Integer to String (AIC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
ASCII Read Characters (ARD). . . . . . . . . . . . . . . . . . . . . . . 17-10
ASCII Read Line (ARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
ASCII String Search (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
ASCII String Compare (ASR). . . . . . . . . . . . . . . . . . . . . . . . 17-15
ASCII Write with Append (AWA) . . . . . . . . . . . . . . . . . . . . . 17-15
ASCII Write (AWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
Custom Application Routine Chapter 18

Instructions SDS, DFA Chapter Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Smart Directed Sequencer (SDS) Overview . . . . . . . . . . . . . 18-2
Programming the SDS Instruction . . . . . . . . . . . . . . . . . . 18-2
Diagnostic Fault Annunciator (DFA) Overview . . . . . . . . . . . 18-3
Programming the DFA Instruction . . . . . . . . . . . . . . . . . . 18-3
1785-6.1 November 1998

Instruction Timing and Appendix A-1

Memory Requirements Instruction Timing and Memory Requirements. . . . . . . . . . . . A-1
Timing for Enhanced PLC-5 Processors. . . . . . . . . . . . . . . . . A-2
Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . A-2
File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Timing for Classic PLC-5 Processors . . . . . . . . . . . . . . . . . . A-10
Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . A-10
File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Program Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
Direct and Indirect Elements: Enhanced PLC-5 Processors . A-17
Direct and Indirect Elements: Classic PLC-5 Processors . . . A-18
Indirect Bit or Elements Addresses: Classic
PLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19
Additional Timing Considerations: Classic
PLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
SFC Reference Appendix B-1

Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
SFC Status Information in the Processor Status File. . . . . . . . B-1
Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Dynamic Constraints – Classic PLC-5 Processors Only . . . . . B-5
Scanning Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Step and Transition Scanning . . . . . . . . . . . . . . . . . . . . . . B-7
Selected Branch Scanning. . . . . . . . . . . . . . . . . . . . . . . . . B-8
Simultaneous Branch Scanning . . . . . . . . . . . . . . . . . . . . . B-9
SFC Example and Scan Sequence . . . . . . . . . . . . . . . . . . B-11
Run Times – Classic PLC-5 Processors . . . . . . . . . . . . . . . . B-12
Using Sequence Diagrams to Determine Run Time . . . . . B-13
Using Equations to Determine Run Time . . . . . . . . . . . . . B-14
Valid Data Types for Appendix C-1

Instruction Operands Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Instruction Operands and Valid Data Types . . . . . . . . . . . . . . C-1
1785-6.1 November 1998

Chapter 1
Relay-Type Instructions XIC, XIO, OTE,
OTL, OTU, IIN, IOT, IDI, IDO
Using Relay-Type Instructions 8VHUHOD\W\SHLQVWUXFWLRQVWRPRQLWRUDQGFRQWUROWKHVWDWXVRIELWVLQ
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LQVWUXFWLRQVOHW\RX
If You Want to: Use this Instruction: Found on Page:
Examine a bit for an ON condition XIC 1-3
Examine a bit for an OFF condition XIO 1-3
Hold a bit ON or OFF (non-retentive) OTE 1-4
Latch a bit to ON (retentive) OTL 1-4
Unlatch a bit to OFF (retentive) OTU 1-5
Immediately update input image bits IIN 1-6
Immediately update outputs IOT 1-7
Immediately perform an update of IDI 1-8

the ControlNet™ data input file from
the ControlNet memory buffers.
Immediately perform an update of IDO 1-8

the ControlNet memory buffers from
the source file before the next
output-image update
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1785-6.1 November 1998

1-2 Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO
I/O Image Files in Data Storage

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FRQQHFWHGWRLQSXWPRGXOHWHUPLQDOV
If the Input Sensor Is: Then Its Corresponding Input Image Bit Is:
closed (on) on (1)
open (off) off (0)
<RXSURJUDPLQVWUXFWLRQVLQODGGHUORJLFWRPRQLWRUELWV8VHD
ORJLFDODGGUHVVIRUWKHELW
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PRGXOHWHUPLQDOV
If the Output Image Bit Is: Then Its Corresponding Output Is:
on (1) energized (on)
off (0) de-energized (off)
<RXSURJUDPLQVWUXFWLRQVLQODGGHUORJLFWRFRQWUROELWV
Rung Logic
$VHDFKFRQGLWLRQLQJLQVWUXFWLRQLVH[HFXWHGWKHDGGUHVVHGELWLV
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FRPSOHWHSDWKRIWUXHFRQGLWLRQVH[DPLQHGIRUDUHIRXQGWKHUXQJ
LVVHWWRWUXH7KHUXQJPXVWFRQWDLQDFRQWLQXRXVSDWKRIWUXH
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1785-6.1 November 1998

Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO 1-3
Examine On (XIC)
Description: :KHQDGHYLFHFORVHVLWVFLUFXLWWKHPRGXOHZKRVHLQSXWWHUPLQDOLV
ZLUHGWRWKHGHYLFHGHWHFWVWKHFORVHGFLUFXLW7KHSURFHVVRUUHIOHFWV
WKLV21VWDWHLQWKHGDWDWDEOH:KHQWKHSURFHVVRUILQGVDQ;,&
LQVWUXFWLRQWKDWDGGUHVVHVWKHELWWKDWFRUUHVSRQGVWRWKHLQSXW
Example:
WHUPLQDOWKHSURFHVVRUGHWHUPLQHVZKHWKHUWKHGHYLFHLV21FORVHG
I:012 ,IWKHSURFHVVRUILQGVDQ21VWDWHLWVHWVWKHORJLFIRUWKLVLQVWUXFWLRQ
WUXHLIWKHSURFHVVRUILQGVDQ2))VWDWHLWVHWVWKHORJLFIRUWKH
07 LQVWUXFWLRQQRWWUXH
If you find an ON condition at bit I:012/07 in
the input table, set this instruction true. ,IWKH;,&LQVWUXFWLRQLVWKHRQO\FRQGLWLRQLQJLQVWUXFWLRQRQWKHUXQJ
This bit corresponds to input terminal 7 of a WKHSURFHVVRUHQDEOHVWKHRXWSXWLQVWUXFWLRQZKHQWKH;,&LQVWUXFWLRQ
module in I/O group 2 of I/O rack 1. If the input LVWUXHLQSXWFORVHG7KHSURFHVVRUGLVDEOHVDQRXWSXWLQVWUXFWLRQ
circuit is true, the instruction is true.
ZKHQWKH;,&LQVWUXFWLRQLVIDOVHLQSXWRSHQ
7KHH[DPLQHRQLQVWUXFWLRQLVWUXHRUIDOVHGHSHQGLQJRQZKHWKHUWKH
SURFHVVRUILQGVDQ21RU2))FRQGLWLRQDWWKHDGGUHVVHGELW
If the Bit Is: Then the Instruction Is: Bit Logic State:
on true 1
off false 0
Examine Off (XIO)
Description: :KHQDGHYLFHRSHQVLWVFLUFXLWWKHPRGXOHZKRVHLQSXWWHUPLQDOLV
ZLUHGWRWKHGHYLFHGHWHFWVDQRSHQFLUFXLW7KHSURFHVVRUUHIOHFWV
WKLV2))VWDWHLQWKHGDWDWDEOH:KHQWKHSURFHVVRUILQGVDQ;,2
Example: LQVWUXFWLRQWKDWDGGUHVVHVWKHELWWKDWFRUUHVSRQGVWRWKHLQSXW
WHUPLQDOWKHSURFHVVRUGHWHUPLQHVZKHWKHUWKHGHYLFHLV2))
I:012
RSHQ,IWKHSURFHVVRUILQGVDQ2))VWDWHLWVHWVWKHORJLFIRUWKLV
07
LQVWUXFWLRQWUXH,IWKHSURFHVVRUILQGVDQ21VWDWHLWVHWVWKH;,2
LQVWUXFWLRQWRIDOVH
If you find an OFF condition at bit I:012/07 in
the input table, set this instruction true. ,IWKH;,2LQVWUXFWLRQLVWKHRQO\FRQGLWLRQLQJLQVWUXFWLRQRQWKHUXQJ
This bit corresponds to input terminal 7 of a WKHSURFHVVRUHQDEOHVWKHRXWSXWLQVWUXFWLRQZKHQWKH;,2LQVWUXFWLRQ
module in I/O group 2 of I/O rack 1. If the input LVWUXHLQSXWRSHQ
circuit is false, the instruction is true.
7KHH[DPLQHRIILQVWUXFWLRQLVWUXHRUIDOVHGHSHQGLQJRQZKHWKHUWKH
SURFHVVRUILQGVDQ2))RU21FRQGLWLRQDWWKHDGGUHVVHGELW
If the Bit Is: Then the Instruction Is: Bit Logic State:
off true 0
on false 1
1785-6.1 November 1998

Energize (OTE)
Description: 8VHWKH27(LQVWUXFWLRQWRFRQWURODELWLQPHPRU\,IWKHELW
FRUUHVSRQGVWRDQRXWSXWPRGXOHWHUPLQDOWKHGHYLFHZLUHGWRWKLV
WHUPLQDOLVHQHUJL]HGZKHQWKHLQVWUXFWLRQLVHQDEOHGDQG
Example: GHHQHUJL]HGZKHQWKHLQVWUXFWLRQLVGLVDEOHG,IWKHLQSXWFRQGLWLRQV
WKDWSUHFHGHWKH27(LQVWUXFWLRQDUHWUXHWKHSURFHVVRUHQDEOHVWKH
O:013 27(LQVWUXFWLRQ,IWKHLQSXWFRQGLWLRQVWKDWSUHFHGHWKH27(
LQVWUXFWLRQDUHIDOVHWKHSURFHVVRUGLVDEOHVWKH27(LQVWUXFWLRQ
01 :KHQUXQJFRQGLWLRQVEHFRPHIDOVHWKHFRUUHVSRQGLQJGHYLFH
Turn ON bit O:013/01 of the output image table if GHHQHUJL]HV
the rung is true. Turn it OFF if the rung is false.
$Q27(LQVWUXFWLRQLVVLPLODUWRDUHOD\FRLO7KH27(LQVWUXFWLRQLV
This bit corresponds to output terminal 01 of a
module in /O group 3 of I/O rack 1. FRQWUROOHGE\SUHFHGLQJLQSXWLQVWUXFWLRQVWKHUHOD\FRLOLVFRQWUROOHG
E\FRQWDFWVLQLWVKDUGZLUHGUXQJ
7KH27(LQVWUXFWLRQWHOOVWKHSURFHVVRUWRFRQWUROWKHDGGUHVVHGELW
EDVHGRQWKHUXQJFRQGLWLRQ
If the Rung Is: Then the Processor Turns the Bit: Bit Logic State:
true on 1
false off 0
Latch (OTL)
Description: 7KH27/LQVWUXFWLRQLVDUHWHQWLYHRXWSXWLQVWUXFWLRQWKDWFDQRQO\
L WXUQRQDELWLWFDQQRWWXUQRIIDELW7KLVLQVWUXFWLRQLVXVXDOO\XVHG
LQSDLUVZLWKDQ278XQODWFKLQVWUXFWLRQZLWKERWKLQVWUXFWLRQV
Example: DGGUHVVLQJWKHVDPHELW
O:013
:KHQ\RXDVVLJQDQDGGUHVVWRDQ27/LQVWUXFWLRQWKDWFRUUHVSRQGV
L
01
WRDWHUPLQDORIDQRXWSXWPRGXOHWKHRXWSXWGHYLFHZLUHGWRWKLV
WHUPLQDOLVHQHUJL]HGZKHQWKHSURFHVVRUVHWVHQDEOHVWKHELWLQ
Turn ON bit O:013/01 of the output image table SURFHVVRUPHPRU\,IWKHLQSXWFRQGLWLRQVWKDWSUHFHGHWKH27/
if the rung is true.
This bit corresponds to output terminal 1 of a
LQVWUXFWLRQDUHWUXHWKHSURFHVVRUHQDEOHVWKH27/LQVWUXFWLRQ:KHQ
module in I/O group 3 of I/O rack 1. UXQJFRQGLWLRQVEHFRPHIDOVHDIWHUEHLQJWUXHWKHELWUHPDLQVVHW
DQGWKHFRUUHVSRQGLQJRXWSXWGHYLFHUHPDLQVHQHUJL]HG8VHWKH278
LQVWUXFWLRQWRWXUQ2))WKHELW\RXODWFKHGRQZLWKWKH27/
LQVWUXFWLRQ
1785-6.1 November 1998

:KHQHQDEOHGWKHODWFKLQVWUXFWLRQWHOOVWKHSURFHVVRUWRWXUQRQWKH
DGGUHVVHGELW7KHUHDIWHUWKHELWUHPDLQVRQUHJDUGOHVVRIWKHUXQJ
FRQGLWLRQXQWLOWKHELWLVWXUQHGRIIW\SLFDOO\E\DQXQODWFK278
LQVWUXFWLRQLQDQRWKHUUXQJ
If the Rung Is: Then the Processor Turns the Bit:
true on
false no change
:KHQWKHSURFHVVRUFKDQJHVIURP5XQWR3URJUDPPRGHRUZKHQWKH
SURFHVVRUORVHVSRZHUDQGWKHUHLVEDWWHU\EDFNXSWKHODVWWUXH27/
LQVWUXFWLRQFRQWLQXHVWRFRQWUROWKHELWLQPHPRU\7KHODWFKHGRXWSXW
GHYLFHLVHQHUJL]HGHYHQWKRXJKWKHUXQJFRQGLWLRQVWKDWFRQWUROWKH
LQVWUXFWLRQPD\KDYHJRQHIDOVH
,PSRUWDQW 7KH27/LQVWUXFWLRQLVUHWHQWLYH:KHQWKHSURFHVVRU
ORVHVSRZHULVVZLWFKHGWR3URJUDPPRGHRU7HVW
PRGHRUGHWHFWVDPDMRUIDXOWRXWSXWVJRRIIEXWWKH
VWDWHVRIUHWHQWLYHRXWSXWVDUHUHWDLQHGLQPHPRU\
:KHQWKHSURFHVVRUUHVXPHVRSHUDWLRQLQ5XQPRGH
UHWHQWLYHRXWSXWVLPPHGLDWHO\UHWXUQWRWKHLUSUHYLRXV
VWDWHV1RQUHWHQWLYHRXWSXWVVXFKDV27(RXWSXWVDUH
UHVHW
Unlatch (OTU)
Description: 7KH278LQVWUXFWLRQLVDUHWHQWLYHRXWSXWLQVWUXFWLRQWKDWFDQRQO\
WXUQRIIDELWLWFDQQRWWXUQRQDELW7KLVLQVWUXFWLRQLVXVXDOO\XVHG
U
LQSDLUVZLWKDQ27/RXWSXWODWFKLQVWUXFWLRQZLWKERWKLQVWUXFWLRQV
DGGUHVVLQJWKHVDPHELW7KH278LQVWUXFWLRQWXUQV2))WKHELW
Example: ZKLFKZDVWXUQHG21ODWFKHGE\WKH27/LQVWUXFWLRQ
O:013
:KHQWKHSURFHVVRUFKDQJHVIURP5XQWR3URJUDPPRGHRUZKHQWKH
U
SURFHVVRUORVHVSRZHUDQGWKHUHLVEDWWHU\EDFNXSWKHELWLVUHWDLQHG
01
LQWKHVWDWHVHWE\WKHODVWUXQJRIWKHODWFKXQODWFKSDLUWKDWZDVWUXH
Turn OFF bit O:013/01 of the output image table
if the rung is true. 7KHXQODWFKLQVWUXFWLRQWHOOVWKHSURFHVVRUWRWXUQRIIWKHDGGUHVVHGELW
This bit corresponds to output terminal 1 of a EDVHGRQWKHUXQJFRQGLWLRQ7KHUHDIWHUWKHELWUHPDLQVRII
module in I/O group 3 in I/O rack 1. UHJDUGOHVVRIWKHUXQJFRQGLWLRQXQWLOLWLVWXUQHGRQW\SLFDOO\E\D
27/LQVWUXFWLRQLQDQRWKHUUXQJ
If the Rung is: Then the Processor Turns the Bit:
true off
false no change
1785-6.1 November 1998

Immediate Input (IIN)
Description: 7KH,,1LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWZKHQHQDEOHG
XSGDWHVDZRUGRILQSXWLPDJHELWVEHIRUHWKHQH[WUHJXODU
IIN LQSXWLPDJHXSGDWH
Example: )RULQSXWVLQWKHORFDOFKDVVLVWKHSURJUDPVFDQLVLQWHUUXSWHG
RRG ZKLOHWKHLQSXWVRIWKHDGGUHVVHG,2JURXSDUHH[DPLQHG7KLV
IIN VHWVWKHLQSXWLPDJHELWVWRWKHFXUUHQWVWDWHVRIWKHLQSXWVEHIRUH
Where: WKHSURJUDPVFDQFRQWLQXHV,IWKHSURJUDPUHDFKHVDQHQDEOHG
RR = I/O rack number ,,1LQVWUXFWLRQZKLOHDEORFNWUDQVIHUZLWKWKHORFDOFKDVVLVLVLQ
00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/20
00-07 PLC-5/25, -5/30
SURJUHVVWKHSURFHVVRUFRPSOHWHVWKHEORFNWUDQVIHUEHIRUHH[HFXWLQJ
000-177 PLC-5/40, -5/40L WKH,,1LQVWUXFWLRQ
000-277 PLC-5/60, -5/60L, -5/80
G = I/O group number (0 - 7) )RULQSXWVLQDUHPRWHFKDVVLVWKHSURJUDPVFDQLVLQWHUUXSWHGRQO\
001 WRXSGDWHWKHLQSXWLPDJHZLWKWKHODWHVWVWDWHVRIWKHLQSXWVDVIRXQG
IIN LQWKHUHPRWH,2EXIIHUIURPWKHPRVWUHFHQWUHPRWH,2VFDQ7KH
When the input conditions are true, update the LQSXWVDUHQRWVFDQQHGEHIRUHWKHSURJUDPVFDQFRQWLQXHV
input image word corresponding to I/O rack 0,
group 1. 3ODFHWKHUXQJZLWKWKH,,1LQVWUXFWLRQLPPHGLDWHO\EHIRUHUXQJVWKDW
H[DPLQHFULWLFDOLQSXWELWVXSGDWHGE\WKH,,1LQVWUXFWLRQ
)RUWKH,,1LQVWUXFWLRQ\RXRQO\QHHGWRHQWHUWKH,2UDFNQXPEHU
DQGWKH,2JURXSQXPEHU\RXGRQRWHQWHUDILOHQXPEHU
$77(17,21 'RQRWHQWHUDQDGGUHVVWKDWLQFOXGHVD
ILOHQXPEHUVXFKDV,7KHSURFHVVRULQWHUSUHWVWKH
ELWSDWWHUQIRXQGDWWKDWDGGUHVVDVWKH,2UDFNDQG,2
JURXSQXPEHURIWKHLQSXWVWRXSGDWH8QH[SHFWHG
RSHUDWLRQZLOOUHVXOWZLWKSRVVLEOHGDPDJHWRHTXLSPHQW
DQGLQMXU\WRSHUVRQQHO
)RUPRUHLQIRUPDWLRQRQ,2VFDQQLQJDQGEORFNWUDQVIHUVVHH
FKDSWHU
1785-6.1 November 1998

Immediate Output (IOT)
Description: 7KH,27LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWZKHQHQDEOHG
IOT
XSGDWHVDQ,2JURXSRIRXWSXWVEHIRUHWKHQH[WQRUPDORXWSXW
LPDJHXSGDWH
Example:
)RURXWSXWVLQWKHORFDOFKDVVLVWKHSURJUDPVFDQLVLQWHUUXSWHGZKLOH
RRG
WKHRXWSXWVRIWKHDGGUHVVHG,2JURXSDUHH[DPLQHG7KLVVHWVWKH
IOT
RXWSXWFLUFXLWVWRWKHFXUUHQWVWDWHVRIWKHRXWSXWELWVLQWKHRXWSXW
Where:
LPDJHWDEOHEHIRUHWKHSURJUDPVFDQFRQWLQXHV,IWKHSURJUDP
RR = I/O rack number
00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/20 UHDFKHVDQHQDEOHG,27LQVWUXFWLRQZKLOHDEORFNWUDQVIHULVLQ
00-07 PLC-5/25, -5/30 SURJUHVVWKHSURFHVVRUFRPSOHWHVWKHEORFNWUDQVIHUEHIRUHH[HFXWLQJ
000-177 PLC-5/40, -5/40L
000-277 PLC-5/60, -5/60L, -5/80 WKH,27LQVWUXFWLRQ
G = I/O group number (0 - 7)
)RURXWSXWVLQDUHPRWHFKDVVLVWKHSURJUDPVFDQLVLQWHUUXSWHGRQO\
001 WRXSGDWHWKHUHPRWH,2EXIIHUZLWKWKHFXUUHQWVWDWHVRIWKH
IOT
RXWSXWLPDJHELWV7KLVPDNHVWKHVHVWDWHVLPPHGLDWHO\DYDLODEOHIRU
When the input conditions are true, update the WKHQH[WUHPRWH,2VFDQZKLOHWKHSURJUDPVFDQFRQWLQXHV7KH
output image word corresponding to I/O rack 0,
group 1.
RXWSXWVDUHQRWVFDQQHGEHIRUHWKHSURJUDPVFDQFRQWLQXHV
3ODFHWKHUXQJZLWKWKH,27RXWSXWLQVWUXFWLRQLPPHGLDWHO\DIWHU
UXQJVWKDWFRQWUROFULWLFDORXWSXWLPDJHELWVWREHXSGDWHGE\WKH
,27LQVWUXFWLRQ
)RUWKH,27LQVWUXFWLRQ\RXRQO\QHHGWRHQWHUWKH,2UDFNQXPEHU
DQGWKH,2JURXSQXPEHU\RXGRQRWQHHGWRHQWHUWKHILOHQXPEHU
$77(17,21 'RQRWHQWHUDQDGGUHVVWKDWLQFOXGHVD
ILOHQXPEHUVXFKDV27KHSURFHVVRULQWHUSUHWVWKH
ELWSDWWHUQIRXQGDWWKDWDGGUHVVDVWKH,2UDFNDQG,2
JURXSQXPEHURIWKHRXWSXWVWREHXSGDWHG8QH[SHFWHG
RSHUDWLRQZLOOUHVXOWZLWKSRVVLEOHGDPDJHWRHTXLSPHQW
DQGLQMXU\WRSHUVRQQHO
)RUPRUHLQIRUPDWLRQRQ,2VFDQQLQJDQGEORFNWUDQVIHUVVHH
FKDSWHU
1785-6.1 November 1998

Immediate Data Input (IDI)
Description: :KHQWKHUXQJJRHVWUXHWKH,',LQVWUXFWLRQSHUIRUPVDQLPPHGLDWH
IDI
XSGDWHRIWKH&RQWURO1HWGDWDLQSXWILOHIURPWKH&RQWURO1HWPHPRU\
IMMEDIATE DATA INPUT
EXIIHUVEHIRUHWKHQH[WQRUPDOLQSXWLPDJHXSGDWHZKLFKRFFXUVDW
Data file offset 232
Length 10
WKHHQGRIWKHSURJUDPVFDQ
Destination N10:232
7RSURJUDPDQ,',LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJLQIRUPDWLRQWKDWLWVWRUHVLQLWVFRQWUROEORFN
'DWDILOHRIIVHWVSHFLILHVWKHRIIVHWLQWRWKH'DWD,QSXW)LOH',)
ZKHUHZRUGVDUHUHDG±FDQEHDQLPPHGLDWHYDOXHRUD
ORJLFDODGGUHVVWKDWVSHFLILHVWKHGDWDLPDJHILOHRIIVHW
/HQJWKVSHFLILHVWKHQXPEHURIZRUGVWREHWUDQVIHUUHG±DQ
LPPHGLDWHYDOXHRUDORJLFDODGGUHVVWKDWVSHFLILHVWKH
QXPEHURIZRUGVWREHWUDQVIHUUHG
'HVWLQDWLRQVSHFLILHVDGDWDWDEOHDGGUHVVWREHXVHGDVWKH
GHVWLQDWLRQRIWKHZRUGVWREHWUDQVIHUUHG
,PSRUWDQW 7KH'HVWLQDWLRQVKRXOGEHWKHPDWFKLQJGDWDWDEOH
DGGUHVVLQWKH'DWD,QSXW)LOH',)H[FHSWZKHQ\RX
XVHWKHLQVWUXFWLRQWRHQVXUHGDWDEORFNLQWHJULW\LQWKH
FDVHRI6HOHFWDEOH7LPHG,QWHUUXSWV67,V)RUPRUH
LQIRUPDWLRQVHHSDJH
Immediate Data Output (IDO)
Description: :KHQWKHUXQJJRHVWUXHWKH,'2LQVWUXFWLRQSHUIRUPVDQLPPHGLDWH
IDO
XSGDWHRIWKH&RQWURO1HWPHPRU\EXIIHUVIURPWKHVRXUFHILOHEHIRUH
IMMEDIATE DATA OUTPUT WKHQH[WRXWSXWLPDJHXSGDWHVHQGLQJWKHXSGDWHGGDWDRXWSXWILOH
LQIRUPDWLRQDFURVVWKH&RQWURO1HWQHWZRUNWRWKHDSSURSULDWH
Data file offset 232
Length 10
Source N7:232
&RQWURO1HWGHYLFH
7RSURJUDPDQ,'2LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJLQIRUPDWLRQWKDWLWVWRUHVLQLWVFRQWUROEORFN
'DWDILOHRIIVHWVSHFLILHVWKHRIIVHWLQWRWKH'DWD2XWSXW)LOH
'2)ZKHUHZRUGVDUHZULWWHQ±FDQEHDQLPPHGLDWHYDOXH
RUDORJLFDODGGUHVVWKDWVSHFLILHVWKHGDWDLPDJH
ILOHRIIVHW
/HQJWKVSHFLILHVWKHQXPEHURIZRUGVWREHWUDQVIHUUHG±DQ
LPPHGLDWHYDOXHRUDORJLFDODGGUHVVWKDWVSHFLILHVWKH
QXPEHURIZRUGVWREHWUDQVIHUUHG
6RXUFHVSHFLILHVDGDWDWDEOHDGGUHVVWREHXVHGDVWKHVRXUFHRI
WKHZRUGVWREHWUDQVIHUUHG
,PSRUWDQW 7KH6RXUFHVKRXOGEHWKHPDWFKLQJGDWDWDEOHDGGUHVVLQ
WKH'DWD2XWSXW)LOH'2)H[FHSWZKHQ\RXXVHWKH
LQVWUXFWLRQWRHQVXUHGDWDEORFNLQWHJULW\LQWKHFDVHRI
6HOHFWDEOH7LPHG,QWHUUXSWV67,V)RUPRUH
LQIRUPDWLRQVHHSDJH
1785-6.1 November 1998

Using IDI and IDO Instructions <RXFDQXVHWKH,',DQG,'2LQVWUXFWLRQVIRULPPHGLDWHGDWDLQSXW

DQGRXWSXWRQ&RQWURO1HW
)RUPRUHGHWDLOHGLQIRUPDWLRQDERXWZULWLQJODGGHUSURJUDPVVHH
\RXUSURJUDPPLQJPDQXDO
,PSRUWDQW %HFDUHIXOZKHQXVLQJ6HOHFWDEOH7LPHG,QWHUUXSWV
67,VZLWKDSURJUDPRQD&RQWURO1HWQHWZRUN
$6HOHFWDEOH7LPHG,QWHUUXSW67,SHULRGLFDOO\LQWHUUXSWVSULPDU\

SURJUDPH[HFXWLRQLQRUGHUWRUXQDVXESURJUDPWRFRPSOHWLRQ,IDQ
67,RFFXUVZKLOHDQRUPDO&RQWURO1HWQRQGLVFUHWH,2WUDQVIHURUD
&RQWURO1HW,PPHGLDWH'DWD,2LQVWUXFWLRQ,',RU,'2LVLQ
SURJUHVVDQGWKH\ERWKRSHUDWHRQWKHVDPHVHWRIGDWDWKHLQWHJULW\RI
WKDWEORFNRIGDWDLVMHRSDUGL]HG
7RHQVXUHGDWDEORFNLQWHJULW\ZULWH\RXU67,URXWLQHVRWKDWLW
RSHUDWHVRQLWVRZQFRS\RIWKHGDWDEORFNWKDWLWQHHGV8VH
&RQWURO1HW,PPHGLDWH'DWD,2LQVWUXFWLRQV,',DQG,'2ZLWKLQ
\RXU67,WRFRS\WKHQHHGHGEORFNRIGDWDRXWWRDQGEDFNIURPD
WHPSRUDU\ORFDWLRQWKDWLVGLIIHUHQWIURPWKDWXVHGE\WKHQRUPDO
GDWDWDEOH
)RUGHWDLOHGLQIRUPDWLRQRQ67,VVHH\RXUVRIWZDUHXVHUPDQXDO
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 2
Timer Instructions TON, TOF, RTO
Counter Instructions CTU, CTD
Reset RES
Using Timers and Counters 7LPHUVDQGFRXQWHUVOHW\RXFRQWURORSHUDWLRQVEDVHGRQWLPHRU
QXPEHURIHYHQWV7DEOH$OLVWVWKHDYDLODEOHWLPHUDQGFRXQWHU
LQVWUXFWLRQV
Table 2.A
Available Timer and Counter Instructions
Delay turning on an output TON 2-4
Delay turning off an output TOF 2-7
Time an event retentively RTO 2-10
Count up CTU 2-15
Count down CTD 2-17
Reset a counter, timer, or counter RE 2-20

instruction
$SSHQGL[&
Using Timers
%HIRUH\RXSURJUDPWLPHULQVWUXFWLRQV\RXQHHGWRXQGHUVWDQGWKH
SDUDPHWHUVWKDW\RXHQWHUIRUWLPHULQVWUXFWLRQVDQGKRZWLPHU
DFFXUDF\ZRUNV
1785-6.1 November 1998

2-2 Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES
Entering Parameters 7RSURJUDPDWLPHULQVWUXFWLRQSURYLGHWKHSURFHVVRUZLWKWKH

TON IROORZLQJLQIRUPDWLRQ
TIMER ON DELAY EN
Timer
7LPHULVWKHWLPHUFRQWURODGGUHVVLQWKHWLPHU7DUHDRIGDWD
Time base DN VWRUDJH8VHWKHIROORZLQJDGGUHVVIRUPDW
Preset
Accum T f : s
timer structure number (0-999)
timer file number (3-999)

timer (file type)
,PSRUWDQW <RXFDQXVHDQ\WLPHUILOHQXPEHUIURPWR
KRZHYHUWKHGHIDXOWWLPHUILOHQXPEHULV,I\RXZDQW
WRVSHFLI\DWLPHUILOHQXPEHUDVDQ\ILOHEHWZHHQDQG
RWKHUWKDQWKHGHIDXOW\RXPXVWILUVWGHOHWHWKH
HQWLUHGHIDXOWILOHIRUWKDWQXPEHUDQGWKHQFUHDWHWKH
WLPHUILOH)RUH[DPSOHLI\RXZDQWDWLPHUILOHQXPEHU
DVILOH\RXPXVWILUVWGHOHWHWKHHQWLUHGHIDXOWELQDU\
ILOHDQGWKHQFUHDWHWKHWLPHUILOHDVILOH
7RDFFHVVDWLPHUVWDWXVELWSUHVHWRUDFFXPXODWHGYDOXHVWRUHGDWWKH
WLPHUFRQWURODGGUHVVXVHWKHIROORZLQJDGGUHVVIRUPDW
Status Bit Preset Accumulated Value
Tf:s.sb Tf:s.PRE Tf:s.ACC
7KHVEVSHFLILHVDVWDWXVELWPQHPRQLFVXFKDV'1
,PSRUWDQW 7KHSURFHVVRUVWRUHVWLPHUVWDWXVELWVDQGWKHSUHVHWDQG
DFFXPXODWHGYDOXHVLQDELWVWRUDJHVWUXFWXUHWKUHH
ELWZRUGVLQDWLPHUILOH7
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
T4:0
EN TT DN internal use only Control word
for T4:0
preset value (16 bits)
accumulated value (16 bits)
T4:1 EN TT DN internal use only Control word

for T4:1
preset value (16 bits)

T4:2 .
.
.
1785-6.1 November 1998

Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES 2-3
7LPH%DVHGHWHUPLQHVKRZWKHWLPHURSHUDWHV7DEOH%OLVWVWKH
SRVVLEOHWLPHEDVHV
Table 1.B
Available Time Base Values
Enter This Time Base: The Accumulated Value Range Is:
1 second to 32,767 time-base intervals (to 9.1hours)
0.01 seconds (10ms) to 32,767 time-base intervals (to 5.5

minutes)
3UHVHWVSHFLILHVWKHYDOXHZKLFKWKHWLPHUPXVWUHDFKEHIRUHWKH
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Timer Accuracy 7LPHUDFFXUDF\UHIHUVWRWKHOHQJWKRIWLPHEHWZHHQWKHPRPHQWWKH

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FRPSOHWHVWKHWLPHGLQWHUYDO7LPHUDFFXUDF\GHSHQGVRQWKH
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VHFRQGVPVIRUDVHFRQGWLPHEDVHRUVHFRQGIRUDVHFRQG
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7KHGLVSOD\HGDFFXPXODWHGYDOXHRIDWLPHUVKRZVDFWXDOWLPHEXWLV
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1785-6.1 November 1998

Timer On Delay (TON)
Description: 8VHWKH721LQVWUXFWLRQWRWXUQDQRXWSXWRQRURIIDIWHUWKHWLPHUKDV
EHHQRQIRUDSUHVHWWLPHLQWHUYDO7KH721LQVWUXFWLRQVWDUWV
TON
TIMER ON DELAY EN
DFFXPXODWLQJWLPHZKHQWKHUXQJJRHVWUXHDQGFRQWLQXHVXQWLORQH
Timer RIWKHIROORZLQJKDSSHQV
Time base DN
Preset
WKHDFFXPXODWHGYDOXHHTXDOVLWVSUHVHWYDOXH
Accum WKHUXQJJRHVIDOVH
DUHVHWLQVWUXFWLRQUHVHWVWKHWLPHU
WKH6)&VWHSJRHVLQDFWLYH
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FRQGLWLRQVJRIDOVHUHJDUGOHVVRIZKHWKHUWKHWLPHUWLPHG
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Using Status Bits

([DPLQHVWDWXVELWVLQWKHODGGHUSURJUDPWRWULJJHUVRPHHYHQW7KH
SURFHVVRUFKDQJHVWKHVWDWHVRIVWDWXVELWVZKHQWKHSURFHVVRUUXQV
WKLVLQVWUXFWLRQ<RXDGGUHVVVWDWXVELWVE\PQHPRQLF
This Bit: Is Set When: Indicates: And Remains Set Until One of the
Following Occurs:
Timer Enable.EN (bit 15) the rung goes true that the timer is enabled • the rung goes false
• a reset instruction resets the timer
• the SFC step goes inactive
Timer Timing Bit .TT (bit 14) the rung goes true that a timing operation is • the rung goes false
in progress • the .DN bit is set (.ACC = .PRE)
• the associated SFC step goes inactive
Timer Done Bit .DN (bit 13) the accumulated value is that a timing operation • the rung goes false
equal to the preset value is complete • a reset instruction resets the timer
1785-6.1 November 1998

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\RXFDQSDXVHWKHWLPHU7KH(1DQG77ELWVUHPDLQVHWEXWWKH
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FOHDUWKH'1ELW,IWKHUXQJJRHVIDOVHZKLOHWKHWLPHULVSDXVHGWKH
WLPHUUHVHWVDVQRUPDO
,I\RXFKDQJHWR3URJUDPPRGHRUWKHSURFHVVRUORVHVSRZHU
EHIRUHWKHLQVWUXFWLRQUHDFKHVWKHSUHVHWYDOXHWKHIROORZLQJ
RFFXUV
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WLPHUWLPLQJ77ELWUHPDLQVVHW
DFFXPXODWHG$&&YDOXHUHPDLQVWKHVDPH
7KHQZKHQ\RXVZLWFKEDFNWR5XQPRGHRU7HVWPRGHRUSRZHU
LVUHVWRUHGWKHIROORZLQJKDSSHQV
Condition: Result:
If the rung is true: .EN bit remains set

.TT bit remains set
.DN bit remains reset
.ACC value is reset and starts counting up
If the rung is false: .EN bit is reset

.TT bit is reset
.DN bit is reset
.ACC value is reset
Figure 2.1
Example TON Ladder Diagram
I:012 TON
TIMER ON DELAY EN
10 When the input condition is true, the Timer T4:0
processor increments the accumulated value
of T4:0 in 1-second increments. Time base 1.0 DN
Preset 180
Accum 0
T4:0 Sets the output while the timer is timing O:013
TT 01
T4:0 Sets the output when the timer is done timing O:013
DN 02
When bit I:012/10 is set, the processor starts T4:0. The accumulated value increments in 1-second intervals.
T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.
When the timer is finished (.ACC = .PRE) T4:0.TT is reset (so O:013/01 and the associated output device is
de-energized) and T4:0.DN is set (so O:013/02 is set and the associated output device is energized). When the
accumulated value reaches 180, the .DN bit is set. Or if the rung goes false, the timer is reset.
1785-6.1 November 1998

Figure 2.2
Example TON Timing Diagram
ON
Rung Condition OFF
ON
Timer Enable Bit
OFF
ON
Timer Timing Bit OFF
ON
Timer Done Bit
OFF
Output Device ON
(Controlled by Done Bit) OFF
3 minutes ON
Delay
Timer Accumulated Value 2 minutes
(Accumulator)
180
120
0
Timer Preset = 180 16649
1785-6.1 November 1998

Timer Off Delay (TOF)
Description: 8VHWKH72)LQVWUXFWLRQWRWXUQDQRXWSXWRQRURIIDIWHULWVUXQJKDV
EHHQRIIIRUDSUHVHWWLPHLQWHUYDO7KH72)LQVWUXFWLRQVWDUWV
TOF
DFFXPXODWLQJWLPHZKHQWKHUXQJJRHVIDOVHDQGFRQWLQXHVWLPLQJ
TIMER OFF DELAY
Timer
EN
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Time base DN
WKHDFFXPXODWHGYDOXHHTXDOVLWVSUHVHWYDOXH
Preset
Accum WKHUXQJJRHVWUXH
DUHVHWLQVWUXFWLRQUHVHWVWKHWLPHU
7KHSURFHVVRUUHVHWVWKHDFFXPXODWHGYDOXHZKHQWKHUXQJFRQGLWLRQV
JRWUXHUHJDUGOHVVRIZKHWKHUWKHWLPHUWLPHGRXWRUQRW
Using Status Bits

WKLVLQVWUXFWLRQ<RXDGGUHVVWKHVWDWXVELWVE\PQHPRQLF
This Bit: Is Set When: And Remains Set Until One of the
Following Occurs:
Timer Enable .EN (bit 15) the rung goes true • the rung goes false
• the SFC step goes inactive
Timer Timing Bit .TT (bit 14) the rung goes false and the • the rung goes true
accumulated value is less than • the .DN bit is set (.ACC = .PRE)
the preset • a reset instruction resets the timer
Timer Done Bit .DN (bit 13) the rung goes true • the accumulated value is equal to the
preset value
1785-6.1 November 1998

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7KHQLI\RXVZLWFKWR5XQPRGHRU7HVWPRGHWKHIROORZLQJ
KDSSHQV
Condition: Result:
If the rung is true: .EN bit is set

.TT bit is reset
.DN bit remains set
.ACC value is cleared

.TT bit is reset
.DN bit is reset
.ACC value equals PRE value
(the timer does not start timing)
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1785-6.1 November 1998

Figure 2.3
Example TOF Ladder Diagram
I:012 TOF
TIMER OFF DELAY EN
10 Timer T4:0
When the input goes false, the processor starts
incrementing the accumulated value in T4:0 in Time base 1.0 DN
1-second increments until the input goes true.
Preset 180
Accum 0
T4:0 Sets the output while the timer is timing O:013
TT 01
T4:0 Resets the output when the timer is done timing O:013
DN 02
When bit I:012/10 is reset, the processor starts timer T4:0. The accumulated value increments by 1-second intervals as long as the
rung remains false. T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.
When the timer is finished (.ACC = .PRE), T4:0.TT is reset (so O:013/01 is reset and the associated output device is de-energized)
and T4:0.DN is reset (so O:013/02 is reset and the associated output device is de-energized). When the accumulated value reaches
180 or when the rung conditions go true, the timer stops.
Figure 2.4
Example TOF Timing Diagram
ON
Rung Condition OFF
ON
Timer Enable Bit
OFF
ON
Timer Timing Bit
OFF
ON
Timer Done Bit
OFF
Output Device ON
(Controlled by Done Bit)
OFF
OFF Delay
2 minutes 3 minutes
Time 180
120
Timer Accumulated Value

(Accumulator) 0
1785-6.1 November 1998

Retentive Timer On (RTO)
Description: 8VHWKH572LQVWUXFWLRQWRWXUQDQRXWSXWRQRURIIDIWHULWVWLPHUKDV
EHHQRQIRUDSUHVHWWLPHLQWHUYDO7KH572LQVWUXFWLRQOHWVWKHWLPHU
RTO
RETENTIVE TIMER ON
VWRSDQGVWDUWZLWKRXWUHVHWWLQJWKHDFFXPXODWHGYDOXH
EN
Timer
7KH572LQVWUXFWLRQEHJLQVWLPLQJZKHQLWVUXQJJRHVWUXH$VORQJ
Time base DN
DVWKHUXQJUHPDLQVWUXHWKHWLPHUXSGDWHVWKHDFFXPXODWHGYDOXH
Preset
Accum
HDFKSURJUDPVFDQXQWLOLWUHDFKHVWKHSUHVHWYDOXH7KH572
LQVWUXFWLRQUHWDLQVLWVDFFXPXODWHGYDOXHHYHQLIRQHRIWKHIROORZLQJ
RFFXUV
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\RXFKDQJHWR3URJUDPPRGH
WKHSURFHVVRUIDXOWVRUORVHVSRZHU
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FRQWLQXHVIURPWKHUHWDLQHGDFFXPXODWHGYDOXH%\UHWDLQLQJLWV
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Using Status Bits

This Bit: Is Set When: Indicates: And Remains Set Until One of the
Following Occurs:
Timer Enable Bit .EN (bit 15) the rung goes true that a timing operation is • the rung goes false
in progress • a reset instruction resets the timer
Timer Timing Bit .TT (bit 14) the rung goes true that a timing operation is • the rung goes false
in progress • the .DN bit is set
• the accumulated value is equal to
the preset value (.ACC=.PRE)
Timer Done Bit .DN (bit 13) the accumulated value is that a timing operation • the .DN bit is reset with the
equal to the preset value is complete RES instruction.
1785-6.1 November 1998

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:KHQ\RXVZLWFKEDFNWR5XQPRGHRU7HVWPRGHWKHIROORZLQJ
KDSSHQV
Condition: Result:
If the rung is true: .EN bit remains set

.TT bit remains set
.ACC value continues timing

.TT bit is reset
.DN bit remains the same
.ACC value remains the same
Figure 2.5
Example RTO Ladder Diagram
I:012 RTO
RETENTIVE TIMER ON EN
10 Timer T4:10
When the input is true, the processor starts incrementing
the accumulated value of T4:10 in 1-second increments. Time base 1.0 DN
The timer values remain when the input goes false. Preset 180
Accum 0
I:017 Resets the timer T4:10

RES
12
1785-6.1 November 1998

Figure 2.6
Retentive Timer Timing Diagram
ON
Rung Condition OFF
ON
Timer Enable Bit
OFF
ON
Reset Pulse
OFF
ON
Timer Timing Bit
OFF
ON
Timer Done Bit
OFF
ON
Output Device OFF

(Controlled by Done Bit)
180
120
100
Timer Accumulated Value
(Accumulator) 40
0
1785-6.1 November 1998

Using Counters %HIRUHXVLQJFRXQWHULQVWUXFWLRQV\RXQHHGWRXQGHUVWDQGWKH

CTU
SDUDPHWHUVWKDW\RXHQWHU
COUNT UP CU
Counter Entering Parameters
Preset DN
Accum 7RSURJUDPDFRXQWHULQVWUXFWLRQSURYLGHWKHSURFHVVRUZLWKWKHIROORZLQJ
LQIRUPDWLRQ
&RXQWHULVWKHFRXQWHUFRQWURODGGUHVVLQWKHFRXQWHU&DUHDRI
GDWDVWRUDJH8VHWKHIROORZLQJDGGUHVVIRUPDW
C f : s
counter structure number (0-999)
counter file number (3-999)

counter (file type)
,PSRUWDQW <RXFDQXVHDQ\FRXQWHUILOHQXPEHUIURPWR
KRZHYHUWKHGHIDXOWFRXQWHUILOHQXPEHULV,I\RX
ZDQWWRVSHFLI\DFRXQWHUILOHQXPEHUDVDQ\ILOH
EHWZHHQDQGRWKHUWKDQWKHGHIDXOW\RXPXVW
ILUVWGHOHWHWKHHQWLUHGHIDXOWILOHIRUWKDWQXPEHUDQG
WKHQFUHDWHWKHFRXQWHUILOH)RUH[DPSOHLI\RXZDQWD
FRXQWHUILOHQXPEHUDVILOH\RXPXVWILUVWGHOHWHWKH
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DVILOH
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WKHIROORZLQJDGGUHVVIRUPDW
Status Bit Preset Accumulated Value
Cf:s.bb Cf:s.PRE Cf:s.ACC
7KHEELVDVWDWXVELWPQHPRQLFVXFKDV'1
,PSRUWDQW 7KHSURFHVVRUVWRUHVFRXQWHUVWDWXVELWVDQGWKHSUHVHW
DQGDFFXPXODWHGYDOXHVLQDVWRUDJHVWUXFWXUHELWV±
WKUHHELWZRUGVLQDFRXQWHUILOH&LQWKHGDWDWDEOH
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
C5:0
CU CD DN OV UN internal use only Control word
preset (16 bits) for C5:0

C5:1 CU CD DN OV UN internal use only Control word
for C5:1
preset (16 bits)

C5:2 ..
.
1785-6.1 November 1998

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VHWVWKHGRQHELW'1(QWHUDSUHVHWYDOXHIURP±XSWR
7KHSUHVHWYDOXHLVVWRUHGDVDELWLQWHJHUYDOXH
1HJDWLYHYDOXHVDUHVWRUHGLQWZRVFRPSOHPHQWIRUP
$FFXPXODWHG9DOXHLVWKHFXUUHQWFRXQWEDVHGRQWKHQXPEHURI
WLPHVWKHUXQJJRHVIURPIDOVHWRWUXH7KHDFFXPXODWHGYDOXHLV
VWRUHGDVDELWLQWHJHUYDOXH1HJDWLYHYDOXHVDUHVWRUHGLQ
WZRVFRPSOHPHQWIRUP7KHUDQJHRIWKHDFFXPXODWHGYDOXHLV±
WR7\SLFDOO\\RXHQWHUD]HURYDOXHZKHQ
SURJUDPPLQJFRXQWHULQVWUXFWLRQV,I\RXHQWHUDQRQ]HURYDOXH
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UHVHWWKHDFFXPXODWHGYDOXHLVVHWWR]HUR
1785-6.1 November 1998

Count Up (CTU)
Description: 7KH&78LQVWUXFWLRQFRXQWVXSZDUGRYHUDUDQJHRI±WR
CTU
(DFKWLPHWKHUXQJJRHVIURPIDOVHWRWUXHWKH&78
COUNT UP CU LQVWUXFWLRQLQFUHPHQWVWKHDFFXPXODWHGYDOXHE\RQHFRXQW:KHQ
Counter WKHDFFXPXODWHGYDOXHHTXDOVRUH[FHHGVWKHSUHVHWYDOXHWKH
Preset DN &78LQVWUXFWLRQVHWVDGRQHELW'1ZKLFK\RXUODGGHUSURJUDPFDQ
Accum
XVHWRLQLWLDWHVRPHDFWLRQVXFKDVFRQWUROOLQJDVWRUDJHELWRUDQ
RXWSXWGHYLFH
7KHDFFXPXODWHGYDOXHRIDFRXQWHULVUHWHQWLYH7KHFRXQWLVUHWDLQHG
XQWLOUHVHWE\DUHVHWLQVWUXFWLRQ5(6WKDWKDVWKHVDPHDGGUHVVDV
WKHFRXQWHU
Using Status Bits

SURFHVVRUFKDQJHVWKHVWDWHVRIVWDWXVELWVZKHQWKHSURFHVVRUUXQVWKH
&78LQVWUXFWLRQ<RXDGGUHVVWKHVWDWXVELWVE\PQHPRQLF
This Bit: Is Set: And Remains Set Until One of the Following Occurs:
Count Up when the rung goes true to indicate the • the rung goes false
Enable Bit .CU (bit 15) instruction has increased its count • a RES instruction resets the .DN bit
Note: During prescan, this bit is set to prevent
a false count when the program scan begins.
Count Up when the accumulated value is greater than or • the accumulated value counts below the preset, either
Done Bit .DN (bit 13) equal to the preset value by using a CTD instruction to count down or changing
the accumulated value
• a RES instruction resets the .DN bit
Count Up when the up counter has exceeded the upper • a RES instruction resets the .DN bit
Overflow Bit .OV (bit 12) limit of +32,767 and has wrapped around to – • counting back down to 32,767 with a CTD instruction
32,768. The CTU counts up from there. with the same address
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1785-6.1 November 1998

Figure 2.7
Example CTU Ladder Diagram
I:012 CTU
COUNT UP CU
10 Each time the input goes false to true, Counter C5:0
the processor increments the counter
by 1. Preset 4 DN
Accum 0
C5:0 Tells when the count is reached (ACC > or = PRE) O:020
01
DN
C5:0 Tells when the counter overflows +32,767 O:021
02
OV
I:017 Reset the counter C5:0
RES
12
Figure 2.8
Example CTU Timing Diagram
Counter preset = 4 counts
Rung condition that ON

controls counter OFF
ON
Count-up enable bit
OFF
Rung condition that ON

controls reset instruction
OFF
ON
Done Bit
OFF
Output instruction on rung ON

controlled by counter
OFF
4
3
2
1 0
Counter Accumulated Value 0 16636
1785-6.1 November 1998

Count Down (CTD)
Description: 7KH&7'LQVWUXFWLRQFRXQWVGRZQZDUGRYHUDUDQJHRIWR
CTD
±(DFKWLPHWKHUXQJJRHVIURPIDOVHWRWUXHWKH&7'
COUNT DOWN CD
LQVWUXFWLRQGHFUHPHQWVWKHDFFXPXODWHGYDOXHE\RQHFRXQW7KH
Counter GRQHELW'1LVVHWDVORQJDVWKHDFFXPXODWHGYDOXHLVJUHDWHUWKDQRU
Preset DN HTXDOWRWKHSUHVHWYDOXH:KHQWKHDFFXPXODWHGYDOXHLVOHVVWKDQWKH
Accum SUHVHWYDOXHWKHGRQHELW'1LVUHVHWZKLFK\RXUODGGHUSURJUDPFDQ
XVHWRLQLWLDWHVRPHDFWLRQVXFKDVFRQWUROOLQJDVWRUDJHELWRUDQ
RXWSXWGHYLFH
7KHDFFXPXODWHGYDOXHRIDFRXQWHULVUHWHQWLYH7KHFRXQWLVUHWDLQHG
XQWLOUHVHWE\DUHVHWLQVWUXFWLRQ5(6WKDWKDVWKHVDPHDGGUHVVDV
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Using Status Bits

This Bit: Is Set: And Remains Set Until One of the Following Occurs:
Count Down when the rung goes true to indicate that the • the rung goes false
Enable Bit .CD (bit 14) counter is enabled as a down-counter. • a RES instruction resets the .DN bit
Note: During prescan, this bit is set to prevent
a false count when the program scan begins.
Count Down when the accumulated value is greater than or • the accumulated value counts below the preset
Done Bit .DN (bit 13) equal to the preset value. • another instruction changes the accumulated value
• a RES instruction resets the .DN bit
Count Down by the processor to show that the down • a RES instruction resets the .DN bit
Underflow Bit (.UN) (Bit 11) counter went below the lower limit of –32,768 • count back up to -32,768 with a CTU instruction
and has wrapped around to +32,767. The CTD
instruction counts down from there.
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1785-6.1 November 1998

Figure 2.9
Example CTD Ladder Diagram
I:012 CTD
COUNT DOWN CD
10 Each time the input goes from false to true, Counter C5:0
the processor decrements the counter by 1.
Preset 4 DN
Accum 8
DN 01
C5:0 Tells when the counter underflows -32,768 O:021
UN 02
I:017 Resets the counter C5:0

RES
12
Figure 2.10
Example CTD Timing Diagram
Counter preset = 4 counts
Counter accumulated = 8
ON
Rung condition that
controls counter OFF
Count-up enable bit
Rung condition that

controls reset instruction
Done Bit
Output instruction on rung

controlled by counter
8
7
Counter Accumulated Value 6
5
4
3
0
16637
1785-6.1 November 1998

Figure 2.11
Example CTU and CTD Logic Diagram
I:012 CTU
Count up pushbutton
COUNT UP CU
10 Counter C5:0
Preset 4 DN
Accum 0
I:012 CTD
Count down pushbutton
COUNT DOWN CD
11 Counter C5:0
Preset 4
DN
Accum 0
DN 01
C5:0 Tells when the counter overflows +32,767 O:013
OV 02
C5:0 Tells when the counter underflows -32,768 O:013
UN 03
RES
12
Figure 2.12
Example CTU and CTD Timing Diagram
ON
Count Up Pushbutton
OFF
ON
Count Down Pushbutton OFF
ON
Reset Pulse
OFF
ON
Done Bit
OFF
5
4 4
3 3 3
2 2 2
1 1 1
0 0
Counter Accumulated Value
Count Up Preset = 4
Count Down Preset = 4 16652
1785-6.1 November 1998

Timer and Counter Reset (RES)
Description: 7KH5(6LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWUHVHWVDWLPHURU
FRXQWHU7KH5(6LQVWUXFWLRQH[HFXWHVZKHQLWVUXQJLVWUXH
RES
When Using a RES Instruction for a: The Processor Resets the:
Timer .ACC value

(Do not use a RES instruction for a TOF.) .EN bit
.TT bit
.DN bit
Counter .ACC value

.EN bit
.OV or .UN bit
.DN bit
,IWKHFRXQWHUUXQJLVHQDEOHGWKH&8RU&'ELWZLOOEHUHVHWDVORQJ
DVWKH5(6LQVWUXFWLRQLVHQDEOHG
,PSRUWDQW <RXFDQXVHDQHJDWLYHSUHVHWYDOXHLQD&78RU&7'
LQVWUXFWLRQLI\RXLQWHQGWRXVHWKH5(6LQVWUXFWLRQ
+RZHYHUQRWHWKDWWKH5(6LQVWUXFWLRQVHWVWKH
DFFXPXODWHGYDOXHWR]HURZKLFKPD\VHWWKH'1ELW
DQGSUHYHQWWKH&78RU&7'LQVWUXFWLRQIURPRSHUDWLQJ
WKHQH[WWLPHLWLVHQDEOHG
$77(17,21 %HFDXVHWKH5(6LQVWUXFWLRQUHVHWVWKH
DFFXPXODWHGYDOXH'1ELWDQG77ELWRIDWLPLQJ
LQVWUXFWLRQGRQRWXVHWKH5(6LQVWUXFWLRQWRUHVHWD72)
LQVWUXFWLRQXQSUHGLFWDEOHPDFKLQHRSHUDWLRQRULQMXU\
WRSHUVRQQHOPD\RFFXU
Figure 2.13
Example RES Ladder Diagram
I:012 CTD
COUNT DOWN CD
10 Each time the input goes from false to true, the Counter C5:0
processor decrements the counter by 1.
Preset 4 DN
Accum 8
DN 01

RES
12
1785-6.1 November 1998

Chapter 3
Compare Instructions CMP, EQU, GEQ,
GRT, LEQ, LES, LIM, MEQ, NEQ
Using Compare Instructions 7KHFRPSDULVRQLQVWUXFWLRQVOHW\RXFRPSDUHYDOXHVXVLQJDQ
H[SUHVVLRQRUDVSHFLILFFRPSDULVRQLQVWUXFWLRQ7DEOH$OLVWVWKH
DYDLODEOHFRPSDUHLQVWUXFWLRQV
Table 3.A
Available Compare Instructions
Use the On
If You Want to:
Instruction: Page:
Compare values based on an expression CMP 3-2
Test whether two values are equal EQU 3-5
Test whether one value is greater than or equal to a GEQ 3-5

second value
Test whether one value is greater than a second value GRT 3-6
Test whether one value is less than or equal to a LEQ 3-6

second value
Test whether one value is less than a second value LES 3-7
Test whether one value is between two other values LIM 3-7
Pass two values through a mask and test whether MEQ 3-9
they are equal
Test whether one value is not equal to a second value NEQ 3-10
,PSRUWDQW <RXFDQFRPSDUHYDOXHVRIGLIIHUHQWGDWDW\SHVVXFKDV
IORDWLQJSRLQWDQGLQWHJHU<RXVKRXOGXVH%&'DQG
$6&,,YDOXHVIRUGLVSOD\SXUSRVHV,I\RXHQWHU%&'RU
$6&,,YDOXHVWKHSURFHVVRUWUHDWVWKRVHYDOXHVDV
LQWHJHUV)RUH[DPSOHLIWKHYDOXHDW1LV
GHFLPDODQGWKHYDOXHDW'LV%&'WKH
FRPSDULVRQRI1 'HYDOXDWHVDVIDOVH7KHLQ
%&'WUDQVODWHVWRWKHLQ
GHFLPDOWUDQVODWHVWR
7KHSDUDPHWHUV\RXHQWHUDUHSURJUDPFRQVWDQWVRUORJLFDODGGUHVVHV
RIWKHYDOXHV\RXZDQWWRFRPSDUH
$SSHQGL[&
1785-6.1 November 1998

3-2 Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ
Using Arithmetic Status Flags 7KHDULWKPHWLFVWDWXVIODJVDUHLQZRUGELWVLQWKHSURFHVVRU

VWDWXVILOH60RQLWRUWKHVHELWVLI\RXSHUIRUPDQDULWKPHWLF
IXQFWLRQZLWKLQWKH&03LQVWUXFWLRQ7DEOH%OLVWVWKHVWDWXVELWV
Table 3.B
Arithmetic Status Bits
This Bit: Description:
S:0/0 Carry (C)
S:0/1 Overflow (V)
S:0/2 Zero (Z)
S:0/3 Sign (S)
Compare (CMP) 7KH&03LQVWUXFWLRQFRPSDUHVYDOXHVDQGSHUIRUPVORJLFDO

FRPSDULVRQV
Description: 7KH&03LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWSHUIRUPVD
CMP FRPSDULVRQRQDULWKPHWLFRSHUDWLRQV\RXVSHFLI\LQWKHH[SUHVVLRQ
COMPARE :KHQWKHSURFHVVRUILQGVWKHH[SUHVVLRQLVWUXHWKHUXQJJRHVWUXH
Expression 2WKHUZLVHWKHUXQJLVIDOVH:LWK(QKDQFHG3/&SURFHVVRUV\RX
FDQHQWHUPXOWLSOHRSHUDQGVFRPSOH[H[SUHVVLRQ
7KHH[HFXWLRQWLPHRID&03LQVWUXFWLRQLVORQJHUWKDQWKHH[HFXWLRQ
WLPHRIRQHRIWKHRWKHUFRPSDULVRQLQVWUXFWLRQVHJ*57/(4
HWF$&03LQVWUXFWLRQDOVRXVHVPRUHZRUGVLQ\RXUSURJUDPILOH
WKDQWKHFRUUHVSRQGLQJFRPSDULVRQLQVWUXFWLRQ
Entering the CMP Expression

7KHH[SUHVVLRQGHILQHVWKHRSHUDWLRQV\RXZDQWWRSHUIRUP'HILQH
WKHH[SUHVVLRQZLWKRSHUDWRUVDQGDGGUHVVHVRUSURJUDPFRQVWDQWV
:LWK(QKDQFHG3/&SURFHVVRUV\RXFDQHQWHUFRPSOH[
H[SUHVVLRQV7DEOH&OLVWVYDOLGRSHUDWLRQVIRUDQH[SUHVVLRQWKH
IROORZLQJOLVWSURYLGHVJXLGHOLQHVIRUZULWLQJH[SUHVVLRQV
2SHUDWRUVV\PEROVGHILQHWKHRSHUDWLRQV
$GGUHVVHVFDQEHGLUHFWLQGLUHFWRULQGH[HGDGGUHVVHVPXVWEH
ZRUGOHYHO
:LWK(QKDQFHG3/&SURFHVVRUVSURJUDPFRQVWDQWVFDQEH
LQWHJHURUIORDWLQJSRLQWQXPEHUVLI\RXHQWHURFWDOYDOXHVXVHD
OHDGLQJ 2LI\RXHQWHUKH[DGHFLPDOYDOXHVXVHDOHDGLQJ +
LI\RXHQWHUELQDU\YDOXHVXVHDOHDGLQJ %
1785-6.1 November 1998

Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ 3-3
Table 3.C
Valid Operations for Use in a CMP Expression
Type Operator Description Example Operation
Comparison = equal to if A = B, then ...
<> not equal to if A <> B, then ...
< less than if A < B, then ...
<= less than or equal to if A <= B, then ...
> greater than if A > B, then ...
>= greater than or equal to if A >= B, then ...
Arithmetic + add 2 + 3 Enhanced PLC-5 processor:

2+3+7
– subtract 12 – 5
* multiply 5 * 2 PLC-5/30, -5/40, -5/60,

-5/80: 6 * (5 * 2)
| (vertical bar) divide 24 | 6
– negate – N7:0
SQR square root SQR N7:0
** exponential 10**3
(x to the power of y) (Enhanced PLC-5 processors only)
Conversion FRD convert from BCD FRD N7:0

to binary
TOD convert from binary TOD N7:0

to BCD
Determining the Length of an Expression

(QKDQFHG3/&SURFHVVRUVVXSSRUWFRPSOH[LQVWUXFWLRQVXSWRD
WRWDORIFKDUDFWHUVLQFOXGLQJVSDFHVDQGSDUHQWKHVHV'HSHQGLQJ
RQWKHRSHUDWRUWKHSURFHVVRULQVHUWVFKDUDFWHUVEHIRUHDIWHUWKH
RSHUDWRULQ\RXUH[SUHVVLRQWRIRUPDWWKHH[SUHVVLRQIRUHDVLHU
LQWHUSUHWDWLRQ8VH7DEOH'WRGHWHUPLQHWKHQXPEHURIFKDUDFWHUV
HDFKRSHUDWRUXVHVLQDQH[SUHVVLRQ
,PSRUWDQW <RXFDQQRWHQWHUIORDWLQJSRLQWQXPEHUVLQVFLHQWLILF
QRWDWLRQZLWKQHJDWLYHH[SRQHQWVLQFRPSOH[
H[SUHVVLRQV,QVWHDGXVHWKHGHFLPDOHTXLYDOHQWRUSXW
WKHQXPEHULQDIORDWLQJSRLQWILOHDQGXVHWKHGDWD
DGGUHVVLQWKHFRPSOH[H[SUHVVLRQ
1785-6.1 November 1998

:LWKWKH&03LQVWUXFWLRQDPD[LPXPRIFKDUDFWHUVRIWKH
H[SUHVVLRQFDQEHGLVSOD\HG,IWKHH[SUHVVLRQ\RXHQWHULVQHDUWKLV
FKDUDFWHUPD[LPXPZKHQ\RXDFFHSWWKHUXQJFRQWDLQLQJWKH
LQVWUXFWLRQWKHSURFHVVRUPD\H[SDQGLWEH\RQGFKDUDFWHUV:KHQ
\RXWU\WRHGLWWKHH[SUHVVLRQRQO\WKHILUVWFKDUDFWHUVDUH
GLVSOD\HGDQGWKHUXQJLVGLVSOD\HGDVDQHUURUUXQJ7KHSURFHVVRU
GRHVFRQWDLQWKHFRPSOHWHH[SUHVVLRQKRZHYHUDQGWKHLQVWUXFWLRQ
UXQVSURSHUO\
7RDYRLGWKLVGLVSOD\SUREOHPH[SRUWWKHSURFHVVRUPHPRU\ILOHDQG
PDNH\RXUHGLWVLQWKH3&WH[WILOH7KHQLPSRUWWKLVWH[WILOH)RU
PRUHLQIRUPDWLRQRQLPSRUWLQJH[SRUWLQJSURFHVVRUPHPRU\ILOHVVHH
Table 3.D
Character Lengths for Operators
Uses this Number

This Operation: Using this Operator:
of Characters:
math binary +, –, *, | 3
OR, ** 4
AND, XOR 5
math unary – (negate) 2
LN 3
FRD, TOD, DEG, RAD, SQR, NOT, LOG, SIN, 4

COS, TAN, ASN, ACS, ATN
comparative =, <, > 3
<>, <=, >= 4
Example:
CMP O:013
COMPARE
Expression 01
(N7:0 + N7:1) > (N7:2 + N7:3)
The CMP instruction tells an Enhanced PLC-5 processor: if the sum of the values in N7:0 and N7:1 is greater than the sum of the
values in N7:2 and N7:3, set output bit O:013/01. (The total number of characters used in this expressions is 3.)
)RUPRUHLQIRUPDWLRQRQHQWHULQJFRPSOH[H[SUHVVLRQVVHHFKDSWHU
1785-6.1 November 1998

Equal to (EQU)
Description: 8VHWKH(48LQVWUXFWLRQWRWHVWZKHWKHUWZRYDOXHVDUHHTXDO
6RXUFH $DQG6RXUFH%FDQHLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQ
EQU
YDOXHV
EQUAL
Source A
Source B
Example:
EQU O:013
EQUAL
Source A N7:5 01
Source B N7:10
If the value in N7:5 is equal to the value in N7:10, set output bit O:013/01.
)ORDWLQJSRLQWYDOXHVDUHUDUHO\DEVROXWHO\HTXDO,I\RXQHHGWR
GHWHUPLQHWKHHTXDOLW\RIIORDWLQJSRLQWYDOXHVXVHWKH/,0
LQVWUXFWLRQLQVWHDGRIWKH(48)RULQIRUPDWLRQRQWKH/,0
LQVWUXFWLRQVHHSDJH
Greater than or Equal to (GEQ)
Description: 8VHWKH*(4LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LV

GEQ JUHDWHUWKDQRUHTXDOWRDQRWKHUYDOXH6RXUFH%6RXUFH$DQG
GREATER THAN OR EQUAL 6RXUFH%FDQEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV
Source A
Source B
Example:
GEQ O:013
GREATER THAN OR EQUAL
Source A N7:5 01
Source B N7:10
If the value in N7:5 is greater than or equal to the value in N7:10, set output bit O:013/01.
1785-6.1 November 1998

Greater than (GRT)
Description: 8VHWKH*57LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LV

GRT
JUHDWHUWKDQDQRWKHUYDOXH6RXUFH%6RXUFH$DQG6RXUFH%FDQ
GREATER THAN OR EQUAL
HLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV
Source A
Source B
Example:
GRT O:013
GREATER THAN
Source A N7:5 01
Source B N7:10
If the value in N7:5 is greater than the value in N7:10, set output bit O:013/01.
Less than or Equal to (LEQ)
Description: 8VHWKH/(4LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LVOHVV

LEQ
WKDQRUHTXDOWRDQRWKHUYDOXH6RXUFH%6RXUFH$DQG6RXUFH%FDQ
LESS THAN OR EQUAL
HLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV
Source A
Source B
Example:
LEQ O:013
LESS THAN OR EQUAL
Source A N7:5 01
Source B N7:10
If the value in N7:5 is less than or equal to the value in N7:10, set output bit O:013/01.
1785-6.1 November 1998

Less than (LES)
Description: 8VHWKH/(6LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LVOHVV

LES WKDQDQRWKHUYDOXH6RXUFH%6RXUFH$DQG6RXUFH%FDQEHYDOXHV
LESS THAN RUDGGUHVVHVWKDWFRQWDLQYDOXHV
Source A
Source B
Example:
LES O:013
LESS THAN
Source A N7:5 01
Source B N7:10
If the value in N7:5 is less than the value in N7:10, set output bit O:013/01.
Limit Test (LIM)
Description: 7KH/,0LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWWHVWVIRUYDOXHVLQVLGH
LIM RIRURXWVLGHRIDVSHFLILHGUDQJH7KHLQVWUXFWLRQLVIDOVHXQWLOLW
LIMIT TEST (CIRC) GHWHFWVWKDWWKHWHVWYDOXHLVZLWKLQFHUWDLQOLPLWV7KHQWKHLQVWUXFWLRQ
Low limit JRHVWUXH:KHQWKHLQVWUXFWLRQGHWHFWVWKDWWKHWHVWYDOXHJRHVRXWVLGH
Test FHUWDLQOLPLWVLWJRHVIDOVH
High limit
<RXFDQXVHWKH/,0LQVWUXFWLRQWRWHVWLIDQDQDORJLQSXWYDOXHLV
ZLWKLQVSHFLILHGOLPLWV
Entering Parameters
7RSURJUDPWKH/,0LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJ
Parameter: Definition:
Low Limit a constant or an address from which the instruction reads the
lower range of the specified limit range. The address contains an
integer or floating-point value.
Test Value the address that contains the integer or floating-point value you
examine to see whether the value is inside or outside the
specified limit range.
High Limit a constant or an address from which the instruction reads the
upper range of the specified limit range. The address contains an
integer or floating-point value.
1785-6.1 November 1998

LIM Example Using Integer: ,IYDOXH/RZ/LPLW≤YDOXH+LJK/LPLW:KHQWKHSURFHVVRU

GHWHFWVWKDWWKHYDOXHRI%7HVWLVHTXDOWRRUEHWZHHQOLPLWVWKH
LQVWUXFWLRQLVWUXHLIYDOXH7HVWLVRXWVLGHWKHOLPLWVWKH
LQVWUXFWLRQLVIDOVH
false < -------true------ > false
from -32,768 . . . . . . . . . . . . A ................C .......... to +32,767
< value B >
,IYDOXH/RZ/LPLW≥YDOXH+LJK/LPLW:KHQWKHSURFHVVRU
GHWHFWVWKDWWKHYDOXHRI7HVWLVHTXDOWRRURXWVLGHWKHOLPLWVWKH
LQVWUXFWLRQLVWUXHLIYDOXH7HVWLVEHWZHHQEXWQRWHTXDOWRHLWKHU
OLPLWWKHLQVWUXFWLRQLVIDOVH
true < ------false------ > true
from -32,768 . . . . . . . . . . . . C A . . . . . . . . . . . . to +32,767
value B < < value B
Example (when the Low Limit is less

than the High Limit):
LIM O:013
LIMIT TEST (CIRC)
Low lim N7:10 01
Test N7:15
High lim N7:20
If the value in N7:15 is greater than or equal to the value in N7:10 and less than or equal to the value in
N7:20, set output bit O:013/01.
1785-6.1 November 1998

Mask Compare Equal to (MEQ)
Description: 7KH0(4LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWFRPSDUHVDYDOXH
MEQ IURPDVRXUFHDGGUHVVZLWKGDWDDWDFRPSDUHDGGUHVVDQGDOORZV
MASKED EQUAL SRUWLRQVRIWKHGDWDWREHPDVNHG,IWKHGDWDDWWKHVRXUFHDGGUHVV
Source PDWFKHVWKHGDWDDWWKHFRPSDUHDGGUHVVELWE\ELWOHVVPDVNHGELWV
Mask WKHLQVWUXFWLRQLVWUXH7KHLQVWUXFWLRQJRHVIDOVHDVVRRQDVLWGHWHFWVD
Compare PLVPDWFK
<RXFDQXVHWKH0(4LQVWUXFWLRQWRH[WUDFWIRUFRPSDULVRQELWGDWD
VXFKDVVWDWXVRUFRQWUROELWVIURPDQHOHPHQWWKDWFRQWDLQVELWDQG
ZRUGGDWD
Entering Parameters
7RSURJUDPWKH0(4LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRU
ZLWKWKH IROORZLQJ
Source a program constant or data address from which the instruction reads an
image of the value. The source remains unchanged.
Mask specifies which bits to pass or block. A mask passes data when the
mask bits are set (1); a mask blocks data when the mask bits are reset
(0). The mask must be the same element size (16-bits) as the source
and compare address. In order for bits to be compared, you must set (1)
mask bits; bits in the compare address that correspond to zeros (0) in
the mask are not compared. If you want the ladder program to change
the mask value, store the mask at a data address. Otherwise, enter a
hexadecimal value for a constant mask value. If you enter a hexadecimal
value that starts with a letter (such a F800), enter the value with a
leading zero. For example, type 0F800
Compare specifies whether you want the ladder program to vary the compare
value, or a program constant for a fixed reference. Use 16-bit elements,
the same as the source.
Example: Source 01010101 01011111

Mask 11111111 11110000
Compare 01010101 0101xxxx
Result The instruction is true because
reference bits xxxx are not compared.
MEQ O:013
MASKED EQUAL
01
Source N7:5
Mask N7:6
Compare N7:10
The processor passes the value in N7:5 through the mask in N7:6. It then passes the value in N7:10 through the mask
in N7:6. If the two masked values are equal, set output bit O:013/01
1785-6.1 November 1998

Not Equal to (NEQ)
Description: 8VHWKH1(4LQVWUXFWLRQWRWHVWZKHWKHUWZRYDOXHVDUHQRWHTXDO
NEQ 6RXUFH$DQG6RXUFH%FDQEHYDOXHVRUDGGUHVVHV
NOT EQUAL
Source A
Source B
Example:
NEQ O:013
NOT EQUAL
Source A N7:5 01
Source B N7:10
If the value in N7:5 is not equal to the value in N7:10, set output bit O:013/01.
1785-6.1 November 1998

Chapter 4
Compute Instructions CPT, ACS, ADD,
ASN, ATN, AVE, CLR, COS, DIV, LN, LOG,
MUL, NEG, SIN, SRT, SQR, STD, SUB,
TAN, XPY
Using Compute Instructions 7KHFRPSXWHLQVWUXFWLRQVHYDOXDWHDULWKPHWLFRSHUDWLRQVXVLQJDQ
H[SUHVVLRQRUDVSHFLILFDULWKPHWLFLQVWUXFWLRQ7DEOH$OLVWVWKH
DYDLODEOHFRPSXWHLQVWUXFWLRQV
Table 4.A
Available Compute Instructions
Use this Found on

If You Want to:
Instruction: Page:
Evaluate an expression CPT 4-5
Take the arc cosine of a number ACS* 4-11
Add two values ADD 4-12
Take the arc sine of a number ASN* 4-13
Take the arc tangent of a number ATN* 4-14
Calculate the average for a set of values AVE* 4-15
Clear an address word (set all bits to zero) CLR 4-17
Take the cosine of a number COS* 4-18
Divide two values DIV 4-19
Take the natural log of a number LN* 4-20
Take the log of a number LOG* 4-21
* Only Enhanced PLC-5 processors support this instruction.
(Continued)
1785-6.1 November 1998

4-2 Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY
Use this Found on

If You Want to:
Instruction: Page:
Multiply two values MUL 4-22
Take the opposite sign of a value NEG 4-23
Take the sine of a number SIN* 4-24
Take the square root of a value SQR 4-25
Sort a set of values into ascending order SRT* 4-26
Calculate the standard deviation for a set of values STD* 4-28
Subtract two values SUB 4-31
Take the tangent of a number TAN* 4-32
Raise a number to a power XPY* 4-33
* Only Enhanced PLC-5 processors support this instruction.
$SSHQGL[&
Using Arithmetic Status Flags 7KHDULWKPHWLFVWDWXVIODJVDUHLQZRUGELWVLQWKHSURFHVVRU

VWDWXVILOH67DEOH%OLVWVWKHVWDWXVELWV
Table 4.B
Arithmetic Status Bits
S:0/0 Carry (C)
S:0/1 Overflow (V)
S:0/2 Zero (Z)
S:0/3 Sign (S)
1785-6.1 November 1998

Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY 4-3
Data Types and the <RXFDQFRPSXWHYDOXHVRIGLIIHUHQWGDWDW\SHVVXFKDVIORDWLQJSRLQW

Compute Instruction DQGLQWHJHU,I\RXXVHDIORDWLQJSRLQWDVWKHVRXUFHXVHD
IORDWLQJSRLQWDVWKHGHVWLQDWLRQRWKHUZLVHWKHGHVWLQDWLRQYDOXHZLOO
EHURXQGHG
<RXVKRXOGXVH%&'DQG$6&,,YDOXHVIRUGLVSOD\SXUSRVHV,I\RX
HQWHU%&'RU$6&,,YDOXHVWKHSURFHVVRUWUHDWVWKRVHYDOXHVDV
LQWHJHUV
RIWKHYDOXHV\RXZDQW
If You are Using this Processor: The Processor Rounds:
Classic PLC-5 the final value of a mathematical operation before

storing the final result. The processor rounds to
the nearest whole number: The processor rounds
values of 0.5-0.9 up to the next whole number; the
processor rounds values of 0.1- 0.4 down to the
closest whole number. If this value is greater than
32,767 or less than –32,768, the overflow status
bit is set.
Enhanced PLC-5 down if the value is < 0.5, up if the value is > 0.5,
and to the nearest even number if the value is =
0.5. If this value is greater than 32,767 or less
than –32,768, the processor “wraps” negative
(32,767, –32,768, –32,767, –32,766, etc.). For
example, if you have an ADD instruction with a
result greater than 32,767, the overflow bit is set,
the sign bit is set, and the result is negative:
32,767 + 5 = –32,764.
,PSRUWDQW ,I\RXDUHXVLQJDQ(QKDQFHG3/&SURFHVVRUDQGDQ
DULWKPHWLFRSHUDWLRQJHQHUDWHVDQRYHUIORZWKHXSSHU
ELWVDUHORVWEXWWKHORZHUELWVDUHFRUUHFW,I\RXWKHQ
SHUIRUPDORJLFDORSHUDWLRQRQWKHORZHUZRUG$1'RU
25\RXFDQJHWWKHSURSHUUHVXOW$OVRXVLQJWKHFDUU\
ELW\RXFDQGRPXOWLZRUGDULWKPHWLFLHDGGWZR
ELWZRUGV
1785-6.1 November 1998

)RUH[DPSOHLI YDOXH 1DQG1

YDOXH 1DQG1
UHVXOW 1DQG1
DQG\RXZDQWWRDGGYDOXHWRYDOXH\RXUODGGHUSURJUDPZRXOGEH
I:012 ADD
]
] ADD
10 Add the lower words of value1 and value2. Source A N7:1
Source B N7:3
Dest N7:5
I:012 ADD
AND
]
] BITWISE AND
10 Capture the carry bit. S:0
Source A
Source B 1
Dest N7:4
I:012 ADD
]
] ADD
10 Add the high word of value1 to the carry bit.
Source A N7:0
Source B N7:4
Dest N7:4
I:012 ADD
]
]
ADD
10 Add the high word of value2 to this sum. Source A N7:2
Source B N7:4
Dest N7:4
Using Floating Point Data Types )RUDQ(QKDQFHG3/&SURFHVVRULI\RXXVHIORDWLQJSRLQWGDWD

W\SHVDQGWKHUHVXOWLVWRRODUJHRULILWLVXQGHILQHGLHQDWXUDOORJRI
WKHSURFHVVRUVHWVWKHRYHUIORZELW
,IWKHUHVXOWLWWRRODUJHD!+INF!LVGLVSOD\HGLIWKHUHVXOWWRWRR
VPDOOD!-INF!LVGLVSOD\HG,IWKHYDOXHLVQRWDQXPEHU!NAN!
LV GLVSOD\HG
,PSRUWDQW ,I\RXDUHXVLQJIORDWLQJSRLQWDQGWKHQXPEHULVJUHDWHU
WKDQRUOHVVWKDQ±\RXPXVWXVHD
GHFLPDOSRLQW,I\RXGRQRWXVHDGHFLPDOSRLQWWKH
HUURUINVALID OPERAND DSSHDUV
:KHQ\RXXVHFRPSOH[H[SUHVVLRQVLIDQ\RSHUDQGLVIORDWLQJ
SRLQWWKHHQWLUHH[SUHVVLRQLVHYDOXDWHGDVIORDWLQJSRLQW6HHWKH
H[DPSOHLQWKH³([SUHVVLRQ([DPSOHV´VHFWLRQRQSDJHIRU
PRUHLQIRUPDWLRQ
1785-6.1 November 1998

Compute (CPT) 7KH&37LQVWUXFWLRQSHUIRUPVFRS\DULWKPHWLFORJLFDODQG

FRQYHUVLRQRSHUDWLRQV
Description: 7KH&37LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWSHUIRUPVWKH
CPT
RSHUDWLRQV\RXGHILQHLQWKHH[SUHVVLRQDQGZULWHVWKHUHVXOWLQWRWKH
COMPUTE
GHVWLQDWLRQDGGUHVV7KH&37LQVWUXFWLRQFDQDOVRFRS\GDWDIURPRQH
Destination
DGGUHVVWRDQRWKHUDQGDXWRPDWLFDOO\FRQYHUWVWKHGDWDW\SHDWWKH
VRXUFHDGGUHVVWRWKHGDWDW\SH\RXVSHFLI\LQWKHGHVWLQDWLRQDGGUHVV
Expression
7KHH[HFXWLRQWLPHRID&37LQVWUXFWLRQLVORQJHUWKDQWKHH[HFXWLRQ
WLPHRIDQDULWKPHWLFORJLFRUPRYHLQVWUXFWLRQLH$''$1'
029HWF7KH&37LQVWUXFWLRQDOVRXVHVPRUHZRUGVLQ\RXU
SURJUDPILOH
$IWHUHDFK&37LQVWUXFWLRQLVSHUIRUPHGWKHDULWKPHWLFVWDWXVELWVLQ
WKHVWDWXVILOHRIWKHGDWDWDEOHDUHXSGDWHGWKHVDPHDVWKH
FRUUHVSRQGLQJDULWKPHWLFORJLFRUPRYHLQVWUXFWLRQ)RUH[DPSOH
UHIHUWRWKHGHVFULSWLRQRIWKH$''LQVWUXFWLRQWRVHHKRZWKHVWDWXV
ELWVDUHXSGDWHGDIWHUD&37DGGLQVWUXFWLRQLVH[HFXWHG
Entering the CPT Expression

7KHH[SUHVVLRQGHILQHVWKHRSHUDWLRQV\RXZDQWWRSHUIRUP<RX
GHILQHWKHH[SUHVVLRQZLWKRSHUDWRUVDQGDGGUHVVHVRUSURJUDP
FRQVWDQWV:LWK(QKDQFHG3/&SURFHVVRUV\RXFDQHQWHUFRPSOH[
H[SUHVVLRQV7DEOH&OLVWVYDOLGRSHUDWLRQVIRUDQH[SUHVVLRQWKH
IROORZLQJOLVWSURYLGHVJXLGHOLQHVIRUZULWLQJH[SUHVVLRQV
2SHUDWRUVV\PEROVGHILQHWKHRSHUDWLRQV
$GGUHVVHVFDQEHGLUHFWRULQGLUHFWORJLFDODGGUHVVHVPXVWEH
HOHPHQWRUELWOHYHO
:LWK(QKDQFHG3/&SURFHVVRUVSURJUDPFRQVWDQWVFDQEH
LQWHJHURUIORDWLQJSRLQWQXPEHUVLI\RXHQWHURFWDOYDOXHVXVHD
OHDGLQJ 2LI\RXHQWHUKH[DGHFLPDOYDOXHVXVHDOHDGLQJ +
([SUHVVLRQVFDQRQO\WRWDOFKDUDFWHUVLQFOXGLQJVSDFHVDQG
SDUHQWKHVHV
1785-6.1 November 1998

Table 4.C
Valid Operations for Use in a CPT Expression
Copy none copy from A to B enter source address in the expression enter
destination address in destination
Clear none set a value to zero 0 (enter 0 for the expression)
Arithmetic + add 2+3

2+3+7 (Enhanced PLC-5 processors)
(12 – 5) – 7 (Enhanced PLC-5 processors)
* multiply 5*2
6 * (5 * 2) (Enhanced PLC-5 processors)
| (vertical bar) divide 24 | 6

(24 | 6) *2 (Enhanced PLC-5 processors)
– negate – N7:0
** exponential * 10**3
(x to the power of y)
LN natural log * LN F8:20
LOG log to the base 10* LOG F8:3
Trigonometric ACS arc cosine* ACS F8:18
ASN arc sine* ASN F8:20
ATN arc tangent * ATN F8:22
COS cosine* COS F8:14
SIN sine* SIN F8:12
TAN tangent* TAN F8:16
Bitwise AND bitwise AND D9:3 AND D10:4
OR bitwise OR D10:4 OR D10:5
XOR bitwise exclusive OR D9:5 XOR D10:4
NOT bitwise complement NOT D9:3
Conversion FRD convert from BCD FRD N7:0

to binary

to BCD
DEG convert radians DEG F8:8

to degrees*
RAD convert degrees RAD F8:10

to radians*
* Available in Enhanced PLC-5 processors only.
1785-6.1 November 1998

Determining the Length of an Expression

:LWK(QKDQFHG3/&SURFHVVRUV\RXFDQHQWHUFRPSOH[LQVWUXFWLRQV
XSWRDWRWDORIFKDUDFWHUVLQFOXGLQJVSDFHVDQGSDUHQWKHVHV
'HSHQGLQJRQWKHRSHUDWRUWKHSURFHVVRULQVHUWVFKDUDFWHUV
EHIRUHDIWHUWKHRSHUDWRULQ\RXUH[SUHVVLRQWRIRUPDWWKHH[SUHVVLRQ
IRUHDVLHULQWHUSUHWDWLRQ8VH7DEOH'EHORZWRGHWHUPLQHWKH
QXPEHURIFKDUDFWHUVHDFKRSHUDWRUXVHVLQDQH[SUHVVLRQ
:LWKWKH&37LQVWUXFWLRQDPD[LPXPRIFKDUDFWHUVRIWKH
H[SUHVVLRQDUHGLVSOD\DEOH,IWKHH[SUHVVLRQ\RXHQWHULVQHDUWKLV
UXQVSURSHUO\
7RZRUNDURXQGWKLVGLVSOD\SUREOHPH[SRUWWKHSURFHVVRUPHPRU\
ILOHDQGPDNH\RXUHGLWVLQWKH3&WH[WILOH7KHQLPSRUWWKLV
WH[W ILOH
,PSRUWDQW <RXFDQQRWHQWHUIORDWLQJSRLQWQXPEHUVLQVFLHQWLILF
QRWDWLRQZLWKQHJDWLYHH[SRQHQWVLQFRPSOH[
H[SUHVVLRQV,QVWHDGXVHWKHGHFLPDOHTXLYDOHQWRUSXW
WKHQXPEHULQDIORDWLQJSRLQWILOHDQGXVHWKHGDWD
DGGUHVVLQWKHFRPSOH[H[SUHVVLRQ
Table 4.D
Character Lengths for Operators
Uses this
This Operation: Using this Operator: Number of
Characters:
math binary +, –, *, | 3
OR, ** 4
AND, XOR 5
math unary – (negate) 2
LN * 3
FRD, TOD, DEG*, RAD*, SQR, NOT, LOG*, SIN*, 4

COS*, TAN*, ASN*, ACS*, ATN*
comparative =, <, > 3
<>, <=, >= 4
1785-6.1 November 1998

Determining the Order of Operation

7KHRSHUDWLRQV\RXZULWHLQWRWKHH[SUHVVLRQDUHSHUIRUPHGE\WKH
SURFHVVRULQDSUHVFULEHGRUGHUQRWQHFHVVDULO\WKHRUGHU\RXZULWH
WKHP<RXFDQRYHUULGHWKHRUGHURIRSHUDWLRQE\JURXSLQJWHUPV
ZLWKLQSDUHQWKHVHVIRUFLQJWKHSURFHVVRUWRSHUIRUPWKHRSHUDWLRQ
ZLWKLQWKHSDUHQWKHVHVDKHDGRIRWKHURSHUDWLRQV
2SHUDWLRQVRIHTXDORUGHUDUHSHUIRUPHGOHIWWRULJKW7KHH[SUHVVLRQ
\RXXVHPXVWLQFOXGHDQRSHUDWRU7DEOH(VKRZVWKHRUGHURI
RSHUDWLRQ
Table 4.E
Order of Operation for CPT Expressions
Order Operation Description
1 ** exponential (XY)
Enhanced PLC-5 processors only
2 – negate
NOT bitwise complement
3 * multiply
| divide
4 + add
– subtract
5 AND bitwise AND
6 XOR bitwise exclusive OR
7 OR bitwise OR
Expression Examples
6LQJOH9DOXH7KHH[SUHVVLRQ6451ZLWKGHVWLQDWLRQ1
WHOOVWKHSURFHVVRUWRWDNHWKHVTXDUHURRWRIWKHYDOXHVWRUHGDW1
DQGVWRUHWKHUHVXOWDW1
0XOWLSOH9DOXHV:LWK(QKDQFHG3/&SURFHVVRUV\RXFDQDOVRXVH
IXQFWLRQVWRRSHUDWHRQRQHRUPRUHYDOXHVLQWKHH[SUHVVLRQ
FRPSOH[H[SUHVVLRQVIRUFRPSXWHDQGFRPSDUHRSHUDWLRQV
&RPSOH[H[SUHVVLRQVFDQEHXSWRFKDUDFWHUVORQJVSDFHVDQG
SDUHQWKHVHVDUHFRQVLGHUHGFKDUDFWHUV)RUH[DPSOH\RXFRXOGHQWHU
DQH[SUHVVLRQVXFKDV
1785-6.1 November 1998

Example:
I:012 CPT
]
] COMPUTE
10
Destination N7:20
Expression
(N7:1 * 5) | (N7:2 | 7)
If the input word 12, bit 10 is set, multiply the value of N7:1 by 5. Divide this result by the quotient of N7:2 divided by 7.
If N7:1=5 and N7:2=9, the result is 25. (The result is rounded to the nearest whole number because the constants 5 and 7
were specified as whole numbers.)
:KHQ\RXXVHFRPSOH[H[SUHVVLRQVLIDQ\RSHUDQGLVIORDWLQJSRLQW
WKHHQWLUHH[SUHVVLRQLVHYDOXDWHGDVIORDWLQJSRLQW
Example:
I:012 CPT
]
] COMPUTE
10 Destination N7:20
Expression
(N7:1 * 5.0) | (N7:2 | 7.0)
If the input word 12, bit 10 is set, multiply the value of N7:1 by 5. Divide this result by the quotient of N7:2 divided by 7. If N7:1=5 and
N7:2=9, the result is 19. (The result is rounded differently because the constants 5.0 and 7.0 were specified to 1 decimal place.
Entering the Destination

(QWHUDGLUHFWRULQGLUHFWORJLFDODGGUHVVIRUWKHGHVWLQDWLRQ7KH
LQVWUXFWLRQVWRUHVWKHUHVXOWRIWKHRSHUDWLRQLQWKHGHVWLQDWLRQDGGUHVV
,PSRUWDQW 7KHSURFHVVRUDXWRPDWLFDOO\FRQYHUWVWKHGDWDW\SH
VSHFLILHGE\WKHVRXUFHDGGUHVVWRWKDWVSHFLILHGE\WKH
GHVWLQDWLRQDGGUHVV7KHSURFHVVRUXVHV%&'IRUGLVSOD\
RUFRPSDWLELOLW\ZLWK3/&IDPLO\SURFHVVRUV<RX
PXVWSURJUDPDQ\%&'FRQYHUVLRQV
Using CPT Functions

8VHIXQFWLRQVWRRSHUDWHRQRQHRUPRUHYDOXHVLQWKHH[SUHVVLRQRID
&37LQVWUXFWLRQWRSHUIRUPWKHVHW\SHVRIRSHUDWLRQV
FRQYHUWIURPRQHQXPEHUIRUPDWWRDQRWKHU
PDQLSXODWHQXPEHUV
SHUIRUPWULJRQRPHWULFIXQFWLRQV
1785-6.1 November 1998

7KHLQVWUXFWLRQSHUIRUPVWKHIXQFWLRQV\RXVSHFLI\EDVHGRQD
PQHPRQLF:KHQ\RXHQWHUWKHH[SUHVVLRQHQWHUWKHPQHPRQLFDV
WKHSUHIL[WRWKHDGGUHVVRIWKHYDOXHRQZKLFK\RXZDQWWRRSHUDWHRU
DVDSUHIL[WRWKHYDOXHLWVHOIZKHQHQWHUHGDVDSURJUDPFRQVWDQW
,PSRUWDQW )ORDWLQJSRLQWQXPEHUVDUHELWYDOXHV,QWHJHUVDUH
ELWYDOXHV7KHLQVWUXFWLRQDXWRPDWLFDOO\FRQYHUWVWKH
GDWDW\SHVIRXQGLQWKHH[SUHVVLRQWRWKHGDWDW\SH
VSHFLILHGE\WKHGHVWLQDWLRQDGGUHVV
$77(17,21 ,IWKHH[SUHVVLRQRUGHVWLQDWLRQ
DGGUHVVHVUHTXLUHFRQYHUVLRQIURPELWWRELWGDWD
DQGWKHYDOXHLVWRRODUJHWKHSURFHVVRUVHWVDQRYHUIORZ
ELWLQ6DQGVHWVDPLQRUIDXOW67KHUHVXOWLQJ
HUURQHRXVYDOXHFRXOGOHDGWRDGDQJHURXVVLWXDWLRQ
0RQLWRUWKLVELWLQ\RXUODGGHUSURJUDP
7DEOH)OLVWVWKH&37IXQFWLRQV\RXFDQXVH
Table 4.F
CPT Functions for Number Conversion
Mnemonic Title Description
RAD * radians Converts from degrees to radians
DEG * degrees Converts from radians to degrees
TOD to BCD Converts from integer to BCD (supports 4-digit BCD

numbers)
FRD from BCD Converts from BCD to integer (supports 4-digit BCD
numbers)
SQR square root Takes the square root of the number; accurate to 6
significant digits
LOG * – Log to the base 10; accurate to 6 significant digits
LN * – Natural log; accurate to 6 significant digits
SIN * sine; manipulated in radians, accurate to 6 significant digits
COS * cosine; manipulated in radians, accurate to 6 significant digits
TAN * tangent; manipulated in radians, accurate to 6 significant digits
ASN * inverse sine; manipulated in radians, accurate to 6 significant digits
ACS * inverse cosine; manipulated in radians, accurate to 6 significant digits
ATN * inverse tangent; manipulated in radians, accurate to 6 significant digits
<RXFDQXVHWKHDERYH&37DULWKPHWLFIXQFWLRQVZLWKLQH[SUHVVLRQV
RUDVVWDQGDORQHLQVWUXFWLRQVVHHWKHLQGLYLGXDOLQVWUXFWLRQV
GHVFULEHGLQWKLVFKDSWHU
1785-6.1 November 1998

Arc Cosine (ACS)

(Enhanced PLC-5 Processors Only)
Description: 8VHWKH$&6LQVWUXFWLRQWRWDNHWKHDUFFRVLQHRIWKHVRXUFHLQ

UDGLDQVDQGVWRUHWKHUHVXOWLQUDGLDQVLQWKH'HVWLQDWLRQ6HH7DEOH
ACS
*IRUVWDWXVIODJVIRUWKH$&6LQVWUXFWLRQ
ARCCOSINE
Source 7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQRU
Destination HTXDOWR,ILWLVQRWLQWKLVUDQJHWKHSURFHVVRUUHWXUQVD!NAN!
UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLV
DOZD\VJUHDWHUWKDQRUHTXDOWRDQGOHVVWKDQRUHTXDOWRπ
ZKHUHπ
Table 4.G
Updating Arithmetic Status Flags for an ACS Instruction
With this Bit: The Processor:
Carry (C) always resets
Overflow (V) sets if overflow generated; otherwise resets
Zero (Z) sets if result is zero; otherwise resets
Sign (S) always resets
Example:
I:012 ACS
]
] ARCCOSINE
Source F8:19
10 0.7853982
Destination F8:20
0.6674572
If input word 12, bit 10 is set, take the arc cosine of the value in F8:19 and store the result in F8:20.
1785-6.1 November 1998

Addition (ADD)
Description: 8VHWKH$''LQVWUXFWLRQWRDGGRQHYDOXH6RXUFH$WRDQRWKHU

YDOXH6RXUFH%DQGSODFHWKHUHVXOWLQWKHGHVWLQDWLRQ6RXUFH$DQG
ADD
6RXUFH%FDQHLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV6HH
ADD
7DEOH+IRUVWDWXVIODJVIRUWKH$''LQVWUXFWLRQ
Source A
Source B ,PSRUWDQW 7KH$''LQVWUXFWLRQH[HFXWHVRQFHHDFKVFDQDVORQJDV

Destination
WKHUXQJLVWUXHLI\RXRQO\ZDQWYDOXHVDGGHGRQFH
LQFOXGHWKH216FRPPDQGVHHFKDSWHU
Table 4.H
Updating Arithmetic Status Flags for an ADD Instruction
Carry (C) sets if carry generated; otherwise resets
Sign (S) sets if result is negative; otherwise resets
Example:
I:012 ADD
]
] ADD
10 Source A N7:3
Source B N7:4
Destination N7:20
If input word 12, bit 10 is set, add the value in N7:3 to the value in N7:4 and store the result in N7:20.
1785-6.1 November 1998

Arc Sine (ASN)

Description: 8VHWKH$61LQVWUXFWLRQWRWDNHWKHDUFVLQHWKHVRXUFHLQUDGLDQV

ASN
DQGVWRUHWKHUHVXOWLQUDGLDQVLQWKH'HVWLQDWLRQ6HH7DEOH,IRU
ARCSINE VWDWXVIODJVIRU$61LQVWUXFWLRQ
Source
Destination
7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQRU
HTXDOWR,ILWLVQRWLQWKLVUDQJHWKHSURFHVVRUUHWXUQVD!NAN!
UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLV
DOZD\VJUHDWHUWKDQRUHTXDOWR±πDQGOHVVWKDQRUHTXDOWRπ/2
ZKHUHπ
Table 4.I
Updating Arithmetic Status Flags for an ASN Instruction
Example:
I:012 ASN
]
]
ARCSINE
10 Source F8:17
0.7853982
Dest F8:18
0.9033391
If input word 12, bit 10 is set, take the arc sine of the value in F8:17 and store the result in F8:18.
1785-6.1 November 1998

Arc Tangent (ATN)

Description: 8VHWKH$71LQVWUXFWLRQWRWDNHWKHDUFWDQJHQWRIWKHVRXUFHLQ

UDGLDQVDQGVWRUHWKHUHVXOWLQUDGLDQVLQWKH'HVWLQDWLRQ7KH
ATN
UHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLVDOZD\VJUHDWHUWKDQRU
ARCTANGENT
HTXDOWR±πDQGOHVVWKDQRUHTXDOWRπ/2ZKHUHπ
Source
6HH7DEOH-IRUVWDWXVIODJVIRU$71LQVWUXFWLRQ
Destination
Table 4.J
Updating Arithmetic Status Flags for an ATN Instruction
Example:
I:012 ATN
ARCTANGENT
]
]
10 Source F8:21
0.7853982
Destination F8:22
0.6657737
If input word 12, bit 10 is set, take the arc tangent of the value in F8:21 and store the result in F8:22.
1785-6.1 November 1998

Average File (AVE)

Description: 7KH$9(LQVWUXFWLRQFDOFXODWHVWKHDYHUDJHRIDVHWRIYDOXHV:KHQ
AVE
WKHUXQJJRHVIURPIDOVHWRWUXHWKHYDOXHDWWKHFXUUHQWSRVLWLRQLV
AVERAGE FILE EN DGGHGWRWKHQH[WYDOXHZKLFKLVDGGHGWRWKHQH[WYDOXHDQGVRRQ
File
Destination 6HH7DEOH.IRUVWDWXVIODJVIRU$9(LQVWUXFWLRQ
Control DN
Length
Position (DFKWLPHDQRWKHUYDOXHLVDGGHGWKHSRVLWLRQILHOGDQGWKHVWDWXV
ZRUG6LVLQFUHPHQWHG7KHILQDOVXPLVGLYLGHGE\WKHQXPEHU
RIYDOXHVDGGHGDQGWKHUHVXOWLVVWRUHGLQWKHGHVWLQDWLRQ
Table 4.K
Updating Arithmetic Status Flags for an AVE Instruction
$QRYHUIORZFDQRFFXULI
WKHLQWHUPHGLDWHVXPH[FHHGVWKHPD[LPXPIORDWLQJSRLQWYDOXH
WKHGHVWLQDWLRQLVDQLQWHJHUDGGUHVVDQGWKHILQDOYDOXHLVJUHDWHU
WKDQRUOHVVWKDQ±
,IDQRYHUIORZRFFXUVWKHSURFHVVRUVWRSVWKHFDOFXODWLRQVHWVWKH(5
ELWDQGWKH'HVWLQDWLRQUHPDLQVXQFKDQJHG7KHSRVLWLRQLGHQWLILHV
WKHHOHPHQWWKDWFDXVHGWKHRYHUIORZ:KHQ\RXFOHDUWKH(5ELWWKH
SRVLWLRQUHVHWVWRDQGWKHDYHUDJHLVUHFDOFXODWHG
,PSRUWDQW 8VHWKH5(6LQVWUXFWLRQWRFOHDUWKHVWDWXVIODJV
Entering Parameters
7RSURJUDPWKH$9(LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRU
ZLWKWKHIROORZLQJ
)LOHLVWKHDGGUHVVWKDWFRQWDLQVWKHILUVWYDOXHWREHDGGHG7KLV
DGGUHVVFDQEHIORDWLQJSRLQWRULQWHJHU
'HVWLQDWLRQLVWKHDGGUHVVZKHUHWKHUHVXOWRIWKHLQVWUXFWLRQLV
VWRUHG7KLVDGGUHVVFDQEHIORDWLQJSRLQWRULQWHJHU
&RQWUROLVWKHDGGUHVVRIWKHFRQWUROVWUXFWXUHLQWKHFRQWURODUHD
5RISURFHVVRUPHPRU\7KHSURFHVVRUVWRUHVLQIRUPDWLRQVXFK
DVWKHOHQJWKSRVLWLRQDQGVWDWXVDQGXVHVWKLVLQIRUPDWLRQWR
H[HFXWHWKHLQVWUXFWLRQ
/HQJWKLVWKHQXPEHURIZRUGVLQWKHILOH
3RVLWLRQSRLQWVWRWKHZRUGWKDWWKHLQVWUXFWLRQLVFXUUHQWO\XVLQJ
1785-6.1 November 1998

Using Status Bits

7RXVHWKH$9(LQVWUXFWLRQFRUUHFWO\H[DPLQHVWDWXVELWVLQWKH
FRQWUROVWUXFWXUH$GGUHVVWKHVHELWVE\PQHPRQLF
This Bit: Is Set:
Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instruction
is enabled. The instruction follows the rung condition.
Done .DN (bit 13) after the instruction finishes operating. After the rung goes
false, the processor resets the .DN bit on the next false-to-true
rung transition.
Error .ER (bit 11) when the operation generates an overflow. The instruction
stops until the ladder program resets the .ER bit.
,PSRUWDQW 7KH$9(LQVWUXFWLRQFDOFXODWHVWKHDYHUDJHXVLQJ
IORDWLQJSRLQWUHJDUGOHVVRIWKHW\SHVSHFLILHGIRUWKHILOH
RUGHVWLQDWLRQSDUDPHWHUV
$77(17,21 7KH$9(LQVWUXFWLRQLQFUHPHQWVWKH
RIIVHWYDOXHVWRUHGDW60DNHVXUH\RXPRQLWRURU
ORDGWKHRIIVHWYDOXH\RXZDQWSULRUWRXVLQJDQLQGH[HG
DGGUHVV2WKHUZLVHXQSUHGLFWDEOHPDFKLQHRSHUDWLRQ
FRXOGRFFXUZLWKSRVVLEOHGDPDJHWRHTXLSPHQWDQGRU
LQMXU\WRSHUVRQQHO
Example:
I:012 AVE
]
] AVERAGE FILE EN
10 File #N7:1
Dest N7:0 DN
Control R6:0
Length 4
Position 0
R6:0 O:010
]
]
EN 5
R6:0 O:010
]
]
DN 7
R6:0
RES
If input word 12, bit 10 is set, the AVE instruction is enabled. The values in N7:1, N7:2, N7:3, and N7:4 are
added together and divided by 4. The result is stored in N7:0. When the calculation is complete, output
word 10, bit 7 is set. Then the RES instruction resets the status bits of the control file R6:0.
1785-6.1 November 1998

Clear (CLR)
Description: 8VHWKH&/5LQVWUXFWLRQWRVHWDOOWKHELWVRIDZRUGWR]HUR7KH
CLR
GHVWLQDWLRQPXVWEHDZRUGDGGUHVV6HH7DEOH/IRUVWDWXVIODJVIRU
CLEAR &/5LQVWUXFWLRQ
Destination Table 4.L
Updating Arithmetic Status Flags for a CLR Instruction
Overflow (V) always resets
Zero (Z) always sets
Example:
I:012 CLR
]
]
CLEAR
10 Destination N7:3
If input word 12, bit 10 is set, clear all of the bits in N7:3 to zero.
1785-6.1 November 1998

Cosine (COS)
Description: 8VHWKH&26LQVWUXFWLRQWRWDNHWKHFRVLQHRIDQXPEHU6RXUFHLQ

UDGLDQVDQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6HH7DEOH0IRU
COS
VWDWXVIODJVIRU&26LQVWUXFWLRQ
COSINE
Source 7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQ
Destination RUHTXDOWR,ILWLVQRWLQWKLVUDQJHWKHSURFHVVRUUHWXUQVD
!INF!UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJYDOXHLQWKH
'HVWLQDWLRQLVDOZD\VJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQRU
HTXDOWR
,PSRUWDQW )RUJUHDWHVWDFFXUDF\WKHVRXUFHGDWDVKRXOGEHJUHDWHU
WKDQRUHTXDOWR±πDQGOHVVWKDQRUHTXDOWRπ
Table 4.M
Updating Arithmetic Status Flags for an COS Instruction
Example:
I:012 COS
]
] COSINE
10 Source F8:13
0.7853982
Destination F8:14
0.7071068
If input word 12, bit 10 is set, take the cosine of the value in F8:13 and store the result in F8:14.
1785-6.1 November 1998

Divide (DIV)
Description: 8VHWKH',9LQVWUXFWLRQWRGLYLGHRQHYDOXH6RXUFH$E\DQRWKHU

YDOXH6RXUFH%DQGSODFHWKHUHVXOWLQWKH'HVWLQDWLRQ6RXUFH$DQG
DIV
DIVIDE
6RXUFH%FDQHLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV6HH
Source A 7DEOH1IRUVWDWXVIODJVIRU',9LQVWUXFWLRQ
Source B
,PSRUWDQW 7KHFRPSXWHLQVWUXFWLRQVH[HFXWHIRUHDFKVFDQDVORQJ
Destination
DVWKHUXQJLVWUXHLI\RXRQO\ZDQWYDOXHVFRPSXWHG
RQFHLQFOXGHWKH216FRPPDQGVHHFKDSWHU
Table 4.N
Updating Arithmetic Status Flags for a DIV Instruction
Overflow (V) sets if division by zero or if overflow generated;

otherwise resets
Zero (Z) sets if result is zero; otherwise resets;

undefined if overflow is set
Sign (S) sets if result is negative; otherwise resets;

undefined if overflow is set
Example:
I:012 DIV
]
] DIVIDE
10 Source A N7:3
Source B N7:4
Destination N7:20
If input word 12, bit 10 is set, divide the value in N7:3 by the value in N7:4 and store the result in N7:20.
1785-6.1 November 1998

Natural Log (LN)

Description: 8VHWKH/1LQVWUXFWLRQWRWDNHWKHQDWXUDOORJRIWKHYDOXHLQWKH
LN 6RXUFHDQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6HH7DEOH2IRUVWDWXV
NATURAL LOG IODJVIRU/1LQVWUXFWLRQ
Source
,IWKH6RXUFHLVHTXDOWRWKHUHVXOWLQWKH'HVWLQDWLRQZLOOEH
Destination
!-INF!LIWKHYDOXHLQWKH6RXUFHLVOHVVWKDQWKHUHVXOWLQWKH
'HVWLQDWLRQZLOOEH!NAN!7KHUHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLV
DOZD\VJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQRUHTXDOWR

Table 4.O
Updating Arithmetic Status Flags for an LN Instruction
Example:
I:012 LN
]
] NATURAL LOG
10 Source N7:0
5
Destination F8:20
1.609438
If input word 12, bit 10 is set, take the natural log of the value in N7:0 and store the result in F8:20.
1785-6.1 November 1998

Log to the Base 10 (LOG)

Description: 8VHWKH/2*LQVWUXFWLRQWRWDNHWKHORJEDVHRIWKHYDOXHLQWKH
LOG
6RXUFHDQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6HH7DEOH3IRUVWDWXV
LOG BASE 10
IODJVIRU/2*LQVWUXFWLRQ
Source
,IWKH6RXUFHLVHTXDOWRWKHUHVXOWLQWKH'HVWLQDWLRQZLOOEH
Destination
!-INF!LIWKHYDOXHLQWKH6RXUFHLVOHVVWKDQWKHUHVXOWLQWKH
'HVWLQDWLRQZLOOEH!NAN!7KHUHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLV
DOZD\VJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQRUHTXDOWR

Table 4.P
Updating Arithmetic Status Flags for an LOG Instruction
Example:
I:012 LOG
]
] LOG BASE 10
10 Source N7:2
5
Destination F8:3
0.6989700
If input word 12, bit 10 is set, take the log base 10 of the value in N7:2 and store the result in F8:3.
1785-6.1 November 1998

Multiply (MUL)
Description: 8VHWKH08/LQVWUXFWLRQWRPXOWLSO\RQHYDOXH6RXUFH$E\DQRWKHU

YDOXH6RXUFH%DQGSODFHWKHUHVXOWLQWKHGHVWLQDWLRQ6RXUFH$DQG
MUL
6RXUFH%FDQEHYDOXHVRUDGGUHVVHV6HH7DEOH4IRUVWDWXVIODJVIRU
MULTIPLY
08/LQVWUXFWLRQ
Source A
Source B Table 4.Q

Updating Arithmetic Status Flags for a MUL Instruction
Destination
Example:
I:012 MUL
]
] MULTIPLY
10 Source A N7:3
Source B N7:4
Destination N7:20
If input word 12, bit 10 is set, multiply the value in N7:3 by the value in N7:4 and store the result in N7:20.
1785-6.1 November 1998

Negate (NEG)
Description: 8VHWKH1(*LQVWUXFWLRQWRFKDQJHWKHVLJQRIDYDOXH,I\RXQHJDWHD
QHJDWLYHYDOXHWKHUHVXOWLVSRVLWLYHLI\RXQHJDWHDSRVLWLYHYDOXH
NEG
WKHUHVXOWLVQHJDWLYH6HH7DEOH5IRUVWDWXVIODJVIRU1(*
NEGATE
LQVWUXFWLRQ
Source
Destination ,PSRUWDQW 7KHFRPSXWHLQVWUXFWLRQVH[HFXWHIRUHDFKVFDQDVORQJ
DVWKHUXQJLVWUXHLI\RXRQO\ZDQWYDOXHVFRPSXWHG
RQFHLQFOXGHWKH216FRPPDQGVHHFKDSWHU
Table 4.R
Updating Arithmetic Status Flags for a NEG Instruction
Carry (C) sets if the operation generates a carry
Example:
I:012 NEG
]
] NEGATE
10 Source N7:3
Destination N7:20
If input word 12, bit 10 is set, take the opposite sign of the value in N7:3 and store the result in N7:20.
1785-6.1 November 1998

Sine (SIN)
Description: 8VHWKH6,1LQVWUXFWLRQWRWDNHWKHVLQHRIDQXPEHU6RXUFHLQ

UDGLDQVDQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6HH7DEOH6IRU
SIN
SINE
VWDWXVIODJVIRU6,1LQVWUXFWLRQ
Source
7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQ
Destination
RUHTXDOWR,ILWLVQRWLQWKLVUDQJHWKHSURFHVVRUUHWXUQVD
!INF!UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJYDOXHLQWKH
'HVWLQDWLRQLVDOZD\VJUHDWHUWKDQRUHTXDOWR±DQGOHVVWKDQRU
HTXDOWR
WKDQRUHTXDOWR±πDQGOHVVWKDQRUHTXDOWR π
Table 4.S
Updating Arithmetic Status Flags for an SIN Instruction
Example:
I:012 SIN
]
] SINE
Source F8:11
10
0.7853982
Destination F8:12
0.7071068
If input word 12, bit 10 is set, take the sine of F8:11 and store the result in F8:12.
1785-6.1 November 1998

Square Root (SQR)
Description: 8VHWKH645LQVWUXFWLRQWRWDNHWKHVTXDUHURRWRIDYDOXHDQGVWRUH
WKHUHVXOWLQWKHGHVWLQDWLRQ7KHVRXUFHFDQEHDYDOXHRUDQDGGUHVV
SQR
SQUARE ROOT
,IWKHVRXUFHYDOXHLVQHJDWLYHWKHSURFHVVRUWDNHVLWVDEVROXWHYDOXH
Source
DQGSHUIRUPVWKHVTXDUHURRWIXQFWLRQ6HH7DEOH7IRUVWDWXVIODJV
Destination IRU645LQVWUXFWLRQ
,PSRUWDQW 7KH645LQVWUXFWLRQH[HFXWHVRQFHIRUHDFKVFDQDV
ORQJDVWKHUXQJLVWUXHLI\RXRQO\ZDQWYDOXHV
FRPSXWHGRQFHLQFOXGHWKH216FRPPDQGVHH
FKDSWHU
Table 4.T
Updating Arithmetic Status Flags for a SQR Instruction
Overflow (V) sets if overflow generated during floating-point

to integer conversion; otherwise resets
Example:
I:012 SQR
]
] SQUARE ROOT
10 Source N7:3
Destination N7:20
If input word 12, bit 10 is set, take the square root of the value in N7:3 and store the result in N7:20.
1785-6.1 November 1998

Sort File (SRT)

Description: 7KH657LQVWUXFWLRQVRUWVDVHWRIYDOXHVLQWRDVFHQGLQJRUGHU7KLV
LQVWUXFWLRQLVH[HFXWHGRQDIDOVHWRWUXHWUDQVLWLRQ
SRT
SORT FILE EN ,PSRUWDQW 0DNHVXUHWKHILOHOHQJWKYDOXH\RXVSHFLI\LQWKH
File
LQVWUXFWLRQGRHVQRWFDXVHWKHLQGH[HGDGGUHVVWRH[FHHG
Control DN
Length WKHILOHERXQGV7KHSURFHVVRUGRHVQRWFKHFNWKLV
Position
XQOHVV\RXH[FHHGWKHGDWDILOHDUHDRIPHPRU\
,IWKHLQGH[HGDGGUHVVH[FHHGVWKHGDWDILOHDUHDWKH
SURFHVVRULQLWLDWHVDUXQWLPHHUURUDQGVHWVDPDMRU
IDXOW7KHSURFHVVRUGRHVQRWFKHFNWRVHHZKHWKHUWKH
LQGH[HGDGGUHVVFURVVHVILOHW\SHVVXFKDV1WR)
Entering Parameters
7RSURJUDPWKH657LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJ
file the address that contains the first value to be sorted. This address can be
floating point or integer.
control the address of the control structure in the control area (R) of processor
memory. The processor stores information such as the length, position
and status, and uses this information to execute the instruction.
length the number of words in the file (1-1000).
position points to the element that the instruction is currently using.
1785-6.1 November 1998

Using Status Bits

7RXVHWKH657LQVWUXFWLRQFRUUHFWO\WKHODGGHUSURJUDPPXVW
H[DPLQHVWDWXVELWVLQWKHFRQWUROVWUXFWXUH<RXDGGUHVVWKHVHELWV
E\ PQHPRQLF
This Bit: Is Set:
Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instruction is
enabled. The instruction follows the rung condition.
Done .DN (bit 13) after the instruction finishes operating. After the rung goes false,
the processor resets the .DN bit on the next false-to-true rung
transition.
Error .ER (bit 11) when the length value is less than or equal to zero or when the
position value is less than zero.
$77(17,21 7KH657LQVWUXFWLRQPDQLSXODWHVWKH
LQMXU\WRSHUVRQQHO
Example:
I:012 SRT
]
] SORT FILE EN
10 File #N7:1
Control R6:0
Length 4 DN
Position 0
R6:0 O:010
]
]
EN 5
R6:0 O:010
]
]
DN 7
If input word 12, bit 10 is set, the SRT instruction is enabled. The elements N7:1, N7:2, N7:3, and N7:4 are sorted into ascending
order. When the sort operation is complete, output word 10, bit 7 is set.
1785-6.1 November 1998

Standard Deviation (STD)

Description: 7KH67'LQVWUXFWLRQFDOFXODWHVWKHVWDQGDUGGHYLDWLRQRIDVHWRI
STD
YDOXHVDQGVWRUHVWKHUHVXOWLQWKHGHVWLQDWLRQ7KLVLQVWUXFWLRQLV
STANDARD DEVIATION EN H[HFXWHGRQDIDOVHWRWUXHWUDQVLWLRQ6HH7DEOH8IRUVWDWXVIODJV
File IRU67'LQVWUXFWLRQ
Destination DN
Control
Length
7KHVWDQGDUGGHYLDWLRQLVFDOFXODWHGDFFRUGLQJWRWKHIROORZLQJ
Position IRUPXOD
Standard 2
Deviation =  SUM((xi – AVE(xi)) 

 (N – 1) 
:KHUH
680 ±VXPPDWLRQIXQFWLRQRIWKHHQFORVHGYDULDEOHV
$9( ±DYHUDJHIXQFWLRQRIWKHHQFORVHGYDULDEOHV
[L±YDULDEOHHOHPHQWVRIWKHGDWDILOH
1±QXPEHURIHOHPHQWVLQWKHGDWDILOH
,PSRUWDQW 0DNHVXUHWKHILOHOHQJWKYDOXH\RXVSHFLI\LQWKH
LQVWUXFWLRQGRHVQRWFDXVHWKHLQGH[HGDGGUHVVWRH[FHHG
WKHILOHERXQGV7KHSURFHVVRUGRHVQRWFKHFNWKLV
XQOHVV\RXXVHDQLQGH[HGLQGLUHFWDGGUHVVRUH[FHHGWKH
GDWDILOHDUHDRIPHPRU\,IWKHLQGH[HGDGGUHVVH[FHHGV
WKHGDWDILOHDUHDWKHSURFHVVRULQLWLDWHVDUXQWLPHHUURU
DQGVHWVDPDMRUIDXOW7KHSURFHVVRUGRHVQRWFKHFNWR
VHHZKHWKHUWKHLQGH[HGDGGUHVVFURVVHVILOHW\SHVVXFK
DV1WR)
Table 4.U
Updating Arithmetic Status Flags for an STD Instruction
1785-6.1 November 1998

7KHUHDUHWZRZD\VDQRYHUIORZFDQRFFXU
WKHLQWHUPHGLDWHVXPH[FHHGVWKHPD[LPXPIORDWLQJSRLQWYDOXH
IORDWLQJSRLQWYDOXHVDUH± WR±
H±
H
WKHGHVWLQDWLRQLVDQLQWHJHUDGGUHVVDQGWKHILQDOYDOXHLVJUHDWHU
WKDQ
,IDQRYHUIORZRFFXUVWKHSURFHVVRUVWRSVWKHFDOFXODWLRQVHWVWKH(5
ELWDQGOHDYHVWKHGHVWLQDWLRQXQFKDQJHG7KHSRVLWLRQLGHQWLILHVWKH
HOHPHQWWKDWFDXVHGWKHRYHUIORZ:KHQ\RXFOHDUWKH(5ELWWKH
SRVLWLRQUHVHWVWRDQGWKHVWDQGDUGGHYLDWLRQLVUHFDOFXODWHG
,PSRUWDQW 8VHWKH5(6LQVWUXFWLRQWRFOHDUWKHVWDWXVELWV
Entering Parameters
7RSURJUDPWKH67'LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJ
Parameter: Defines:
file the address that contains the first value to be calculated. This address
can be floating point or integer.
destination the address where the result of the instruction is stored. This address
can be floating point or integer.
control the address of the control structure in the control area (R) of processor
memory. The processor stores information such as the length, position
and status, and uses this information to execute the instruction.
length the number of words in the file (1-1000).
position points to the element that the instruction is currently using.
Using Status Bits

7RXVHWKH67'LQVWUXFWLRQFRUUHFWO\H[DPLQHVWDWXVELWVLQWKH
FRQWUROVWUXFWXUH<RXDGGUHVVWKHVHELWVE\PQHPRQLF
This Bit: Is Set:
Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instruction
is enabled. The instruction follows the rung condition.
Done .DN (bit 13) after the instruction finishes operating. After the rung goes
false, the processor resets the .DN bit on the next false-to-true
rung transition.
Error .ER (bit 11) when the operation generates an overflow. The instruction
stops until the ladder program resets the .ER bit.
1785-6.1 November 1998

,PSRUWDQW 7KH67'LQVWUXFWLRQFDOFXODWHVWKHVWDQGDUGGHYLDWLRQ
XVLQJIORDWLQJSRLQWUHJDUGOHVVRIWKHW\SHVSHFLILHGIRU
WKHILOHRUGHVWLQDWLRQSDUDPHWHUV
$77(17,21 7KH67'LQVWUXFWLRQPDQLSXODWHVWKH
LQMXU\WRSHUVRQQHO
Example:
I:012 STD
]
] STANDARD DEVIATION EN
10 File #N7:1
Destination N7:0
Control R6:0 DN
Length 4
Position 0
R6:0 O:010
]
]
EN 5
R6:0 O:010
]
]
DN 7
R6:0
RES
If input word 12, bit 10 is set, the STD instruction is enabled. The elements N7:1, N7:2, N7:3, and N7:4 are used to calculate the
standard deviation. When the calculation is complete, output word 10, bit 7 is set. Then the RES instruction resets the status bits of
the control file R6:0.
1785-6.1 November 1998

Subtract (SUB)
Description: 8VHWKH68%LQVWUXFWLRQWRVXEWUDFWRQHYDOXH6RXUFH%IURP

SUB
DQRWKHUYDOXH6RXUFH$DQGSODFHWKHUHVXOWLQWKHGHVWLQDWLRQ
SUBTRACT 6RXUFH$DQG6RXUFH%FDQEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQ
Source A YDOXHV6HH7DEOH9IRUVWDWXVIODJVIRU68%LQVWUXFWLRQ
Source B
Destination ,PSRUWDQW 7KH68%LQVWUXFWLRQH[HFXWHVRQFHIRUHDFKVFDQDV
ORQJDVWKHUXQJLVWUXHLI\RXRQO\ZDQWYDOXHV
VXEWUDFWHGRQFHLQFOXGHWKH216FRPPDQGVHH
FKDSWHU
Table 4.V
Updating Arithmetic Status Flags for a SUB Instruction
Carry (C) sets if borrow generated; otherwise resets
Overflow (V) sets if underflow generated; otherwise resets
Example:
I:012 SUB
]
] SUBTRACT
10 Source A N7:3
Source B N7:4
Destination N7:20
If input word 12, bit 10 is set, subtract the value in N7:4 from the value in N7:3 and store the result in N7:20.
1785-6.1 November 1998

Tangent (TAN)
Description: 8VHWKH7$1LQVWUXFWLRQWRWDNHWKHWDQJHQWRIDQXPEHU6RXUFHLQ

UDGLDQVDQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6HH7DEOH:IRU
TAN
TANGENT
VWDWXVIODJVIRU7$1LQVWUXFWLRQ
Source
7KHYDOXHLQWKH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWR±
Destination
DQGOHVVWKDQRUHTXDOWR,ILWLVQRWLQWKLVUDQJHWKH
SURFHVVRUUHWXUQVD!INF!UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJ
YDOXHLQWKH'HVWLQDWLRQLVDOZD\VDUHDOQXPEHU
WKDQRUHTXDOWR±πDQGOHVVWKDQRUHTXDOWRπ
Table 4.W
Updating Arithmetic Status Flags for an TAN Instruction
Example:
I:012 TAN
]
] TANGENT
10 Source F8:15
0.7853982
Destination F8:16
1.000000
If input word 12, bit 10 is set, take the tangent of the value in F8:15 and store the result in F8:16.
1785-6.1 November 1998

X to the Power of Y (XPY)

Description: 8VHWKH;3<LQVWUXFWLRQWRUDLVHDYDOXH6RXUFH$WRDSRZHU

XPY
6RXUFH%DQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ,IWKHYDOXHLQ
X TO POWER OF Y 6RXUFH$LVQHJDWLYHWKHH[SRQHQW6RXUFH%VKRXOGEHDQLQWHJHU
Source A YDOXHLIWKHH[SRQHQWLVQRWDQLQWHJHUIRUH[DPSOHLILWLVDIORDWLQJ
Source B SRLQWYDOXHWKHRYHUIORZELWLVVHWDQGWKHDEVROXWHYDOXHRIWKHEDVH
Destination
LVXVHGLQWKHFDOFXODWLRQ6HH7DEOH;IRUVWDWXVIODJVIRU;3<
LQVWUXFWLRQ
7KH;3<LQVWUXFWLRQXVHVWKHIROORZLQJDOJRULWKP
;3< < ORJ;
,IDQ\RIWKHLQWHUPHGLDWHRSHUDWLRQVLQWKLVDOJRULWKPSURGXFHDQ
RYHUIORZWKHDULWKPHWLFPLQRUIDXOWELWLVVHW67KH
DULWKPHWLFVWDWXVIODJELWLVVHWRQO\LIWKHILQDOUHVXOWLVDQRYHUIORZ
,PSRUWDQW .HHSLQPLQGWKDW[LVHTXDOWR[LVHTXDOWR)RU
IORDWLQJSRLQWQXPEHUVLVHTXDOWR!NAN! DQ
LQYDOLGPDWKHPDWLFDOYDOXHDQGIRULQWHJHUVLVHTXDO
WR±.
Table 4.X
Updating Arithmetic Status Flags for an XPY Instruction
Example:
I:012 XPY
]
] X TO POWER OF Y
10 Source A N7:4
5
Source B N7:5
2
Destination N7:6
25
If input word 12, bit 10 is set, take the value in N7:4, raise it to the power of the value in N7:5, and stores
the result in N7:6.
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 5
Logical Instructions AND, NOT, OR, XOR
Using Logical Instructions 7KHVHLQVWUXFWLRQV7DEOH$SHUIRUPORJLFDORSHUDWLRQV
Table 5.A
Available Logical Instructions
Perform an AND operation AND 5-2
Perform a NOT operation NOT 5-3
Perform an OR operation OR 5-4
Perform an XOR operation XOR 5-5
7KHSDUDPHWHUV\RXHQWHUDUHSURJUDPFRQVWDQWVRUGLUHFWORJLFDO
DGGUHVVHV
$SSHQGL[&
Using Arithmetic Status Flags

7KHDULWKPHWLFVWDWXVELWVDUHLQZRUGELWVLQWKHSURFHVVRUVWDWXV
ILOH67DEOH%OLVWVWKHVWDWXVIODJV
Table 5.B
Arithmetic Status Flags
S:0/0 Carry (C)
S:0/1 Overflow (V)
S:0/2 Zero (Z)
S:0/3 Sign (S)
1785-6.1 November 1998

5-2 Logical Instructions AND, NOT, OR, XOR
AND Operation (AND)
Description: 8VHWKH$1'LQVWUXFWLRQWRSHUIRUPDQ$1'RSHUDWLRQXVLQJWKHELWV
LQWKHWZRVRXUFHDGGUHVVHV
AND
BITWISE AND Table 5.C
Source A Truth Table for an AND Operation
Source B
Destination
Source A Source B Result
0 0 0
1 0 0
0 1 0
1 1 1
Table 5.D
Updating Arithmetic Status Flags for an AND Instruction
Sign (S) sets if most-significant bit is set;

otherwise resets
Example:
I:012 AND
[
[
AND
10 Source A N9:3
Source B N10:4
Destination N12:3
If input word 12, bit 10 is set, the processor performs an AND

operation on N9:3 and N10:4 and stores the result in N12:3.
Source A
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Source B
N10:4 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Destination
N12:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
1785-6.1 November 1998

Logical Instructions AND, NOT, OR, XOR 5-3
NOT Operation (NOT)
Description: 8VHWKH127LQVWUXFWLRQWRSHUIRUPD127RSHUDWLRQXVLQJWKHELWVLQ
WKHVRXUFHDGGUHVV7KLVRSHUDWLRQLVDOVRNQRZDVDELWLQYHUVLRQ
NOT
NOT ,PSRUWDQW 7KH127LQVWUXFWLRQLVQRWDYDLODEOHRQ3/&
Source VHULHV$SURFHVVRUV
Destination
Table 5.E
Truth Table for a NOT Operation
Source Result
0 1
1 0
Table 5.F
Updating Arithmetic Status Flags for a NOT Instruction

otherwise resets
Example:
I:012 NOT
[
[
NOT
10 Source N9:3
Destination N10:4
If input word 12, bit 10 is set, the processor performs a

NOT operation on N9:3 and stores the result in N10:4
Source
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Destination
N10:4
1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1
1785-6.1 November 1998

OR Operation (OR)
Description: 8VHWKH25LQVWUXFWLRQWRSHUIRUPDQ25RSHUDWLRQXVLQJWKHELWVLQ
OR
WKHWZRVRXUFHVFRQVWDQWVRUDGGUHVVHV
BITWISE INCLUSIVE OR Table 5.G
Source A Truth Table for an OR Operation
Source B
Destination
Source A Source B Result
0 0 0
1 0 1
0 1 1
1 1 1
Table 5.H
Updating Arithmetic Status Flags for an OR Instruction

otherwise resets
Example:
I:012 OR
[
[ INCLUSIVE OR
10 Source A N9:3
Source B N10:4
Destination N12:3
If input word 12, bit 10 is set, the processor performs
an OR operation on N9:3 and N10:4 and stores the
result in N12:3.
Source A
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Source B
N10:4 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Destination
N12:3
0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
1785-6.1 November 1998

Logical Instructions AND, NOT, OR, XOR 5-5
Exclusive OR Operation (XOR)
Description: 8VHWKH;25LQVWUXFWLRQWRSHUIRUPDQH[FOXVLYH25RSHUDWLRQXVLQJ
WKHELWVLQWKHWZRVRXUFHVFRQVWDQWVRUDGGUHVVHV
XOR
BITWISE EXCLUSIVE OR Table 5.I
Source A Truth Table for an XOR Operation
Source B
Destination Source A Source B Result
0 0 0
1 0 1
0 1 1
1 1 0
Table 5.J
Updating Arithmetic Status Bits for an XOR Instruction
Sign (S) sets if most-significant bit is set; otherwise resets
Example:
I:012 XOR
[ EXCLUSIVE OR
[
10 Source A N9:3
Source B N10:4
If input word 12, bit 10 is set, the processor performs Destination N12:3
an XOR operation on N9:3 and N10:4 and stores the
result in N12:3.
Source A
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Source B
N10:4 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Destination
N12:3
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 6
Conversion Instructions FRD and TOD,
DEG and RAD
Using the Conversion Instructions 7KHFRQYHUVLRQLQVWUXFWLRQVFRQYHUWLQWHJHUWR%&'DQGFRQYHUW%&'
WRLQWHJHUXVLQJ72'DQG)5')RUH[DPSOHXVH72'DQG)5'IRU
VLJQDOVWRIURP%&',2GHYLFHVIRUGLVSOD\SXUSRVHVRUIRUQXPEHU
FRPSDWLELOLW\ZLWK3/&IDPLO\SURFHVVRUV<RXFDQDOVRFRQYHUW
UDGLDQVWRGHJUHHVDQGGHJUHHVWRUDGLDQVXVLQJ'(*DQG5$')RU
H[DPSOH\RXFDQXVH'(*DQG5$'ZLWKWKHWULJRQRPHWULF
LQVWUXFWLRQVVHHFKDSWHU
7DEOH$OLVWVWKHDYDLODEOHFRQYHUVLRQLQVWUXFWLRQV
Table 6.A
Available Conversion Instructions
Convert from integer to BCD TOD 6-2
Convert from BCD to integer FRD 6-2
Convert radians to degrees DEG* 6-3
Convert degrees to radians RAD* 6-4
* These instructions are only supported by Enhanced PLC-5 processors.
RIWKHYDOXHV\RXZDQW
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Using Arithmetic Status Flags

7KHDULWKPHWLFVWDWXVIODJVDUHLQZRUGELWVLQWKHSURFHVVRU
VWDWXVILOH67DEOH%OLVWVWKHVWDWXVIODJV
Table 6.B
Arithmetic Status Flags
S:0/0 Carry (C)
S:0/1 Overflow (V)
S:0/2 Zero (Z)
S:0/3 Sign (S)
1785-6.1 November 1998

6-2 Conversion Instructions FRD and TOD, DEG and RAD
Convert to BCD (TOD)
Description: 8VHWKH72'LQVWUXFWLRQWRFRQYHUWDQLQWHJHUYDOXHWRD%&'YDOXH
,IWKHLQWHJHUYDOXHLVJUHDWHUWKDQWKHSURFHVVRUVWRUHVDQG
TOD
VHWVWKHRYHUIORZELW,IWKHLQWHJHUYDOXHLVQHJDWLYHWKHSURFHVVRU
TO BCD
VWRUHVLQWKHGHVWLQDWLRQDQGVHWVWKHRYHUIORZDQG]HURVWDWXVELWV
Source
Table 6.C
Destination
Updating Arithmetic Status Flags for a TOD Instruction
Overflow (V) sets if integer value is outside the range

0-9999; otherwise resets
Zero (Z) sets if destination value is negative or

zero; otherwise resets
Example:
I:012 TOD
]
] TO BCD
10 Source N7:3
Destination D9:3
If input word 12, bit 10 is set, convert the value in N7:3 to a BCD value and store the result in D9:3.
Convert from BCD (FRD)
Description: 8VHWKH)5'LQVWUXFWLRQWRFRQYHUWD%&'YDOXHWRDQLQWHJHUYDOXH
&RQYHUW%&'YDOXHVWRLQWHJHUYDOXHVEHIRUH\RXPDQLSXODWHWKRVH
FRD
YDOXHVZLWKODGGHUORJLFEHFDXVHWKHSURFHVVRUWUHDWV%&'YDOXHVDV
FROM BCD LQWHJHUYDOXHV7KHDFWXDO%&'YDOXHPD\EHORVWRUGLVWRUWHG
Source
Table 6.D
Destination
Updating Arithmetic Status Flags for a TOD Instruction
Zero (Z) sets if destination value is zero; otherwise resets
1785-6.1 November 1998

Conversion Instructions FRD and TOD, DEG and RAD 6-3
7KH)5'LQVWUXFWLRQZLOOFRQYHUWDQRQGHFLPDOQXPEHUZLWKRXWDQ\
HUURUFRQGLWLRQ)RUH[DPSOHLID³&´LVLQWKHVRXUFHLWLVFRQYHUWHG
WR³´HYHQWKRXJK³&´LVQRWDYDOLGGHFLPDOQXPEHU
Example:
I:012 FRD
]
] FROM BCD
10 Source D9:3
Destination N7:3
If input word 12, bit 10 is set, convert the value in D9:3 to an integer value and store the result in N7:3.
Degree (DEG)
Description: 8VHWKH'(*LQVWUXFWLRQWRFRQYHUWUDGLDQV6RXUFHWRGHJUHHVDQG

DEG
VWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6RXUFHWLPHVπ
RADIANS TO DEGREE Table 6.E
Source Updating Arithmetic Status Flags for an DEG Instruction
Destination
Example:
I:012 DEG
]
] RADIANS TO DEGREE
10 Source F8:7
0.7853982
Destination F8:8
45
If input word 12, bit 10 is set, convert the value in F8:7 to degrees and store the result on F8:8.
1785-6.1 November 1998

6-4 Conversion Instructions FRD and TOD, DEG and RAD
Radian (RAD)
Description: 8VHWKH5$'LQVWUXFWLRQWRFRQYHUWGHJUHHV6RXUFHWRUDGLDQVDQG

RAD
VWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6RXUFHWLPHVπ
DEGREES TO RADIANS Table 6.F
Source Updating Arithmetic Status Flags for an RAD Instruction
Destination
Example:
I:012 RAD
]
] DEGREES TO RADIANS
10 Source N7:9
45
Destination F8:10
0.7853982
If input word 12, bit 10 is set, convert the value in N7:9 to radians and store the result on F8:10.
1785-6.1 November 1998

Chapter 7
Bit Modify and Move Instructions
BTD, MOV, MVM
Using Bit Modify and Move 7KHELWPRGLI\DQGPRYHLQVWUXFWLRQVOHW\RXPRGLI\DQGPRYHELWV
Instructions 7DEOH$OLVWVWKHDYDLODEOHPRYHLQVWUXFWLRQV
Table 7.A
Available Bit Modify and Move Instructions
Move bits within a word or between words BTD 7-2
Copy the value in one word to another word MOV 7-3
Copy the desired part of a 16-bit value by MVM 7-4

masking the rest of the value with a mask
7KHVHLQVWUXFWLRQVRSHUDWHRQELWLQWHJHUELQDU\RUIORDWLQJSRLQW
QXPEHUVWRPRYHRUFRS\ELWVEHWZHHQZRUGV7KH090LQVWUXFWLRQ
XVHVDPDVNWRHLWKHUSDVVRUEORFNVRXUFHGDWDELWV$PDVNSDVVHV
GDWDZKHQWKHPDVNELWVDUHVHWDPDVNEORFNVGDWDZKHQWKH
PDVNELWVDUHUHVHW7KHPDVNPXVWEHWKHVDPHZRUGVL]HDVWKH
VRXUFHDQGGHVWLQDWLRQ
:KHQURXQGLQJIORDWLQJSRLQWQXPEHUVGXULQJDPRYHWRDQLQWHJHU
ZRUGWKHSURFHVVRUGRHVQRWFRUUHFWO\URXQGQXPEHUVOHVVWKDQ±
$SSHQGL[&
1785-6.1 November 1998

7-2 Bit Modify and Move Instructions BTD, MOV, MVM
Bit Distribute (BTD)
Description: 7KH%7'LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWPRYHVXSWRELWV
RIGDWDZLWKLQDZRUGRUEHWZHHQZRUGV7KH6RXUFHUHPDLQV
BTD
XQFKDQJHG7KHLQVWUXFWLRQZULWHVRYHUWKH'HVWLQDWLRQZLWKWKH
BIT FIELD DISTRIB
VSHFLILHGELWV,IWKHOHQJWKRIWKHELWILHOGH[WHQGVEH\RQGWKH
Source
Source bit
'HVWLQDWLRQZRUGWKHSURFHVVRUGRHVQRWVDYHWKHRYHUIORZELWV
Destination 7KHVHRYHUIORZELWVDUHORVWWKH\GRQRWZUDSLQWRWKHQH[WZRUG
Destination bit
Length 2QHDFKVFDQZKHQWKHUXQJWKDWFRQWDLQVWKH%7'LQVWUXFWLRQLVWUXH
WKHSURFHVVRUPRYHVWKHELWILHOGIURPWKHVRXUFHZRUGWRWKH
GHVWLQDWLRQZRUG7RPRYHGDWDZLWKLQDZRUGHQWHUWKHVDPHDGGUHVV
IRUWKHVRXUFHDQGGHVWLQDWLRQ
Entering Parameters
7RSURJUDPWKH%7'LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJ
Source the address of the source word in binary or integer. The source
remains unchanged.
Source bit the number of the bit (lowest bit number) in the source word from
which to start the move.
Destination the address of the destination word in a binary or integer file. The
instruction writes over any data already stored at the destination.
Destination bit the number of the bit (lowest bit number) in the destination word
where the processor starts copying the bits from the source word.
Length the number of bits to be moved.
Example:
Moving Bits Within a Word
BTD
Destination Bit Source Bit
BIT FIELD DISTRIB N70:22/10 N70:22/3
Source N70:22 15 08 07 00
Source bit 3
Destination N70:22 1 0 1 1 0 1 1 0 1 1 0 1 N70:22
Destination bit 10
Length 6
13384
1785-6.1 November 1998

Bit Modify and Move Instructions BTD, MOV, MVM 7-3
Example:
Moving Bits Between Words
BTD Source Bit
N7:020/3
BIT FIELD DISTRIB 15 08 07 00
Source N7:20 0 1 1 1 0 1 1 1 0 1 N7:20
Source bit 3
Destination N7:22
Destination bit 5 Destination Bit
Length 10 N7:022/5
15 08 07 00
0 1 1 1 0 1 1 1 0 1 N7:22
13384
,PSRUWDQW %LWVDUHORVWLIWKH\H[WHQGEH\RQGWKHHQGRIWKH
GHVWLQDWLRQZRUGWKHELWVDUHQRWZUDSSHGWRWKHQH[W
KLJKHUZRUG
Move (MOV)
Description: 7KH029LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWFRSLHVWKH6RXUFH
DGGUHVVWRD'HVWLQDWLRQ$VORQJDVWKHUXQJUHPDLQVWUXHWKH
MOV
LQVWUXFWLRQPRYHVWKHGDWDHDFKVFDQ
MOVE
Source 7DEOH%GHVFULEHVKRZWKHSURFHVVRUXSGDWHVWKHDULWKPHWLFVWDWXV
Destination IODJV
Table 7.B
Updating Arithmetic Status Flags for a MOV Instruction
Overflow (V) sets if overflow generated during floating

point-to-integer conversion; otherwise resets
Example: 7RSURJUDPWKLVLQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWKWKH
IROORZLQJ
MOV
MOVE
Source N7:0 Parameter: Definition:
Destination N7:2
source is a program constant or data address from which the instruction
reads an image of the value.
You can also use a symbol, as long as the symbol name is more
than 1 character. The source remains unchanged.
destination the data address to which the instruction writes the result of
the operation. The instruction writes over any data stored at
the destination.
1785-6.1 November 1998

Masked Move (MVM)
Description: 7KH090LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWFRSLHVWKH6RXUFH
WRD'HVWLQDWLRQDQGDOORZVSRUWLRQVRIWKHGDWDWREHPDVNHG$V
MVM
ORQJDVWKHUXQJUHPDLQVWUXHWKHLQVWUXFWLRQPRYHVGDWDHDFKVFDQ
MASKED MOVE
Source <RXFDQXVHWKH090LQVWUXFWLRQWRFRS\,2LPDJHELQDU\RU
Mask
LQWHJHUYDOXHV)RUH[DPSOHXVH090WRH[WUDFWELWGDWDVXFKDV
Destination
VWDWXVRUFRQWUROELWVIURPDQHOHPHQWWKDWFRQWDLQVELWDQGZRUGGDWD
7DEOH&GHVFULEHVKRZWKHSURFHVVRUXSGDWHVWKHDULWKPHWLF
VWDWXV IODJV
Table 7.C
Updating Arithmetic Status Flags for a MVM Instruction
Entering Parameters
7RSURJUDPWKLVLQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKH IROORZLQJ
Source a program constant or data address from which the instruction reads an
image of the value. The source remains unchanged.
Mask an address or hexadecimal value that specifies which bits to pass or

block.
You must set (1) mask bits to move data. Moved data overwrites
destination data. Bits at the destination that correspond to zeros in the
mask are not altered.
If you want the ladder program to change the mask value, store the mask
at a data address. When you enter a value in this field, make sure that
you include the data type, file number and word number. For example,
type B100:0.
Otherwise, enter a hexadecimal value for a constant mask value. For
example, type F800.
Destination the data address to which the instruction writes the result of the
operation. The instruction writes over any data stored at the destination.
Example:
1785-6.1 November 1998

Bit Modify and Move Instructions BTD, MOV, MVM 7-5
MVM Destination
MASKED MOVE N7:2 Before Move
Source N7:0
Mask 1111000011110000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Destination N7:2
Source Mask
N7:0 F0F0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
Destination
N7:2 After Move
0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1
13360
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 8
File Instruction Concepts
Concepts of File Operation 7KLVFKDSWHUSUHVHQWVFRQFHSWVRIEORFNRSHUDWLRQIRUWKH)LOH
$ULWKPHWLFDQG/RJLFDO)$/DQG)LOH6HDUFKDQG&RPSDUH)6&
LQVWUXFWLRQV
7KH)$/LQVWUXFWLRQSHUIRUPVDULWKPHWLFDQGORJLFDORSHUDWLRQVRQ
EORFNVRIZRUGV7KH)6&LQVWUXFWLRQSHUIRUPVFRPSDULVRQ
RSHUDWLRQVRQEORFNVRIZRUGV)RUVSHFLILFLQIRUPDWLRQDERXWWKH
)$/RU)6&LQVWUXFWLRQVHHFKDSWHU
$SSHQGL[&
Entering Parameters <RXQHHGWRSURYLGHWKHSURFHVVRUZLWKWKHIROORZLQJLQIRUPDWLRQ

FAL ZKHQ\RXHQWHUDILOHLQVWUXFWLRQ
FILE ARITH/LOGICAL EN
Control
Length Parameter: Definition:
DN
Position
Mode Control the address of the control structure in a control type (R) file. The
Destination ER
processor uses this information to run the instruction. See “Using the
Expression
Control Structure” on page 8-2.
Length the number of words in the data block on which the file instruction
operates. Enter any decimal number 1-1000.
Position the current word within the data block that the processor is accessing.
You generally enter a zero to start at the beginning of a block.
Mode the number of file words operated on each time the rung is scanned in
the program. The mode lets you distribute operation on the complete
block of words. Specify one of the following:
• for All mode, type an A
• for Numerical mode, type a decimal number (1-1000)
• for Incremental mode, type an I
For more information about the different modes, see “Choosing Modes of
Block Operation” on page 8-5.
Destination the address where the processor stores the result of the operation. The
instruction converts to the data type specified by the destination address.
Expression contains addresses, program constants, and operators that specify the
source of data and the operations to be performed.
If you enter the index prefix (#) for a destination or expression address,
the processor accepts it as the address of the first word of a block to be
operated upon. The processor assigns and uses the offset value in
module status to process the block address. If you omit the # prefix, the
processor accepts this as the address of a single work to be operated
upon.
1785-6.1 November 1998

8-2 File Instruction Concepts
,PSRUWDQW 0DNHVXUHWKHLQGH[YDOXHSRVLWLYHRUQHJDWLYHGRHV

QRWFDXVHWKHLQGH[HGDGGUHVVWRH[FHHGWKHILOHW\SH
ERXQGDU\7KHSURFHVVRUGRHVQRWFKHFNWKLVXQOHVV\RX
XVHDQLQGH[HGLQGLUHFWDGGUHVVRUH[FHHGWKHGDWDWDEOH
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WDEOHDUHDWKHSURFHVVRULQLWLDWHVDUXQWLPHHUURUDQG
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PDQLSXODWHWKHRIIVHWYDOXHVWRUHGDW60DNHVXUH
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XVLQJDQLQGH[HGDGGUHVV2WKHUZLVHXQSUHGLFWDEOH
PDFKLQHRSHUDWLRQFRXOGRFFXUZLWKSRVVLEOHGDPDJHWR
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)RUPRUHLQIRUPDWLRQRQLQGH[HGDGGUHVVLQJVHHWKHFKDSWHURQ
DGGUHVVLQJGDWDWDEOHILOHVLQ\RXUVRIWZDUHXVHUPDQXDO
Using the Control Structure 7KHFRQWUROVWUXFWXUHILOHW\SH5FRQWUROVWKHRSHUDWLRQRIWKHILOH

LQVWUXFWLRQ6LPLODUWRDFRXQWHULWFRQWUROVWKHILOHE\OHQJWKSRVLWLRQ
DQGVWDWXVDQGFRQWUROELWV)LJXUH<RXHQWHUWKHFRQWURO
VWUXFWXUHDGGUHVVIRUH[DPSOH5LQWKH&RQWUROILHOGZKHQ\RX
SURJUDPD)$/RU)6&LQVWUXFWLRQ
Figure 8.1
Example Control File R6:0
Memory Control Structure Address
Status
Length R6:0
Position
Status
Length R6:1
Position
Status
Length R6:2
Position
13370
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FDXVLQJGDPDJHWRHTXLSPHQWDQGRULQMXU\WRSHUVRQQHO
1785-6.1 November 1998

File Instruction Concepts 8-3
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6WDWXVELWV
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VWDWXVELWV6HHFKDSWHUIRUWKH)$/RU)6&LQVWUXFWLRQIRUD
GHVFULSWLRQRIWKHVHVWDWXVELWV
Manipulating File Data 7\SLFDOGDWDPDQLSXODWLRQVZLWKILOHLQVWUXFWLRQVLQFOXGH

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DEVHQFHRIWKHSUHIL[HVWDEOLVKHVLWDVWKHDGGUHVVRIDVLQJOHZRUGWR
EHRSHUDWHGXSRQ
FAL
Control R6:5
Length 4
Position 0 DN
Mode ALL
Dest #N28:0 The # prefix for the destination address and the
ER absence of a # prefix for the expression address
Expression N27:3
establish this as a word-to-block operation.
FAL
Control R6:5
Length 4
DN
Position 0
Mode ALL
Dest N28:0 ER The absence of a # prefix for the destination
Expression #N27:3 address and the # prefix for the expression address
establish this as a block-to-word operation.
FAL
Control R6:5
Length 4
DN
Position 0
Mode ALL
Dest #N28:0 ER The # prefix for the destination address and the
Expression #N27:3 # prefix for the expression address establish this
as a block-to-block operation.
1785-6.1 November 1998

7KHIROORZLQJH[DPSOHVKRZVJHQHULFGDWDPDQLSXODWLRQVXVHGZLWK
ILOHLQVWUXFWLRQV( H[SUHVVLRQ' GHVWLQDWLRQ[ RSHUDWLRQ
Moving Data
E D E D E D
Word to Block Block to Block Block to Word
Operating on Data
E D E D
Block x Word = Result Word x Block = Result
E D E D
Word x Word = Result Block x Block = Result
E D E D
Word x Block = Result Block x Word = Result
E D
16617a
Block x Block = Result
1785-6.1 November 1998

Choosing Modes of Block 7KHEORFNPRGHWHOOVWKHSURFHVVRUKRZWRGLVWULEXWHWKHEORFN

Operation RSHUDWLRQRYHURQHRUPRUHSURJUDPVFDQV6HOHFWRQHRIWKH
IROORZLQJPRGHV
All Mode
,QWKH$OOPRGHWKHHQWLUHILOHLVRSHUDWHGRQEHIRUHFRQWLQXLQJRQWR
WKHQH[WUXQJRIWKHSURJUDP7\SHDQ$IRUWKHPRGHSDUDPHWHU
ZKHQ\RXHQWHUWKHLQVWUXFWLRQ
Word
Data File One Scan
512
14 Word File
525
16639
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SRVLWLRQ326YDOXHLQWKHFRQWUROVWUXFWXUHSRLQWVWRWKHZRUGLQWKH
GDWDEORFNWKDWWKHLQVWUXFWLRQLVFXUUHQWO\XVLQJ2SHUDWLRQVWRSV
ZKHQWKHIXQFWLRQFRPSOHWHVRUZKHQWKHSURFHVVRUGHWHFWVDQHUURU
7KHIROORZLQJWLPLQJGLDJUDPVKRZVWKHUHODWLRQVKLSEHWZHHQVWDWXV
ELWVDQGLQVWUXFWLRQRSHUDWLRQ:KHQWKHLQVWUXFWLRQH[HFXWLRQLV
FRPSOHWHWKHGRQHELWLVWXUQHGRQ7KHGRQHDQGHQDEOHELWVDUHQRW
WXUQHGRIIDQGWKHSRVLWLRQYDOXHLVQRW]HURHGXQWLOWKHUXQJ
FRQGLWLRQVDUHQRORQJHUWUXH2QO\WKHQFDQDQRWKHURSHUDWLRQEH
WULJJHUHGE\DQRWWUXHWRWUXHWUDQVLWLRQRIWKHUXQJFRQGLWLRQV
One
program
scan
Condition of rung that

controls file/block instruction
Enable (bit 15)
Done (bit 13)

The processor turns
off status bits and
zeroes position value.
Execution of the instruction
16640
Operation complete
1785-6.1 November 1998

Numerical Mode
1XPHULFDOPRGHGLVWULEXWHVWKHILOHRSHUDWLRQRYHUDQXPEHURI
SURJUDPVFDQV7RVHOHFWWKHQXPHULFDOPRGHHQWHUWKHQXPEHURI
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WRWUXH2QFHWULJJHUHGWKHLQVWUXFWLRQLVH[HFXWHGFRQWLQXDOO\HDFK
WLPHWKHUXQJLVVFDQQHGLQWKHSURJUDPIRUWKHQXPEHURIVFDQV
QHFHVVDU\WRFRPSOHWHRSHUDWLRQRQWKHHQWLUHILOH2QFHWULJJHUHG
UXQJORJLFFDQFKDQJHUHSHDWHGO\ZLWKRXWLQWHUUXSWLQJH[HFXWLRQRI
WKHLQVWUXFWLRQ
(DFKWLPHWKHUXQJLVVFDQQHGWKHLQVWUXFWLRQRSHUDWHVRQWKHQXPEHU
RIZRUGVHTXDOWRWKHUDWH\RXHQWHUHGIRUWKHPRGHYDOXHXQWLOLWKDV
RSHUDWHGRQWKHQXPEHURIZRUGV\RXVSHFLILHGE\WKHOHQJWKYDOXH,Q
WKHODVWVFDQRIWKHUXQJWKHSURFHVVRUPD\RSHUDWHRQOHVVWKDQWKH
QXPEHURIZRUGV\RXHQWHUHG
File
Word
Scan #1
512
5 words
Scan #1 516 Scan #2
517
14-Word Block 5 words
Scan #2 521 Scan #3

522
Remaining
4 words
Scan #3 525
16641
,PSRUWDQW $YRLGXVLQJWKHUHVXOWVRIDILOHLQVWUXFWLRQRSHUDWLQJLQ
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ZLOOEHLQFRPSOHWH
ELWVDQGLQVWUXFWLRQRSHUDWLRQ
Rung is true at completion Rung is not true at completion
Multiple program
scans Multiple program
scans
controls file instruction
Enable (bit 15)
Done (bit 13)
Execution of instruction
Operation complete The processor turns off Operation complete The processor
enable and done bit and turns off done
zeroes position value. bit and zeroes
position value.
16642
1785-6.1 November 1998

:KHQWKHLQVWUXFWLRQH[HFXWLRQLVFRPSOHWHWKHGRQHELWLVWXUQHGRQ
,IWKHUXQJLVWUXHDWFRPSOHWLRQWKHHQDEOHELWDQGGRQHELWDUHQRW
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,IWKHUXQJLVQRWWUXHDWFRPSOHWLRQWKHHQDEOHELWLVWXUQHGRII
LPPHGLDWHO\DQGRQHVFDQDIWHUWKHHQDEOHELWLVWXUQHGRIIWKHGRQH
ELWLVWXUQHGRIIDQGWKHSRVLWLRQYDOXHLV]HURHG
2QO\DIWHUWKHHQDEOHDQGGRQHELWVDUHWXUQHGRIIFDQDQRWKHU
RSHUDWLRQEHWULJJHUHGE\DQRWWUXHWRWUXHWUDQVLWLRQRIWKH
UXQJ FRQGLWLRQV
Incremental Mode
,QFUHPHQWDOPRGHPDQLSXODWHVRQHZRUGRIWKHILOHHDFKWLPHWKH
UXQJJRHVIURPQRWWUXHWRWUXH7\SHDQ,IRUWKHPRGHSDUDPHWHU
ZKHQ\RXHQWHUWKHLQVWUXFWLRQ
File
Word
File Word
1-Word Operation 1st Rung Enable
Word #0 512
1-Word Operation 2nd Rung Enable
Word #1 513
1-Word Operation 3rd Rung Enable
Word #2 514
Word #3 515
Word File
Word #12 524

1-Word Operation 14th Rung Enable
Word #13 (last word) 525
16
ELWVDQGLQVWUXFWLRQRSHUDWLRQ
One or more
program
scans
controls file instruction
Enable (bit 15)
Done (bit 13)
Execution of instruction
The processor The processor turns

turns off enable bit. off status bits and
Operation complete zeroes position value.
16644
1785-6.1 November 1998

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QRWWUXHWRWUXH(DFKWLPHWKLVGRHVRFFXURQO\RQHZRUGRIWKHILOHLV
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Special Case, Numerical Mode with Words Per Scan = 1

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VFDQDQGLQFUHPHQWDOPRGHLV
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1785-6.1 November 1998

Chapter 9
File Instructions FAL, FSC, COP, FLL
Using File Instructions 7KHILOHLQVWUXFWLRQVSHUIRUPRSHUDWLRQVRQILOHGDWDDQGFRPSDUHILOH
GDWD7DEOH$OLVWVWKHDYDLODEOHILOHLQVWUXFWLRQV
Table 9.A
Available File Instructions
Found on
If You Want to: Use this Operation:
Page:
Perform arithmetic, logic, shift, and FAL 9-2

function operations on file data
Perform search and compare operations on FSC 9-14

file data
Copy the contents of a file into another file COP 9-19
Fill a file with specific values FLL 9-20
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RSHUDWLRQLQWKHSUHYLRXVFKDSWHU)RUPRUHLQIRUPDWLRQRQXVLQJ
LQGH[HGDGGUHVVHVVHH\RXUVRIWZDUHXVHUPDQXDO
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1785-6.1 November 1998

9-2 File Instructions FAL, FSC, COP, FLL
File Arithmetic and Logic (FAL) 7KH)$/LQVWUXFWLRQSHUIRUPVFRS\DULWKPHWLFORJLFDQGIXQFWLRQ

RSHUDWLRQVRQWKHGDWDVWRUHGLQILOHV7KH)$/LQVWUXFWLRQSHUIRUPV
WKHVDPHRSHUDWLRQVDVWKH&37LQVWUXFWLRQ7KHGLIIHUHQFHLVWKDWWKH
)$/LQVWUXFWLRQSHUIRUPVRSHUDWLRQVRQPXOWLSOHZRUGVZKLOHWKH
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Description: 7KH)$/LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWSHUIRUPVWKH
FAL RSHUDWLRQVGHILQHGE\VRXUFHDGGUHVVHVDQGRSHUDWRUV\RXZULWH
FILE ARITH/LOGICAL EN LQWKHH[SUHVVLRQ7KHLQVWUXFWLRQZULWHVWKHUHVXOWVLQWRD
Control
Length GHVWLQDWLRQDGGUHVV
DN
Position
Mode
ER
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Destination
Expression SURJUDPVFDQVE\\RXUVHOHFWLRQRILQVWUXFWLRQPRGH)RUPRUH
LQIRUPDWLRQDERXWPRGHVRIILOHRSHUDWLRQVHHFKDSWHU
7KH)$/LQVWUXFWLRQDXWRPDWLFDOO\FRQYHUWVWKHGDWDW\SHDWWKH
VRXUFHDGGUHVVHVWRWKHGDWDW\SHWKDW\RXVSHFLI\LQWKHGHVWLQDWLRQ
DGGUHVV
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]HURDILOH
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XQORDGDILOHRIHUURUFRGHVRQHDWDWLPHIRUGLVSOD\
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PDQLSXODWHWKHRIIVHWYDOXHVWRUHGDW60DNHVXUH
\RXPRQLWRURUORDGWKHRIIVHWYDOXH\RXZDQWSULRUWR
XVLQJDQLQGH[HGDGGUHVV2WKHUZLVHXQSUHGLFWDEOH
PDFKLQHRSHUDWLRQFRXOGRFFXUZLWKSRVVLEOHGDPDJHWR
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1785-6.1 November 1998

File Instructions FAL, FSC, COP, FLL 9-3
Table 9.B
FAL Operations
Copy none copy from A to B enter source address in the expression enter
destination address in destination
Clear none set a value to zero 0 (enter 0 for the expression)
Arithmetic + add 2+3

2+3+7 (Enhanced PLC-5 processors)
(12 – 5) – 1 (Enhanced PLC-5 processors)
* multiply 5*2
6 * (5 * 2) (Enhanced PLC-5 processors)
| divide 24 | 6
(24 | 6) * 2 (Enhanced PLC-5 processors)
– negate – N7:0
** exponential 10**3
(x to the power of y) (Enhanced PLC-5 processors only)
Bitwise AND bitwise AND D9:3 AND D10:4
OR bitwise OR D9:4 OR D9:5
XOR bitwise exclusive OR D10:10 XOR D10:11
NOT bitwise complement NOT D9:4
Conversion FRD convert from BCD FRD D14:0

to binary

to BCD
1785-6.1 November 1998

Using Status Bits

7RXVHWKH)$/LQVWUXFWLRQFRUUHFWO\H[DPLQHDQGFRQWUROVWDWXVELWV
LQWKHFRQWUROHOHPHQW<RXDGGUHVVWKHVHELWVE\PQHPRQLF
This Bit: Is Set:
Enable .EN (bit 15) by a false-to-true rung transition and indicates the instruction is
enabled.
In incremental mode, the .EN bit follows the rung condition.
In numerical and ALL modes, the .EN bit remains set until the
instruction completes its operation, regardless of the rung
condition. The .EN bit is reset when the rung goes false and the
instruction completes its operation.
Done .DN (bit 13) after the instruction has operated on the last set of words.
In numerical mode if the instruction is false at completion, it resets
the .DN bit one program scan after the operation is complete. If
the instruction is true at completion, the .DN bit is reset when the
instruction goes false.
Error .ER (bit 11) when the operation generates an overflow. The instruction stops
until the ladder program resets the .ER bit.
When the processor detects an error, the position value stores the
number of the word that faulted.
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UXQVSURSHUO\
ILOHDQGPDNH\RXUHGLWVLQWKH3&WH[WILOH7KHQLPSRUWWKLVWH[W
ILOH6HH\RXUSURJUDPPLQJPDQXDOIRUPRUHLQIRUPDWLRQRQ
LPSRUWLQJH[SRUWLQJSURFHVVRUPHPRU\ILOHV
1785-6.1 November 1998

FAL Copy Operations 7KH)$/FRS\RSHUDWLRQFRSLHVGDWD

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File-to-File Copy Example:
FAL File #N27 File #N28

Control R6:5 9732 9732
Element 3 0 Element
Length 4
DN
Position 0 1015 1015
Mode ALL 4 1
Destination #N28:0 ER
2000 2000
Expression #N27:3 2
5
19000 19000
6 3
13366
This Parameter: Tells the Processor:
Control (R6:5) What control structure controls the operation.

This parameter is controlled by the rung condition, the state of
the .EN and .DN bits, and by the mode (incremental, numeric, or
all). It contains the location of the last value written to by the FAL
instruction.
For example, if, in incremental mode, position = 0 and length =
4, the last word written to by the FAL instruction would be word
3 since the instruction starts at location 0.
Length (4) To move four words
Position (0) To start at the source address
Mode (ALL) To execute the length in one program scan
Destination (#N28:0) Where to write the data (the # indicates that the operation is to
be performed on a file)
Expression (#N27:3) Where to read the data (the # indicates that the operation is to
be performed on a file)
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LQWHJHUILOH1VWDUWLQJDWHOHPHQW,WZULWHVRYHUDQ\GDWDLQWKH
GHVWLQDWLRQILOH
1785-6.1 November 1998

File-to-Word Copy Example:
1st move
FAL
2nd move Word 29:5
FILE ARITH/LOGICAL File # N29:0
EN
Control R6:6
Length 5 Word 0 Word
DN
Position 0
Mode INC 1
Destination N29:5 ER
Expression #N29:0 2
5th move
3
4th move
4 3rd move
13372
Control (R6:6) What control structure controls the operation
Length (5) To copy five words
Mode (incremental) To copy one word each time the rung goes true
Destination (N29:5) Where to write the data (word address)
Expression (#N29:0) Where to read the data (the # indicates that the
operation is to be performed on a file)
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LQWRHOHPHQWRILQWHJHUILOH17KHLQVWUXFWLRQZULWHVRYHUDQ\
GDWDLQWKHGHVWLQDWLRQ
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RUDGLIIHUHQWILOH
1785-6.1 November 1998

FAL Arithmetic Operations <RXFDQSHUIRUPPXOWLSOHDULWKPHWLFRSHUDWLRQVRQILOHGDWDLQWHJHU

RUIORDWLQJSRLQWZLWKWKHIROORZLQJRSHUDWRUV
Operator: Meaning: Operator: Meaning:
+ add | divide
– subtract – negate
* multiply 0 clear
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Upper and Lower Limits

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RQWKHW\SHRIILOHLQZKLFKWKHGDWDLVVWRUHG7KHIROORZLQJ
JXLGHOLQHVDSSO\
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QHJDWLYHYDOXHVDUHVWRUHGLQWZR¶VFRPSOHPHQW
IORDWLQJSRLQWQXPEHUVDUHIRUPDWWHGDVDVXEVHWRI,(((
VLQJOHSUHFLVLRQIORDWLQJSRLQW
Type of File: Range Stored in Word:
bit –32,768 to +32,767 for integers
integer –32,768 to +32,767
timer 0 to +32,767
counter –32,768 to +32,767
control 0 to +32,767
floating point ±1.1754944e–38 to ±3.4028237e+38
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ORZHURUXSSHUOLPLWRIWKHGHVWLQDWLRQZRUGLQZKLFKLWLVVWRUHG7KH
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LQVWUXFWLRQDOVRVHWVWKHHUURUELWLQWKHVWDWXVE\WHRILWVFRQWUROZRUG
1785-6.1 November 1998

Addition Example: :KHQWKHUXQJJRHVWUXHWKHSURFHVVRUDGGVYDOXHVLQILOH1

FAL WRWKHFRUUHVSRQGLQJYDOXHVLQILOH1XVLQJWKHQXPHULFDOPRGH
FILE ARITH/LOGICAL EN RIZRUGVSHUVFDQ7KHRSHUDWLRQLVSHUIRUPHGLQVFDQVDQGWKH
Control
Length
R6:0
100 LQVWUXFWLRQVHTXHQWLDOO\DGGVWKHYDOXHVLQWKHH[SUHVVLRQVWRULQJWKH
DN
Position
Mode
0
10
UHVXOWLQILOH1
Dest #N13:0 ER
Expression
#N11:0 + #N12:0
File # N11:0 + File # N12:0 = File # N13:0
328 0 10 0 338 0
150 1 32 1 182 1
10 2 1 2 11 2
32 3 147 3 179 3
First Scan
0 4 99 4 99 4
45 5 572 5 617 5
1579 6 300 6 1879 6
620 7 42 7 662 7
800 8 19 8 819 8
1243 9 1000 9 2243 9
Second Scan next 10 words
Third Scan next 10 words
Fourth Scan next 10 words
//
//
//
//
//
//
Tenth Scan last 10 elements 99 99 99
13386
Control (R6:0) What control structure controls operation
Length (100) To operate on one hundred elements
Mode (10) To execute the data in 10 words per scan
Destination (#N13:0) Where to write the result data
Expression The operators, program constants, and

(#N11:0 + #N12:0) source addresses
1785-6.1 November 1998

Subtraction Example:
File #N14 -256 = File #N14

FAL
328 0 72 10
Control R6:1
Length 8 1 -106
DN 150 11
Position 0
Mode ALL
ER
10 2 -246 12
Dest #N15:10
Expression 32 3 -224 13
One
#N14:0 - 256
Scan 0 4 -256 14
Required 5
45 -211 15
1579 6 1323 16
620 7 364 17
16655a
Length (8) To operate on eight words
Mode (ALL) To execute the data in one program scan

(#N14:0 – 256) source addresses
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LQWHJHUILOH1ZRUGE\ZRUGVWDUWLQJDWHOHPHQWVXEWUDFWVD
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GHVWLQDWLRQILOH1VWDUWLQJDWHOHPHQWDOOLQRQHVFDQ
1785-6.1 November 1998

Multiplication Example:
FAL
Control R6:2
Length 16
DN
Position 0
Mode INC
Dest #F8:16 ER
Expression
#F8:0 * #N17:0
File #F8:0 * File #N17:0 = File #F8:16
First Transition 0.01 0 314 0 3.14 16

Second Transition 0.1 1 315 1 31.5 17
Third Transition 1.0 2 316 2 316 18
Fourth Transition 10.0 3 317 3 3170 19
4 4 20
5 5 21
6 6 22
7 7 23
8 8 24
9 9 25
//
//
//
//
//
//
15 15 31
15290
Length (16) To operate on sixteen words
Mode (incremental) To execute using incremental mode
Destination (#F8:16) Where to write the result data

(#F8:0 * #N17:0) source addresses
:KHQWKHUXQJJRHVWUXHWKHSURFHVVRUPXOWLSOLHVYDOXHVLQILOH
)E\WKHFRUUHVSRQGLQJYDOXHVLQILOH1XVLQJLQFUHPHQWDO
PRGH2QHPXOWLSOLFDWLRQLVSHUIRUPHGIRUHDFKIDOVHWRWUXH
WUDQVLWLRQ7KHRSHUDWLRQUHTXLUHVWUDQVLWLRQVVWRULQJWKHUHVXOWLQ
ILOH)
1785-6.1 November 1998

Division Example:
FAL
Control R6:2
Length 16
DN
Position 0
Mode INC
Expression
#N11:0 | #N12:0
File N11:0 | File N12:0 = File N13:0

Word Word Word
First Transition 60 0 12 0 5 0
Second Transition 175 1 5 1 35 1
Third Transition 1128 2 8 2 141 2
Fourth Transition 45 3 9 3 5 3
4 4 4
5 5 5
6 6 6
7 7 7
8 8 8
9 9 9
//
//
//
//
//
//
15 15 15
17955
Length (16) To operate on sixteen words
Mode (incremental) To execute using incremental mode
Expression The operators and source addresses

(#N11:0 | #N12:0)
:KHQWKHUXQJJRHVWUXHWKHSURFHVVRUVWDUWVWRGLYLGHYDOXHV
VWDUWLQJDW1E\WKHFRUUHVSRQGLQJYDOXHVLQILOH1XVLQJ
LQFUHPHQWDOPRGH2QHGLYLVLRQLVSHUIRUPHGIRUHDFKWUDQVLWLRQWR
WUXH7KHRSHUDWLRQUHTXLUHVWUDQVLWLRQVVWRULQJWKHUHVXOWLQD
ZRUGILOHVWDUWLQJDW1
1785-6.1 November 1998

File Square Root Example: :KHQUXQJFRQGLWLRQVJRWUXHWKHLQVWUXFWLRQREWDLQVWKHSRVLWLYH

FAL VTXDUHURRWRIWKHYDOXHDWWKHVRXUFH7KHUDWHLVGHWHUPLQHGE\WKH
FILE ARITH/LOGICAL EN PRGH\RXVHOHFW7KHUHVXOWRIHDFKVTXDUHURRWRSHUDWLRQLVVWRUHGLQ
Control
Length
R6:4
64 DN WKHFRUUHVSRQGLQJZRUGLQWKHGHVWLQDWLRQRQHZRUGDWDWLPH
Position 0
Mode
Destination
4
#N23:4 ER 7KHSURFHVVRUWDNHVWKHVTXDUHURRWRIWKHDEVROXWHYDOXHLIWKHVLJQ
Expression LVQHJDWLYHWKHSURFHVVRUGLVUHJDUGVWKHVLJQ
SQR #N22:25
Length (64) To take the square root of 64 words
Mode (4) To operate on 4 words each scan
Expression (SQR #N22:25) The operator and source address
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EHJLQQLQJDW1LVFDOFXODWHGDQGWKHUHVXOWLVZULWWHQLQWKH
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WKHUHDIWHUWKHQH[WIRXUZRUGVDUHFDOFXODWHGDQGWKHUHVXOWZULWWHQ
WRWKHGHVWLQDWLRQILOH7KHSURFHVVRUUHTXLUHVDWRWDORIVFDQV
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FAL Logic Operations 3HUIRUPPXOWLSOHORJLFRSHUDWLRQVRQELQDU\ILOHGDWDZLWKWKH

IROORZLQJELWZLVHORJLFRSHUDWRUV
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25
;25
127
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DGGUHVVLQWKHGHVWLQDWLRQ
1785-6.1 November 1998

Logical OR Example:
FAL
Control R6:4
Length 6 DN
Position 0
Mode 2
Destination #B5:24 ER
Expression
#I:000 OR #B3:6
File I:000 Word or File B3 Word = File B5 Word

0000000000000000 0 1010101010101010 6 1010101010101010 24
First Scan
1111111111111111 1 1111111100000000 7 1111111111111111 25
1111000011110000 2 0000000000000000 8 1111000011110000 26
Second Scan
1010101010101010 3 1100110011001100 9 1110111011101110 27
4 10 28
Third Scan
5 11 29
16618a
Length (6) To OR 6 words
Mode (2) To move 2 words each scan
Destination (#B5:24) Where to write the result data
Expression The operator(s) and source addresses

(#I:000 OR #B3:6)
$IWHUUXQJJRHVWUXHWKHSURFHVVRUSHUIRUPVDORJLFDORURSHUDWLRQRQ
WZRZRUGVEHJLQQLQJDW,DQG%7KHUHVXOWLVZULWWHQLQWKH
GHVWLQDWLRQILOHEHJLQQLQJDW%(YHU\WLPHWKHUXQJLVVFDQQHG
WKHUHDIWHUWKHQH[WWZRZRUGVDUHFDOFXODWHGDQGWKHUHVXOWZULWWHQWR
WKHGHVWLQDWLRQILOH7KHSURFHVVRUUHTXLUHVDWRWDORIVFDQV
OHQJWK PRGH WRFRPSOHWHWKHLQVWUXFWLRQ
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1785-6.1 November 1998

FAL Convert Operations 7KH)$/LQVWUXFWLRQFDQSHUIRUPWKHVHFRQYHUWRSHUDWLRQV

FRQYHUWIURPLQWHJHUWR%&'72'
FRQYHUWIURP%&'WRLQWHJHU)5'
Example: Convert to BCD :KHQUXQJFRQGLWLRQVJRWRWUXHWKHSURFHVVRUFRQYHUWVWKHYDOXHLQ

FAL WKHVRXUFHIURPLQWHJHUWR%&'7KHUDWHLVGHWHUPLQHGE\WKHPRGH
FILE ARITH/LOGICAL EN WKDW\RXVHOHFW7KHUHVXOWRIWKHRSHUDWLRQLVVWRUHGLQWKH
Control
Length
R6:2
12
FRUUHVSRQGLQJZRUGLQWKHGHVWLQDWLRQ
DN
Position 0
Mode ALL
Expression
TOD #N7:0
Example: Convert from BCD :KHQUXQJFRQGLWLRQVJRWRWUXHWKHSURFHVVRUFRQYHUWVWKHYDOXHLQ

WKHVRXUFHIURP%&'WRLQWHJHU7KHUDWHLVGHWHUPLQHGE\WKHPRGH
WKDW\RXVHOHFW7KHUHVXOWRIWKHRSHUDWLRQLVVWRUHGLQWKH
FRUUHVSRQGLQJZRUGLQWKHGHVWLQDWLRQ
,PSRUWDQW &RQYHUW%&'YDOXHVWRLQWHJHUEHIRUHPDQLSXODWLQJ
WKHPLI\RXGRQRWFRQYHUWWKHYDOXHVWKHSURFHVVRU
PDQLSXODWHVWKHPDVLQWHJHUDQGWKHLU%&'YDOXHLVORVW
File Search and Compare (FSC) 7KH)6&LQVWUXFWLRQSHUIRUPVVHDUFKDQGFRPSDUHRSHUDWLRQV

7KHVHDUHWKHVDPHRSHUDWLRQVDVWKH&03LQVWUXFWLRQLQFOXGLQJ
FRPSOH[H[SUHVVLRQV(QKDQFHG3/&SURFHVVRUVRQO\7KH
GLIIHUHQFHLVWKDWWKH)6&LQVWUXFWLRQSHUIRUPVORJLFDORSHUDWLRQVRQ
ILOHVZKLOHWKH&03LQVWUXFWLRQRSHUDWHVRQDVLQJOHZRUG$OVRWKH
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DQLQSXWLQVWUXFWLRQ
Description: 7KH)6&LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWFRPSDUHVYDOXHVLQ
FSC
VRXUFHILOHVZRUGE\ZRUGIRUWKHORJLFDORSHUDWLRQV\RXVSHFLI\LQ
FILE SEARCH/COMPAR EN
WKHH[SUHVVLRQ:KHQWKHSURFHVVRUILQGVWKHVSHFLILHGFRPSDULVRQLV
Control WUXHLWVHWVWKHIRXQGELW)'DQGUHFRUGVWKHSRVLWLRQ326ZKHUHWKH
Length
Position
DN WUXHFRPSDULVRQZDVIRXQG7KHLQKLELWELW,1LVVHWWRSUHYHQWDQ\
Mode IXUWKHUVHDUFKLQJRIWKHILOHV
Expression ER
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326WRWDNHDSSURSULDWHDFWLRQ5HVHWWKHLQKLELWELW,1VRWKH
LQVWUXFWLRQFDQFRQWLQXH
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LQIRUPDWLRQDERXWPRGHVRIILOHRSHUDWLRQVHHFKDSWHU
8VHWKLVLQVWUXFWLRQWRSHUIRUPRSHUDWLRQVVXFKDV
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EDWFKRSHUDWLRQ
1785-6.1 November 1998

Using Status Bits

7RXVHWKH)6&LQVWUXFWLRQFRUUHFWO\\RXUODGGHUSURJUDPPXVW
H[DPLQHDQGFRQWUROVWDWXVELWVLQWKHFRQWUROVWUXFWXUH<RXPXVW
DGGUHVVWKHVHELWVE\PQHPRQLF
This Bit: Is Set:
Enable .EN (bit 15) by a false-to-true rung transition and indicates the instruction
is enabled.
In incremental mode this bit follows the rung condition. In
Numerical and All modes, this bit remains set until the instruction
completes its operation, regardless of the rung condition. The .EN
bit is reset when rung conditions go false, but only after the
instruction has set the .DN bit.
Done .DN (bit 13) after the instruction has operated on the last set of words.
In numerical mode if the instruction is false at completion, it
resets the .DN bit one program scan after the operation is
complete. If the instruction is true at completion, the .DN bit is
reset when the instruction goes false.
Error .ER (bit 11) when the operation generates an overflow. The instruction stops
until the ladder program resets this bit.
When the processor detects an error, the position value stores
the number of the element that faulted.
Inhibit .IN (bit 9) when the processor detects a true comparison.

Your ladder program must reset this bit to continue the search
after taking an action initiated by examining the .FD bit. The
ladder program must reset this bit to continue operation.
Found .FD (bit 8) when the processor detects a true comparison. The processor
stops the search and also sets the inhibit .IN bit. The .FD bit is the
output of the FSC instruction.
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UXQVSURSHUO\
ILOHDQGPDNH\RXUHGLWVLQWKH3&WH[WILOH7KHQLPSRUWWKLVWH[W
ILOH6HH\RXUSURJUDPPLQJPDQXDOIRUPRUHLQIRUPDWLRQRQ
LPSRUWLQJH[SRUWLQJSURFHVVRUPHPRU\ILOHV
1785-6.1 November 1998

7KHIROORZLQJWLPLQJGLDJUDPIRU$OOPRGHVKRZVUHODWLRQVKLSV
EHWZHHQVWDWXVELWVDQGLQVWUXFWLRQH[HFXWLRQZKHQWKHLQVWUXFWLRQ
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Scan Markers
Only
1 Scan
Rung Condition
Enable Bit (.EN)
Done Bit (.DN)
Instruction Execution
Inhibit (.IN) and Found (.FD) Bit
Comparison Found
Ladder Program 16656

Resets Inhibit (.IN) Bit
)RUPRUHLQIRUPDWLRQDERXWKRZWKH)6&LQVWUXFWLRQUHVSRQGVZKHQ
LWILQGVQRWUXHFRPSDULVRQVVHHWKHWLPLQJGLDJUDPVLQFKDSWHU
1785-6.1 November 1998

FSC Search and Compare 7KH)6&LQVWUXFWLRQSHUIRUPVWKHVHFRPSDULVRQVRQILOHGDWD

Operations DFFRUGLQJWRKRZ\RXVSHFLI\WKHPLQWKH([SUHVVLRQ&RPSOH[
H[SUHVVLRQVDUHYDOLGLQ(QKDQFHG3/&SURFHVVRUVRQO\
Comparison: Example Expression:
Search Equal #N50:0 = #N51:0
Search Not Equal #N52:0 <> N52:11
Search Less Than #B3:100 < #N53:0
Search Less Than or Equal #F60:0 <= F60:12
Search Greater Than #N54:0 > 256
Search Greater Than or Equal F60:10 >= #N61:0
Data Conversion
7KHSURFHVVRUFRPSDUHVILOHVRIGLIIHUHQWGDWDW\SHVE\LQWHUQDOO\
FRQYHUWLQJGDWDLQWRLWVELQDU\HTXLYDOHQWEHIRUHSHUIRUPLQJWKH
FRPSDULVRQ7KHSURFHVVRUWUHDWVWKHIROORZLQJGDWDW\SHVDVLQWHJHU
WLPHUVWDWXVELWFRXQWHULQSXW$6&,,FRQWURORXWSXW%&'
,PSRUWDQW :KHQ\RXFRPSDUHIORDWLQJSRLQWDQGLQWHJHUYDOXHVLQ
WKH)6&LQVWUXFWLRQOLPLWWKHFRPSDULVRQVWR³OHVVWKDQ
RUHTXDO´DQG³JUHDWHUWKDQRUHTXDO´
,PSRUWDQW 8VH$6&,,DQG%&'IRUGLVSOD\RQO\DQGQRWDVYDOXHV
6LQFHWKHSURFHVVRULQWHUSUHWVWKHPDVLQWHJHUWKH\PD\
ORVHWKHLUPHDQLQJLI\RXHQWHUWKHPDVYDOXHV
)RUWKHRUGHULQZKLFKWKHLQVWUXFWLRQSHUIRUPVORJLFDORSHUDWLRQVVHH
WKHVHFWLRQ³'HWHUPLQLQJWKH2UGHURI2SHUDWLRQ´LQFKDSWHU
File Search Operation

:KHQWKHUXQJFRQGLWLRQJRHVWRWUXHWKHGHVLUHGFRPSDULVRQLV
SHUIRUPHGRQGDWDDGGUHVVHGLQWKHH[SUHVVLRQ:RUGVDUHFRPSDUHG
LQDVFHQGLQJRUGHUVWDUWLQJDWWKHEHJLQQLQJ7KHUDWHLVGHWHUPLQHG
E\WKHPRGHRIRSHUDWLRQWKDW\RXVSHFLI\
7KH'1ELWELWLVVHWDIWHUWKHSURFHVVRUKDVFRPSDUHGWKHODVW
SDLU,IWKHUXQJLVWUXHDWFRPSOHWLRQWKH'1ELWLVWXUQHGRIIZKHQ
WKHUXQJLVQRORQJHUWUXH,QQXPHULFDOPRGHKRZHYHULIWKHUXQJLV
QRWWUXHDWFRPSOHWLRQWKH'1ELWVWD\VRQRQHSURJUDPVFDQDIWHU
WKHRSHUDWLRQLVFRPSOHWH
1785-6.1 November 1998

Example of Search Not Equal:

FSC
FILE SEARCH/COMPARE EN
Control R6:0
Length 90
DN
Position 0
Mode 10
Expression ER
#B4:0 <> #B5:0
File B4 Word File B5 Word

0000000100000000(100) 0 0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 (1 0 0 ) 0
0000000000000001(1) 1 0000000000000001(1) 1
First scan 0000000000000010(2) 2 0000000000000010(2) 2
0000000000000110(6) 3 0 0 00 0 0 0 0 0 0 0 0 0 1 1 0 (6 ) 3 Processor stops and
0000000000000111(7) 0 0 00 0 0 0 0 0 0 0 0 0 1 1 0 (6 ) sets the found and
4 4
inhibit bits. To continue,
the program must reset
the inhibit bit.
10 10
Second scan
Next 10 words Next 10 words
Next 10 words Next 10 words
Ninth scan
Last 10 words Last 10 words
89 89
16620a
Length (90) To search through 90 words
Position (0) To start at source addresses
Mode (10) To search 10 words per program scan
Expression The comparison to perform and the source addresses

(#B4:0 <> #B5:0)
:KHQDUXQJFRQWDLQLQJWKH)6&LQVWUXFWLRQJRHVWRWUXHWKH
SURFHVVRUSHUIRUPVWKHQRWHTXDOWRFRPSDULVRQEHWZHHQZRUGV
VWDUWLQJDW%DQG%7KHQXPEHURIZRUGVFRPSDUHGSHU
SURJUDPVFDQLQWKLVH[DPSOHLVGHWHUPLQHGE\WKHPRGH
\RXVHOHFW
:KHQWKHSURFHVVRUILQGVWKDWFRUUHVSRQGLQJVRXUFHZRUGVDUHQRW
HTXDOZRUGV%DQG%LQWKLVH[DPSOHWKHSURFHVVRUVWRSVWKH
VHDUFKDQGWXUQVRQWKHIRXQG)'DQGLQKLELW,1ELWVVR\RXUODGGHU
SURJUDPFDQWDNHDSSURSULDWHDFWLRQ7RFRQWLQXHWKHVHDUFK
FRPSDULVRQ\RXPXVWWXUQRIIWKH,1ELW
1785-6.1 November 1998

File Copy (COP)
Description: 7KH&23LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWFRSLHVWKHYDOXHVLQ
COP WKHVRXUFHILOHLQWRWKHGHVWLQDWLRQILOH7KHVRXUFHUHPDLQV
COPY FILE XQFKDQJHG7KH&23LQVWUXFWLRQGRHVQRWXVHVWDWXVELWV,I\RXQHHG
Source DQHQDEOHELWSURJUDPDSDUDOOHORXWSXWWKDWXVHVDVWRUDJHDGGUHVV
Destination
Length 7KH&23LQVWUXFWLRQGRHVQRWZULWHRYHUILOHERXQGDULHV$Q\
RYHUIORZGDWDLVORVW$OVRQRGDWDFRQYHUVLRQRFFXUVLIWKHVRXUFH
DQGGHVWLQDWLRQILOHVDUHGLIIHUHQWGDWDW\SHVXVHILOHVRIWKHVDPHGDWD
W\SHIRUHDFK
,IWKHGHVWLQDWLRQLVLQDILOHRIZRUGVVXFKDVDQLQWHJHUILOH\RX
VSHFLI\WKHOHQJWKLQZRUGV,IWKHGHVWLQDWLRQLVLQDILOHRIVWUXFWXUHV
VXFKDVDFRXQWHUILOH\RXVSHFLI\WKHOHQJWKLQVWUXFWXUHV)RU
H[DPSOHLIWKHVRXUFHLVLQDQLQWHJHUILOHWKHGHVWLQDWLRQLVLQD
FRXQWHUILOHDQG\RXVSHFLI\DOHQJWKRILQWHJHUZRUGVDUH
FRSLHGLQWRFRXQWHUVWUXFWXUHV
Entering Parameters
7RSURJUDPWKH&23LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJ
Source the starting address of the source file. The source remains unchanged.
Destination address of the destination file. The instruction writes over any data
already stored at the destination.
Length the number of the words/structures to overwrite in the destination file.
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PDMRUIDXOWFRGHEDGXVHUSURJUDPFKHFNVXP,I
WKHLQGLUHFWDGGUHVVLVZULWWHQRXWVLGHRIWKHSURJUDP
DUHDXQH[SHFWHGUHVXOWVFRXOGRFFXU
,I\RXXVHWKH&23LQVWUXFWLRQZLWKDQ(QKDQFHG
3/&SURFHVVRUVVHULHV(DQGKLJKHUWKLVFRQGLWLRQLV
FRUUHFWO\LGHQWLILHGE\HLWKHUPDMRUIDXOWFRGH
LQGLUHFWDGGUHVVRXWRIUDQJHKLJKRUPDMRUIDXOW
FRGH LQGLUHFWDGGUHVVRXWRIUDQJHORZ
1785-6.1 November 1998

Example:
I:012 COP
[
[ COPY FILE
10
Source #N7:0
Destination #N12:0
Length 5
If input word 12, bit 10 is on, copy the values

of the first five words starting at N7:0 into the first
five words of N12:0.
File Fill (FLL)
Description: 7KH)//LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWILOOVWKHZRUGVRID
ILOHZLWKDVRXUFHYDOXH7KHVRXUFHUHPDLQVXQFKDQJHG7KH)//
FLL
LQVWUXFWLRQGRHVQRWXVHVWDWXVELWV,I\RXQHHGDQHQDEOHELWSURJUDP
FILL FILE
DSDUDOOHORXWSXWWKDWXVHVDVWRUDJHDGGUHVV
Source
Destination 7KH)//LQVWUXFWLRQGRHVQRWZULWHRYHUILOHERXQGDULHV$Q\
Length RYHUIORZGDWDLVORVW$OVRQRGDWDFRQYHUVLRQRFFXUVLIWKHVRXUFH
DQGGHVWLQDWLRQILOHVDUHGLIIHUHQWGDWDW\SHVXVHILOHVRIWKHVDPHGDWD
W\SHIRUHDFK
,IWKHGHVWLQDWLRQLVLQDILOHRIZRUGVVXFKDVDQLQWHJHUILOH\RX
VSHFLI\WKHOHQJWKLQZRUGV,IWKHGHVWLQDWLRQLVLQDILOHRIVWUXFWXUHV
VXFKDVDFRXQWHUILOH\RXVSHFLI\WKHOHQJWKLQVWUXFWXUHV)RU
H[DPSOHLIWKHVRXUFHZRUGLVDQLQWHJHUILOHWKHGHVWLQDWLRQLVLQD
FRXQWHUILOHDQG\RXVSHFLI\DOHQJWKRIWKHVRXUFHZRUGLVFRSLHG
WLPHVWRILOOWKHFRXQWHUVWUXFWXUHV
7KH)//LQVWUXFWLRQLVOHYHOVHQVLWLYH
Entering Parameters
7RSURJUDPWKH)//LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJ
Source the address of the source word or a program constant. The source
remains unchanged.
Destination the starting address of the destination file. The instruction writes over
any data already stored at the destination.
Length the number of the words/structures to fill in the destination file
1785-6.1 November 1998

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PDMRUIDXOWFRGHEDGXVHUSURJUDPFKHFNVXP,I
WKHLQGLUHFWDGGUHVVLVZULWWHQRXWVLGHRIWKHSURJUDP
DUHDXQH[SHFWHGUHVXOWVFRXOGRFFXU
,I\RXXVHWKH)//LQVWUXFWLRQZLWKDQ(QKDQFHG
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FRUUHFWO\LGHQWLILHGE\HLWKHUPDMRUIDXOWFRGH
LQGLUHFWDGGUHVVRXWRIUDQJHKLJKRUPDMRUIDXOW
FRGH LQGLUHFWDGGUHVVRXWRIUDQJHORZ
Example:
I:012 FLL
[
[ FILL FILE
10
Source N7:0
Destination #N12:0
Length 5
If input word 12, bit 10 is on, copy the value
of word N7:0 into the first five words
starting at N12:0
:RUGVDUHFRSLHGIURPWKHVSHFLILHGVRXUFHILOHLQWRWKHVSHFLILHG
GHVWLQDWLRQILOHHYHU\VFDQWKDWWKHUXQJLVWUXH7KH\DUHFRSLHGLQ
DVFHQGLQJRUGHUZLWKQRWUDQVIRUPDWLRQRIGDWDXSWRWKHVSHFLILHG
QXPEHURUXQWLOWKHODVWZRUGRIWKHGHVWLQDWLRQILOHLVUHDFKHG
ZKLFKHYHURFFXUVILUVW
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VXFKDVEHWZHHQILOHV1DQG1DWWKHGHVWLQDWLRQ7KHRYHUIORZ
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1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 10
Diagnostic Instructions FBC, DDT, DTR
Using Diagnostic Instructions 7KHGLDJQRVWLFLQVWUXFWLRQVOHW\RXGHWHFWSUREOHPVZLWKGDWDLQ\RXU
SURJUDPV7DEOH$OLVWVWKHDYDLODEOHGLDJQRVWLFLQVWUXFWLRQV
Table 10.A
Available Diagnostic Instructions
If You Want to: Use this Operation: Found on Page:
Compare I/O data against a known, good FBC 10-2

reference and record any mismatches
Compare I/O data against a known, good DDT 10-2

reference, record any mismatches, and
update the reference file to match the
source file
Pass source data through a mask and DTR 10-8

compare the result to reference data, and
then write the source word into the
reference address of the next comparison.
$SSHQGL[&
1785-6.1 November 1998

10-2 Diagnostic Instructions FBC, DDT, DTR
File Bit Comparison (FBC) and 7KH)%&DQG''7GLDJQRVWLFLQVWUXFWLRQVDUHRXWSXWLQVWUXFWLRQV

Diagnostic Detect (DDT) WKDW\RXXVHWRPRQLWRUPDFKLQHRUSURFHVVRSHUDWLRQVWR
GHWHFWPDOIXQFWLRQV
Table 10.B
Available Diagnostic Instructions
If You Want to Detect Malfunctions By: Use this Instruction:
Comparing bits in a file of real-time inputs with a FBC

reference bit file that represents correct operation
Change-of-state diagnostics DDT
Description: %RWKWKH)%&DQG''7LQVWUXFWLRQVFRPSDUHELWVLQDILOHRIUHDOWLPH
FBC
PDFKLQHRUSURFHVVYDOXHVLQSXWILOHZLWKELWVLQDUHIHUHQFHILOH
FILE BIT COMPARE EN GHWHFWGHYLDWLRQVDQGUHFRUGPLVPDWFKHGELWQXPEHUV7KHVH
Source DN LQVWUXFWLRQVUHFRUGWKHSRVLWLRQRIHDFKPLVPDWFKIRXQGDQGSODFHWKLV
Reference
Result
FD LQIRUPDWLRQLQWKHUHVXOWILOH,IQRPLVPDWFKHVDUHIRXQGWKH'1ELW
Compare Control
Length
IN
LVVHWEXWWKHUHVXOWILOHUHPDLQVXQFKDQJHG
ER
Position
Result control 7KHGLIIHUHQFHEHWZHHQWKH''7DQG)%&LQVWUXFWLRQLVWKDWHDFK
Length
Position
WLPHWKH''7LQVWUXFWLRQILQGVDPLVPDWFKWKHSURFHVVRUFKDQJHVWKH
UHIHUHQFHELWWRPDWFKWKHVRXUFHELW7KH)%&LQVWUXFWLRQGRHVQRW
FKDQJHWKHUHIHUHQFHELW8VHWKH''7LQVWUXFWLRQWRXSGDWH\RXU
UHIHUHQFHILOHWRUHIOHFWFKDQJLQJPDFKLQHRUSURFHVVFRQGLWLRQV
Selecting the Search Mode

6HOHFWZKHWKHUWKHGLDJQRVWLFLQVWUXFWLRQVHDUFKHVIRURQHPLVPDWFK
DWDWLPHRUZKHWKHULWVHDUFKHVIRUDOOPLVPDWFKHVGXULQJRQH
SURJUDPVFDQ
One Mismatch at a Time

:LWKHDFKIDOVHWRWUXHUXQJWUDQVLWLRQWKHLQVWUXFWLRQVHDUFKHVIRU
WKHQH[WPLVPDWFKEHWZHHQWKHLQSXWDQGUHIHUHQFHILOHV8SRQ
ILQGLQJDPLVPDWFKWKHLQVWUXFWLRQVWRSVDQGVHWVWKHIRXQG)'ELW
7KHQWKHLQVWUXFWLRQHQWHUVWKHSRVLWLRQQXPEHURIWKHPLVPDWFKLQWR
WKHUHVXOWILOH
7KH''7LQVWUXFWLRQDOVRFKDQJHVWKHVWDWXVRIWKHUHIHUHQFHELWWR
PDWFKWKHVWDWXVRIWKHFRUUHVSRQGLQJLQSXWELW7KHLQVWUXFWLRQUHVHWV
WKHIRXQGELWZKHQWKHUXQJJRHVIDOVH
1785-6.1 November 1998

Diagnostic Instructions FBC, DDT, DTR 10-3
:KHQWKHLQVWUXFWLRQUHDFKHVWKHHQGRIWKHILOHWKHGRQHELWELW
'1RIWKHFRPSDUHFRQWUROHOHPHQWLVVHW7KHQZKHQWKHUXQJJRHV
IDOVHWKHLQVWUXFWLRQUHVHWV
HQDEOHELW
IRXQGELWLIVHW
FRPSDUHGRQHELW
UHVXOWGRQHELWLIVHW
ERWKFRQWUROFRXQWHUV
7RHQDEOHWKLVPRGHRIRSHUDWLRQVHWWKHLQKLELWELW,1 HLWKHUE\
ODGGHUSURJUDPRUPDQXDOO\EHIRUHSURJUDPH[HFXWLRQ
All Per Scan

7KHLQVWUXFWLRQVHDUFKHVIRUDOOPLVPDWFKHVEHWZHHQWKHLQSXWDQG
UHIHUHQFHILOHVLQRQHSURJUDPVFDQ8SRQILQGLQJPLVPDWFKHVWKH
LQVWUXFWLRQHQWHUVWKHSRVLWLRQQXPEHUVRIPLVPDWFKHGELWVLQWRWKH
UHVXOWILOHLQWKHRUGHULWILQGVWKHP$IWHUUHDFKLQJWKHHQGRIWKH
LQSXWDQGUHIHUHQFHILOHVWKHLQVWUXFWLRQVHWVWKH)'ELWLILWILQGVDW
OHDVWRQHPLVPDWFK7KHQWKHLQVWUXFWLRQVHWVWKH'1ELW
,I\RXXVHDUHVXOWILOHWKDWFDQQRWKROGDOOGHWHFWHGPLVPDWFKHVLIWKH
UHVXOWILOHILOOVWKHLQVWUXFWLRQVWRSVDQGUHTXLUHVDQRWKHUIDOVHWRWUXH
UXQJWUDQVLWLRQWRFRQWLQXHRSHUDWLRQ7KHLQVWUXFWLRQZUDSVWKHQHZ
PLVPDWFKHGELWSRVLWLRQVLQWRWKHEHJLQQLQJRIWKHUHVXOWILOHZULWLQJ
RYHUWKHROG
$IWHUFRPSOHWLQJWKHFRPSDULVRQDQGZKHQWKHUXQJJRHVIDOVHWKH
LQVWUXFWLRQUHVHWV
HQDEOHELW
IRXQGELWLIVHW
FRPSDUHGRQHELW
UHVXOWGRQHELWLIVHW
ERWKFRQWUROFRXQWHUV
7RHQDEOHWKLVPRGHRIRSHUDWLRQUHVHWWKHLQKLELWELW,1 E\
ODGGHUSURJUDPRUPDQXDOO\EHIRUHSURJUDPH[HFXWLRQ
1785-6.1 November 1998

Entering Parameters
7RSURJUDPWKHVHLQVWUXFWLRQV\RXQHHGWRSURYLGHWKHSURFHVVRUZLWK
WKHIROORZLQJLQIRUPDWLRQ
Parameter: Description:
Source the indexed address of your input file.
Reference the indexed address of the file that contains the data with which you
compare your input file.
Result the indexed address of the file where the instruction stores the position
(bit) number of each detected mismatch.
Cmp Control the address of the comparison control structure (R) that stores status
bits, the length of the source and reference files (both should be the
same), and the current position during operation. Use the compare
control address with mnemonic when you address these parameters:
Length (.LEN) is the decimal number of bits to be compared in the
source and reference files. Remember that bits in I/O files are
numbered in octal 00-17, but that bits in all other files are numbered in
decimal 0-15.
Position (.POS) is the current position of the bit to which the instruction
points. Enter a value only if you want the instruction to start at an
offset concurrent with a control file offset for one scan.
Result Control the address of the result control structure (R) that stores the bit
position number each time the instruction finds a mismatch between
source and reference files.
8VHWKHUHVXOWFRQWURODGGUHVVZLWKPQHPRQLFZKHQ\RXDGGUHVV
WKHVH SDUDPHWHUV
/HQJWK/(1LVWKHGHFLPDOQXPEHURIHOHPHQWVLQWKHUHVXOW
ILOH0DNHWKHOHQJWKORQJHQRXJKWRUHFRUGWKHPD[LPXP
QXPEHURIH[SHFWHGPLVPDWFKHV
3RVLWLRQ326LVWKHFXUUHQWSRVLWLRQLQWKHUHVXOWILOH(QWHUD
YDOXHRQO\LI\RXZDQWWKHLQVWUXFWLRQWRVWDUWDWDQRIIVHW
FRQFXUUHQWZLWKDFRQWUROILOHRIIVHWIRURQHVFDQ
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WKDQRQHFRQWUROVWUXFWXUH'XSOLFDWLRQRIWKHVH
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SHUVRQQHO
1785-6.1 November 1998

Using Status Bits

7RXVHWKH)%&RU''7LQVWUXFWLRQFRUUHFWO\H[DPLQHDQGFRQWURO
ELWVLQERWKWKHFRPSDULVRQDQGUHVXOWFRQWUROHOHPHQWV<RXDGGUHVV
WKHVHELWVE\PQHPRQLF
Bit: Function:
Comparison Enable .EN (bit 15) starts operation on a false-to-true rung transition
Control Bits If the .IN bit is set for one-at-a-time operation, the ladder program
must toggle the .EN bit after the instruction detects each mismatch.
Done .DN (bit 13) is set when the processor reaches the end of the source and reference files
Error .ER (bit 11) is set when the processor detects an error and stops operation of
the instruction
For example, an error occurs if the length (.LEN) is less than or equal to zero
or if the position (.POS) is less than zero. The ladder program must reset the
.ER bit if the instruction detects an error.
Inhibit .IN (bit 09) determines the mode of operation

When this bit is reset, the processor detects all mismatches in one scan.
When this bit is set, the processor stops the search at each mismatch and
waits for the ladder program to re-enable the instruction before continuing
the search.
Found .FD (bit 08) is set each time the processor records a mismatch bit number in the result file
(one-at-a-time operation) or after recording all mismatches (all per scan).
Result Done .DN (bit 13) is set when the result file fills
Control Bits The instruction stops and requires another false-to-true rung transition to
reset the result .DN bit and then continue. If the instruction finds another
mismatch, it wraps the new position number around to the beginning of the
file, writing over previous position numbers.
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LQVWUXFWLRQLVUHVHWZKHQWKHUXQJ¶VLQSXWFRQGLWLRQVJRIDOVH7KH
LQVWUXFWLRQUHVHWVLWVVWDWXVELWVDQGERWKFRQWUROHOHPHQWV
1785-6.1 November 1998

Example: 7KH''7LQVWUXFWLRQDERYHFRPSDUHVWKHELWVLQWKHVRXUFHILOH
DDT ,ZLWKWKHELWVLQWKHUHIHUHQFHILOH%UHFRUGLQJWKH
DIAGNOSTIC DETECT EN PLVPDWFKHGELWSRVLWLRQVLQWKHUHVXOWILOH1
Source #I:030 DN
Reference #B3:0
Result #N10:0 FD
Compare control R6:0 IN
Length 48
Position 0 ER
Result control R6:1
Length 10
Position 0
Input Reference Result File 2

File File 1 (mismatched bit #s)
bit 3 #N10
#I:030 #B3
17 10 07 00 15 08 07 00
0 3
1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 31
1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
2 32
1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
bit 31
3 40
bit 40 bit32
9
The FBC and DDT instructions detect mismatches and record their locations by bit number in a result file.
1
The DDT instruction changes the status of the corresponding bit in the reference file to match the input file
when it detects a mismatch.
2
The length of the result file is the length that you enter for RESULT CONTROL.
16657a
Source (#I:030) Where to find input data for comparison
Reference (#B3:0) Where to find the reference file
Result (#N10:0) Where to store mismatched bit numbers
CMP Control (R6:0) What control structure controls the comparison
Length (48) The number of bits to be compared
Position (0) To start at the beginning of the file
Result Control (R6:1) What control structure controls the result
Length (10) The number of words reserved for mismatches
Position (0) To start at the beginning of the file
1785-6.1 November 1998

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1785-6.1 November 1998

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Source the address of the input word, typically real inputs.
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Reference the address of the reference word

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Reference N63:11
1785-6.1 November 1998

15 08 07 00 15 08 07 00
Source Word
1 8 3 I:002 1 8 7
15 08 07 00 15 08 07 00
Mask Value
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFF 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
15 08 07 00 15 08 07 00
Current Current
Scan 1 8 3 Reference Word 1 8 7 Scan
N63:11
Previous 1 8 3 1 8 3 Previous
Scan Scan
Rung remains false as long as Rung goes true for one scan
input value does not change when change is detected 13385
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 11
Shift Register Instructions BSL, BSR, FFL,
FFU, LFL, LFU
Applying Shift Registers 8VHWKHVKLIWUHJLVWHULQVWUXFWLRQWRVLPXODWHWKHPRYHPHQWRUIORZRI
SDUWVDQGLQIRUPDWLRQ
If You Use a Shift Register for: Data in the Shift Register Could Represent:
Tracking parts through an assembly line Part types, quality, size, and status
Controlling machine or process operations The order in which events occur
Inventory control Identification numbers or locations
System diagnostics A fault condition that caused a shutdown
7DEOH$OLVWVWKHDYDLODEOHVKLIWLQVWUXFWLRQV
Table 11.A
Available Shift Instructions
If You Want to: Use these Instructions: Found on Page:
Load bits into, shift bits through, and unload bits from a bit array one bit at BSL, BSR 11-2
a time, such as for tracking bottles through a bottling line where each bit
represents a bottle
Load and unload values in the same order, such as for tracking parts FFL, FFU 11-5
through an assembly line where parts are represented by values that have
a part number and assembly code
Load and unload values in reverse order, such as tracking stacked LFL, LFU * 11-8
inventory in a warehouse, where goods are represented by serial number
and inventory codes
* These instructions are only supported by Enhanced PLC-5 processors.
$SSHQGL[&
1785-6.1 November 1998

11-2 Shift Register Instructions BSL, BSR, FFL, FFU, LFL, LFU
Using Bit Shift Instructions
Description: %LWVKLIWLQVWUXFWLRQVVKLIWDOOELWVZLWKLQWKHVSHFLILHGDGGUHVV
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BIT SHIFT LEFT EN LQVWUXFWLRQVDUH
File
Control DN
%LW6KLIW/HIW%6/
Bit address
Length %LW6KLIW5LJKW%65
Entering Parameters
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File the address of the bit array you want to manipulate. You must start the
array at a 16-bit word boundary. For example, use bit 0 of word number
1, 2, 3, etc. You can end the array at any bit number up to 15,999.
However, you cannot use the remaining bits in that particular element
because the instruction invalidates them.
Control The address of the control structure (48 bits – three 16-bit words) in the
control area (R) of memory that stores the instruction’s status bits, the
size of the array (number of bits), and the bit pointer.
Position the current position of the bit to which the instruction points. Enter a
value only if you want the instruction to start at an offset concurrent with
a control file offset for one scan. Use the control address with mnemonic
when you address this parameter.
Bit Address the address of the source bit. The instruction inserts the status of this bit
in either the first (lowest) bit position (for the BSL instruction) or the last
(highest) bit position (for the BSR instruction) in the array.
Length the decimal number of bits to be shifted. Remember that bits in I/O files
are numbered in octal 00-17, but that bits in all other files are numbered
in decimal 0-15. Use the control address with mnemonic when you
address this parameter.
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1785-6.1 November 1998

Shift Register Instructions BSL, BSR, FFL, FFU, LFL, LFU 11-3
Using Status Bits

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Bit: Definition:
Enable .EN (bit 15) is set when the rung makes a false-to-true rung transition to
indicate the instruction is enabled.
Done .DN (bit 13) is set to indicate that the bit array shifted one bit position
Error .ER (bit 11) is set to indicate that the instruction detected an error, such as if
you entered a negative file length
Unload .UL (bit 10) is the instruction’s output.

The .UL bit stores the status of the bit removed from the array
each time the instruction is enabled. Avoid using the .UL bit when
the .ER bit is set.
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Bit Shift Left (BSL) Example:

Source
BSL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I:022/12
BIT SHIFT LEFT EN
File #B3:1 31 16
Control R6:53 DN L
Bit address I:022/12
Length 58 47 32
58-Bit
L
#B3/16
63 48 (B3:1)
L
invalid 73 64
Unload Bit
L
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
16658
File (#B3:1) The location of the bit array
Control (R6:53) The instruction’s address and control element
Bit Address (I:022/12) The location of the source bit (bit 12 of input word 22)
Length (58) The number of bits in the bit array
1785-6.1 November 1998

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Bit Shift Right (BSR) Example:

BSR
BIT SHIFT RIGHT EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
File #B3:2 Unload Bit
Control R6:54 DN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit address I:023/06 47 32
Length 38
R
38-Bit
48 Array
Bit R #B3/32
Address (#B3:2)
I:023/06 invalid 69 64
R
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
16659
File (#B3:2) The location of the bit array
Control (R6:54) The instruction’s address and control element
Bit Address (I:023/06) The source bit address (bit 06 in input word 23)
Length (38) The number of bits in the bit array
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1785-6.1 November 1998

Using FIFO and LIFO Instructions
Description: 8VH),)2LQVWUXFWLRQV)LUVW,Q±)LUVW2XW))/DQG))8DQG/,)2

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FIFO LOAD EN UHWULHYHGDWDLQDSUHVFULEHGRUGHU
Source
FIFO
DN
Control
Length
These Instructions: Retrieve Data:
Position EM
FFL and FFU In the order stored (first in, first out)
FFU LFL and LFU * In reverse of the order stored (last in, first out)
FIFO UNLOAD EU
* Available in Enhanced PLC-5 processors only
FIFO
Destination DN
Control
Length
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Position
EM UHJLVWHUVWDFN
Entering Parameters
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This Instruction: Unloads the Value from:
FIFO’s FFU Word zero
LIFO’s LFU The last word entered
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1785-6.1 November 1998

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Using Status Bits

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LQWKHFRQWUROVWUXFWXUH<RXDGGUHVVWKHVHELWVE\PQHPRQLF
This Bit: Is Set:
Enable Load .EN (bit 15) when the rung makes a false-to-true rung transition to
indicate the instruction is enabled (used in FFL and LFL
instructions).
Note: During prescan, this bit is set to prevent a false load
when the program scan begins.
Enable Unload .EU (bit 14) when rung conditions are true to indicate the instruction is
enabled (used in FFU and LFU instructions).
Note: During prescan, this bit is set to prevent a false
unload when the program scan begins.
Done .DN (bit 13) by the processor to indicate that the stack is full. The .DN
bit inhibits loading the stack until there is room.
Empty .EM (bit 12) by the processor to indicate that the stack is empty. Do not
enable the FIFO or LIFO unload commands if the .EM bit is
set.
1785-6.1 November 1998

FIFO Load (FFL) and FIFO Unload (FFU)

Example:
FFL DESTINATION File #N60:3 Word

FIFO LOAD EN N60:2 3
Source N60:1 4
FIFO #N60:3 FIFO Unload removes data from stack
Control R6:51
DN 5
Length 64 6
Position 0 EM 7
8 64 words
FFU 9 allocated
FIFO UNLOAD EU SOURCE 10 for FIFO
FIFO #N60:3 N60:1 11 stack at
Destination N60:2 DN #N60:3
Control R6:51 FIFO Load enters data into
Length 64
Position 0 EM stack at next position
66
16660a
Source (N60:1) The location of the “next in” source word
FIFO (#N60:3) The location of the stack (FIFO file)
Destination (N60:2) The location of the “exit” word
Control (R6:51) The instruction’s address and control structure
Length (64) The maximum number of words you can load
Position (0) To start at the FIFO file address
FIFO Load Description: :KHQWKHUXQJWKDWFRQWDLQVWKH))/LQVWUXFWLRQJRHVIURPIDOVHWR

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1LQWRWKHQH[WDYDLODEOHHOHPHQWLQWKHVWDFNDVSRLQWHGWRE\
WKHFRQWUROVWUXFWXUH¶VSRVLWLRQ7KHSURFHVVRUORDGVDQHOHPHQWHDFK
WLPHWKHUXQJJRHVIURPIDOVHWRWUXHXQWLOLWILOOVWKHVWDFN:KHQWKH
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SURJUDPVKRXOGGHWHFWWKDWWKHVWDFNLVIXOODQGLQKLELWIXUWKHUORDGLQJ
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LQVWUXFWLRQZKLOHLQKLELWLQJWKHXQORDGLQVWUXFWLRQXQWLOWKHVWDFN
FRQWDLQVWKHGHVLUHGGDWD
FIFO Unload Description: :KHQWKHUXQJWKDWFRQWDLQVWKH))8LQVWUXFWLRQJRHVIURPIDOVHWR

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HOHPHQWVWRUHGLQWKH),)2VWDFNLQWRWKHGHVWLQDWLRQZRUG1$W
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1785-6.1 November 1998

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7KHUHDIWHUWKHSURFHVVRUWUDQVIHUVD]HURYDOXHIRUHDFKIDOVHWRWUXH
UXQJWUDQVLWLRQXQWLOWKH))/LQVWUXFWLRQORDGVQHZYDOXHV<RXU
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LIFO Load (LFL) and LIFO Unload (LFU)

Example:
(Enhanced PLC-5 processors only)
LFL
File #N70:3
LIFO LOAD
Word
EN
Source N70:1 3
LIFO #N70:3 DN 4
Control R6:61
Length
5
64
Position 0 EM 6
7
LFU 8
LIFO UNLOAD EU
9 64 words allocated for
LIFO #N70:3 10 LIFO stack at #N70:3
Destination N70:2 DN 11
Control R6:61 SOURCE N70:1 DESTINATION N70:2
Length 64
Position 0 EM
LIFO Load enters LIFO Unload removes

data into stack at 63 data from stack in
next position reverse order
16621
Source (N70:1) the location of the “next in” source word
LIFO (#N70:3) the location of the stack (LIFO file)
Destination (N70:2) the location of the “exit” word
Control (R6:61) the instruction’s control structure
Length (64) the maximum number of words you can load
Position (0) to start at the LIFO file address
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1785-6.1 November 1998

LIFO Load Description: :KHQWKHUXQJWKDWFRQWDLQVWKH/)/LQVWUXFWLRQJRHVIURPIDOVHWR

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LQWRWKHQH[WDYDLODEOHZRUGLQWKHVWDFNDVSRLQWHGWRE\WKHFRQWURO
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EHFRPHVIXOOWKHSURFHVVRUVHWVWKH'1ELW7KHODGGHUSURJUDP
VKRXOGGHWHFWWKDWWKHVWDFNLVIXOODQGLQKLELWIXUWKHUORDGLQJRIGDWD
IURPWKHVRXUFH
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LQVWUXFWLRQZKLOHLQKLELWLQJWKHXQORDGLQVWUXFWLRQXQWLOWKHVWDFN
FRQWDLQVWKHGHVLUHGGDWD
LIFO Unload Description: :KHQWKHUXQJWKDWFRQWDLQVWKH/)8LQVWUXFWLRQJRHVIURPIDOVHWR

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1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 12
Sequencer Instructions SQO, SQI, SQL
Applying Sequencers 6HTXHQFHULQVWUXFWLRQVDUHW\SLFDOO\XVHGWRFRQWURODXWRPDWLF
DVVHPEO\PDFKLQHVWKDWKDYHDFRQVLVWHQWDQGUHSHDWDEOHRSHUDWLRQ
8VHWKHVHTXHQFHULQSXWLQVWUXFWLRQWRGHWHFWZKHQDVWHSLVFRPSOHWH
XVHWKHVHTXHQFHURXWSXWLQVWUXFWLRQWRVHWRXWSXWFRQGLWLRQVIRUWKH
QH[WVWHS8VHWKHVHTXHQFHUORDGLQVWUXFWLRQWRORDGUHIHUHQFH
FRQGLWLRQVLQWRWKHVHTXHQFHULQSXWDQGRXWSXWILOH
7DEOH$OLVWVWKHDYDLODEOHVHTXHQFHULQVWUXFWLRQV
Table 12.A
Available Sequencer Instructions
Control sequential machine operations by SQO 12-5

transferring 16-bit data through a mask to
output image addresses
Monitor machine operating conditions for SQI 12-7

diagnostic purposes by comparing 16-bit
image data (through a mask) with data in a
reference file
Capture reference conditions by manually SQL 12-8

stepping the machine through its operating
sequences and loading I/O or storage data
into destination files
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1785-6.1 November 1998

12-2 Sequencer Instructions SQO, SQI, SQL
Using Sequencer Instructions
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SQI SQO
SEQUENCER OUTPUT EN SQL
SEQUENCER INPUT
File SEQUENCER LOAD EN
File
Mask Mask DN File
Source Destination Source
DN
Control Control Control
Length Length Length
Position Position Position
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In this Instruction: The Sequencer File Stores Data for:
SQO Controlling outputs
SQI Reference to detect completion of a

step or a fault condition
SQL Creating the SQO or SQI file
1785-6.1 November 1998

Sequencer Instructions SQO, SQI, SQL 12-3
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For this Instruction: The Control Structure Is Incremented:
SQO and SQL By the instruction itself
SQI Externally, either by the paired SQO with the same

control address, or by another instruction
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Using Status Bits

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This Bit: Is Set:
Enable .EN (bit 15) (SQO or SQL) is set on a false-to-true rung transition to indicate
that the instruction is enabled. The instruction follows the rung
condition.
Note: During prescan, this bit is set to prevent a false increment of
the table pointer when the program scan begins.
Done .DN (bit 13) (SQO or SQL) is set after the instruction finishes operating on the
last word in the sequencer file. After the rung goes false, the
processor resets the .DN bit on the next false-to-true rung
transition.
Error .ER (bit 11) when the length value is less than or equal to zero or when the
position value is less than zero
1785-6.1 November 1998

Sequencer Output (SQO) Example:

SQO File #N7:1
SEQUENCER OUTPUT EN
N7:1 17 10 07 00 0
File #N7:1
Sequencer
Mask 0F0F DN N7:2 10 10 00 10 11 11 01 01 1
Destination O:014
Output File
Control R6:20
N7:3 11 11 01 01 01 00 10 10 2
Length 4
Position 2 01 01 01 01 01 01 0 0 0 1 3 Current Step
N7:4
00 10 01 00 10 01 00 10 4
N7:5
17 10 07 00
00 00 11 11 00 00 11 11
Mask
Value
0F0F
17 10 07 00
Destination O:014 00 00 01 01 00 00 10 10
Output Module (s)

= No Change
17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 = Off
Rack 1
I/O group 4 = On
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
SQO instruction moves the data of the current step through a mask to an output word for controlling
multiple outputs. 16645a
1785-6.1 November 1998

File (#N7:1) The location of the sequencer file
Mask (0F0F) The fixed hexadecimal value of the mask
Destination (O:014) The output image address to be changed
Control (R6:20) The structure that controls the operation
Length (4) The number of words to step through
Position (2) The current position
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Resetting the Position of SQO

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S1 MOV
MOVE
15
Source 0
The bit S:1/15 is the "first pass" bit. This bit is set when the processor Dest R6:20.POS
first scans a program. When this rung goes true, the processor moves
the value of 0 to the position word of the SQO instruction. After the
position is set to 0, the next false to true transition will cause the
processor to run step 1.
1785-6.1 November 1998

Sequencer Input (SQI) Example:

SQI
SEQUENCER INPUT
File #N7:11
Sequencer Reference File #N7:11
Mask FFF0 Word
Source I:031
15 08 07 00 Step
Control R6:21 N 7 :11 0
Length 4
Position 2 12 1
13 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 2
Input Word (Source) Mask Value FFFO 14 3
17 10 07 00 15 08 07 00
00 10 01 00 10 01 11 01 15 4
11 11 11 11 11 11 00 00
1 Mask bits are reset

SQI instruction is true when it detects that an input word matches
(through a mask) its corresponding reference word. 16646a
1 These bits are not compared. Therefore, the instruction is true in this example.
File (#N7:11) The location of the reference file
Mask (FFF0) The fixed hexadecimal value of the mask
Source (#I:031) The input image address to be compared
Control (R6:21) The element that controls the operation
Length (4) The number of elements to step through
Position (2) The current position
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Using SQI Without SQO

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SQI ADD
Rung 0
SEQUENCER INPUT ADD
File #N7:0 Source A R6:0.POS
Mask F0FF Source B 1
Source I:005 Destination R6:0.POS
Control R6:0 0
Length 20
Position 0
Rung 1 GTR MOV

GREATER THAN MOVE
Source A R6:0.POS Source 0

Source B R6:0.LEN Destination R6:0.POS
0
Sequencer Load (SQL) Example:

SQL
SEQUENCER LOAD EN
File #N7:20
Source I:002
DN Source Word I:002
Control R6:22
Length 5 17 10 0 7 00
Position 3
00 00 10 10 11 00 11 01 Source I:002
Input Module (s)
0
1
2 Destination File #N7:20
3
4 15 08 07 00
Word
5 0
N70:20
6
7
21 1 Sequencer
10 Destination
11 2 File #N7:20
12 22
13 23 00 00 10 10 11 00 11 01 3
14
15 24 4
16 Current Step
17 5
25
Rack 0 I/O Group 2
SQL instruction loads data from the input word into a destination
16661a
file from where it can be moved to other sequencer files.
1785-6.1 November 1998

File (#N7:20) The location of the destination file
Source (I:002) The input image address to be read
Control (R6:22) The structure that controls the operation
Length (5) The number of words to step through
Position (3) The current step
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1785-6.1 November 1998

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1785-6.1 November 1998

Chapter 13
Program Control Instructions MCR, JMP,
LBL, FOR, NXT, BRK, JSR, SBR, RET, TND,
AFI, ONS, OSR, OSF, SFR, EOT, UIE, UID
Selecting Program Flow 3URJUDPIORZLQVWUXFWLRQVFKDQJHWKHIORZRIODGGHUSURJUDP
Instructions H[HFXWLRQ8VH7DEOH$WRVHOHFWWKHSURJUDPFRQWUROLQVWUXFWLRQRU
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Table 13.A
Available Program Control Instructions
Then Use these Found on

If You Want to:
Instructions: Page:
Turn off all non-retentive outputs in a section MCR 13-2

of ladder program
Jump over a section of a program that does JMP, LBL 13-3

not always need to be executed
Loop through a set of rungs for a preset FOR, NXT, BRK 13-5
number of times
Jump to a separate subroutine file, pass data JSR, SBR, RET 13-8
to the subroutine, perform an operation, and
return the results
Mark a temporary end that halts program TND 13-13

execution beyond it
Disable a rung AFI 13-13
Trigger a one-shot event based on a change in ONS, OSR,* OSF* 13-14 (ONS),
rung condition 13-15 (OSR),
13-16 (OSF)
Reset a sequential function chart SFR* 13-17
End a transition file EOT 13-18
Enable or disable user interrupts UIE,* UID* 13-19 (UID),

13-20 (UIE)
*These instructions are only supported by Enhanced PLC-5 processors.
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1785-6.1 November 1998

13-2 Program Control Instructions MCR, JMP, LBL, FOR, NXT, BRK, JSR, SBR, RET, TND, AFI, ONS, OSR, OSF, SFR, EOT, UIE, UID
Master Control Reset (MCR)
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If the MCR Rung

that Starts the Then the Processor:
Zone Is:
True Executes the rungs in the MCR zone based on each rung’s
individual input conditions (as if the zone did not exist).
False Resets all non-retentive output instructions in the MCR zone

regardless of each rung’s individual input conditions.
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1785-6.1 November 1998

Program Control Instructions MCR, JMP, LBL, FOR, NXT, BRK, JSR, SBR, RET, TND, AFI, ONS, OSR, OSF, SFR, EOT, UIE, UID 13-3
Example: :KHQWKHUXQJFRQWDLQLQJWKHILUVW0&5LQVWUXFWLRQLVWUXHWKH
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I:012 I:012 I:012

MCR Beginning of zone
01 02 03
I:012 O:013
04 01 When the first MCR

instruction is true, the
I:012 I:012 O:013 processor executes
the rungs in the zone.
11 12 02
I:012
When the first MCR
instruction is false, the
03 processor resets all
non-retentive outputs
I:012 I:012 O:013 in the zone.
13 10 03
MCR End of zone
Jump (JMP) and Label (LBL)
Description: 8VH-03DQG/%/LQVWUXFWLRQVLQSDLUVWRVNLSSRUWLRQVRIWKHODGGHU
SURJUDP
JMP
If the Jump Rung Is: Then the Processor:
] LBL [
True Skips from the JMP rung to the LBL rung and continues
executing the program. You can jump forward or backward.
False Ignores the JMP instruction
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1785-6.1 November 1998

Using JMP
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Using LBL
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Valid Amount Per

If You Have this Processor: Valid LBL Numbers:
Program File:
Enhanced PLC-5 000-255 256
Classic PLC-5 0-31 32
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$VVHPEOHWKHILUVWHGLWWKHQPRGLI\WKHUXQJDJDLQWRPDNHWKH
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1785-6.1 November 1998

JMP and LBL Example: :KHQWKHUXQJFRQWDLQLQJWKH-03LQVWUXFWLRQJRHVWUXHWKH

SURFHVVRUMXPSVRYHUVXFFHVVLYHUXQJVXQWLOLWUHDFKHVWKHUXQJWKDW
FRQWDLQVWKH/%/LQVWUXFWLRQZLWKWKHVDPHQXPEHU7KHSURFHVVRU
UHVXPHVH[HFXWLQJDWWKH/%/UXQJ
I:012 I:012 O:013
10 11 01
I:012 20
JMP
13 When input I:012/13 is set, the processor jumps to
label 20 and continues program execution. It does not
execute the rungs between these two points.
T4:0 TON
TIMER ON DELAY EN
DN Timer T4:0
Time base 1.0 DN
Preset 100
Accum 0
I:012 O:013
10 13
20 I:012 O:013
LBL
17 02
7KHWLPHU721ZLOOQRWXSGDWHDVORQJDV,LVWUXH
For Next Loop (FOR, NXT),

Break (BRK)
Description: 8VH)25%5.DQG1;7LQVWUXFWLRQVWRFUHDWH\RXURZQ
FOR SURJUDPPLQJURXWLQHVZKHUH\RXFRQWUROWKHQXPEHURIWLPHVWKH
FOR ORRSLVH[HFXWHG
Label number
Index ,PSRUWDQW 'XULQJSUHVFDQODGGHULQVWUXFWLRQVZLWKLQWKH
Initial value
Terminal value )251;7ORRSDUHSUHVFDQQHGQRWVNLSSHG
Step size
NXT
NEXT $77(17,21 8VLQJ)25DQG1;7LQVWUXFWLRQV
Label Number
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PDFKLQHRSHUDWLRQ
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EUDQFKLQDODGGHUSURJUDPWKHH[HFXWLRQRIWKH
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1785-6.1 November 1998

Entering Parameters
7RSURJUDPWKH)25LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK
Label number the unique label number that marks the location of the FOR instruction. Enter a unique
number. Classic PLC-5 processors support label numbers 0-31; Enhanced PLC-5
processors support label numbers 0-255.
Index the logical address where the instruction stores the index value it computes. The index
value is the sum of the initial value plus the accumulating step values. The FOR
instruction uses the index value to determine the number of times the loop is executed.
When you enable the FOR instruction, the processor sets the index value equal to the
initial value. Then, if the index values is less than or equal to the terminal value, the
processor loops through the following instructions. If the index is greater than the
terminal value, the processor jumps to the NXT instruction.
When the processor encounters a NXT instruction, it returns to the corresponding FOR
instruction, then it compares the index with the terminal value. If the index is less than
or equal to the terminal value, the processor jumps back to the FOR instruction.
Otherwise it steps to the following instruction. If the processor encounters a BRK on a
true rung, the processor skips to the instruction following the NXT.
Initial value (index value) is an integer value or integer address that represents the starting value for
the loop.
Terminal value (reference value) is an integer value or integer address that represents the ending value
for the loop.
Step size (constant) is an integer value that specifies the amount to increment the index value.
You can change the step value from the ladder program.
Using FOR
:KHQWKHUXQJLVWUXHWKH)25LQVWUXFWLRQH[HFXWHVWKHUXQJV
EHWZHHQWKH)25DQG1;7UHSHDWHGO\LQRQHSURJUDPVFDQXQWLOLW
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RSHUDWLRQ7KH)25LQVWUXFWLRQUHSHDWVWKLVRSHUDWLRQHDFKVFDQLWV
UXQJLVWUXH7KH)25LQVWUXFWLRQGRHVQRWUHTXLUHDUXQJWUDQVLWLRQWR
EHJLQRSHUDWLRQ
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SURJUDPVFDQ$QH[FHVVLYHQXPEHURIFDOOVFDXVHVWKH
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SURJUDPEHIRUHH[HFXWLQJWKH)25LQVWUXFWLRQ<RXVKRXOGQRW
FKDQJHWKHLQGH[YDOXH
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WKHLQVWUXFWLRQWRH[HFXWHWKHORRSDQXQH[SHFWHGQXPEHU
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LQMXU\WRSHUVRQQHO
1785-6.1 November 1998

$OVRLI\RXHGLWD)251;7LQVWUXFWLRQLQ5HPRWH581PRGH
PDNHVXUHWKDW\RXPDNHWKHFRUUHVSRQGLQJFKDQJHVWRERWKUXQJV
EHIRUHDVVHPEOLQJHGLWV)RUH[DPSOHLI\RXZDQWWRFKDQJHWKHODEHO
QXPEHUIRUWKH)251;7SDLUFKDQJHWKHODEHOLQWKH)25
LQVWUXFWLRQDQGLQWKH1;7LQVWUXFWLRQWKHQDVVHPEOHWKHHGLWV,I
\RXDVVHPEOHHGLWVDIWHUFKDQJLQJRQO\RQHRIWKHLQVWUXFWLRQVLQ
WKH)251;7SDLUWKHSURFHVVRUFDXVHVDUXQWLPHHUURURU
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Using BRK
7KH%5.LQVWUXFWLRQVWRSVWKH)25LQVWUXFWLRQ¶VRSHUDWLRQ3ODFHWKH
%5.UXQJDQ\ZKHUHEHWZHHQWKH)25DQG1;7UXQJV:KHQWKH
UXQJJRHVWUXHLWUHWXUQVWKHSURFHVVRUWRWKHQH[WKLJKHVWORRSLI\RX
DUHXVLQJQHVWHGORRSVRUWRWKHIROORZLQJLQVWUXFWLRQDIWHUWKH
FRUUHVSRQGLQJ1;7LQVWUXFWLRQLQWKHPDLQSURJUDP
8VH%5.WRH[LWWKHORRSZKHQHYHUWKHSURFHVVRUGHWHFWVDQHUURURU
WRDYRLGSURORQJHGORRSVWKDWFRXOGFDXVHWKHZDWFKGRJWLPHUWRWLPH
RXWZKLFKZRXOGIDXOWWKHSURFHVVRU
Using NXT
7KH1;7LQVWUXFWLRQPXVWEHSURJUDPPHGRQDQXQFRQGLWLRQDOUXQJ
WKDWLVWKHODVWUXQJWREHUHSHDWHGE\WKH)RU1H[WORRS7KH1;7
LQVWUXFWLRQUHWXUQVWKHSURFHVVRUWRWKHFRUUHVSRQGLQJ)25
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1;7 LQVWUXFWLRQ
FOR, BRK, and NXT Example:
If integer file 7, word 10, bit 5 is false,

N7:10 skip to the rung following the NXT instruction. FOR
FOR
5 If integer file 7, word 10, bit 5 is true, initialize N7:0 to
zero and execute the rungs until the NXT. When the Label number 0
processor encounters the NXT, increment N7:0 and Index N7:0
rung jump back to the FOR instruction. As long as N7:0 Initial value 0
rung is less than or equal to 10, keep executing the loop. Terminal value 10
rung When N7:0 is greater than 10, jump to the rung Step size 1
following the NXT.
N7:10
/ BRK
5 If integer file 7, word 10, bit 5 ever goes true,
rung break out of the loop and jump to the rung
rung following the NXT instruction.
rung NXT
NEXT
Label Number 0
rung
rung
rung
1785-6.1 November 1998

Jump to Subroutine (JSR),

Subroutine (SBR), and
Return (RET)
Description: 7KH-656%5DQG5(7LQVWUXFWLRQVGLUHFWWKHSURFHVVRUWRJRWRD
JSR VHSDUDWHVXEURXWLQHILOHZLWKLQWKHODGGHUSURJUDPVFDQWKDW
JUMP TO SUBROUTINE VXEURXWLQHILOHRQFHDQGUHWXUQWRWKHSRLQWRIGHSDUWXUH
Prog file number
Input parameter
Return parameter 7KH-65LQVWUXFWLRQGLUHFWVWKHSURFHVVRUWRWKHVSHFLILHGVXEURXWLQH
SBR
ILOHDQGLIUHTXLUHGGHILQHVWKHSDUDPHWHUVSDVVHGWRDQGUHFHLYHG
SUBROUTINE IURPWKHVXEURXWLQH7KHRSWLRQDO6%5LQVWUXFWLRQLVWKHKHDGHU
Input parameter
LQVWUXFWLRQWKDWVWRUHVLQFRPLQJSDUDPHWHUV8VH6%5RQO\LI\RX
RET ZDQWWRSDVVSDUDPHWHUV7KH5(7LQVWUXFWLRQHQGVWKHVXEURXWLQH
RETURN ( )
Return parameter
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LQWKHPDLQSURJUDP
,PSRUWDQW ,I\RXXVHWKH6%5LQVWUXFWLRQWKH6%5LQVWUXFWLRQ
PXVWEHWKHILUVWLQVWUXFWLRQRQWKHILUVWUXQJLQWKH
SURJUDPILOHWKDWFRQWDLQVWKHVXEURXWLQH
8VHDVXEURXWLQHWRVWRUHUHFXUULQJVHFWLRQVRISURJUDPORJLFWKDWFDQ
EHDFFHVVHGIURPPXOWLSOHSURJUDPILOHV$VXEURXWLQHVDYHVPHPRU\
EHFDXVH\RXSURJUDPLWRQO\RQFH
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QRWXSGDWH,2XQWLOLWUHDFKHVWKHHQGRIWKHPDLQSURJUDPDIWHU
H[HFXWLQJDOOVXEURXWLQHV2XWSXWVLQVXEURXWLQHVDUHOHIWLQWKHLU
ODVWVWDWH
Passing Parameters
3DVVVHOHFWHGYDOXHVWRDVXEURXWLQHEHIRUHH[HFXWLRQVRWKH
VXEURXWLQHFDQSHUIRUPPDWKHPDWLFDORUORJLFDORSHUDWLRQVRQWKH
GDWDDQGUHWXUQWKHUHVXOWVWRWKHPDLQSURJUDP
)RUH[DPSOH\RXFDQZULWHDJHQHULFVXEURXWLQHIRUPXOWLSOHUHFLSH
RSHUDWLRQV7KHQSDVVSUHVHWYDOXHVIRUHDFKUHFLSHWRWKHVXEURXWLQH
LQDGYDQFHRUKDYHWKHPDLQSURJUDPVSHFLI\DQGSDVVSUHVHWV
DFFRUGLQJWRDSSOLFDWLRQUHTXLUHPHQWV
1785-6.1 November 1998

<RXFDQSDVVWKHIROORZLQJW\SHVRISDUDPHWHUV
Type: Example:
Program constant (integer) 256
Program constant (floating point) 23.467
Logical element address N7:0
Logical structure address C5:0.ACC
,I\RXSDVVIORDWLQJSRLQWGDWDWRDQLQWHJHUDGGUHVVWKHIUDFWLRQDOSDUW
RIWKHYDOXHLVWUXQFDWHGORVW
,PSRUWDQW 'RQRWPL[IORDWLQJSRLQWDQGLQWHJHUGDWDDQGDGGUHVVHV
ZKHQSDVVLQJGDWDRU\RXZLOOORVHDFFXUDF\
Example of Passing Parameters: 7KHIROORZLQJGLDJUDPVKRZVWKHSDVVLQJRISDUDPHWHUVEHWZHHQD

PDLQSURJUDPILOHDQGDVXEURXWLQHILOH
Main Ladder Program
JSR
JUMP TO SUBROUTINE
Prog file number 90 Program constants and values
Input parameter N16:23 stored at logical addresses are
Input parameter N16:24 passed to the SBR instruction
Values are Input parameter 231 when execution jumps to the
returned Return parameter N19:11 subroutine file.
Return parameter N19:12
Execution resumes
Subroutine File 090
SBR
SUBROUTINE
Values and program constants Input parameter N43:0
are stored at logical addresses
Input parameter N43:1
in the subroutine as subroutine
execution begins. Input parameter N10:3
RET
Values stored at logical RETURN ( )
addresses are returned to the
addresses that you specified in Return parameter N43:5
the JSR instruction when Return parameter N43:4
execution returns to the main
ladder program.
1785-6.1 November 1998

Entering Parameters
7RSURJUDPWKHVHLQVWUXFWLRQVSURYLGHWKHSURFHVVRUZLWKWKH
IROORZLQJLQIRUPDWLRQ
Program file number the program file number of the file that contains
the subroutine
Input parameter (JSR) a program constant or an address of a parameter to

be sent to the subroutine (optional)
Input parameter (SBR) an address where the subroutine stores the incoming
data (optional)
Return parameter (JSR) an address that stores the data received from the
subroutine (optional)
Return parameter (RET) a program constant or an address of a parameter

to be returned to the JSR instruction in the main
program (optional)
:KHQHQWHULQJLQSXWDQGUHWXUQSDUDPHWHUV
:KHQ\RXHQWHUWKH-65LQVWUXFWLRQWKHSURJUDPPLQJVRIWZDUH
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SDUDPHWHUSUHVV[Enter]7KHVRIWZDUHSURPSWV\RXIRUDQRWKHU
LQSXWSDUDPHWHU:KHQ\RXGRQRWKDYHDQ\PRUHLQSXW
SDUDPHWHUVWRHQWHUSUHVV[Enter] DJDLQ7KHQWKHSURJUDPPLQJ
VRIWZDUHSURPSWV\RXIRUUHWXUQSDUDPHWHUVLQWKHVDPHPDQQHU
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HLJKWLQSXWDQGUHWXUQSDUDPHWHUVFRPELQHG
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HTXDOWRWKHQXPEHURILQSXWSDUDPHWHUDGGUHVVHVLQWKH6%5
LQVWUXFWLRQ)HZHULQSXWVWKDQDGGUHVVHVWRUHFHLYHWKHPFDXVHVD
UXQWLPHHUURU
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RXWSXWVWKDQDGGUHVVHVWRUHFHLYHWKHPFDXVHVDUXQWLPHHUURU
Nesting Subroutine Files

<RXFDQQHVWXSWRHLJKWVXEURXWLQHVZLWKLQDSURJUDPILOH7KLV
PHDQV\RXFDQGLUHFWSURJUDPIORZIURPWKHPDLQSURJUDPWRD
VXEURXWLQHDQGRQWRDQRWKHUVXEURXWLQHDVORQJWKHUHDUHQRPRUH
WKDQOHYHOVRIVXEURXWLQHV
1785-6.1 November 1998

7KHSDWKEDFNLVWKHUHYHUVH$W5(7WKHSURFHVVRUDXWRPDWLFDOO\
UHWXUQVWRWKHQH[WLQVWUXFWLRQDIWHUWKHSUHYLRXV-65LQVWUXFWLRQ7KH
SURFHVVRUIROORZVWKLVSURFHGXUHXQWLOLWUHWXUQVWRWKHPDLQSURJUDP
Level 1 Level 2 Level 3

Subroutine File 90 Subroutine File 91 Subroutine File 92
Main Program SBR SBR SBR

90
JS R
91 92
JS R JS R
RET RET RET
15294
Using JSR
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ILOHDQGLIUHTXLUHGGHILQHVWKHSDUDPHWHUVSDVVHGWRDQGUHFHLYHG
IURPWKHVXEURXWLQH
:KHQSURJUDPPLQJWKH-65NHHSWKHIROORZLQJLQPLQG
(DFKVXEURXWLQHWKDWLVH[WHUQDOWRWKHPDLQSURJUDPILOHPXVW
KDYHLWVRZQILOHLGHQWLILHGE\DXQLTXHILOHGHVFULSWRU
<RXFDQQRWMXPSLQWRDQ\SDUWRIWKHVXEURXWLQHILOHH[FHSWIRU
WKHILUVW6%5LQVWUXFWLRQLQWKDWILOH
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Using SBR
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LQFRPLQJSDUDPHWHUV8VH6%5RQO\LI\RXZDQWWRSDVVSDUDPHWHUV
:KHQ\RXSDVVSDUDPHWHUVWKH6%5LQVWUXFWLRQPXVWEHWKHILUVW
LQVWUXFWLRQLQWKHILUVWUXQJRIWKHVXEURXWLQH7KLVUXQJPXVWDOVR
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1785-6.1 November 1998

Using RET
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SDUDPHWHUVWREHUHWXUQHGWRWKH-65LQVWUXFWLRQLQWKHPDLQSURJUDP
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JSR, SBR, and RET Example: :KHQWKHUXQJWKDWFRQWDLQVWKH-65LQVWUXFWLRQJRHVWUXHWKH

SURFHVVRUMXPSVWRWKHVXEURXWLQHILOHVSHFLILHGE\WKH-65
LQVWUXFWLRQ7KHSURFHVVRUDOVRSDVVHVWKUHHYDOXHVWRWKHVXEURXWLQH
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7KHQWKHSURFHVVRUUXQVWKHVXEURXWLQHORJLF
:KHQWKHSURFHVVRUUXQVWKH5(7LQVWUXFWLRQLQWKHVXEURXWLQHWKH
SURFHVVRUUHWXUQVWRWKHLQVWUXFWLRQIROORZLQJWKHSUHYLRXV-65
LQVWUXFWLRQLQWKHPDLQSURJUDP7KHVXEURXWLQHUHWXUQVWZRYDOXHVWR
WKHPDLQSURJUDPWKHYDOXHVWRUHGDW1LVWUDQVIHUUHGWR1
WKHYDOXHVWRUHGDW1LVWUDQVIHUUHGWR1
JSR
JUMP TO SUBROUTINE
Prog file number 90
Input par N16:23
Input par N16:24
Balance of Main Program Input par 231
Return par N19:11
Subroutine Return par N19:12
SBR
SUBROUTINE
Input par N43:0
Input par N43:1
Input par N43:2
(Enter your own logic operation)

RET
RETURN ( )
Return par N43:3
Return par N43:4
1785-6.1 November 1998

Temporary End (TND)
Description: :KHQWKHSURFHVVRUHQFRXQWHUVWKH71'LQVWUXFWLRQWKHSURFHVVRU
UHVHWVWKHZDWFKGRJWLPHUWR]HURSHUIRUPVDQ,2XSGDWHDQG
TND EHJLQVUXQQLQJWKHODGGHUSURJUDPDWWKHILUVWLQVWUXFWLRQLQWKH
PDLQSURJUDP
Example:
I:012 I:012
,QVHUWWKH71'LQVWUXFWLRQZKHQGHEXJJLQJRUWURXEOHVKRRWLQJ\RXU
TND
ODGGHUSURJUDP7KH71'LQVWUXFWLRQOHWV\RXUSURJUDPUXQRQO\XS
04 05
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Always False (AFI)
Description: 7KH$),LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWPDNHVWKHUXQJIDOVH
ZKHQLQVHUWHGLQWKHFRQGLWLRQVLGHRIWKHUXQJ<RXFDQXVHWKH$),
Example:
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AFI
1785-6.1 November 1998

One Shot (ONS)
Description: 7KH216LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWPDNHVWKHUXQJWUXH
IRURQHSURJUDPVFDQXSRQDIDOVHWRWUXHWUDQVLWLRQVRIWKHFRQGLWLRQV
[ ONS ] SUHFHGLQJWKH216LQVWUXFWLRQRQWKHUXQJ
8VHWKH216LQVWUXFWLRQWRVWDUWHYHQWVWKDWDUHWULJJHUHGE\D
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IUHH]LQJUDSLGO\GLVSOD\HG/('YDOXHV<RXPXVWHQWHUDELWDGGUHVV
IRUWKHELW8VHHLWKHUDELQDU\ILOHRULQWHJHUILOHDGGUHVV$XQLTXHELW
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IRUWKH216EXWEHDZDUHRIWKHIROORZLQJ
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LQVWUXFWLRQFDQEHGDQJHURXVEHFDXVHWKHRXWSXWPD\
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HQHUJL]LQJLWVRXWSXW
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WULJJHULQJZKHQWKHSURJUDPVFDQEHJLQV
Example:
I:011 N7:10 B3
ONS
04 10 5
When the input condition goes from false to true, the ONS conditions the rung so that
the output turns on for one scan. The output turns off for successive scans until the
input goes from false to true again.
1785-6.1 November 1998

One Shot Rising (OSR)

Description: 7KH265LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWWULJJHUVDQHYHQWWR
OSR
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ONE SHOT RISING OB
Storage BIt This Bit: Changes State as Follows:
Output Bit SB
Output Word
Output .OB Is set for one program scan when the rung goes from false to true
Note: During prescan, this bit is cleared to inhibit false triggering
Storage .SB Follows the rung status

Note: During prescan, this bit is cleared to inhibit false triggering
8VHWKH265LQVWUXFWLRQZKHQHYHUDQHYHQWPXVWVWDUWEDVHGRQWKH
FKDQJHRIVWDWHRIWKHUXQJIURPIDOVHWRWUXHQRWFRQWLQXRXVO\ZKHQ
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Entering Parameters
7RSURJUDPWKHVHLQVWUXFWLRQV\RXPXVWSURYLGHWKHSURFHVVRUZLWK
Storage bit the address where you want the storage bit status stored. For
example, B3/17
Output bit the bit position in the output word where you want the output
bit status stored. For example 5
Output word the word address where you want the output bit status
stored. For example, N7:0
1785-6.1 November 1998

One Shot Falling (OSF)

Description: 7KH26)LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWWULJJHUVDQHYHQWWR
OSF
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ONE SHOT FALLING OB LQVWUXFWLRQVHWVWKHIROORZLQJELWV
Storage BIt
Output Bit SB
Output Word This Bit: Changes State as Follows:
Output .OB Is set for one program scan when the rung goes from true to false
Storage .SB Follows the rung status
8VHWKH26)LQVWUXFWLRQZKHQHYHUDQHYHQWPXVWVWDUWEDVHGRQWKH
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8VHHLWKHUDELQDU\ILOHRULQWHJHUILOHDGGUHVV
Entering Parameters
7RSURJUDPWKHVHLQVWUXFWLRQV\RXPXVWSURYLGHWKHSURFHVVRUZLWK
Storage bit the address where you want the storage bit status stored. For
example, B3/17
Output bit the bit position of the output word where you want the output
bit status stored. For example 5
Output word the word address where you want the output bit status
stored. For example, N7:0
1785-6.1 November 1998

Sequential Function Chart Reset

(SFR)
Description: 7KH6)5LQVWUXFWLRQUHVHWVWKHORJLFLQDVHTXHQWLDOIXQFWLRQFKDUW
:KHQDQ6)5LQVWUXFWLRQJRHVWUXHWKHSURFHVVRUSHUIRUPVD
SFR
SRVWVFDQODVWVFDQRQDOODFWLYHVWHSVDQGDFWLRQVLQWKHVHOHFWHG
SFC Reset
ILOHDQGWKHQUHVHWVWKHORJLFLQWKH6)&RQWKHQH[WSURJUDPVFDQ
Prog file number
7KHFKDUWUHPDLQVLQWKLVUHVHWVWDWHXQWLOWKH6)5LQVWUXFWLRQJRHV
Restart step at
IDOVH7KH6)5LQVWUXFWLRQDOVRUHVHWVDOOUHWHQWLYHDFWLRQVWKDWDUH
FXUUHQWO\DFWLYH
Entering Parameters
Example: 7RSURJUDPWKLVLQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWKWKH
SFR
SFC Reset
Prog file number 2 Parameter: Definition:
Restart step at N7:5
Program File Number a valid SFC program file number
Restart Step at enter one of the following:

• a valid step reference number, 0 to 32767 (entering a 0
defaults to restarting at the initial step)
• a valid step name
• an integer address (that stores a step reference number)
• an address symbol (of an integer address that stores a step
reference number)
,PSRUWDQW 7KH5HVWDUW6WHSDWSDUDPHWHULVRQO\DYDLODEOHZLWK
3/&VHULHV$DQG3/&/
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SURFHVVRUV,I\RXDUHXVLQJD3/&RU
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QXPEHUV)RULQIRUPDWLRQRQFRQILJXULQJ\RXUGLVSOD\VHH\RXU
SURJUDPPLQJPDQXDO
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,PSRUWDQW 0DNHVXUHWKDWWKHVWHSLVDFWXDOO\DVWHSDQGQRWD
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1785-6.1 November 1998

,PSRUWDQW 8VHRQO\RQH6)5LQVWUXFWLRQWRDVLQJOHFKDUW0XOWLSOH
6)5¶VLQWKHVDPHFKDUWFDQSURGXFHXQGHVLUHGUHVXOWV
VLQFHWUXHDQGIDOVHVFDQVRIWKH6)5FDXVHGLIIHUHQW
SURJUDPEHKDYLRU
$QDQDORJ\ZRXOGEHXVLQJPXOWLSOH721WLPHULQVWUXFWLRQVXVLQJWKH
VDPHFRQWUROILOH,I\RXZDQWWRUHVHWDFKDUWWRGLIIHUHQWSRVLWLRQVLQ
WKHFKDUWEDVHGRQGLIIHUHQWFRQGLWLRQVWKHQORDGWKHµVWHSWRUHVHWWR¶
LQWRDQLQWHJHUGDWDWDEOHORFDWLRQEDVHGRIWKHFRQGLWLRQDQGWKHQ
WULJJHUWKH6)5
End of Transition (EOT)
Description: 7KH(27LQVWUXFWLRQVKRXOGEHODVWLQVWUXFWLRQLQDWUDQVLWLRQILOH,I
\RXGRQRWSODFHDQ(27LQVWUXFWLRQLQDWUDQVLWLRQILOHWKHSURFHVVRU
Example: DOZD\VHYDOXDWHVWKHWUDQVLWLRQILOHDVWUXH
[ EOT ]
,PSRUWDQW 'XULQJSUHVFDQWKH(27LQVWUXFWLRQLVVNLSSHGVRWKDW
DOOODGGHULQVWUXFWLRQVFDQEHSUHVFDQQHG
1785-6.1 November 1998

User Interrupt Disable (UID)

Description: 7KH8,'LQVWUXFWLRQLVXVHGWRWHPSRUDULO\GLVDEOHLQWHUUXSW
SURJUDPVVXFKDV6HOHFWDEOH7LPHG,QWHUUXSWV67,RU3URFHVVRU
UID ,QSXW,QWHUUXSWV3,,
:KHQWKHUXQJLVWUXHWKH8,'LQVWUXFWLRQLQFUHPHQWVDQ
LQWHUQDOLQWHUUXSWGLVDEOHFRXQWHU$VORQJDVWKLVFRXQWHUYDOXH
GRHVQRWHTXDO]HURWKHFXUUHQWO\H[HFXWLQJSURJUDPFDQQRWEH
LQWHUUXSWHGE\DQ67,RUD3,,$OVRLI\RXKDYHDVXEURXWLQHFDOO
ZLWKLQD8,(8,'SDLUWKDWVXEURXWLQHUXQVZLWKRXWLQWHUUXSWLRQ
7KH8,'LQVWUXFWLRQGRHVQRWGLVDEOHWKHXVHUIDXOWURXWLQH
,PSRUWDQW 6LQFHWKH8,'LQVWUXFWLRQPDNHVDSURJUDP
XQLQWHUUXSWLEOHWKHSURFHVVRU¶VUHVSRQVHWLPHWRDQ67,
RU3,,HYHQWPD\EHDIIHFWHG7KH8,'8,(VHFWLRQRI
\RXUSURJUDPVKRXOGEHDVVKRUWDVSRVVLEOH/HDYLQJ
67,VDQG3,,VGLVDEOHGIRUH[WHQGHGSHULRGVRIWLPH
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,PSRUWDQW ,I\RXKDYHDQ\EORFNWUDQVIHULQDQ67,RU3,,DQGWKDW
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\RXUSURJUDPWKHPDLQSURJUDPVFDQVWRSVXQWLOWKH
EORFNWUDQVIHUFRPSOHWHV
1785-6.1 November 1998

User Interrupt Enable (UIE)

Description: 7KH8,(LQVWUXFWLRQUHHQDEOHV67,RU3,,LQWHUUXSWSURJUDPV
UIE :KHQWKHUXQJLVWUXHDQGWKHLQWHUQDOLQWHUUXSWGLVDEOHFRXQWHULV
JUHDWHUWKDQ]HURWKHLQWHUUXSWGLVDEOHFRXQWHULVGHFUHPHQWHG
:KHQWKHFRXQWHUHTXDOV]HURWKHSURJUDPFXUUHQWO\H[HFXWLQJLV
WKHQDEOHWREHLQWHUUXSWHGDJDLQ,IWKHUHDUHDQ\LQWHUUXSWSURJUDPV
SHQGLQJWKH\DUHH[HFXWHGDWWKLVWLPH
Example:
I:012 I:012 I:012 O:013

Program can be interrupted
01 02 03 02
UID
I:012 I:012 O:013
01 04 02 Program cannot
be interrupted
I:012
03
I:012 I:012 O:013
04 02 03
UIE Program can be interrupted
1785-6.1 November 1998

Chapter 14
Process Control Instruction PID
Using PID 3,'FORVHGORRSFRQWUROKROGVDSURFHVVYDULDEOHDWDGHVLUHGVHW
SRLQW)LJXUHVKRZVDIORZUDWHIOXLGOHYHOH[DPSOH
Figure 14.1
PID Control Example
FFWD
or
Bias
Set Point Error
R PID Equation R
Flow Control
Rate Process
Variable Output
Level
Detector
14271
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VHQGLQJDQRXWSXWVLJQDOWRWKHFRQWUROYDOYH7KHJUHDWHUWKHHUURU
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VLJQDODQGYLFHYHUVD$QDGGLWLRQDOYDOXHIHHGIRUZDUGRUELDV
FDQEHDGGHGWRWKHFRQWURORXWSXWDVDQRIIVHW7KHJRDORI3,'
FDOFXODWLRQVLVWRPDLQWDLQWKHSURFHVVYDULDEOH\RXDUHFRQWUROOLQJDW
WKHVHWSRLQW
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HDFKRSHUDQGXVHGE\WKH3,'LQVWUXFWLRQVHH$SSHQGL[&
1785-6.1 November 1998

14-2 Process Control Instruction PID
PID Features
7KH3,'LQVWUXFWLRQOHWVWKHSURFHVVPRQLWRUDQGFRQWUROSURFHVV
ORRSVIRUVXFKTXDQWLWLHVDVSUHVVXUHWHPSHUDWXUHIORZUDWHDQGIOXLG
OHYHO)HDWXUHVRIWKH3,'LQVWUXFWLRQLQFOXGH
3,'HTXDWLRQVH[SUHVVHGLQ,6$RU,QGHSHQGHQW*DLQV
LQSXWDQGRXWSXWUDQJHIURPELWDQDORJ
LQSXWVFDOLQJLQHQJLQHHULQJXQLWV
]HURFURVVLQJGHDGEDQG
GHULYDWLYHWHUPFDQDFWRQ39RUHUURU
GLUHFWRUUHYHUVHDFWLQJFRQWURO
RXWSXWDODUPV
RXWSXWOLPLWLQJZLWKDQWLUHVHWZLQGXS
PDQXDOPRGHZLWKEXPSOHVVWUDQVIHU
IHHGIRUZDUGRURXWSXWELDVLQJ
GLVSOD\LQJDQGPRQLWRULQJ3,'YDOXHV
Using PID Equations 7KH3,'LQVWUXFWLRQKDVWZRVSHFLILFIRUPDWVLQWHJHUFRQWUROEORFN

W\SHDQG3'FRQWUROEORFNW\SH%RWKIRUPDWVXVHWKHVDPH
FRPSXWDWLRQDOPHFKDQLFVIRUWKHEDVHHTXDWLRQEXWGLIIHULQ
RSWLRQVDQGW\SHRIPDWKSHUIRUPHGVSHFLILFDOO\LQWHJHUDQG
IORDWLQJSRLQWPDWK
7KHEDVH3,'HTXDWLRQXVHGLQERWKFDVHVLVWKHVWDQGDUGSDUDOOHO
SRVLWLRQ3,'$OJRULWKPZLWKRSWLRQIRUHQWHULQJJDLQVDV
µLQGHSHQGHQW¶RUµGHSHQGHQW¶7KHODWWHURSWLRQLVUHFRJQL]HGDV
,6$VWDQGDUGIRUPDW
7KHSURFHVVRUJLYHV\RXVL[FKRLFHVRI3,'DOJRULWKPVDVIROORZV
6WDQGDUGHTXDWLRQZLWKGHSHQGHQWJDLQV,6$VWDQGDUG
'HULYDWLYHRI(UURU
1 t d(E)
CV = K c ( E ) + ∫ ( E ) dt + T d + Bias
Ti 0 dt
'HULYDWLYHRI39
1 t d(PV)
CV = K c ( E ) + ∫ ( E ) dt + T d + Bias ( E = SP – PV )
Ti 0 dt
1 t d(PV)
CV = K c ( E ) + ∫ ( E ) dt + T d + Bias ( E = PV – SP )
Ti 0 dt
1785-6.1 November 1998

Process Control Instruction PID 14-3
,QGHSHQGHQWJDLQVHTXDWLRQ
'HULYDWLYHRI(UURU
d(E)
CV = K P ( E ) + K i ∫ ( E ) dt + K d + Bias
t
0 dt
'HULYDWLYHRI39
d(PV)
CV = K P ( E ) + K i ∫ ( E ) dt – K d + Bias ( E = SP – PV )
t
0 dt
d(PV)
CV = K P ( E ) + K i ∫ ( E ) dt + K d + Bias ( E = PV – SP )
t
0 dt
:KHUH
Kp = Proportional Gain (Unitless) SP = Set Point
Ki = Integral Gain (Seconds–1) PV = Process Variable
Kd = Derivative Gain (Seconds) Error = (SP – PV) or (PV – SP)
1 Bias = Feed-Forward or External Bias

= Reset Gain (Repeats/Minute)
T1 CV = Output Control Variable
Td = Rate Gain (Repeats/Minute) ∆t = Loop Update Time
Conversion of Gain Constants

&RQYHUWIURPVWDQGDUGWRLQGHSHQGHQWJDLQVFRQVWDQWVE\VXEVWLWXWLQJ
FRQWUROOHUJDLQ.FUHVHW7LDQGUDWH7GYDOXHVLQWKH
IROORZLQJ IRUPXODV
Kp = Kc unitless
Kc
Ki = inverse seconds
60Ti
Kd = Kc(Td)60 seconds
Integral Term Implementation

3HUIRUPLQWHJUDWLRQE\PDLQWDLQLQJDQDFFXPXODWHGVXP6N
,QWKHFDVHRI,QGHSHQGHQW*DLQV6N .L(N∆W6N ±
1
:LWK'HSHQGHQW*DLQVVHOHFWHG S k = ( E k )∆ t + S k – 1
Ti
1785-6.1 November 1998

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VHWVWR]HURLQ$XWRPRGH
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DFFXPXODWLQJZKHQHYHUWKHRXWSXW&9UHDFKHVLWVPD[LPXPRU
PLQLPXPYDOXHV7KHVHYDOXHVDUHHLWKHUDQGRUWKHXVHU
VSHFLILHGOLPLWVLQRXWSXWOLPLWLQJ,QWKLVFDVH6N 6N±
7KHDFFXPXODWHGVXPUHPDLQVµIUR]HQ¶XQWLOWKHRXWSXWGURSVEHORZ
LWVPD[LPXPYDOXHRUULVHVDERYHLWVPLQLPXPYDOXHWKHQQRUPDO
DFFXPXODWLRQUHVXPHV
:KHQH[HFXWLQJWKH3,'LQVWUXFWLRQLQPDQXDOPRGHDµEXPSOHVV¶
WUDQVIHUEDFNWR$XWRPRGHFDQEHDFKLHYHGE\XVLQJWKHDFFXPXODWHG
VXPWRFRPSXWDWLRQDOO\WUDFNWKHPDQXDORXWSXW
d(E
k = CVManual – Bias – K p ( E ) – K d
dt
:KHQ\RXVZLWFKEDFNWRDXWRPRGHWKH3,'FRPSXWDWLRQ\LHOGVWKLV
0DQXDO2XWSXWYDOXHDQGQRµMXPS¶LQRXWSXWRFFXUVDVDUHVXOWRIWKH
PRGHFKDQJH
Derivative Term
7KHIROORZLQJDSSUR[LPDWLRQLVXVHGWRFDOFXODWHWKHGHULYDWLYHWHUP
( Q ) Q k – Qk – 1
d
=
dt ∆t
Where Q represents either Error or PV,
depending upon your settings.
7KHFDOFXODWLRQLVIXUWKHUHQKDQFHGE\XVLQJDµGHULYDWLYHVPRRWKLQJ
ILOWHU¶7KLVILUVWRUGHUORZSDVVGLJLWDOILOWHUHOLPLQDWHVODUJH
GHULYDWLYHWHUPµVSLNHV¶FDXVHGE\QRLVHLQWKH39
$GGLQJWKLVILOWHUWRWKHRYHUDOOGHULYDWLYHWHUP\LHOGV
Qk – Qk – 1
D k = ( 1 – α ) K d + αD k – 1
∆t
Where:
Kd = the derivative gain
Dk = the current derivative term
Dk–1 = the previous derivative term
Qk = (as previously defined)
1
α =
∆t
16 + 1
Kd
∆t = Loop Update Time
1785-6.1 November 1998

Setting Input/Output Ranges 7KHLQSXWPRGXOHWKDWPHDVXUHVWKHSURFHVVRUYDULDEOH39PXVW

KDYHDIXOOVFDOHELQDU\UDQJHRI7KHSURFHVVRULJQRUHV
WKHXSSHUIRXUPRVWVLJQLILFDQWELWVRIWKHELWSURFHVVYDULDEOH
LQWHJHU3,'RQO\
7KHFRQWURORXWSXWKDVWKHVDPHUDQJHRI<RXFDQVHWOLPLWV
RQWKHRXWSXWWROLPLWWKHRXWSXWFDOFXODWHGE\WKH3,'LQVWUXFWLRQWR
DQ\YDOXHLQWKHUDQJHRI
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WRFDOFXODWHWKHLQWHJUDODFFXPXODWHGYDOXHZKLFKDOORZVIRU
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7KH3,'LQVWUXFWLRQDOVRFRSLHVWKHWLHEDFNYDOXHLQWRWKHFRQWURO
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XVHGZKHQ\RXXVHDKDUGZDUHDXWRPDQXDOVWDWLRQ2WKHUZLVHVHWWKH
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Implementing Scaling to <RXFDQVFDOHWKHVHWSRLQWDQG]HURFURVVLQJGHDGEDQGYDOXHVWR

Engineering Units – HQJLQHHULQJXQLWVIRULQWHJHUILOHW\SHV<RXFDQDOVRGLVSOD\WKH
SURFHVVYDULDEOHDQGHUURUYDOXHVLQWKHVHVDPHHQJLQHHULQJXQLWV
Integer File Type
:KHQ\RXVHOHFWVFDOLQJWKH3,'LQVWUXFWLRQVFDOHVWKHVHWSRLQWGHDG
EDQGSURFHVVYDULDEOHDQGHUURUYDOXHV<RXDOVRKDYH
(QWHUWKHPD[LPXPDQGPLQLPXPYDOXHV6 DQG6 LQWKH
PD[ PLQ
3,'FRQWUROEORFNZRUGVDQG7KH6 YDOXHFRUUHVSRQGVWR

PLQ
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YDULDEOHWKH6 YDOXHFRUUHVSRQGVWRDQDQDORJYDOXHRI
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UHSUHVHQWSURFHVVOLPLWV6HW6 DQG6 WRLI\RXGRQRW
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±39 WR39 HQWHU±IRU6 DQG PLQ
IRU6
PD[
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LQWKHUDQJHVHH³'HVFDOLQJ,QSXWV´RQSDJHLQ
WKLVFKDSWHU
5HVHWELWRIZRUGLQWKH3,'FRQWUROEORFNLQWHJHUILOHW\SH
RQO\6HWWKLVELWRQO\LI\RXZDQWWRLQKLELWVFDOLQJWKHVHWSRLQW
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1785-6.1 November 1998

(QWHUWKHVHWSRLQWZRUGDQGGHDGEDQGZRUGLQWHJHUILOH
W\SHRQO\YDOXHVLQWKHVDPHVFDOHGHQJLQHHULQJXQLWV7KH
FRQWURORXWSXWZRUGGLVSOD\VDVDSHUFHQWDJHRIWKH
UDQJH7KHRXWSXWWKHSURFHVVRUWUDQVIHUVWRWKHRXWSXWPRGXOHLV
DOZD\VXQVFDOHG
$77(17,21 'RQRWFKDQJHVFDOLQJZKHQWKH
SURFHVVRULVLQ5XQPRGH7KHSURFHVVRU
FRXOGIDXOWDQGFDXVHDQXQGHVLUDEOHSURFHVVUHVSRQVH
SRVVLEOHHTXLSPHQWGDPDJHDQG
SHUVRQDOLQMXU\
Setting the Dead Band 7KHDGMXVWDEOHGHDGEDQGOHWV\RXVHOHFWDQHUURUUDQJHDERYHDQG

EHORZWKHVHWSRLQWZKHUHRXWSXWGRHVQRWFKDQJHDVORQJDVWKHHUURU
UHPDLQVZLWKLQWKLVUDQJH
7KLVGHDGEDQGOHWV\RXFRQWUROKRZFORVHO\WKHSURFHVVYDULDEOH
PDWFKHVWKHVHWSRLQWZLWKRXWFKDQJLQJWKHRXWSXW
high alarm
+DB
process error within

SP dead band range
variable
-DB
low alarm
time
Using Zero-Crossing
=HURFURVVLQJLVGHDGEDQGFRQWUROWKDWOHWVWKHLQVWUXFWLRQXVHWKH
HUURUIRUFRPSXWDWLRQDOSXUSRVHVDVWKHSURFHVVYDULDEOHFURVVHVLQWR
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SURFHVVYDULDEOHFURVVHVWKHVHWSRLQWHUURUFURVVHV]HURDQGFKDQJHV
VLJQDQGDVORQJDVWKHSURFHVVYDULDEOHUHPDLQVLQWKHGHDGEDQGWKH
LQVWUXFWLRQFRQVLGHUVWKHHUURUYDOXH]HUR
(QWHU\RXUGHDGEDQGYDOXHLQZRUGRIWKHFRQWUROEORFN'%ZRUG
RID3'GDWDILOHW\SH7KHGHDGEDQGH[WHQGVDERYHDQGEHORZWKH
VHWSRLQWE\WKHYDOXH\RXVSHFLI\(QWHUWRLQKLELWWKHGHDGEDQG,I
VFDOHGWKHGHDGEDQGKDVWKHVDPHVFDOHGXQLWVDVWKHVHWSRLQW
1785-6.1 November 1998

Using No Zero Crossing

7KHVHULHV(SURFHVVRUDGGHGDQR]HURFURVVLQJIHDWXUHZKLFKLV
XVHIXOIRUDSSOLFDWLRQVWKDWUXQKLJKLQHUWLDSURFHVVHVWKDWVORZO\
PRYHDKLJKPDVVZKLFKLVKDUGWRVWRS7KHQR]HURFURVVLQJIHDWXUH
FDXVHVWKH&9RXWSXWQRWWRFKDQJHYDOXHDVORQJDVWKH39LVLQVLGH
WKHGHDGEDQGUDQJHLQVWHDGRIRQO\DIWHUUHDFKLQJWKHVHWSRLQWYDOXH
:LWKWKHSURSHUWXQLQJLWLVWKHQSRVVLEOHWRKDYHWKH39GULIWWRWKH
VHWSRLQWYDOXH
Selecting the Derivative Term (Acts 'HULYDWLYHLVDFKDQJHRIVWDWHYDULDEOH<RXFDQVHOHFWZKHWKHUWKH

on PV or Error) GHULYDWLYHWHUPLQHLWKHU3,'HTXDWLRQDFWVRQFKDQJHVLQWKH
SURFHVVRUYDULDEOHRUHUURUYDOXH8VHELWRIZRUGLQWKHFRQWURO
EORFN'2ZRUGRID3'GDWDILOHW\SHWRVHOHFWWKHW\SHRI
GHULYDWLYHDFWLRQ\RXZDQW
Setting Output Alarms <RXFDQVHWDQRXWSXWDODUPRQWKHFRQWUROYDULDEOHRXWSXWDWD

VHOHFWHGYDOXHDERYHRUEHORZWKHVHWSRLQW:KHQWKHLQVWUXFWLRQ
GHWHFWVWKDWWKHRXWSXWKDVUHDFKHGHLWKHUYDOXHWKHSURFHVVRUVHWVDQ
DODUPELWELWIRUORZHUOLPLWELWIRUXSSHUOLPLWLQZRUGRIWKH
FRQWUROEORFN2/+DQG2//ELWVRID3'GDWDILOHW\SH$ODUPELWV
DUHUHVHWE\WKHLQVWUXFWLRQZKHQWKHRXWSXWFRPHVEDFNLQVLGHWKH
OLPLWV7KHLQVWUXFWLRQGRHVQRWSUHYHQWWKHRXWSXWIURPH[FHHGLQJWKH
DODUPYDOXHVXQOHVV\RXVHOHFWRXWSXWOLPLWLQJ
(QWHUWKHXSSHURXWSXWDODUPLQZRUG0$;2DQGWKHORZHU
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1785-6.1 November 1998

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Figure 14.2
Example Diagram for Moving Analog Inputs to a PID Instruction
Ladder Program
BTR
12-bit BLOCK TRANSFER READ

Analog Input Module Rack 0 EN
Group 0
DN
Main Control Station Module 0
PV 1st channel Control Block N7:0
Output Input (word 1) ER
Tracking Block Transfer Data File N7:109
(Tieback Input) Length 6
Continuous N
2nd channel
(word 2)
Output
PID
Module located in rack 0,
I/O group 0, module slot 0 PID
Control block N7:20
Process Variable N7:109
Tieback N7:110
Control variable N7:120
15297
Set Output
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1785-6.1 November 1998

Table 14.A
Set Output Mode Procedure
Integer Control Block (N7:0) PD Control Block (PD10:0)
Select Automatic Mode Mode:0 (0:auto/1:manual) A/M Station Mode = Auto

(bit N7:0/1 = 0) (bit PD10:0.MO = 0)
Select Set Output Mode SET OUTPUT MODE: 1 (0:no/1:yes) Software A/M Mode = Manual
(bit N7:0/4 = 1) (bit PD10:0.SWM = 1)
Note: In data monitor, MODE=AUTO changes to

MODE=SW MANUAL.
Enter % in Set Output SET OUTPUT VALUE % SET OUTPUT %

Value (0-100%) (word N7:10 = %value) (word PD10:0.SO = % value)
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IRUFDOFXODWLQJEXPSOHVVWUDQVIHU
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Operational Status Bits
Integer Block
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State False
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the PID Instruction
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1785-6.1 November 1998

PD Block
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1785-6.1 November 1998

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Control Block a file that stores PID status and control bits, constants, variables,
and internally used parameters.
Based on the data type you use, a different configuration screen
appears for you to enter PID information (see the next sections for
more information).
If you have an Enhanced PLC-5 processor, you can use an integer
control block or a PD control block. Using a PD file, words 0, 1 are
the status words; words 2-80 store the PID values.
If you use an Integer control block, the PID calculations are
performed using integer values. If you use a PD control block, the
PID calculations are performed using floating point values.
If you have a Classic PLC-5 processor, you must use an integer file
(N) for your control block. Using an integer file, word 0 is the status
word; words 1-22 store the PID values.
Process Variable a word address that stores the process input value.
Tieback a word address used to implement bumpless transfer when using a

manual control station. The tieback is an output of a BTR instruction
from the station.
Control Variable a word address to which the PID instruction sends its calculated PID
output value.
Note: If a value greater than 4095 is written to the “control variable”
location of the Integer Type PID instruction, the output of the PID
instruction obtains a permanent offset which can only be removed
by writing to the “control variable” with a value between 0 and
4095. This happens whether you write to this location via rung logic
or directly to the data table location.
Note: The file PD type PID instruction does not exhibit this behavior.
1785-6.1 November 1998

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Table 14.B
PID Parameter Descriptions (Integer Control Block)
Equation Enter whether you want to use independent (0) or dependent (1) gains. Displays one of
the following:
INDEPENDENT (0) – for independent gains

DEPENDENT (1) – for dependent gains (ISA)
Use dependent gains when you want to use standard loop tuning methods. Use
independent gains when you want the three gain constants (P, I, and D) to
operate independently.
Mode Displays operating mode:
AUTO (0) – automatic PID control

MANUAL (1) – control from a manual control station
Sets the use of the tieback parameter for manual operation
Error Displays one of the following error value:

Reverse acting: 0 = SP-PV
Direct acting: 1 = PV-SP
Output Limiting Displays whether or not the instruction clamps the output at the high and low limiting
values. Displays one of the following:
NO (0) – output not clamped

YES (1) – output clamped
The PID algorithm has an anti-reset windup feature that prevents the integral term from
becoming too large when the output reaches the high or low alarm limits. If the limits
are reached, the algorithm stops calculating the integral term until the output comes
back into range.
Set output mode Selects the use of set output value % for manual operation
Setpoint scaling Selects if the setpoint is to be interpreted as a value in the engineering units or an
unscaled (0 to 4095) value
Derivative input Selects if derivative term is based on changes in PV or on changes in error
Last state resume Selects if you want to resume last state or hold last state
(Continued)
1785-6.1 November 1998

Deadband status Set if the PV is inside the selected deadband range; reset if it is not
Upper CV limit alarm Set if calculated CV is greater than the CV upper limit word %
Lower CV limit alarm Set if calculated CV is less than the CV lower limit word %
Setpoint out of range Displays whether or not the setpoint is out of the range of engineering units you
selected on the PID Configuration screen. Displays one of the following:
NO (0) – SP within range

YES (1) – SP out of range
Note: A major processor fault occurs if the SP is out of range when the instruction is
first enabled.
PID done Displays whether the PID instruction has completed (1 = done; 0 = not done).
PID enabled Displays whether the PID instruction is enabled (1 = enabled; 0 = not enabled).
Feed forward Enter a value between –4095 and 4095 for the amount of feed forward.
The ladder program can enter a feedforward value to bump the output in anticipation of
a disturbance. This value is often used to control a process with transportation lag.
Max scaled input Enter the integer number (–32,768 - 32,767) that is the maximum value available from
the analog module. For example, use 4095 for a module whose range is 0-4095.
Min scaled input Enter the number that is the minimum value available from the analog module. For
example, use 0 for a module whose range is 0 to 4095.
Dead band For an unscaled deadband, enter a value in the engineering units you selected on
the PID Configuration screen. Valid range is 0 to 4095 unscaled, –32,768 to
+32,767 scaled.
Note: The deadband is zero crossing.
Set output value % Enter a percent (0-100%) to use as the CV Output when ‘set output mode’ is selected.
Upper CV limit % Enter a percent (0-100) above which the algorithm clamps the output.
Lower CV limit % Enter a percent (0-100) below which the algorithm clamps the output.
Scaled PV value Displays data from the analog input module that the instruction scales to the same
engineering units that you selected for the setpoint.
Scaled error Displays the current error in scaled engineering units
Current CV % Displays current controlled variable output value as a percent
Setpoint Enter an integer. Valid range is 0 to 4095 (unscaled) or Smin- Smax (scaled
engineering units).
Proportional gain Enter an integer. Valid entry range is 0-32,767 (unitless) or Kp 0-32,767. The
(Kc) processor divides the entry value by 100 for calculations.
Reset time (Ti) Enter an integer. Valid entry range for Ti is 0-32,767 (minutes times 100). The
minutes/repeat processor automatically divides the entry value by 100 for calculations.
Valid entry range for Ki is 0-32,767 (inverse seconds times 1000). The processor
automatically divides the entry by 1000 for calculations.
(Continued)
1785-6.1 November 1998

Derivative rate (Td) Enter an integer. Valid entry range is 0-32,767 or KD 0-32,767. The processor divides
the entry value by 100 for calculations.
Loop update time Enter an update time (greater than or equal to 0.01 seconds) at 1/5 to 1/10 times the
natural period of the load (load time constant). Valid entry range is 1-32,767 seconds.
The processor divides the entry value by 100 for calculations. The load time constant
should be greater than:
1ms(algorithm) + block transfer time (ms)
Periodically enable the PID instruction at a constant interval equal to the update time.
For update times of less than 100 msec, use an STI. When update times are greater
than 100 msec, use a timer or a real-time sampling.
Note: If you omit an update time or enter a negative update time, a major fault occurs
the first time the processor runs the PID instruction.
Using Control Block Values

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Table 14.C
PID Control Block (Integer Control Block)
Word: Contains: Term: Entry Range:
0 Bit 15 Enabled (EN)

Bit 13 Done (DN)
Bit 11 Set point out of range
Bit 10 Output alarm, lower limit
Bit 9 Output alarm, upper limit
Bit 8 DB, set when error is in deadband
Bit 7 Resume last state (0=yes; 1=hold last state)
Bit 6 Derivative action (0=PV, 1=error)
Bit 5 Setpoint descaling (0=no, 1=yes)
Bit 4 Set output (0=no, 1=yes)
Bit 3 Output limiting (0=no, 1=yes)
Bit 2 Control (0=reverse, 1=direct)
Bit 1 Mode (0=automatic, 1=manual)
Bit 0 Equation (0=independent, 1=ISA)
Note: During prescan, bits 8, 9, 10, in addition to the Integral
Accumulator and Derivative Error values, are cleared and the
error register value of previous scans is set to 32,767.
1 reserved
2 Setpoint SP 0-4095 (unscaled)

Smin–Smax (scaled)
Note: Terms marked with an asterisk (*) are entered as Yy × 100. The term itself is Yy. The term marked with a double
asterisk (**) is entered as Yy × 1000. The term itself is Yy.
(Continued)
1785-6.1 November 1998

Word: Contains: Term: Entry Range:
3 Independent: Proportional gain x 100 (unitless) Kp * 0-32,767
ISA: Controller gain x 100 (unitless) Kc* 0-32,767
4 Independent: Integral gain x 1000 (1/sec) Ki** 0-32,767
ISA: Reset term x 100 (minutes per repeat) Ti* 0-32,767
5 Independent: Derivative gain x 100 (seconds) Kd* 0-32,767
ISA: Rate term x100 (minutes) Td* 0-32,767
6 Feedforward or bias FF/Bias –4095-+4095
7 Maximum scaling Smax –32,768-+32,767
8 Minimum scaling Smin –32,768-+32,767
9 Dead band DB 0-4095 (unscaled)

Smin–Smax (scaled)
10 Set output SETOUT 0-100%
11 Maximum output limit (% of output) Lmax 0-100%
12 Minimum output limit (% of output) Lmin 0-100%
13 Loop update time x 100 (seconds) dt 0-32,767
14 Scaled PV value (displayed) Smin–Smax
15 Scaled error value (displayed) Smin–Smax
16 Output (% of 4095) CV 0-100%
17-22 internal storage; do not use
Note: Terms marked with an asterisk (*) are entered as Yy × 100. The term itself is Yy. The term marked with a double
asterisk (**) is entered as Yy × 1000. The term itself is Yy.
1785-6.1 November 1998

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Table 14.D
PID Parameter Descriptions (PD Control Block)
Parameter Address Description:

Mnemonic:
Setpoint .SP Enter a floating-point number in the same engineering units that are on the
PID Configuration screen. Valid range is –3.4 E+38 to +3.4 E+38.
Process Variable .PV Displays data from the analog input module that the instruction scales to
the same engineering units that you selected for the setpoint.
Error .ERR Displays one of the following error values:

Reverse acting: Error = PV-SP
Direct acting: Error = SP-PV
Output % .OUT Displays the PID algorithm control output value (0-100%).
Mode .MO Displays operating mode:

.MO=0 AUTO – automatic PID control
.MO=1 MANUAL – control from a manual control station
.SWM=1 SW MANUAL – simulated manual control from the data monitor or
ladder program
PV Alarm Displays whether the PV is within or exceeds the high or low alarm limits
you selected on the PID Configuration screen. Displays one of the following:
.PVHA=1
.PVLA=1 NONE – PV within alarm limits
HIGH – PV exceeds high alarm limit (used with deadband)
LOW – PV exceeds low alarm limit (used with deadband)
Deviation Alarm Displays whether the error is within or exceeds the high or low deviation
alarms you selected on the PID Configuration screen. Displays one of the
following:
.DVPA=1
.DVNA=1
NONE – error within deviation alarm limits
POSITIVE – error exceeds high alarm (used with deadband)
NEGATIVE – error exceeds low alarm (used with deadband)
Output Limiting .OLH=1 Displays whether or not the instruction clamps the output at the high and
.OLL=1 low limiting values (.MAXO and .MINO) you selected on the PID Configuration
screen. Displays one of the following:
NONE – output not clamped

HIGH – output clamped at the high end (.MAXO)
LOW – output clamped at the low end (.MINO)
The PID algorithm has a anti-reset-windup feature that prevents the integral
term from becoming too large when the output reaches the high or low
alarm limits. If the limits are reached, the algorithm stops calculating the
integral term until the output comes back into range.
(Continued)
1785-6.1 November 1998


Mnemonic:
SP Out of Range .SPOR=0 Displays whether or not the setpoint is out of the range of engineering units
.SPOR=1 you selected on the PID Configuration screen. Displays one of the following:
NO – SP within range
YES – SP out of range
Note: A major processor fault occurs if the SP is out of range when the
instruction is first enabled.
Error Within DB .EWD=0 Displays whether the error is within or exceeds the deadband value
.EWD=1 you enter on this screen. The deadband is zero crossing. Displays one
of the following:
RESET – Error exits the deadband zone

SET – Error crosses the deadband centerline
PID Initialized .INI=0 Each time you change a value in the control block, the PID instruction takes
.INI=1 over twice as long to execute (until initialized) on the first scan. Displays one
of the following:
NO – PID instruction not initialized after you changed control block values
YES – PID instruction remains initialized because you did not change any
control block values
Attention: Do not change the range of input or engineering units when

running. If you must do this, then you must reset this bit to re-initialize.
Otherwise, the instruction will malfunction with possible damage to
equipment and injury to personnel.
A/M Station Mode .MO=0 Enter whether you want automatic (0) or manual (1) PID control. Displays
.MO=1 one of the following:

MANUAL (1) – manual PID control
Manual control specified that an output from a manual control station

overrides the calculated output of the PID algorithm.
Note: Manual overrides Set Output Mode.
Software A/M Mode .SWM=0 Enter whether you want automatic PID (0) control or Set Output Mode (1), for
.SWM=1 software-simulated control. Displays one of the following:

SW MANUAL (1) – software-simulated PID control
You can simulate a manual control station with the data monitor when you
program a single loop. To do this, set .SWM to SW MANUAL and enter a
Set Output Percent value.
You can simulate a manual control station with ladder logic, pushwheels,
and pushbutton switches when you program several loops. To do this, set
.SWM to SW MANUAL and move a value into the set output element .SO.
(Continued)
1785-6.1 November 1998


Mnemonic:
Status Enable .EN=0 Enter whether to use (1) or inhibit (0) this bit which displays the rung
.EN=1 condition so you can see whether the PID instruction is operating. Displays
one of the following:
0 – instruction not executing

1 – instruction executing
Proportional Gain .KP Enter a floating-point value. Valid range for independent or standard gains is
0 to 3.4 E+38 (unitless).
Integral Gain .KI Enter a floating-point value. Valid range for independent gains is 0 to 3.4
E+38 inverse seconds; valid range for standard gains is 0 to 3.4 E+38
minutes per repeat.
Derivative Gain .KD Enter a floating-point value. Valid range for independent gains is 0 to 3.4
E+38 seconds; valid range for standard gains is 0 to 3.4E+38 minutes.
Output Bias % .BIAS Enter a value (–100 to +100) to represent the percentage of output you want
to feed forward or use as a bias to the output. The bias value can
compensate for steady-loss of energy from the system.
The ladder program can enter a feedforward value to bump the output in
anticipation of a disturbance. This value is often used to control a process
with transportation lag.
Tieback % .TIE Displays a number (0 to 100) representing the percent of raw tieback (0 –
4095) from the manual control station. The PID algorithm uses this number
to achieve bumpless transfer when switching from manual to auto mode.
Set Output % .SO Enter a percent (0 to 100), from this screen or a ladder program, to
represent the software-manually controlled output.
When you select software-simulated control (.SWM=1), the PID instruction
overrides the algorithm with the set output value (0 - 4095) for transfer to
the output module, and copies it to .OUT for display as a percent. The
transfer to software-simulated control is bumpless because .SO (under your
control) starts with the last automatic algorithm output. Do not vary .SO until
after the transfer.
To achieve bumpless transfer when changing from software-simulated
control to automatic control, the PID algorithm changes the integral term so
that the output is equal to the set output value.
1785-6.1 November 1998

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Table 14.E
PID Configuration Descriptions (PD Control Block)
Parameter: Address Description:

Mnemonic:
PID Equation .PE=0 Enter whether you want to use independent (0) or dependent (1) gains. Displays one of
.PE=1 the following:
INDEPENDENT (0) – for independent gains

DEPENDENT (1) – for dependent gains
Use dependent gains when you want to use standard loop tuning methods. Use
independent gains when you want the three gain constants (P, I, and D) to
operate independently.
Derivative of .DO=0 Enter whether you want the derivative of the PV (0) or the error (1). Displays one of
.DO=1 the following:
PV (0) – for PV derivative

ERROR (1) – for error derivative
Select the PV derivative for more stable control when you do not change the setpoint often.
Select the error derivative for fast responses to setpoint changes when the algorithm can
tolerate overshoots.
Control Action .CA=0 Enter whether you want reverse (0) or direct acting (1). Displays one of the following:
.CA=1
REVERSE (0) – for reverse acting (E = SP-PV)
DIRECT (1) – for direct acting (E = PV-SP)
PV Tracking .PVT=0 Enter whether you do not (0) or do (1) want PV tracking. Displays one of the following:
.PVT=1
NO (0) – for no tracking
YES (1) – for PV tracking
Select no tracking if the algorithm can tolerate a bump when switching from manual to
automatic control. Select PV tracking if you want the setpoint to track the PV in manual
control for bumpless transfer to automatic control.
Update Time .UPD Enter an update time (greater than or equal to .01 seconds) at 1/5 to 1/10 the natural
period of the load (load time constant). The load time constant should be greater than:
3ms(algorithm) + block transfer time (ms)
Periodically enable the PID instruction at a constant interval equal to the update time.
When the program scan time is close to the required update time, use an STI to ensure a
constant update interval. When the program scan is several times faster than the required
update time, use a timer.
Attention: If you omit an update time or enter a negative update time, a major fault occurs
the first time the processor runs the PID instruction.
(Continued)
1785-6.1 November 1998


Mnemonic:
Cascade Loop .CL=0 Enter whether this loop is not (0) or is (1) used in a cascade of loops. Displays one of the
.CL=1 following:
NO (0) – not used in a cascade

YES (1) – used in a cascade
Cascade Type .CT=0 If this loop is part of a cascade of loops, enter whether this loop is the master (1) or a slave
.CT=1 (0). Displays one of the following:
SLAVE (0) – for a slave loop

MASTER (1) – for a master loop
Master to .ADDR If this loop is a slave loop in a cascade, enter the control block address of the master.
this Slave
Tieback is ignored in the master loop of a cascade. When you change cascaded loops to
manual control, the slave forces the master into manual control. When PV tracking is
enabled, the order of events is:
Slave.SP > Master.TIE > Master.OUT > Slave.SP
When you return to automatic control, change the slave first, then the master.
Engineering .MAXS Enter the floating-point value in engineering units that corresponds to the analog module’s
Unit Max full scale output. Valid range is –3.4 E+38 to +3.4 E+38.
Attention: Do not change this value during operation because a processor fault
might occur.
Engineering Unit .MINS Enter the floating-point value in engineering units that corresponds to the analog module’s
Min zero output. Valid range is –3.4 E+38 to +3.4 E+38 (post-scaled number).
Attention: Do not change the maximum scaled value during operation because a
processor fault might occur.
Input .MAXI Enter the floating-point number (–3.4 E+38 to +3.4 E+38) that is the unscaled maximum
Range Max value available from the analog module. For example, use 4095 for a module whose range
is 0-4095.
Input .MINI Enter the floating-point number (–3.4 E+38 to +3.4 E+38) that is the minimum unscaled
Range Min value available from the analog module. For example, use 0 for a module whose range is
0-4095.
Output Limit .MAXO Enter a percent (0-100) above which the algorithm clamps the output.
High %
Output Limit .MINO Enter a percent (0-100) below which the algorithm clamps the output.
Low %
PV Alarm High .PVH Enter a floating-point number (–3.4 E+38 to +3.4 E+38) that represents the highest
PV value that the system can tolerate.
PV Alarm Low .PVL Enter a floating-point number (–3.4 E+38 to +3.4 E+388) that represents the lowest
PV value that the system can tolerate.
PV Alarm .PVDB Enter a floating-point number (0-3.4 E+38) that is sufficient to minimize nuisance alarms.
Deadband This is a one-sided deadband. The alarm bit (.PVH or .PVL) is not set until the PV crosses
the deadband and reaches the alarm limit (DB zero point). The alarm bit remains set until
the PV passes back through and exits from the deadband.
(Continued)
1785-6.1 November 1998


Mnemonic:
Deviation Alarm .DVP Enter a floating-point number (0-3.4 E+38) that specifies the greatest error deviation above
(+) the setpoint that the system can tolerate.
Deviation Alarm .DVN Enter a floating-point number (–3.4 E+38-0) that specifies the greatest error deviation
(–) below the setpoint that the system can tolerate.
Deviation Alarm .DVDB Enter a floating-point number (0-3.4 E+38) that is sufficient to minimize nuisance alarms.
Deadband
This is a one-sided deadband. The alarm bit (.DVP or .DVN) is not set until the error crosses
the deadband and reaches the alarm limit (DB zero point). The alarm bit remains set until
the error passes back through and exits from the deadband.
No Zero Crossing .NOZC=0 Enter whether to use (1) or inhibit (0) the no zero crossing feature:
.NOZC=1
0 – no zero crossing disabled
1 – no zero crossing enabled
No Back .NOBC=0 Enter whether to use (1) or inhibit (0) the no back calculation feature:
Calculation .NOBC=1
0 – no back calculation disabled
1 – no back calculation enabled
No Derivative .NDF=0 Enter whether to use (1) or inhibit (0) the filter in the derivative calculation.
Filter .NDF=1
0 – no filter used in derivative calculation
1 – filter used in derivative calculation
Using Control Block Values

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Table 14.F
PID Control Block
Word: Contains: Range:
0 Control/Status Bits
Bit 15 Enabled (EN)
Bit 11 No back calculation (0=disabled, 1=enabled)
Bit 10 No zero crossing (0=disabled, 1=enabled)
Bit 9 Cascade selection (master, slave)
Bit 8 Cascade loop (0=no, 1=yes)
Bit 7 Process variable tracking (0=no, 1=yes)
Bit 6 Derivative action (0=PV, 1=error)
Bit 5 No derivative filter (0=disabled, 1=enabled)
Bit 4 Set output (0=no, 1=yes)
Bit 2 Control action (0=SP-PV, 1=PV-SP)
Bit 1 Mode (0=automatic, 1=manual)
Bit 0 Equation (0=independent, 1=ISA)
(Continued)
1785-6.1 November 1998

1 Status Bits
Bit 12 PID initialized (0=no, 1=yes)
Bit 11 Set point out of range
Bit 10 Output alarm, lower limit
Bit 9 Output alarm, upper limit
Bit 8 DB, set when error is in DB
Bit 3 Error is alarmed low
Bit 2 Error is alarmed high
Bit 1 Process variable (PV) is alarmed low
Bit 0 Process variable (PV) is alarmed high
Note: During prescan, bit 12 is cleared.
2, 3 Setpoint –3.4 E+38 to +3.4 E+38
4, 5 Independent: Proportional gain (unitless) 0 to +3.4 E+38
ISA: Controller gain (unitless) 0 to +3.4 E+38
6, 7 Independent: Integral gain (1/sec) 0 to +3.4 E+38
ISA: Reset term (minutes per 0 to +3.4 E+38

repeat)
8, 9 Independent: Derivative gain (seconds) 0 to +3.4 E+38
ISA: Rate term (minutes) 0 to +3.4 E+38
10, 11 Feedforward or bias –100 to +100%
12, 13 Maximum scaling –3.4E+38 to +3.4 E+38
14, 15 Minimum scaling –3.4 E+38 to +3.4 E+38
16, 17 Dead band 0 to +3.4 E+38
18, 19 Set output 0-100%
20, 21 Maximum output limit (% of output) 0-100%
22, 23 Minimum output limit (% of output) 0-100%
24, 25 Loop update time (seconds)
26, 27 Scaled PV value (displayed)
28, 29 Scaled error value (displayed)
30, 31 Output (% of 4095) 0-100%
32, 33 Process variable high alarm value –3.4 E+38 to +3.4 E+38
34, 35 Process variable low alarm value –3.4 E+38 to +3.4 E+38
36, 37 Error high alarm value 0 to +3.4 E+38
38, 39 Error low alarm value –3.4 E+38 to 0
40, 41 Process variable alarm deadband 0 to +3.4 E+38
42, 43 Error alarm deadband 0 to +3.4 E+38
(Continued)
1785-6.1 November 1998

44, 45 Maximum input value –3.4 E+38 to +3.4 E+38
46, 47 Minimum input value –3.4 E+38 to +3.4 E+38
48, 49 Tieback value for manual control (0-4095) 0-100%
51 Master PID file number 0-999; 0-9999 for

Enhanced PLC-5
processors only
52 Master PID element number 0-999; 0-9999 for

Enhanced PLC-5
processors only
54-80 internal storage; do not use
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4095
M 2 = ( M 1 – S min1 )
( S max1 – S min1 )
Variable Description
M2 calculated output
M1 measured value from the module in scaled units
Smax1 scaled maximum value from the module
Smin1 scaled minimum value from the module
Smax1 – Smin1 scaled range from the module
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1785-6.1 November 1998

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Figure 14.3
Descaling PID Values Example
FAL
FILE ARITHMETIC/LOGIC
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Length 6
Position 0
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1785-6.1 November 1998

Table 14.G
Variables for the Descaling PID Values Example
Variable Description
Smax maximum scaling value
Smin minimum scaling value
4095 constant for each channel

K =
S max – S min
#N17:0 contains M1 values for each channel
#N18:0 contains Smin constants for each channel
#N19:0 contains the result of M1-Smin for each channel
#N20:0 location where you store K for each channel
#N21:0 contains the resulting unscaled value for each channel
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WKLV3,'DSSOLFDWLRQ'XSOLFDWHWKHWLPHULQVWUXFWLRQHOVHZKHUHLQWKH
SURJUDPLIWKHSURFHVVRUVFDQWLPHORFDO,2VFDQSOXVSURJUDPVFDQ
LVJUHDWHUWKDQVHFRQGV
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GXULQJPDLQSURJUDPVFDQ\RXQHHGDVWRUDJHELWWRHQVXUHWKDWWKH
VWDWHRIWKH3,'LQSXWFRQGLWLRQUHPDLQVFRQVWDQWGXULQJWKHHQWLUH
SURJUDPVFDQ&RQGLWLRQDOO3,'LQVWUXFWLRQVXVLQJWKLVVWRUDJHELW
1785-6.1 November 1998

Figure 14.4
Example PID Programming Conditioned by a Timer in the Main Program
TON
T10:0 TIMER ON DELAY
EN
Timer T10:0
Time base 0.01
DN Preset 10 DN
Accum 0
BTR
BLOCK TRANSFER READ
T10:0 EN
Rack 0
Group 1
DN Module 0 DN
Control Block BT9:0
Data file N7:104
Length 5 ER
Continuous N
BT9:0 B3
DN 0
PID
B3 PID
Control Block N7:20
Process variable N7:104
0
Tieback 0
BTW
BLOCK TRANSFER WRITE
N7:20 EN
Rack 0
Group 0
13 Module 0 DN
Control Block BT9:1
Data file N7:200
Length 13 ER
Continuous N
STI Program File

:KHQ\RXSODFHWKH3,'LQVWUXFWLRQLQDVHOHFWDEOHWLPHGLQWHUUXSWILOH
67,WKH67,FRQWUROVWKHORRSXSGDWHVDPSOLQJWLPHZKHUHWKH
3,'/RRS8SGDWH7LPH 67,LQWHUYDO
,QWKH67,DVHSDUDWHSURJUDPILOHFRQWDLQVDOORIWKHQHFHVVDU\ORJLF
WRDFFRPSOLVKWKHORRSXSGDWH7KH3/&SURFHVVRULVFRQILJXUHG
ZLWKDQ67,WRH[HFXWHWKDWILOHDWWKHXVHU¶VXSGDWHLQWHUYDO67,ORRS
FRRUGLQDWLRQLVGHVLUDEOHZLWK³IDVWHUÓRRSVRUZKHQPRUHORRS
SURFHVVLQJLVUHTXLUHGDWWKHVSHFLILHGXSGDWHLQWHUYDO6HH)LJXUH
IRUSURJUDPPLQJH[DPSOHV
7KH3,'LQVWUXFWLRQRSHUDWHVRQWKHPRVWUHFHQWGDWDZKHQEORFN
WUDQVIHULQVWUXFWLRQVDUHLQFOXGHGLQWKH67,ILOH<RXPXVWSODFHEORFN
WUDQVIHUPRGXOHVLQWKHORFDOFKDVVLVIRUWKLV3,'DSSOLFDWLRQ
8QODWFKLQJWKH3,'DQG%7HQDEOHELWVIRUFHVWKHSURFHVVRUWRUXQWKH
3,'DQGEORFNWUDQVIHULQVWUXFWLRQVHYHU\WLPHWKH67,LVHQDEOHG
1785-6.1 November 1998

,PSRUWDQW 7KHSURJUDPVFDQZDLWVIRUEORFNWUDQVIHULQVWUXFWLRQV
LQWKH67,ILOHWRFRPSOHWHWKHLUWUDQVIHUV
Figure 14.5
Example PID Programming in an STI File
BTR
BLOCK TRANSFER READ
Rack 0 EN
Group 1
0 DN
Module
Control Block BT9:0
Data file N7:104 ER
Length 5
BT9:0 Continuous N
U
EN
PID
PID
Control block N7:20
Tieback 0
N7:20 Control variable N7:200
U
15
BTW
Rack 0 EN
Group 0
Module 0 DN
Control Block BT9:1
Data file N7:200
Length 13 ER
BT9:1 Continuous N
U
EN
1785-6.1 November 1998

RTS Program File

:LWKWKH5HDO7LPH6DPSOH%DVHG576WKH3,'LQVWUXFWLRQ¶V
H[HFXWLRQLVWULJJHUHGE\WKHDYDLODELOLW\RIQHZDQDORJGDWDIURPDQ
DQDORJLQSXWVRXUFHFRQILJXUHGIRUUHDOWLPHVDPSOLQJ6LQFHWKH576
FRQILJXUDWLRQRIDQDQDORJPRGXOHZLOOQRWLQLWLDWHRUDOORZD%75
XQWLOQHZGDWDLVDYDLODEOHWKH3,'LQVWUXFWLRQ¶VUXQJFDQEH
FRQGLWLRQHGE\WKH%75¶VGRQHELW7KLVDVVXUHVWKDWWKH3,'
LQVWUXFWLRQLVH[HFXWHGRQO\ZKHQQHZDQDORJGDWDLVDYDLODEOHDWWKH
576LQWHUYDO6HH)LJXUHIRUSURJUDPPLQJH[DPSOHVZKHUHWKH
3,'/RRS8SGDWH7LPH 576LQWHUYDO
Figure 14.6
Example PID Programming in an RTS File
BTR
BT9:0 BLOCK TRANSFER READ EN
Rack 0
EN Group 1
DN
Module 0
Control Block BT9:0
Data file N7:104 ER
Length 5
Continuous N
PID
BT9:0 PID
Control Block N7:20
DN Process variable N7:104
Tieback 0
BTW
N7:20 BLOCK TRANSFER WRITE EN
Rack 0
Group 0
13 DN
Module 0
Control Block BT9:1
Data file N7:200 ER
Length 13
Continuous N
1785-6.1 November 1998

PD Block Examples Main Program File

:KHQ\RXSODFHWKH3,'LQVWUXFWLRQLQWKHPDLQSURJUDPILOH
FRQWUROWKHVDPSOHWLPHZLWKDWLPHUZKHUHWKH3,'/RRS8SGDWH
7LPH WLPHUSUHVHW
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FRRUGLQDWLRQ:KHQWKHWLPHU¶VDFFXPXODWHGYDOXHUHDFKHVLWVSUHVHW
YDOXHLWWULJJHUVWKHORRSXSGDWHVHTXHQFH7KHWLPHULPPHGLDWHO\
UHVHWVDQGUHVWDUWVWRPDLQWDLQDFRQVLVWHQWXSGDWHLQWHUYDO8VHWLPHU
EDVHGH[HFXWLRQLQ³VORZHUÓRRSDSSOLFDWLRQVRULQDSSOLFDWLRQVZLWK
UHODWLYHO\IHZORRSV6HH)LJXUHIRUSURJUDPPLQJH[DPSOH
7KHDFFXUDF\RIWKHWLPHUGHSHQGVRQWKHWLPHEDVHDQGWKHWRWDOVFDQ
WLPHRIWKHSURFHVVRU$OZD\VFKRRVHWKHVHFRQGWLPHEDVHIRU
WKLV3,'DSSOLFDWLRQ'XSOLFDWHWKHWLPHULQVWUXFWLRQHOVHZKHUHLQWKH
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LVJUHDWHUWKDQVHFRQGV
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GXULQJPDLQSURJUDPVFDQ\RXQHHGDVWRUDJHELWWRHQVXUHWKDWWKH
VWDWHRIWKH3,'LQSXWFRQGLWLRQUHPDLQVFRQVWDQWGXULQJWKHHQWLUH
SURJUDPVFDQ&RQGLWLRQDOO3,'LQVWUXFWLRQVXVLQJWKLVVWRUDJHELW
1785-6.1 November 1998

Figure 14.7
Example PID Programming Conditioned by a Timer in the Main Program
TON
T11:0 TIMER ON DELAY EN
Timer T11:0
DN Time base 0.01
DN
Preset 10
Accum 0
BTR
T11:0 BLOCK TRANSFER READ EN
Rack 0
DN Group 1
DN
Module 0
Control Block BT9:0
Data file N7:104 ER
Length 5
Continuous N
BT9:0 B3
DN 0
PID
B3 B3 PID
ONS Control Block PD10:0
0 1 Process variable N7:104
Tieback 0
BTW
B3 BLOCK TRANSFER WRITE EN

Rack 0
0 Group 0
Module 0 DN
Control Block BT9:1
Data file N7:200 ER
Length 13
Continuous N
STI Program File

:KHQ\RXSODFHWKH3,'LQVWUXFWLRQLQDVHOHFWDEOHWLPHGLQWHUUXSWILOH
67,WKH67,FRQWUROVWKHORRSXSGDWHVDPSOLQJWLPHZKHUHWKH
3,'/RRS8SGDWH7LPH 67,LQWHUYDO
,QWKH67,DVHSDUDWHSURJUDPILOHFRQWDLQVDOORIWKHQHFHVVDU\ORJLF
WRDFFRPSOLVKWKHORRSXSGDWH7KH3/&SURFHVVRULVFRQILJXUHG
ZLWKDQ67,WRH[HFXWHWKDWILOHDWWKHXVHU¶VXSGDWHLQWHUYDO67,ORRS
FRRUGLQDWLRQLVGHVLUDEOHZLWK³IDVWHUÓRRSVRUZKHQPRUHORRS
SURFHVVLQJLVUHTXLUHGDWWKHVSHFLILHGXSGDWHLQWHUYDO6HH)LJXUH
IRUSURJUDPPLQJH[DPSOHV
7KH3,'LQVWUXFWLRQRSHUDWHVRQWKHPRVWUHFHQWGDWDZKHQEORFN
WUDQVIHULQVWUXFWLRQVDUHLQFOXGHGLQWKH67,ILOH<RXPXVWSODFHEORFN
WUDQVIHUPRGXOHVLQWKHORFDOFKDVVLVIRUWKLV3,'DSSOLFDWLRQ
8QODWFKLQJWKH3,'DQG%7HQDEOHELWVIRUFHVWKHSURFHVVRUWRUXQWKH
3,'DQGEORFNWUDQVIHULQVWUXFWLRQVHYHU\WLPHWKH67,LVHQDEOHG
1785-6.1 November 1998

,PSRUWDQW 7KHSURJUDPVFDQZDLWVIRUEORFNWUDQVIHULQVWUXFWLRQV
LQWKH67,ILOHWRFRPSOHWHWKHLUWUDQVIHUV
Figure 14.8
Example PID Programming in an STI File
BTR
BLOCK TRANSFER READ
Rack 0 EN
Group 1
DN
Module 0
Control Block BT9:0
Data file N7:104 ER
Length 5
BT9:0 Continuous N
U
EN
PID
PID
Control block PD10:0
Tieback 0
BTW
Rack 0 EN
Group 0
Module 0 DN
Control Block BT9:1
Data file N7:200
Length 13 ER
BT9:1 Continuous N
U
EN
1785-6.1 November 1998

RTS Program File

:LWKWKH5HDO7LPH6DPSOH%DVHG576WKH3,'LQVWUXFWLRQ¶V
H[HFXWLRQLVWULJJHUHGE\WKHDYDLODELOLW\RIQHZDQDORJGDWDIURPDQ
DQDORJLQSXWVRXUFHFRQILJXUHGIRUUHDOWLPHVDPSOLQJ6LQFHWKH576
FRQILJXUDWLRQRIDQDQDORJPRGXOHZLOOQRWLQLWLDWHRUDOORZD%75
XQWLOQHZGDWDLVDYDLODEOHWKH3,'LQVWUXFWLRQ¶VUXQJFDQEH
FRQGLWLRQHGE\WKH%75¶VGRQHELW7KLVDVVXUHVWKDWWKH3,'
LQVWUXFWLRQLVH[HFXWHGRQO\ZKHQQHZDQDORJGDWDLVDYDLODEOHDWWKH
576LQWHUYDO6HH)LJXUHIRUSURJUDPPLQJH[DPSOHVZKHUHWKH
3,'/RRS8SGDWH7LPH 576LQWHUYDO
Figure 14.9
Example PID Programming in an RTS File
BTR
Rack 0
EN Group 1
DN
Module 0
Control Block BT9:0
Data file N7:104 ER
Length 5
Continuous N
BT9:0 B3
DN 0
PID
B3 B3 PID
ONS Control Block PD10:0
0 1 Process variable N7:104
Tieback 0
BTW
B3
BLOCK TRANSFER WRITE EN
Rack 0
0 Group 0
Module 0 DN
Control Block BT9:1
Data file N7:200 ER
Length 13
Continuous N
1785-6.1 November 1998

Ladder Logic Simulation of a Manual Control Station

:KHQ\RXSURJUDPWKHVLPXODWLRQRIDPDQXDOFRQWUROVWDWLRQPDNH
VXUHWKDWDKDUGZDUHPDQXDOFRQWUROVWDWLRQLVQRWFRQQHFWHGZKHQWKH
SURJUDPLVHQDEOHG$GGWKHUXQJVLQ)LJXUHWRWKH3,'
SURJUDPLQ)LJXUH)LJXUH)LJXUHRU)LJXUH
Figure 14.10
Example Program for Simulating a Manual Control Station
I:001 N7:20
L
00 4
I:001 N7:20
U
01 MOV 4
N7:20 I:001 MOVE
Source I:011
4 002 Destination N7:30
MOV
N7:20 MOVE
Source N7:36
4 Destination N7:30
7KHODVWUXQJLQWKHDERYHH[DPSOHLVIRURXWSXWWUDFNLQJIRU
EXPSOHVVWUDQVIHUIURPDXWRPDWLFWRPDQXDOPRGH
Address: Description:
I:001/00 Manual pushbutton switch
I:001/01 Automatic pushbutton switch
I:001/02 Enter pushbutton switch
I:011 Manual output value
N7:20/4 PID set output bit
N7:30 PID set output value
N7:36 Current control output
1785-6.1 November 1998

Cascading Loops
<RXFDQFDVFDGHWZRORRSVE\DVVLJQLQJWKHFRQWURORXWSXWRIWKH
RXWHUORRSWRWKHVHWSRLQWRIWKHLQQHUORRS7KHVHWSRLQWRIWKHLQQHU
ORRSLVWKHWKLUGZRUGZRUGRIWKHLQWHJHUFRQWUROEORFN,IWKH
FRQWUROEORFNRIWKHLQQHUORRSLV1DGGUHVVWKHRXWHUORRS
FRQWURORXWSXWDW15HSODFHWKH3,'UXQJVLQ)LJXUHRU
)LJXUHZLWKWKRVHLQ)LJXUH
<RXPXVWQRWVFDOHWKHVHWSRLQWRIWKHLQQHUORRS6HWWKHVFDOLQJELW
ZRUGELWWRWRLQKLELWVHWSRLQWVFDOLQJ
Figure 14.11
Cascaded Loops
PID
PID
Control Block N7:20
Tieback N7:106
PID
PID
Control Block N7:50
Tieback N7:108
Ratio Control
<RXFDQPDLQWDLQWZRYDOXHVLQDUDWLRE\XVLQJD08/LQVWUXFWLRQ
7KUHHSDUDPHWHUVDUHLQYROYHG
WKHZLOGRUXQFRQWUROOHGYDOXH
WKHFRQWUROOHGYDOXH
WKHUDWLREHWZHHQWKHVHWZRYDOXHV
(QWHUWKHDGGUHVVRIWKHFRQWUROOHGYDOXHDVWKH'HVWLQDWLRQ(QWHUWKH
DGGUHVVRIWKHZLOGRUXQFRQWUROOHGYDOXHDV6RXUFH$(QWHUHLWKHU
WKHDGGUHVVRIWKHUDWLRYDOXHRUDSURJUDPFRQVWDQWIRUWKHUDWLRDV
6RXUFH%)RUH[DPSOHDGGWKHUXQJVLQ)LJXUHWRWKH3,'
SURJUDPLQ)LJXUHRU)LJXUH
1785-6.1 November 1998

Figure 14.12
Ratio Control with a PID Instruction
PID
PID
Control block N7:20
Tieback N7:106
MUL
MUL
Source A N7:105
Source B 0.350000
Destination N7:52
PID
PID
Control block N7:50
Tieback N7:108
Process Variable Tracking

:KHQLQPDQXDOFRQWURO\RXUSURJUDPFDQIRUFHWKHVHWSRLQWWREH
HTXDOWRWKHSURFHVVYDULDEOH39E\PRYLQJWKH39LQWRWKHVHWSRLQW
ZRUGZRUGRIWKHLQWHJHUFRQWUROEORFNWRDFKLHYHDVPRRWK
PDQXDOWRDXWRPDWLFWUDQVIHU,IWKHVHWSRLQWLVVFDOHGPRYHWKH
VFDOHG39IURPWKH3,'FRQWUROEORFNGLUHFWO\LQWRWKHVHWSRLQW
ZRUG,IWKHVHWSRLQWLVQRWVFDOHGPRYHWKHXQVFDOHGYDOXHIURP
WKH39DGGUHVVLQWKH3,'LQVWUXFWLRQWRWKHVHWSRLQW)RUDQH[DPSOH
DGGWKHUXQJVLQ)LJXUHWRWKH3,'SURJUDPLQ)LJXUHRU
)LJXUH
Figure 14.13
Process Variable Tracking
PID
PID
Control Block N7:20
Tieback N7:106
MOV
MOVE
Source N7:34
Destination N7:22
1785-6.1 November 1998

PID Theory )LJXUHDQG)LJXUHVKRZWKH3/&3,',QWHJHUDQG3'

%ORFNSURFHVVIORZ)LJXUHDQG)LJXUHVKRZWKH3'
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Figure 14.14
PLC-5 PID (Integer Block)
Error
Displayed
as EUs
Convert
Binary % to EU
Smax - Smin
Error x
SetPoint 4095
Scaling
Feed- Set
No Forward Output
12 Bit Error Mode
Truncation
SP-PV Output
SP Limiting
(Error) PID (Out) Off Mode
Yes + +
- Calculation
Convert Eng. Units -1 Auto No
To Binary PV-SP
Output CV
SP-Smin On
x 4095 Limiting
Smax-Smin Set Manual Yes
Output %
Tieback
SP Convert Convert
Displayed as Binary to EU Binary to % Binary
user entry
Smax - Smin 100
PV x + Smin CV x
4095 4095
12 Bit
Truncation
Yes
SetPoint
Scaling Output (CV)
No
displayed as
% Binary
PV
PV
Displayed
as EUs
Smin - Minimum Scaled Input

Smax - Maximum Scaled Input
Figure 14.15
PLC-5 PID (PD Block)
SP Error
Displayed Displayed
as EUs as EUs
Software A/M Output

-or- Bias %
A/M Station Mode Control
Action Set
Software A/M
A/M Mode Output %
Auto SP-PV Station
Convert Eng.
Mode
+ (Error) Units To % PID (Out%) + Auto
- Calculation
Man -1 Error x 100 Auto
SP
PV-SP maxs-mins Output Convert %
PVT Manual Limiting To Binary CV
Out% x 40.95
No Set Manual
Output %
PV
Displayed Tieback %
as EUs Output (CV)
Yes Displayed as
% of EU Scale
Convert Binary
To Eng. Units
(PV-mini)(maxs-mins)
+ mins
maxi-mini
PV PVT - Process Variable Tracking

mini - Input Range Minimum
maxi - Input Range Maximum
mins - Engineering Unit Minimum
maxs - Engineering Unit Maximum
1785-6.1 November 1998

Figure 14.16
PLC-5 PID (PD Block) as Master/Slave Loops
Master
Loop
Software A/M
Output
-or- Control
Bias %
A/M Station Mode Action
Set
Software Output %
Auto SP-PV A/M Mode A/M
Convert Eng. Station
+ (Error) Units To % PID (Out%) + Auto Mode
- Calculation
SP Man -1 Error x 100 Auto
PV-SP maxs-mins Output (Master.Out)
PVT Set Manual Limiting
No Output % Manual
Software
Yes PVT A/M Mode
Auto
Convert Binary No Convert Eng.
SP Items referenced in this box
To Eng. Units Units To % Manual are parameters, units, and
(PV-mini)(maxs-mins) x 100 Manual modes as they pertain to the
+ mins PV
maxi-mini Yes maxs-mins designated Slave loop.
Auto
A/M
Station Mode
PV
Output
Slave Control Bias %
Loop Action Set
Software
A/M Mode A/M Output %
Convert % SP-PV
(Master.Out) (SP) Convert Eng. Station
To Eng. Units
+ Units To % PID + Auto Mode
x (maxs-mins) - Calculation
+ mins -1 Error x 100 Auto
100 PV-SP Convert %
maxs-mins Output
To Binary CV
Manual Limiting
Out% x 40.95
Set Manual
Convert Binary
Output %
To Eng. Units
(PV-mini)(maxs-mins) Tieback %
+ mins
maxi-mini
PV
1785-6.1 November 1998

Figure 14.17
PD Block Master/Slave Interlocking State Transitions
Master Loop Transitions Slave Loop Transitions
Auto Auto
Auto Auto
M-
SW
to
Au
an
M
Man
M-
(on
S-M
M-
n
Ma
)
Au
M-
to
Auto
S-S
S-Man
WM
Man SWM
S-Auto
SWM
(on
S-
)
Auto Auto SW
Man M Auto
(on
M-
S-SWM (on)
to
SW
Au
Man
M-
S-SWM (on)
M-
S-Auto
S-SWM (off)
(of
SW
n
Ma
f)
M
M-
(on
)
Man
( SWM ) Man SWM
S-Auto
Auto Man
Man ( SWM ) SWM
SWM
)
(on
Man SWM
M
SW
M-
SW
S-
M-
Man
(of
SW
( SWM )
f)
M
(on
)
Man Auto
n
to
Man
Ma
( SWM )
M-Au
S-
M-Ma
S-Man
Man
S-Auto
( SWM )
Man
M-
Man
SW
( SWM )
M-
M
(of
SW
f)
M
Man
(on
S-SWM (on)
)
Man
S-SWM (off)
n
S-SWM (off)
( SWM
Ma
( Man
) )
S-
SWM
Man SWM
( SWM ) Man
( SWM )
Man
( SWM )
S-Auto
S-Man
Man
Note: ( SWM ) indicates that this loop
is in Manual with SWM also on". Man
( SWM )
Designates Master Loop Mode SWM
*
Stable State (Composite Mode)
*
Slave Loop Mode
Mode transition
M Designated Master
S Slave
Man Manual
Auto Automatic
SWM Software Manual
1785-6.1 November 1998

Chapter 15
Block-Transfer Instructions BTR and BTW
ControlNet I/O Transfer Instruction CIO
Using Block Transfer and %ORFNWUDQVIHULQVWUXFWLRQVOHW\RXWUDQVIHUZRUGVWRRUIURPDEORFN
ControlNet I/O WUDQVIHUPRGXOH&RQWURO1HW,2WUDQVIHULQVWUXFWLRQVOHW\RXSHUIRUP
XQVFKHGXOHGWUDQVIHUVWR,2PRGXOHVRQD&RQWURO1HWQHWZRUN
Transfer Instructions
7DEOH$OLVWVWKHDYDLODEOHEORFNWUDQVIHUDQG&RQWURO1HW,2
WUDQVIHULQVWUXFWLRQV
Table 15.A
Available Block Transfer and ControlNet I/O Transfer Instructions
Use this
If You Want to: Found on Page:
Instruction:
Transfer words to a block transfer module BTW 15-3
Transfer words from a block transfer BTR 15-3

module
Perform unscheduled transfers to I/O CIO 15-22

modules on a ControlNet network
$SSHQGL[&
Using Block Transfer Instructions :LWKEORFNWUDQVIHULQVWUXFWLRQV\RXFDQWUDQVIHUXSWRZRUGVDWD

WLPHWRRUIURPDEORFNWUDQVIHUPRGXOHLQDORFDORUUHPRWH,2
FKDVVLV<RXFDQDOVRWUDQVIHUXSWRZRUGVDWDWLPHEHWZHHQD
VXSHUYLVRU\SURFHVVRUVFDQQHUPRGHDQGDSURFHVVRUFRQILJXUHGIRU
DGDSWHUPRGH
7KH(QKDQFHG3/&SURFHVVRUVKDYHFRQILJXUDEOHFRPPXQLFDWLRQ
FKDQQHOVFKRRVHEHWZHHQUHPRWH,2VFDQQHUUHPRWH,2DGDSWHURU
'+/DGGHUEORFNWUDQVIHULQVWUXFWLRQVDUHQRWQHFHVVDU\ZKHQXVLQJ
(QKDQFHG3/&SURFHVVRUVLQDGDSWHUPRGH
7DEOH%GHVFULEHVKRZWREORFNWUDQVIHUGDWDWRDORFDORUUHPRWH
UDFNZKHQWKHSURFHVVRULVFRQILJXUHGIRUVFDQQHUPRGH)LJXUH
LOOXVWUDWHVKRZWKHWUDQVIHURFFXUV
1785-6.1 November 1998

15-2 Block-Transfer Instructions BTR and BTW ControlNet I/O Transfer Instruction CIO
Table 15.B
Block Transfer Instructions for Local or Remote Racks in Scanner Mode
If You Want to Transfer Data: Use:
To the BT I/O module BTW (block-transfer write)
From the BT I/O module BTR (block-transfer read)
Figure 15.1
Block Transfer Operation in Scanner Mode
One of Several Remote I/O Chassis
PLC-5 (supervisor) w/ 1771-ASB Adapter (processor)
1 B
7 T
BTD
File BTW 7
1 M
BTR o
- d
A u
S l
B e
7DEOH&GHVFULEHVKRZWREORFNWUDQVIHUGDWDZKHQWKHSURFHVVRU
LVFRQILJXUHGIRUDGDSWHUPRGH)LJXUHLOOXVWUDWHVKRZWKH
WUDQVIHURFFXUV
Table 15.C
Block Transfer Instructions for Adapter Mode
If You Want to Transfer Data: Use:
From the supervisory processor BTR (block-transfer read)
To the supervisory processor BTW (block-transfer write)
Figure 15.2
Block Transfer Operation in Adapter Mode
Supervisor Adapter
Processor PLC-5
Scanner
BTW BTR
BTD
BTR BTW File
Both processors simultaneously execute the opposite block transfer instruction.
1785-6.1 November 1998

Block-Transfer Instructions BTR and BTW ControlNet I/O Transfer Instruction CIO 15-3
Block-Transfer Read (BTR) and

Block-Transfer Write (BTW)
Description: :KHQWKHUXQJJRHVWUXHWKH%7:LQVWUXFWLRQWHOOVWKHSURFHVVRUWR
BTR
ZULWHGDWDVWRUHGLQWKHGDWDILOHWRWKHVSHFLILHGUDFNJURXSPRGXOH
BLOCK TRNSFR READ EN
DGGUHVVWKH%75LQVWUXFWLRQWHOOVWKHSURFHVVRUWRUHDGGDWDIURPWKH
Rack UDFNJURXSPRGXOHDGGUHVVDQGVWRUHLWLQWKHGDWDILOH
Group
DN
Module
Control Block
Data file ER
Block-Transfer Request Queue
Length
Continuous :KHQDIDOVHWRWUXHUXQJWUDQVLWLRQHQDEOHVD%7:RU%75
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For this Processor: The Queue Holds Up to:
Classic PLC-5 17 block transfer requests per logical rack
PLC-5/11, 5/20, -5/30 64 block transfer requests to remote racks

(maximum 64 per channel pair – 1A/1B); no limit for
requests to local racks
PLC-5/40, -5/60, -5/80 128 block transfer requests to remote racks

(maximum 64 per channel pair – 1A/1B, 2A/2B); no
limit for requests to local racks
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1785-6.1 November 1998

Table 15.D
Queue-Full Bits for Block Transfer Requests (Word 7) –
Classic PLC-5 Processors
Bit Description
S:7/8 Block-transfer queue for rack 0 is full
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Table 15.E
Valid Ranges for Rack Number in Block Transfer Instructions
Processor Maximum Racks Valid Range for Rack Numbers (octal)
PLC-5/10, -5/11, -5/12, 4 00-03

-5/15, -5/20, -5/VME
PLC-5/25, -5/30 8 00-07
PLC-5/40, -5/40L 16 00-17
PLC-5/60, -5/60L, -5/80 24 00-27
1785-6.1 November 1998

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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
word 0 EN ST DN ER CO EW NR TO RW rack group slot
word 1 requested word count
word 2 transmitted word count
word 3 file-type number
word 4 element number
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If You Set the

The Processor:
Length to:
0 Reserves 64 words for block transfer data. The block transfer

module transfers the maximum words it can handle.
1 to 64 Transfers the number of words specified.
1785-6.1 November 1998

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If You Specify: The Instruction Uses This Mode:
Yes Continuous – once the rung goes true, the instruction continues
to transfer data until the continuous (.CO) bit is reset and the
rung is false or you edit the instruction and specify NO for
continuous mode.
No Non-continuous – the instruction is enabled each time the

rung goes true and performs only one data transfer per
rung transition.
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This Bit: Is Set:
Enable .EN (bit 15) when the rung goes true. This bit shows that the instruction
is enabled (that the block transfer is in progress).
In non-continuous mode, the .EN bit remains set until the
block transfer finishes or fails and the rung goes false.
In continuous mode, once the .EN bit is set, it remains set
regardless of the rung condition.
Start .ST (bit 14) when the processor begins transferring data. The .ST bit is
reset at the false-to-true transition after the .DN bit or .ER
bit is set.
Done .DN (bit 13) at completion of the block transfer, if the data is valid. The
.DN bit is set asynchronous to the program scan so the .DN
bit may go true any time after the block transfer is initiated.
The .DN bit is reset the next time the associated rung goes
from false to true.
1785-6.1 November 1998

This Bit: Is Set:
Error .ER (bit 12) when the processor detects that the block transfer failed.
The .ER bit is reset the next time the associated rung goes
from false to true.
Continue .CO (bit 11) when you edit the instruction for repeated operation of the
block transfer after the first scan, independent of whether
the processor continues to scan the rung.
Reset the .CO bit if you want the rung condition to initiate
block transfers (return to non-continuous mode). If you are
using continuous block transfers in a sequential function
chart, see Appendix B, “SFC Reference,” in this manual.
Enable-waiting .EW when the block transfer request enters the queue. If the
(bit 10) queue is full, this bit remains reset until there is room in the
queue.
The .EW bit is reset when the associated rung goes from
false to true.
In continuous mode, once the .EW bit it set, it remains set.
Use the .EW bit to verify that a BTW or BTR instruction is
queued before leaving an SFC step.
No Response .NR (bit 09) if the block transfer module does not respond to the first
local block transfer request. The .NR bit is reset when the
associated rung goes from false to true (not used with
remote block transfer).
Time Out .TO (bit 08) if you reset the time out bit through ladder logic or data
monitor, the processor repeatedly tries to send a block
transfer request to an unresponsive module for four
seconds before setting the .ER bit.
If you set the .TO bit through ladder logic or data monitor,
the processor disables the four-second timer and requests
a block transfer one more time before setting the .ER bit.
Read-Write .RW (bit 07) controlled by the instruction. A 0 indicates a write

operation; a 1 indicates a read operation.
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1785-6.1 November 1998

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Table 15.F
Values in the Block Transfer Control Block
Word – Integer
BT Control Block Description
Control Bock
0 .EN through .RW Status bits
1 .RLEN Requested word count
2 .DLEN Transmitted word count / error code

(Enhanced PLC-5 processors)
3 .FILE File type / number
4 .ELEM Element number
Requested Word Count (.RLEN)

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Transmitted Word Count (.DLEN)

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1785-6.1 November 1998

Table 15.G
Enhanced PLC-5 Processor Block Transfer Error Codes
Error Description:
Number:
–1 not used
–2 not used
–3 The size of the block transfer plus the size of the index in the block transfer
data table was greater than the size of the block transfer data table file.
–4 There was an invalid transfer of block transfer write data between the
adapter and the block transfer module.
–5 The checksum of the block transfer read data was wrong.
–6 The block transfer module requested a different length than the associated
block transfer instruction. This could happen if a 64-word block transfer
instruction was executed and the block transfer module’s default length
was not 64 words.
–7 Block transfer data was lost due to a bad communication channel. Possible
reasons are noise, bad connections, and loose wires. Check resistors.
–8 Error in block transfer protocol – unsolicited block transfer.
–9 The block transfer timeout, set in the instruction, timed out before
completion.
–10 No communication channels are configured for remote I/O or rack number
does not appear in rack list.
–11 No communication channels are configured for the requested rack or slot.
–12 The adapter is faulted or not present for the BT command.
–13 Queues for remote block transfers are full.
File Number (.FILE)

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Element Number (.ELEM)

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1785-6.1 November 1998

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1785-6.1 November 1998

Figure 15.3
Timing Diagram for Status Bits in Continuous BTR and BTW Instructions
stage 3
EN
EW
ST
stage 2
CO stage 1
DN
ER
Rung true Request Instruction Instruction Rung false Rung true

enters the begins finishes
queue execution
Stage 1 - If .CO set, return to stage 2; if .CO reset, go to stage 3

Stage 2 - Return here for continuous operation
Stage 3 - Go here if .CO is reset
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1785-6.1 November 1998

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Figure 15.4
Timing Diagram for Status Bits in Non-Continuous BTR and BTW Instructions
EN
EW
ST
CO
DN
ER
Rung true Request Instruction Instruction Rung false Rung true

enters the begins finishes
queue execution
1785-6.1 November 1998

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Instruction Run Time

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Write: Read:
310 + 11.2Q + 5.4W 250 + 11.2Q
Where: Represents:
Q number of queued block transfer requests to the same I/O chassis

with the continuous bit set
W number of words to transfer
Waiting Time in the Queue

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Transfer Time
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Write: Read:
local 0.9 + 0.1W local 0.9 + 0.1W
remote (57.6K baud) 13 + 30C + 0.3W remote (57.6K baud) 9 + 21.3C + 0.3W
Where: Represents:
C number of full remote logical racks
1785-6.1 November 1998

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Waiting Time in the Holding Area

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Transfer Time
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local 600 µsec + x(w)
remote (57.6K baud) 4 + 8C + 0.3W
remote (115K baud) 4 + 4.6C + 0.15W
remote (230K baud) 4 + 3.2C + 0.075W
Where this: Represents:
x • 8 or less block transfers queued in local rack = 86 µsec

• more than 8 block transfers queued in local rack = 300 µsec
Note: This timing assumes that no other block transfers are queued to
the same slot and that successive block transfers to the same slot are
executed every 1000 µsec.
C number of full remote logical racks
1785-6.1 November 1998

Programming Examples 3URJUDP\RXUSURFHVVRUIRUEORFNWUDQVIHUXVLQJRQHRIWKHIROORZLQJ

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Table 15.H
Block Transfer Programming Methods
If You Want to: Use this Method:
Program block transfers to and from the same Bidirectional alternating

module when you want the order of execution to
follow the same order scanned in the program
Continuously repeat bidirectional alternating block Bidirectional alternating repeating

transfers and the step will be scanned
Program block transfers to and from the same Bidirectional continuous*

module when you want the transfers to continue
regardless of which SFC steps are active
Program a BTR from, or a BTW to a module when Directional non-continuous

you want the block transfer to execute based on
an event
Continuously repeat a block transfer and the step Directional repeating

will be scanned
Program a BTR from or BTW to a module when you Directional continuous*

want the transfer to continue regardless of which
SFC steps are active
Ensure block integrity Buffering block transfer data
* Only use continuous mode when you want a block transfer to continue executing even when
the logic which controls it is not being scanned.
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SURFHVVRUVXEVWLWXWHDQDSSURSULDWHLQWHJHUILOH
1785-6.1 November 1998

Example Bidirectional Alternating Block-Transfer

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DVWKHRSWLRQDOFRQGLWLRQLVWUXH
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Figure 15.5
Example Bidirectional Alternating Block Transfer
BTR
Precondition BT10:0 BT10:1 BLOCK TRANSFER READ EN
Rack 3
EN EN Group 2
Module 0 DN
BTR BTW
enable bit enable bit Control Block BT10:0
Data file N11:0 ER
Length 10
Continuous N0
BTW BTR
enable bit enable bit BTW
Precondition BT10:1 BT10:0 BLOCK TRANSFER WRITE EN
Rack 3
EN EN Group 2
DN
Module 0
Control Block BT10:1
Data file N11:10 ER
Length 11
Continuous NO
Block-transfer rungs must be scanned for the transfers to occur.
The preconditions allow time-driven or event-driven transfers.
1785-6.1 November 1998

Example Bidirectional Alternating Repeating Block-Transfer

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;,2FRQGLWLRQVSUHYHQWVWKHEORFNWUDQVIHUUHDGDQGEORFNWUDQVIHU
ZULWHIURPTXHXHLQJVLPXOWDQHRXVO\7KHEORFNWUDQVIHUVFRQWLQXHDV
ORQJDVWKHVWHSLVVFDQQHG
Figure 15.6
Example Bidirectional Alternating Repeating Block Transfer
BTR
BT10:0 BT10:1 BLOCK TRANSFER READ EN
Rack 3
EN EN Group 2
Module 0 DN
BTR BTW
enable bit enable bit Control Block BT10:0
Data file N11:0 ER
Length 10
Continuous N0
BTW BTR
enable bit enable bit BTW
BT10:1 BT10:0 BLOCK TRANSFER WRITE EN
Rack 3
EN EN Group 2
DN
Module 0
Data file N11:10 ER
Length 11
Continuous NO
Block-transfer rungs must be
scanned for the transfers to occur.
1785-6.1 November 1998

Example Bidirectional Continuous Block-Transfer

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Figure 15.7
Example Bidirectional Continuous Block Transfer
BTR
Preconditions BLOCK TRANSFER READ EN
Rack 3
Group 6
Module 1 DN
Data file N7:100 ER
Length 0
Continuous YES
BTW
BLOCK TRANSFER WRITE EN
Preconditions
Rack 3
Group 6
Module 1 DN
Scan the rung once to start continuous block transfers. The continuous Data file N7:200 ER
operation starts on a false-to-true rung transition and continues,
Length 0
whether or not the rungs are scanned again. To stop continuous
operation, use the Data Monitor to reset the continuous bit (.CO or Continuous YES
bit 11), or change the Continuous field in the instruction to NO.
BT10:0 BT10:0
U
ER EN
BT10:1 BT10:1
U
ER EN
These rungs will reset block transfers and should be placed in logic where rungs are
being scanned for error recovery. Your logic must rescan the block transfers with
preconditions true in order to restart continuous block transfers.
1785-6.1 November 1998

Example Directional Non-Continuous Block-Transfer

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Figure 15.8
Example Directional Non-Continuous Block Transfer
BTR
Precondition BLOCK TRANSFER READ EN
Rack 2
Group 5
Module 1 DN
Data file N7:500 ER
Use the same method for a BTW. The rung Length 0
must go from false to true for the transfer Continuous NO
to occur.
Example Directional Repeating Block Transfer

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Figure 15.9
Example Directional Repeating Block Transfer
BTR
Rack 2
EN Group 5
Module 1 DN
Data file N7:500 ER
Use the same method for a BTW. The block Length 0
transfer will continue as long as the step Continuous NO
is scanned.
1785-6.1 November 1998

Example Directional Continuous Block-Transfer

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Figure 15.10
Example Directional Continuous Block Transfer
BTR
Precondition BLOCK TRANSFER READ EN
Rack 2
Group 5
Module 1 DN
Data file N7:500 ER
Use the same method for a BTW. Scan the rung once Length 0
to start continuous block transfers. The continuous Continuous YES
operation starts on a false-to-true rung transition and
continues, whether or not the rungs are scanned
again. To stop continuous operation, use the Data
Monitor to reset the continuous bit (.CO or bit 11), or
change the Continuous field in the instruction to NO.
BTR
error bit
BTR
BT10:0 BT10:0 enable bit
U
ER EN
This rung will reset block transfers and should be placed in logic where rungs are being
scanned for error recovery. Your logic must rescan the block transfers with preconditions
true in order to restart continuous block transfers.
1785-6.1 November 1998

Example Buffering Block Transfer-Data

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GRQHELWLVWUXH7KLVHQVXUHVILOHLQWHJULW\RIWKHEORFNWUDQVIHUUHDG
GDWDILOH
BTR
Rack 2
EN Group 2
Module 1 DN
BTR
enable bit Control Block BT10:0
Data File N7:400 ER
Length 4
Continuous NO
FAL
BT10:0 FILE ARITH/LOGICAL EN
Control R6:4
DN Length 4
DN
BTR Position 0
done bit Mode ALL
Expression #N7:400
1785-6.1 November 1998

ControlNet I/O Transfer (CIO) 8VLQJWKH&,2LQVWUXFWLRQ\RXFDQSHUIRUPODGGHULQLWLDWHG

Instruction XQVFKHGXOHGWUDQVIHUVXSWRHOHPHQWVWR,2PRGXOHVW\SLFDOO\
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CIO
EN
CNET I/O TRANSFER
DN
Control Block CT21:50
ER 3URJUDPPDEOH&RQWUROOHUV8VHU0DQXDO
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SDUDPHWHUVWKHSURJUDPPLQJWHUPLQDOGLVSOD\VDQLQVWUXFWLRQHQWU\
VFUHHQIURPZKLFK\RXHQWHULQVWUXFWLRQSDUDPHWHUVVWRUHGLQWKH
FRQWUROEORFNDGGUHVV
Control Block Address

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ILOHW\SHIRUWKHFRQWUROEORFN)RUH[DPSOH&7LVDYDOLG&,2
FRQWUROEORFNDGGUHVV
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1785-6.1 November 1998

Using the CIO Instruction <RXFDQXVHWKH&,2LQVWUXFWLRQWRWUDQVIHUXSWRHOHPHQWVRIGDWD

SHU&,2LQVWUXFWLRQRYHUD&RQWURO1HWOLQN7KHLQVWUXFWLRQHQWU\
VFUHHQIRUWKH&,2LQVWUXFWLRQOHWV\RXFRQILJXUHWKHIROORZLQJ
LQIRUPDWLRQ7DEOH,
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Table 15.I
CIO Instruction Entry Screen Configuration
If You Want to: Press this Key:
Change the command type. Toggle among the following: [F1] – Command Type
• 1771 Read selects a block transfer read.
• 1771 Write selects a block transfer write.
• 1794 Fault Action selects the action the module takes
when the adapter faults and the connection is terminated.
• 1794 Idle Action selects the action the module takes when
the connection is idle.
• 1794 Config Data changes the configuration for the 1794
module.
• 1794 Safe State Data changes the value of the safe state
data for the 1794 module.
Enter a PLC-5 data table address of the ControlNet processor. [F2] – PLC-5 Address
Enter the size in elements. [F3] – Size in Elements

Type the number of elements and press [Enter].
• 1 (1794 Fault Action and 1794 Idle Action)
• 1-15 (1794 Config Data and 1794 Safe State Data)
• 0-64 (1771 Read and 1771 Write)
Note: If you enter 0 for 1771 Read and/or 1771 Write, 64
words are reserved for block transfer.
Enter the destination network address. [F8] – Local Node

Type a number (1-99) and press [Enter].
Enter the destination slot number. [F9] – Slot Number

Type a number and press [Enter].
• 0-7 (1794 command types)
• 0-15 (1771 command types)
Note: The slot number represents the physical slot in the
chassis occupied by the module. To find your slot number,
count from the left I/O slot starting with 0.
1785-6.1 November 1998

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7DEOH-
Table 15.J
CIO Instruction Control Block Parameters
Toggle the control bit that the cursor is on. You can toggle [F2] – Toggle Bit
among the TO, EW, CO, ER, DN, ST, and EN bits.
Change the size of the block of data to send or receive. [F3] – Size in Elements
Change the address for which the data is displayed. [F5] – Specify Address
Display the data table values for the next file. [F7] – Next File
Display the data table values for the previous file. [F8] – Previous File
Display the data table values for the next element. [F9] – Next Element
Display the data table values for the previous element. [F10] – Previous Element
Using Status Bits 7KH&,2LQVWUXFWLRQXVHVWKHIROORZLQJVWDWXVELWV
This Bit: Is Set:
Enable .EN (bit 15) when the rung goes true. The .EN bit is reset when the .DN bit or .ER bit is set.
This bit shows that the instruction is enabled.
Start .ST (bit 14) when the processor begins executing the CIO instruction. The .ST bit is reset when the
.DN bit or .ER bit is set.
Done .DN (bit 13) when the last word of the CIO instruction transferred. The .DN bit is reset the next time
the associated rung goes from false to true.
The .DN bit is only active in non-continuous mode.
Error .ER (bit 12) when the processor detects that the message transfer failed. The .ER bit is reset the next
time the associated rung goes from false to true.
Continue .CO (bit 11) manually for repeated operation of the CIO instruction after the first scan, independent of
whether the processor continues to scan the rung.
Enable-Waiting .EW (bit 10) when the processor detects that a message request entered the queue. The processor
resets the .EW bit when the .ST bit is set.
Time Out .TO (bit 08) through ladder logic to stop processing the message. The processor sets the .ER bit.
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1785-6.1 November 1998

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Using the CT Control Block

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Word: CT Control Block: Description:
0 .EN through .TO Status bits

See “Using Status Bits” above.
1 .ERR Error code

This is where the processor stores the error code if a problem occurs during
message transmission.
2 .RLEN Requested length

This is the requested number of elements you wish to transfer with the
message instruction.
3 .DLEN Done length

This is the number of elements the module actually transferred after the instruction
completes execution. This number should match the requested length (unless the
requested length is 0).
4 .FILE File number

This number identifies the file number of the file from which the data is written or to
which the data is read. For example, the file number of N12:1 is 12.
5 .ELEM Element number

This number identifies the starting word in the data file address. For example, in
N12:1, the word number is 1.
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 16
Message Instruction MSG
Using the Message Instruction 7KHPHVVDJHLQVWUXFWLRQ06*LVXVHGWRUHDGRUZULWHDEORFNRI
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LQVWUXFWLRQLQODGGHUORJLF
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Message (MSG)
Description: 7KH06*LQVWUXFWLRQWUDQVIHUVXSWRHOHPHQWVRIGDWD

MSG
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SEND/RECEIVE MESSAGE
EN GHSHQGVRQWKHGDWDWDEOHVHFWLRQ\RXVSHFLI\DQGWKHW\SHRIPHVVDJH
Control Block DN FRPPDQG\RXXVH)RUH[DPSOHRQHELQDU\HOHPHQWFRQWDLQVRQH
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1785-6.1 November 1998

16-2 Message Instruction MSG
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Processor
Processors:
Series/Revision:
Series A / revision M PLC-5/40, -5/40L, -5/60, -5/60L
Series A / revision J PLC-5/30
Series A / revision H PLC-5/11, -5/20
Series B / revision J PLC-5/40, -5/40L, -5/60, -5/60L
Series C / revision G Enhanced, Ethernet, and VME PLC-5 processors
Series C / revision H ControlNet PLC-5
Series D / revision A Enhanced, Ethernet, ControlNet, and VME PLC-5 processors
Entering Parameters 6SHFLI\DFRQWUROEORFNDGGUHVVZKHQ\RXILUVWHQWHUWKH06*

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WRWKHPHVVDJHZLOOEHVWRUHG$IWHUHQWHULQJWKHFRQWUROEORFNWKH
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IURPZKLFK\RXHQWHULQVWUXFWLRQSDUDPHWHUVWKDWDUHVWRUHGDWWKH
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WKH06*LQVWUXFWLRQWRHGLWVHOHFWHGSDUDPHWHUV

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V\PEROIRUWKHPHVVDJHFRQWUROEORFN)RUH[DPSOH1LVDYDOLG
06*FRQWUROEORFNDGGUHVV
If You Have this Processor: Use this Control Block Address:
Classic PLC-5 an integer file (N) without the # symbol for the message
control block. Example: N7:0
Enhanced PLC-5, Ethernet an integer file (N) or the message (MG) file type to
PLC-5, or VME PLC-5 access the message control block for DH+ transfers.
Example: MG10:0
Using the MG control block, the control block size is

fixed at 56 words. This size is displayed on the screen
in the BLOCK SIZE field. You must use the MG control
block if you are sending messages to an SLC 500
processor using the SLC read and write commands, or
if you are sending message out any port other than
channel 1A.
Ethernet PLC-5, ControlNet a message (MG) file type to access the VMEbus,
PLC-5, VME PLC-5 Ethernet, or ControlNet network
1785-6.1 November 1998

Message Instruction MSG 16-3
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06*LQVWUXFWLRQ,I\RXKDYHDQ06*LQVWUXFWLRQFUHDWHGZLWK
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LQGLUHFW DGGUHVV
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&RQWURO1HWQHWZRUNWKH06*LQVWUXFWLRQPXVWEHSURJUDPPHGZLWK
DQ0*GDWDW\SHLQWKHFRQWUROEORFN
7KHFRQWUROEORFNVL]HYDULHVDFFRUGLQJWRWKHOHQJWKRIWKHPHVVDJH
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DSSUR[LPDWHO\RUZRUGV,I\RXFRPPXQLFDWHZLWKD3/&
3/&RU3/&SURFHVVRUWKHFRQWUROILOHZLOOEHDSSUR[LPDWHO\
WRZRUGV7KLVVL]HLVGLVSOD\HGRQWKHVFUHHQLQWKH BLOCK
SIZEILHOG
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WRDFFHVVWKHPHVVDJHFRQWUROEORFNIRU'+WUDQVIHUV)RUH[DPSOH
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SURFHVVRUV8VLQJWKH0*ILOHW\SHWKHFRQWUROEORFNVL]HLVIL[HGDW
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ZDUQLQJZKHQ\RXVHOHFWSRUW
MSG Data Entry Screen

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PHVVDJH3UHVVWKHIXQFWLRQNH\IRUWKHGDWD\RXZDQWWRPRGLI\<RX
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This Function Key: Specifies this Information:
[F1] – Command Type Whether the MSG instruction performs a read or write operation and to what type of
processor the message is going to.
[F2] – PLC-5 Address The data file address of the processor containing the message instruction. If the
MSG operation is write, this address is the starting word of the source file. If the
MSG operation is read, this address is the starting word of the destination file.
[F3] – Size in Elements The number of elements (1-1000) to be transferred.
1785-6.1 November 1998

This Function Key: Specifies this Information:
[F4] – Local/Remote LOCAL: the message is sent to a device on the local DH+ link.
REMOTE: the message is sent through a bridge (DH, DH II, etc.) to another
DH+ link.
If you select REMOTE, the function keys [F5] – Remote Station, [F6] – Link ID, and
[F7] – Remote Link are active.
[F5] – Remote Station The DH or DH II address (1-376 octal) of the target station.
PLC-2 and PLC-3 processors require communication adapter modules (1771-KA2

and 1775-KA, respectively) when they operate as stations on data highway. In these
configurations, the remote station address is the address of the communication
adapter module.
[F6] – Link ID The remote link where the processor you want to communicate with resides. The
default is 0.
[F7] – Remote Link Toggles through DH, DH II, and other choices for what connects the remote link to
the local DH+.
[F8] – Local Node The local station address on the DH+ (0-77 octal).
If you communicate with another processor on the local link, this address is the
address of the target station on the local link.
If you communicate with a target station on a remote link, this address is the station
number of the communication adapter module that bridges the data highway.
[F9] – Destination Address The starting address of the source or destination file in the target processor.
[F10] – Port Number The channel for message communications. Valid options are: 0, 1A (default), 1B, 2A,
2B, and 3A for the ASCII command.
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Using the Message Instruction for 7KHPHVVDJH06*LQVWUXFWLRQWUDQVIHUVXSWRHOHPHQWVRI

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1785-6.1 November 1998

This Field: Specifies this Information:
Command Type Whether the MSG instruction performs a read or write operation. The software
toggles between:
• PLC-5 Typed Read
• PLC-5 Typed Write
• PLC-5 Typed Write to SLC
• PLC-5 Typed Read from SLC
• SLC Typed Logical Read
• SLC Typed Logical Write
• PLC-2 Unprotected Read
• PLC-2 Unprotected Write
• PLC-3 Word Range Read
• PLC-3 Word Range Write
• ASCII
PLC-5 Address The data file address of the processor containing the message instruction. If the
MSG operation is write, this address is the starting word of the source file. If the
MSG operation is read, this address is the starting word of the destination file.
Size in Elements The number of elements (1-1000) to be transferred.
IP Address The MSG instruction’s destination node.

• If the destination is another PLC-5/20E, -5/40E, or -5/80E, the destination must be
a full Internet address
• If the destination is an INTERCHANGE™ client program, enter the word “CLIENT”
as the destination node. Do not enter an IP address.
Note: You must set [F10] – Port Number to 2 in order to access this function.
Destination Address The starting address of the source or destination file in the target processor.
Port Number The channel for message communications. Ethernet communications use channel 2.
Multihop Select yes if you want to send the MSG instruction to a ControlLogix device. Then use
the Multihop tab to specify the path of the MSG instruction. For more information, see
“Configuring an Ethernet Multihop MSG Instruction” on page 16-9.
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Command Type Whether the MSG instruction performs a read or write operation. The software
toggles between:
• PLC-5 Typed Read
• PLC-5 Typed Write
• PLC-5 Typed Write to SLC
• PLC-5 Typed Read from SLC
• SLC Typed Logical Read
• SLC Typed Logical Write
• PLC-2 Unprotected Read
• PLC-2 Unprotected Write
• PLC-3 Word Range Read
• PLC-3 Word Range Write
• ASCII
PLC-5 Address The data file address of the processor containing the message instruction. If the MSG
operation is write, this address is the starting word of the source file. If the MSG
operation is read, this address is the starting word of the destination file.
Host/IP Address The MSG instruction’s destination node.

•If the destination is an Enhanced PLC-5 processor, the destination must be a full
Internet address
•If the destination is an INTERCHANGE client program, enter the word “CLIENT”
as the destination node. Do not enter an IP address.
Note: You must set [F10] – Port Number to 2 in order to access this function.
Port Number The channel for message communications. The PLC-5 Ethernet Interface Module
communications use channel 3A.
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Ethernet PLC-5 processor

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ControlLogix chassis
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Command Type Change the command type. Toggle between the following:
• PLC-5 Typed Write selects a write operation to a ControlNet PLC-5 processor
• PLC-5 Typed Read selects a read operation from another ControlNet PLC-5
processor
PLC-5 Address The PLC-5 data table address of the ControlNet processor. If the MSG operation is
write, this address is the starting word of the source file. If the MSG operation is read,
this address is the starting word of the destination file.
Local Node The destination node address (1-99).
Port Number The channel for message communications. The port number must be 2 for ControlNet.
Multihop Select yes if you want to send the MSG instruction to a ControlLogix device. Then use
the Multihop tab to specify the path of the MSG instruction. For more information, see
“Configuring an ControlNet Multihop MSG Instruction” on page 16-11.
1785-6.1 November 1998

Configuring a ControlNet Multihop 7KHVHULHV)UHYLVLRQ$DQGODWHU&RQWURO1HW3/&SURFHVVRUVFDQ

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ControlLogix chassis
SLC 5/05 Processor
DH+ ControlNet

PLC-5 Processor
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This Bit: Is Set:
Enable .EN (bit 15) when the rung goes true. This bit shows that the instruction is enabled (that the
instruction is being executed). In non-continuous mode, .EN bit remains set until the
message is completed and the rung goes false. In continuous mode, once .EN bit is set, it
remains set regardless of the rung condition.
Start .ST (bit 14) when the processor begins executing the MSG instruction. The .ST bit is reset when the
.DN bit or .ER bit is set.
Done .DN (bit 13) when the last packet of the MSG instruction transferred. The .DN bit is reset the next
time the associated rung goes from false to true. The .DN bit is only active in
non-continuous mode.
Error .ER (bit 12) when the processor detects that the message transfer failed. The .ER bit is reset the next
time the associated rung goes from false to true.
Continue .CO (bit 11) manually for repeated operation of the MSG instruction after the first scan, independent
of whether the processor continues to scan the rung. Reset the .CO bit if you want the
rung condition to initiate messages (return to non-continuous mode).
Enable-Waiting .EW (bit 10) when the processor detects that a message request entered the queue. The processor
resets the .EW bit when the .ST bit is set.
No Response .NR (bit 09) if the target processor does not respond to the first MSG request. The .NR bit is reset
when the associated rung goes from false to true.
Time Out .TO (bit 08) if you set the .TO bit through ladder logic, the processor stops processing the message
and sets the .ER bit (timeout error 55). A DH+ message time out in 30-60 seconds. A
ControlNet message will time out in 4 seconds
No Cache .NC if you set the .NC bit, the open connection is closed when the MSG is done. If this bit
(ControlNet processors only) remains reset, the connection remains open even when the MSG is complete.
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1785-6.1 November 1998

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Table 16.A
Values in the Control Block
Word – Integer
Message Control Block Description
Control Block
0 .EN thru .RW Control bits
0 - low byte .ERR Error code
2 - high byte .RLEN Requested length
2 - low byte .DLEN Done length
3 Internal data
Error Code (.ERR)

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1785-6.1 November 1998

Entering Parameters Communication Command

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If You Want the Instruction to: Select the Command:
Read data identified by a type code. This command reads data structures without you specifying the PLC-5 Typed Read
actual word length. For example, if you choose a typed read of the PLC-5 timer data section with a
requested data size of 5 elements, the MSG instruction reads 15 words (5 timer structures of 3
words each).
Write data identified by a type code. This command writes data structures without you specifying the PLC-5 Typed Write
actual word length.
Read 16-bit words from any area of the PLC-2 data table or PLC-2 compatibility file. PLC-2 Unprotected Read
Write 16-bit words to any area of the PLC-2 data table or PLC-2 compatibility file. PLC-2 Unprotected Write
Read data identified by a type code. This command reads data structures without specifying the actual PLC-5 Typed Read from SLC2, 3
word length. This command provides additional data verification for communications between a PLC-5
and SLC 500 processor.1
Write data identified by a type code. This command writes data structures without specifying the actual PLC-5 Typed Write to SLC2, 3
word length. This command provides additional data verification for communications between a PLC-5
and SLC 500 processor.1
Read a range of words, starting at the address specified for the external address in the MSG control file SLC Typed Logical Read3
and reading sequentially the number of words specified for the requested size field in the MSG control
file. The data that is read is stored, starting at the address specified fro the internal address in the MSG
control file. This is used for communicating between a PLC-5 and SLC 500 processor.1
Write a range of words, starting at the address specified for the internal address in the MSG control file SLC Typed Logical Write3
and writing sequentially the number of words specified for the requested size field in the MSG control file.
The data from the internal address is written, starting at the address specified for the external address in
the MSG control file. This is used for communicating between a PLC-5 and SLC 500 processor.1
Read a range of words, starting at the address specified for the external address in the MSG control file PLC-3 Word Range Read
and reading sequentially the number of words specified for the requested size field in the MSG control
file. The data that is read is stored, starting at the address specified for the internal address in the MSG
control file.
Write a range of words, starting at the address specified for the internal address in the MSG control file PLC-3 Word Range Write
and writing sequentially the number of words specified for the requested size field in the MSG control file.
The data from the internal address is written, starting at the address specified for the external address in
the MSG control file.
1The PLC-5 is limited to a maximum message of 103 words (206 bytes). The maximum message size for SLC 5/03™ and SLC 5/04™ processors is 103 words
(206 bytes). The maximum message size capability of all other SLC 500 processors is 41 words (82 bytes).
2
These commands are valid only with any SLC 5/04 and SLC 5/03 series C and later processors.
3
These commands are only valid with processors listed in the table on page 16-2.
<RXFDQXVHWKH7\SHG5HDGDQG7\SHG:ULWHFRPPDQGVWRWUDQVIHU
GDWDWDEOHVHFWLRQVZLWKRXWFRXQWLQJWKHDFWXDOZRUGVSHUGDWDWDEOH
HOHPHQW<RXRQO\KDYHWRVSHFLI\WKHQXPEHURIHOHPHQWV\RXZDQW
WRWUDQVIHU)RUH[DPSOHLQWKHGDWDWDEOHWLPHUVHFWLRQRQHHOHPHQW
FRQWDLQVZRUGVEXWLQWKHELQDU\GDWDWDEOHVHFWLRQRQHHOHPHQW
FRQWDLQVRQHZRUG
1785-6.1 November 1998

External Data Table Addresses

7KHIROORZLQJWDEOHOLVWVWKHYDOLGH[WHUQDOGDWDWDEOHDGGUHVVHV
This Communication Command: To this Device: Requires that You Enter: Example Address:
PLC-5 Typed Read PLC-5/250 the address in double quotes “1N0:0”
PLC-5 Typed Write PLC-5 the address N7:0
1775-S5 the address in double quotes, “$N7:0”

precede with a $ character
1775-SR5
PLC-2 Unprotected Read PLC-2 octal number of 16-bit 025

PLC-2 Unprotected Write PLC-2 word offset
compatibles
PLC-3 Word Range Read PLC-5/250 the address in double quotes “1N7:0”
PLC-3 Word Range Write
PLC-5 the address in double quotes, “$N7:0”
precede with a $ character
1775-S5 the address in double quotes, “$N7:0”

precede with a $ character, or N7:0
1775-SR5 just the address (which will
be slightly faster)
1771-DMC the address in double quotes “01”

Control “00’ to “31” to match
Coprocessors C program
SLC Typed Logical Read SLC 500 the address N7:0

SLC Typed Logical Write processors
PLC-5 Typed Read to SLC SLC 5/03 and the address N7:0
PLC-5 Typed Write from SLC 5/04 processors
PLC-2 to PLC-5 Compatibility Files

,QRUGHUWRVHQGDPHVVDJHEHWZHHQD3/&DQGD3/&\RXPXVW
XVHD3/&FRPSDWLELOLW\ILOHZLWKLQWKH3/&SURFHVVRU7KLVILOH
QXPEHUPXVWEHWKHGHFLPDOHTXLYDOHQWRIWKHRFWDODGGUHVVRIWKH
3/&:HUHFRPPHQGWKDWWKHRFWDODGGUHVVRIWKH3/&EHJUHDWHU
WKDQVRWKDWLWGRHVQRWLQWHUIHUHZLWKWKHGHIDXOW3/&GDWDILOHV
)RUH[DPSOHLID3/&LVDWVWDWLRQDQ\PHVVDJHLWVHQGVWRD
3/&GHIDXOWVWRILOHLQWKH3/&GHFLPDOHTXLYDOHQWWRRFWDO
$OVRQRWHWKDWVLQFHWKH3/&DGGUHVVHVLVRFWDOLI\RXKDYHD
3/&DGGUHVVDVLQDZULWHFRPPDQGWKHZULWHDFWXDOO\RFFXUV
LQWKH3/&¶VZRUGGHFLPDOHTXLYDOHQWWRRFWDO
1785-6.1 November 1998

Sending SLC Typed Logical Read and Typed Logical

Write Commands
)ROORZWKHVHJXLGHOLQHVZKHQSURJUDPPLQJ6/&7\SHG/RJLFDO5HDG
DQG6/&7\SHG/RJLFDO:ULWHFRPPDQGV
<RXPXVWXVHWKH0*GDWDW\SHIRUWKH06*FRQWUROEORFN
3/&'DWD7DEOH$GGUHVVDQGWKH'HVWLQDWLRQDGGUHVVW\SHV
VKRXOGPDWFKZKHQWKHGDWDW\SHLVVXSSRUWHGE\WKH3/&DQG
6/&DQGSURFHVVRUV,I\RXZDQWWRVHQGDGDWDW\SH
WKDWWKH6/&RUSURFHVVRUVGRQRWVXSSRUWWKH6/&
SURFHVVRUVLQWHUSUHWWKDWGDWDDVLQWHJHU7KLVWDEOHPDSVWKHGDWD
W\SHVIURPWKH3/&SURFHVVRUVWRWKH6/&DQG
SURFHVVRUV
Is Interpreted by the SLC 5/03

This PLC-5 Data Type:
and 5/04 Processors as:
Binary (B) Bit
Integer (N) Integer
Output (O) Integer
Input (I) Integer
Status (S) Integer
ASCII (A) ASCII
BCD (D) Integer
SFC status (SC) Integer
String (ST) String
BT control (BT) Integer
ControlNet transfer (CT) Integer
Timer (T) Timer
Counter (C) Counter
Control (R) Control
Float (F) Float
MSG control (MG) Integer
PID control (PD) Integer
7RUHDGZULWHIURPWKH6/&LQSXWRXWSXWUHDGRQO\RUVWDWXV

ILOHVSHFLI\DQLQWHJHU3/&'DWD7DEOH$GGUHVVDQGVSHFLI\WKH
DGGUHVVRIWKH6/&LQSXWRXWSXWRUVWDWXVILOH)RUH[DPSOH6
IRUZRUGRIWKH6/&VWDWXVILOH6SHFLI\6/&LQSXWRXWSXW
DGGUHVVHVE\ORJLFDOIRUPDWLH2UHIHUHQFHVVORW
1785-6.1 November 1998

3/&$6&,,GDWDLVE\WHGDWDZRUGZKHUHDVDQ6/&

$6&,,GDWDHOHPHQWLVRQHZRUG7KHUHIRUHLI\RXUHTXHVWDQ
3/&7\SHG5HDGRIHOHPHQWVWKH6/&SURFHVVRUVHQGV
DSDFNHWFRQWDLQLQJE\WHVZRUGV
3/&SURFHVVRUVDOORZVHOHPHQWVIRUPRVWGDWDW\SHV
ZKHUHDV6/&SURFHVVRUVRQO\DOORZHOHPHQWV
Monitoring a Message Instruction 7RPRQLWRURUHGLW06*LQVWUXFWLRQSDUDPHWHUVDQGVWDWXVELWVDIWHU

\RXHQWHUWKH06*LQVWUXFWLRQGLVSOD\WKHGDWDPRQLWRUVFUHHQIRUWKH
06*LQVWUXFWLRQDQGILOHW\SH\RXDUHXVLQJ
If You Are Using this File Type: See:
integer (N) Table 16.B
message (MG) Table 16.C
,I\RXDUHXVLQJDQLQWHJHU1ILOHW\SH\RXFDQGRWKHIROORZLQJ
IURPWKHGDWDPRQLWRUVFUHHQ7DEOH%
Table 16.B
Data Monitor Screen for the MSG Instruction – N File Type
specify the number of elements (1-1000) you [F3} – Size in Elements

want to read from or write to the network station
set and reset status bits [F9] – Toggle Bit
,I\RXDUHXVLQJDQPHVVDJH0*ILOHW\SH\RXFDQGRWKHIROORZLQJ
IURPWKHGDWDPRQLWRUVFUHHQ7DEOH&
Table 16.C
Data Monitor Screen for the MSG Instruction – MG File Type
Toggle the control bit that the cursor is on. [F2] – Toggle Bit
You can toggle among the TO, NR, EW, CO, ER, DN, ST, and
EN bits
Change the size of the block of data to send or receive. [F3] – Size in Elements
Change the address for which the data is displayed. [F5] – Specify Address
Display the data table values for the next file. [F7] – Next File
Display the data table values for the previous file. [F8] – Previous File
Display the data table values for the next element. [F9] – Next Element
Display the data table values for the previous element. [F10] – Previous Element
1785-6.1 November 1998

Selecting Continuous Operation &RQWLQXRXVPRGHOHWV\RXXVHPXOWLSOHPHVVDJHWUDQVIHUVE\

SURJUDPPLQJRQO\RQH06*LQVWUXFWLRQZLWKQRLQSXWFRQGLWLRQVRQ
WKHUXQJ2QFHWKHFRQWLQXRXVPHVVDJHWUDQVIHUVWDUWVWKHWUDQVIHULV
FRQWLQXRXVO\H[HFXWHGLQGHSHQGHQWRIZKHWKHUWKHSURFHVVRU
FRQWLQXHVWRVFDQWKHDVVRFLDWHGUXQJDQGLQGHSHQGHQWRIWKHUXQJ
FRQGLWLRQ7RHQDEOHFRQWLQXRXVRSHUDWLRQVHWWKH&2ELW
$77(17,21 )RUFRQWLQXRXVPRGHWRRSHUDWH
FRUUHFWO\\RXPXVWVHWWKH&2ELWHLWKHURQWKH
FRQILJXUDWLRQVFUHHQRUWKURXJKODGGHUORJLFEHIRUH\RX
HQDEOHWKH06*LQVWUXFWLRQ
&RQWLQXRXVPRGHZRUNVDVIROORZV)LJXUH
:KHQWKHUXQJWKDWFRQWDLQVWKH06*LQVWUXFWLRQJRHVWUXHWKH
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SURFHVVRUDOVRUHVHWVWKH(5DQG'1ELWV
7KHSURFHVVRUWKHQTXHXHVWKHPHVVDJHUHTXHVW:KHQWKH
PHVVDJHUHTXHVWHQWHUVWKHTXHXHWKHSURFHVVRUVHWVWKH(:ELW
:KHQWKHSURFHVVRUVWDUWVWRSURFHVVWKHPHVVDJHUHTXHVWWKH
SURFHVVRUVHWVWKH67ELW7KHQH[WWLPHWKHSURFHVVRUUHFHLYHV
QHWZRUNFRQWUROWKHSURFHVVRUWUDQVPLWVWKHPHVVDJH
,IDQHUURURFFXUVWKHSURFHVVRUVHWVWKH(5ELWDQGVWRUHVDQ
HUURUFRGHLQWKHORZHUE\WHRIZRUGRIWKHFRQWUROEORFNIRU
&ODVVLF3/&SURFHVVRUVDQGZRUGRIWKHFRQWUROEORFNIRU
(QKDQFHG3/&SURFHVVRUV
,PSRUWDQW )LJXUHLVDSSURSULDWHIRU(QKDQFHG3/&
SURFHVVRUVRQO\<RXFDQUHVHW&ODVVLF3/&
SURFHVVRUVE\WRJJOLQJWKHHUURURUHQDEOHELWV
1785-6.1 November 1998

Figure 16.1
Timing Diagram for Status Bits in Continuous MSG Instructions
EN
EW
A
ST
CO
DN
ER
Rung true Data sent by MSG begins MSG Rung false Rung true
instruction transmission transmission
and received on network completes
in the queue
these events are asynchronous to ladder program scan
A When the MSG transmission completes, the cycle starts over here without rung transitions
$FRQWLQXRXVPHVVDJHWUDQVIHUFRQWLQXHVDVORQJDVWKHSURFHVVRU
VWD\VLQ5XQRU7HVWPRGH,I\RXVZLWFKWR3URJUDPPRGHRUWKH
SURFHVVRUIDXOWVWKHPHVVDJHWUDQVIHUVWRSVDQGZLOOQRWVWDUWDJDLQ
XQWLOWKHSURFHVVRUVFDQVWKHUXQJWKDWFRQWDLQVWKH06*LQVWUXFWLRQ
7RVWRSFRQWLQXRXVRSHUDWLRQUHVHWWKH&2ELW
(DUOLHU3/&SURFHVVRUVSULRUWRVHULHV(UHVHWWKH(1ELWRID
FRQWLQXRXV06*ZKHQHYHUWKHUXQJLVVFDQQHGIDOVHDQGWKH'1RU
(5ELWLVVHW6HULHV(DQGODWHUSURFHVVRUVOHDYHWKH(1ELWVHWZKHQ
WKHUXQJLVIDOVHDQGWKH'1ELWLVVHW7KLVLQGLFDWHVWKHWUXHVWDWHRI
WKH06*LQVWUXFWLRQZKLFKLVVWLOORSHUDWLQJ+RZHYHULIWKHUXQJLV
IDOVHDQGWKH(5ELWLVVHWWKH(1ELWLVUHVHW7KLVOHWV\RXUHVWDUWDQ
HUURUHGFRQWLQXRXV06*LQVWUXFWLRQE\WRJJOLQJWKHVWDWHRIWKHUXQJ
Selecting Non-Continuous 1RQFRQWLQXRXVPRGHSHUIRUPVWKHPHVVDJHWUDQVIHURQHWLPHIRU

Operation HDFKIDOVHWRWUXHWUDQVLWLRQRIWKHUXQJWKDWFRQWDLQVWKH06*
LQVWUXFWLRQ1RQFRQWLQXRXVRSHUDWLRQRFFXUVDVORQJDVWKH&2ELW
UHPDLQVUHVHW8VHQRQFRQWLQXRXVPRGHZKHQ\RXZDQWWRFRQWURO
ZKHQWKHPHVVDJHWUDQVIHURFFXUVRUWKHQXPEHURIWLPHVWKHPHVVDJH
WUDQVIHURFFXUV
1RQFRQWLQXRXVPRGHZRUNVDVIROORZV)LJXUH
:KHQWKHUXQJWKDWFRQWDLQVWKH06*LQVWUXFWLRQJRHVWUXHWKH
SURFHVVRULQLWLDWLQJWKH06*LQVWUXFWLRQVHWVWKH(1ELW7KH
SURFHVVRUDOVRUHVHWVWKH'1DQG(5ELWV
7KHSURFHVVRUWKHQTXHXHVWKHPHVVDJHUHTXHVW:KHQWKHPHV
VDJHUHTXHVWHQWHUVWKHTXHXHWKHSURFHVVRUVHWVWKH(:ELW
1785-6.1 November 1998

:KHQWKHSURFHVVRUVWDUWVWRSURFHVVWKHPHVVDJHUHTXHVWWKH
SURFHVVRUVHWVWKH67ELW7KHQH[WWLPHWKHSURFHVVRUUHFHLYHV
QHWZRUNFRQWUROWKHSURFHVVRUWUDQVPLWVWKHPHVVDJH
,IQRHUURUVRFFXUGXULQJWUDQVPLVVLRQWKHSURFHVVRUVHWVWKH'1
ELWDQGUHVHWVWKH67ELWDIWHUWKHODVWSDFNHWLQWKHILUVWH[HFXWLRQ
RIWKH06*LQVWUXFWLRQWUDQVIHUV,IDQHUURURFFXUVWKHSURFHVVRU
VHWVWKH(5ELWUHVHWVWKH67ELWDQGVWRUHVDQHUURUFRGHLQWKH
ORZHUE\WHRIZRUGRIWKHFRQWUROEORFNIRU&ODVVLF3/&DQG
ZRUGRIWKHFRQWUROEORFNIRU(QKDQFHG3/&SURFHVVRUV
7KHQH[WWLPHWKHUXQJJRHVIDOVHWKHSURFHVVRUUHVHWVWKH(1
ELW7KHQZKHQWKHDVVRFLDWHGUXQJJRHVWUXHDJDLQWKHPHVVDJH
WUDQVIHUF\FOHVWDUWVDJDLQ
Figure 16.2
Timing Diagram for Status Bits in Non-Continuous MSG Instructions
EN
EW
ST
CO
DN
ER
Rung true Data sent by MSG begins MSG Rung false Rung true
instruction transmission transmission
and received on network completes
in the queue
these events are asynchronous to ladder program scan
MSG Timing 7KHWLPHUHTXLUHGIRURQH3/&SURFHVVRUWRVHQGRUUHFHLYHD

PHVVDJHWRIURPDQRWKHUSURFHVVRURQWKH'+OLQNGHSHQGVRQWKH
QXPEHURI
VWDWLRQVRQWKH'+OLQN
PHVVDJHVWUDQVPLWWHGIURPDFWLYHVWDWLRQV
E\WHVRIGDWDRIDOOWUDQVPLWWHGPHVVDJHV
PHVVDJHUHTXHVWVDOUHDG\LQWKHTXHXH
7LPLQJVWDUWVZLWKVHWWLQJWKHHQDEOHELWDQGHQGVZLWKVHWWLQJWKH
GRQHELWLQWKHODGGHUSURJUDPRIWKHVWDWLRQLQLWLDWLQJWKHPHVVDJH
7KHRUGHURIRSHUDWLRQLVVKRZQLQ7DEOH'
1785-6.1 November 1998

Table 16.D
Message Instruction Operation
Receiving MSG Sending MSG

(Station A reading/receiving from Station B) (Station A writing/sending to Station B)
station A enables the message instruction in the station A enables the message instruction in the
ladder program ladder program
station A obtains the token and transmits the read station A obtains the token and transmits data
command (station B acknowledges immediately) (station B acknowledges immediately)
station B obtains the token and transmits station B stores the data in memory
requested data
station A receives the data and station B obtains the token to respond that the
acknowledges immediately write is complete
station A sets the done bit station A sets the done bit when it receives
a response
<RXFDQHVWLPDWHWKHWLPHLQPLOOLVHFRQGVIRUWUDQVPLWWLQJRQH

SDFNHWRYHU'+XVLQJWKHIROORZLQJIRUPXODV
Processor Type: Formula:
Classic PLC-5 Message time = TP + TT + OH + P + 8 (number of messages)
Enhanced PLC-5 Message time = TP + TT + OH + 8 (number of messages)
ZKHUH
TP = WRNHQSDVV QXPEHURIVWDWLRQVRQ'+OLQN
TT WUDQVPLVVLRQWLPH QXPEHURIGDWDZRUGV
1XPEHURIGDWDZRUGVLQDOOWUDQVPLWWHGPHVVDJHV
IRURQHWRNHQSDVVDURXQGWKH'+OLQN
OH '+RYHUKHDG PV
P ORQJHVWSURJUDPVFDQIRUDQ\SURFHVVRURQWKH'+OLQN
DSSOLFDWLRQYDOXHLQPLOOLVHFRQGV
6HHWKH3/&90(EXV3URJUDPPDEOH&RQWUROOHUV8VHU0DQXDODQG
WKH(WKHUQHW3/&3URJUDPPDEOH&RQWUROOHUVPDQXDOIRU
SHUIRUPDQFHQXPEHUVDQGEHQFKPDUNV
1785-6.1 November 1998

Error Codes :KHQWKHSURFHVVRUGHWHFWVDQHUURUGXULQJWKHWUDQVIHURIPHVVDJH

GDWDWKHSURFHVVRUVHWVWKH(5ELWDQGHQWHUVDQHUURUFRGHWKDW\RX
FDQPRQLWRUIURP\RXUSURJUDPPLQJWHUPLQDO,IWKHPHVVDJHLV
QRQFRQWLQXRXVWKHSURFHVVRUVHWVWKH(5ELWWKHILUVWWLPHWKH
SURFHVVRUVFDQVWKH06*LQVWUXFWLRQ
Table 16.E
Errors Detected By the Processor
Code:
Enhanced PLC-51 Classic PLC-52

MG data type N data type Ethernet Only Description (Displayed on the Data Monitor screen):
0037 55 0037 message timed out in local processor
0083 131 0083 processor is disconnected
0089 137 0089 message buffer is full

If the MSG is going out channel 0, there are not enough
internal buffers available. Decrease the number of MSG
instructions to this port.
Otherwise, the destination node sent back a MSG indicating
that its buffers are full. Decrease the number of MSG
instructions going to the destination node.
0092 146 0092 no response (regardless of station type)
00D3 211 00D3 you formatted the control block incorrectly
00D5 213 00D5 incorrect address for the local data table
0200 2 link layer timed out or received a NAK
0300 3 duplicate token holder detected by link layer
0400 4 local port is disconnected
0500 5 application layer timed out waiting for a response
0600 6 duplicate node detected
0700 7 station is off line
0800 8 hardware fault
1000 129 1000 illegal command from local processor
2000 130 2000 communication module not working
3000 131 remote node is missing, disconnected, or shut down
4000 132 4000 processor connected but faulted (hardware)
5000 133 5000 you used the wrong station number
6000 134 6000 requested function is not available
7000 135 7000 processor is in program node

1
Hexadecimal – word 1 of the control block
2
Decimal – low byte of word 0 of the control block
1785-6.1 November 1998

Code:
Enhanced PLC-51 Classic PLC-52

MG data type N data type Ethernet Only Description (Displayed on the Data Monitor screen):
8000 136 8000 processor’s compatibility file does not exist
9000 137 9000 remote node cannot buffer command
B000 139 B000 processor is downloading so it is inaccessible
F001 231 F001 processor incorrectly converted the address
F002 232 F002 incomplete address
F003 233 F003 incorrect address
F006 236 F006 addressed file does not exist in target processor
F007 237 F007 destination file is too small for number of words requested
F00A 240 F00A target processor cannot put requested information

in packets
F00B 241 F00B privilege error, access denied
F00C 242 F00C requested function is not available
F00D 243 F00D request is redundant
F011 247 F011 data type requested does not match data available
F012 248 F012 incorrect command parameters
00103 0010 no IP address configured for the network
00113 0011 already at maximum number of connections
00123 0012 invalid Internet address or host name

3
0013 0013 no such host
00143 0014 cannot communicate with the name server
00153 0015 connection not completed before user-specified timeout
00163 0016 connection timed out by the network

3
0017 0017 connection refused by destination host
00183 0018 connection was broken
00193 0019 reply not received before user-specified timeout
001A3 001A no network buffer space available
F01A file owner active – the file is being used
F01B program owner active – someone is downloading, online

editing, or set the program owner with APS in the WHO
Active screen
1Hexadecimal – word 1 of the control block
2
Decimal – low byte of word 0 of the control block
3Errors detected by a Enhanced PLC-5 processor attached to a PLC-5 Ethernet Interface Module only.
1785-6.1 November 1998

Table 16.F
Errors Detected By the VME Processor
PLC-5/40V (hexadecimal – Description (Displayed on the Data Monitor

word 1 of the control block) screen):
0000 success
0001 invalid ASCII message format
0002 invalid file type
0003 invalid file number
0004 invalid file element
0005 invalid VME address
0006 invalid VME transfer width
0007 invalid number of elements requested for transfer
0008 invalid VME interrupt level
0009 invalid VME interrupt status-id value
000A VMEbus transfer error (bus error)
000B unable to assert requested interrupt (already pending)
000C raw data transfer setup error
000D raw data transfer crash (PLC switched out of run mode)
000E unknown message type (message type not ASCII)
1785-6.1 November 1998

Chapter 17
ASCII Instructions ABL, ACB, ACI, ACN,
AEX, AIC, AHL, ARD, ARL, ASC, ASR,
AWA, AWT
Using ASCII Instructions 7KH$6&,,LQVWUXFWLRQVUHDGZULWHFRPSDUHDQGFRQYHUW$6&,,
Enhanced PLC-5 Processors Only VWULQJV7KHVHLQVWUXFWLRQVDUHRQO\VXSSRUWHGE\(QKDQFHG3/&
SURFHVVRUV7DEOH$OLVWVWKHDYDLODEOH$6&,,LQVWUXFWLRQV
Table 17.A
Available ASCII Instructions
If You Want to: Use this Instruction: On Page:
See how many characters are in the buffer, up to ABL 17-4

and including the end of line character
See how many total characters are in the buffer ACB 17-5
Convert a string to an integer value ACI 17-6
Concatenate two strings into one ACN 17-7
Extract a portion of a string to create a new string AEX 17-7
Configure your modem handshake lines AHL 17-8
Convert an integer value to a string AIC 17-9
Read characters from the buffer and put into a ARD 17-10
string
Read one line of characters from the buffer and ARL 17-12
put into a string
Search a string for another string ASC 17-14
Compare two strings ASR 17-15
Write a string with user-configured characters AWA 17-15

appended
Write a string AWT 17-17
$SSHQGL[&
1785-6.1 November 1998

17-2 ASCII Instructions ABL, ACB, ACI, ACN, AEX, AIC, AHL, ARD, ARL, ASC, ASR, AWA, AWT
7KHUHDUHWZRW\SHVRI$6&,,LQVWUXFWLRQV
Type of ASCII Instruction: Description:
ASCII port control read, write, set/reset handshake lines,

examine the length of the buffer (ARD,
ARL, AWT, AWA, AHL, ACB, ABL)
ASCII string manipulate string data, such as

compare, search, extract, concatenate,
convert to/from integer (ASR, ASC, AEX,
ACN, ACI, AIC)
$6&,,LQVWUXFWLRQVDUHGHSHQGHQWXSRQRQHDQRWKHU)RUH[DPSOHLI
\RXKDYHDQ$5'$6&,,UHDGLQVWUXFWLRQDQGWKHQDQ$:7$6&,,
ZULWHWKHGRQHELWRQWKH$5'PXVWEHVHWEHIRUHWKH$:7FDQ
EHJLQH[HFXWLQJHYHQLIWKH$:7ZDVHQDEOHGZKLOHWKHSURFHVVRU
ZDVH[HFXWLQJWKH$5'$VHFRQG$6&,,LQVWUXFWLRQFDQQRWEHJLQ
XQWLOWKHILUVWKDVFRPSOHWHG+RZHYHUWKHSURFHVVRUGRHVQRWZDLW
IRUDQ$6&,,LQVWUXFWLRQWRFRPSOHWHEHIRUHFRQWLQXLQJWRH[HFXWH
\RXUODGGHUSURJUDPQRQ$6&,,LQVWUXFWLRQV
Using Status Bits

<RXFDQH[DPLQHVWDWXVELWVLQWKHODGGHUSURJUDPWRH[DPLQHVRPH
HYHQW7KHSURFHVVRUFKDQJHVWKHVWDWHVRIVWDWXVELWVDVWKHSURFHVVRU
H[HFXWHVWKHLQVWUXFWLRQ<RXDGGUHVVWKHVWDWXVELWVE\PQHPRQLFRU
ELWQXPEHULQWKHFRQWUROHOHPHQWDGGUHVV
7KH$6&,,LQVWUXFWLRQVXVHWKHOHQJWK/(1DQGSRVLWLRQ326
ILHOGVLQVRPHLQVWUXFWLRQVDVZHOODVWKHIROORZLQJVWDWXVELWV
Description: Explanation of Status Bit:
Found.FD (08) Reserved
Unload.UL (10) This bit may be used by the user to cancel an ASCII read or
write in progress. The time out may occur immediately or up to 6
seconds later.
Error.ER (11) The instruction did not complete successfully.

Note: If this bit is set, the .EN bit is cleared and the .DN bit is set
during prescan.
Synchronous Done.EM (12) The bit is set on the first scan of the instruction after it is completed.
Asynchronous Done.DN (13) The bit is set immediately upon successful completion of the
instruction, asynchronous to program scan.
Note: If this bit is set , the .EN bit is cleared and the .DN bit is set
during prescan.
Queue.EU (14) The bit is set when the instruction is successfully queued.
Enable.EN (15) The bit is set when the rung goes true and is reset after completion
of the instruction and the rung goes false.
Note: If this bit is set and the .DN and .ER bits are cleared, the
control word is cleared during prescan.
1785-6.1 November 1998

ASCII Instructions ABL, ACB, ACI, ACN, AEX, AIC, AHL, ARD, ARL, ASC, ASR, AWA, AWT 17-3
Using the Control Block

,QDGGLWLRQWRWKHVWDWXVELWVWKHFRQWUROEORFNFRQWDLQVRWKHU
SDUDPHWHUVWKHSURFHVVRUXVHVWRFRQWURO$6&,,WUDQVIHULQVWUXFWLRQV
7DEOH%OLVWVWKHVHYDOXHV
Table 17.B
Values in the Control Word
Word – Integer
ASCII Control Block Description
Control Block
0 .EN, .DN, etc Status Bits
1 .LEN Word Length
2 .POS Character Position
Length (.LEN)
7KLVLVWKHQXPEHURIFKDUDFWHUVWKHRSHUDWLRQLVWREHSHUIRUPHGRQ
Position (.POS)
7KLVLVWKHFXUUHQWFKDUDFWHUQXPEHUZKLFKWKHRSHUDWLRQ
KDVH[HFXWHG
Using Strings
<RXFDQDGGUHVVVWULQJOHQJWKVE\DGGLQJD/(1WRDQ\VWULQJDGGUHVV
IRUH[DPSOH67/(1
6WULQJOHQJWKVPXVWEHEHWZHHQDQGE\WHV,QJHQHUDOOHQJWKV
WKDWDUHRXWVLGHRIWKLVUDQJHFDXVHWKHSURFHVVRUWRVHWDPLQRUIDXOW
6DQGWKHLQVWUXFWLRQLVQRWH[HFXWHG
,PSRUWDQW <RXFRQILJXUHDSSHQGRUHQGRIOLQHFKDUDFWHUVRQWKH
&KDQQHO&RQILJXUDWLRQVFUHHQ7KHGHIDXOWDSSHQG
FKDUDFWHUVDUHFDUULDJHUHWXUQDQGOLQHIHHGWKHGHIDXOW
HQGRIOLQHWHUPLQDWLRQFKDUDFWHULVFDUULDJHUHWXUQ
)RUPRUHLQIRUPDWLRQVHH\RXUVRIWZDUHXVHUPDQXDO
1785-6.1 November 1998

Test Buffer for Line (ABL)
Description: 8VHWKH$%/LQVWUXFWLRQWRVHHKRZPDQ\FKDUDFWHUVDUHLQWKHEXIIHU
ABL
XSWRDQGLQFOXGLQJWKHHQGRIOLQHFKDUDFWHUVWHUPLQDWLRQ2QD
ASCII TEST FOR LINE
EN
IDOVHWRWUXHWUDQVLWLRQWKHV\VWHPUHSRUWVWKHQXPEHURIFKDUDFWHUVLQ
Channel DN WKH3RVLWLRQILHOGDQGVHWVWKHGRQHELW7KHVHULDOSRUWPXVWEHLQ
Control
Characters ER
8VHUPRGH
Entering Parameters
7RXVHWKH$%/LQVWUXFWLRQ\RXPXVWVXSSO\WKLVLQIRUPDWLRQ
Channel the number of the RS-232 port. (The only valid value is 0).
Control the address of a control file element used for the control
status bits.
Characters the number of characters in the buffer (including the

end-of-line/termination characters) that the processor finds
(0-256). This field is display only.
Example:
I:012 ABL
[ EN
[ ASCII TEST FOR LINE
10 Channel 0 DN
If input word 12, bit 10 is set, the processor Control R6:32
performs an ABL operation for channel 0.
Characters ER
:KHQWKHUXQJJRHVIURPIDOVHWRWUXHWKHFRQWUROHOHPHQWHQDEOHELW
(1LVVHW7KHLQVWUXFWLRQLVSXWLQWKH$6&,,LQVWUXFWLRQTXHXHWKH
(8ELWLVVHWDQGSURJUDPVFDQFRQWLQXHV7KHLQVWUXFWLRQLVWKHQ
H[HFXWHGSDUDOOHOWRSURJUDPVFDQ
7KHSURFHVVRUGHWHUPLQHVWKHQXPEHURIFKDUDFWHUVXSWRDQG
LQFOXGLQJWKHHQGRIOLQHWHUPLQDWLRQFKDUDFWHUVDQGSXWVWKLVYDOXH
LQWKHSRVLWLRQILHOG7KHGRQHELWLVWKHQVHW,ID]HURDSSHDUVLQWKH
SRVLWLRQILHOGQRHQGRIOLQHWHUPLQDWLRQFKDUDFWHUVZHUHIRXQG7KH
)'ELWLVVHWLIWKHSRVLWLRQILHOGZDVVHWWRDQRQ]HURYDOXH
:KHQWKHSURJUDPVFDQVWKHLQVWUXFWLRQDQGILQGVWKH'1ELWVHWWKH
SURFHVVRUWKHQVHWVWKH(0ELW7KH(0ELWDFWVDVDVHFRQGDU\GRQH
ELWFRUUHVSRQGLQJWRWKHSURJUDPVFDQ
7KHHUURUELW(5LVVHWGXULQJWKHH[HFXWLRQRIWKHLQVWUXFWLRQLI
WKHLQVWUXFWLRQLVDERUWHG±VHULDOSRUWQRWLQ8VHUPRGH
WKHLQVWUXFWLRQLVDERUWHGGXHWRSURFHVVRUPRGHFKDQJH
1785-6.1 November 1998

Number of Characters in Buffer

(ACB)
Description: 8VHWKH$&%LQVWUXFWLRQWRVHHKRZPDQ\WRWDOFKDUDFWHUVDUHLQWKH
ACB
EXIIHU2QDIDOVHWRWUXHWUDQVLWLRQWKHV\VWHPGHWHUPLQHVWKHWRWDO
ASCII CHARS IN BUFFER
EN QXPEHURIFKDUDFWHUVDQGUHSRUWVLWLQWKH&KDUDFWHUVILHOG7KHVHULDO
Channel DN SRUWPXVWEHLQ8VHUPRGH
Control
Characters ER
Entering Parameters
7RXVHWKH$&%LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUWKH
Channel the number of the RS-232 port (The only valid value in this field is 0).
Control the address of a control file element used for control status bits.
Characters the number of the characters in the buffer that the processor finds
(0-256). This field is display only.
Example:
I:012 ACB
EN
[
[
ASCII CHARS IN BUFFER
10 Channel 0
DN
If input word 12, bit 10 is set, the processor Control R6:32
performs an ACB operation for channel 0. Characters
ER
(1LVVHW:KHQWKHLQVWUXFWLRQLVSXWLQWKH$6&,,LQVWUXFWLRQ
TXHXHWKH(8ELWLVVHWDQGSURJUDPVFDQFRQWLQXHV7KHLQVWUXFWLRQ
LVWKHQH[HFXWHGSDUDOOHOWRSURJUDPVFDQ
7KHSURFHVVRUGHWHUPLQHVWKHQXPEHURIFKDUDFWHUVLQWKHEXIIHUDQG
SXWVWKLVYDOXHLQWKHSRVLWLRQILHOG7KHGRQHELWLVWKHQVHW,ID]HUR
DSSHDUVLQWKHSRVLWLRQILHOGQRFKDUDFWHUVZHUHIRXQG7KH)'ELWLV
VHWLIWKHSRVLWLRQILHOGZDVVHWWRDQRQ]HURYDOXH
1785-6.1 November 1998

ASCII String to Integer (ACI)
Description: 8VHWKH$&,LQVWUXFWLRQWRFRQYHUWDQ$6&,,VWULQJWRDQLQWHJHUYDOXH
EHWZHHQ±DQG
ACI
STRING TO INTEGER CONVERSION
Source
7KHSURFHVVRUVHDUFKHVWKHVRXUFHILOHW\SH67IRUWKHILUVWFKDUDFWHU
Destination WKDWLVEHWZHHQDQG$OOQXPHULFFKDUDFWHUVDUHH[WUDFWHGXQWLOD
QRQQXPHULFFKDUDFWHURUWKHHQGRIWKHVWULQJLVUHDFKHG&RPPDV
DQGVLJQV±DUHDOORZHGLQWKHVWULQJ
7KHH[WUDFWHGQXPHULFVWULQJLVWKHQFRQYHUWHGWRDQLQWHJHUEHWZHHQ
±DQG
,IQRQXPHULFFKDUDFWHUVDUHIRXQGQRDFWLRQLVWDNHQ$OVRLIWKH
VWULQJKDVDQLQYDOLGOHQJWKOHVVWKDQ]HURRUJUHDWHUWKDQWKH
IDXOWELWLVVHW6DQGWKHLQVWUXFWLRQLVQRWH[HFXWHG
7KLVLQVWUXFWLRQDOVRVHWVWKHDULWKPHWLFIODJVIRXQGLQZRUGELWV
LQWKHSURFHVVRUVWDWXVILOH6
Bit: Description: Indicating:
S:0/0 Carry (C) the carry was generated while converting the
string to an integer
S:0/1 Overflow (V) the integer value was outside of the valid range
S:0/2 Zero (Z) the integer value is zero
S:0/3 Sign (S) the integer value is negative
Example:
I:012 ACI
[
[ STRING TO INTEGER
10 Source ST38:90
Destination N7:123
If input word 12, bit 10 is set, convert the string in
ST38:90 to an integer and store the result in N7:123. 75
1785-6.1 November 1998

ASCII String Concatenate (ACN)
Description: 7KH$&1LQVWUXFWLRQDSSHQGV6RXUFH%WRWKHHQGRI6RXUFH$DQG
ACN
VWRUHVWKHUHVXOWLQWKH'HVWLQDWLRQ
STRING CONCATENATE
,IWKHUHVXOWLVORQJHUWKDQFKDUDFWHUVRQO\WKHILUVWDUHZULWWHQ
Source A
WRWKHGHVWLQDWLRQILOHDQGWKHHUURUELW6LVVHW$OVRLIWKH
Source B
OHQJWKRIHLWKHUVWULQJLVLQYDOLGOHVVWKDQ]HURRUJUHDWHUWKDQWKH
Destination
IDXOWELWLVVHWDQGWKHVWULQJDWWKHGHVWLQDWLRQDGGUHVVLVQRWFKDQJHG
Example:
I:012 ACN
[
[ STRING CONCATENATE
10 Source A ST37:42
If input word 12, bit 10 is set, concatenate the string Source B ST38:91
in ST37:42 with the string in ST38:91 and store the
result in ST52:76 Destination ST52:76
ASCII String Extract (AEX)
Description: 8VHWKH$(;LQVWUXFWLRQWRFUHDWHDQHZVWULQJE\WDNLQJDSRUWLRQRI
AEX
DQH[LVWLQJVWULQJ
STRING EXTRACT
Source Entering Parameters
Index
Number
Destination
7RXVHWKH$(;LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUWKH
Source the existing string.
Index the starting position (from 1 to 82) of the portion of the string you want to
extract. (An index of 1 indicates the left-most character of the string.)
Number the number of characters (from 0 to 82) you want to extract, starting at
the indexed position. If the Index plus the Number is greater than the total
characters in the source string, the destination string will be the
characters from the index to the end of the source string. If you enter 0
for the number, the destination string length is set to zero.
Destination the string element (ST) where you want the extracted string stored.
Example:
I:012 AEX
[
[ STRING EXTRACT
10 Source ST38:40
If input word 12, bit 10 is set, extract 10 characters Index 42
starting at the 42nd character of ST38:40 and store Number 10
the result in ST52:75. Destination ST52:75
1785-6.1 November 1998

7KHIROORZLQJFRQGLWLRQVFDXVHWKHSURFHVVRUWRVHWWKHIDXOW
ELW 6
LQYDOLGVWULQJOHQJWKRUVWULQJOHQJWKRI]HUR
LQGH[RUQXPEHUYDOXHVRXWVLGHRIUDQJH
LQGH[YDOXHJUHDWHUWKDQWKHOHQJWKRIWKHVRXUFHVWULQJ
7KHGHVWLQDWLRQVWULQJZLOOQRWFKDQJHLQDQ\RIWKHDERYHLQVWDQFHV
ASCII Set or Reset Handshake

Lines (AHL)
Description: 8VHWKH$+/LQVWUXFWLRQWRVHWRUUHVHWWKH56'75DQG576
AHL KDQGVKDNHFRQWUROOLQHVIRU\RXUPRGHP2QDIDOVHWRWUXHWUDQVLWLRQ
ASCII HANDSHAKE LINE
EN
WKHV\VWHPXVHVWKHWZRPDVNVWRGHWHUPLQHZKHWKHUWRVHWRUUHVHWWKH
Channel
AND Mask
DN '75DQG576OLQHVRUOHDYHWKHPXQFKDQJHG
OR Mask
Control ER ,PSRUWDQW %HIRUH\RXXVHWKLVLQVWUXFWLRQPDNHVXUHWKDW\RXGR
Channel Status
QRWFRQIOLFWZLWKWKHDXWRPDWLFFRQWUROOLQHVRQ
\RXU PRGHP
Entering Parameters
7RXVHWKH$+/LQVWUXFWLRQ\RXPXVWSURYLGHWKLVLQIRUPDWLRQ
Channel the number of the RS-232 port that you want to use. Currently, only
channel 0 can be set or reset.
AND Mask the mask to reset the DTR and RTS control lines. Bit 0 corresponds
to the DTR line and bit 1 corresponds to the RTS line. A 1 at the
mask bit causes the line to be reset; a 0 leaves the line unchanged.
OR Mask the mask to set the DTR and RTS control lines. Bit 0 corresponds to
the DTR line and bit 1 corresponds to the RTS line. A 1 at the mask
bit causes the line to be set; a 0 leaves the line unchanged.
Control the address of the result control structure in the control area of
memory for the result.
Channel Status displays the current status (0000 to FFFF) of the handshake lines
for the channel specified above. This field is display only; convert
the hexadecimal status to binary and refer to the table below:
Bit 1 0
Line RTS DTR
1785-6.1 November 1998

Example: (Reset DTR and RTS Lines)

I:012 AHL
[ EN
[ ASCII HANDSHAKE LINES
10 Channel 0
DN
AND Mask 0003
OR Mask 0000
Control ER
If input word 12, bit 10 is set, bit 0 and bit 1 of the AND R6:23
mask is set to RESET (OFF) the DTR and RTS lines. Channel Status
Channel status will display a 000D.
Example: (Set DTR and RTS Lines)
I:012 AHL
[ EN
[ ASCII HANDSHAKE LINES
11 Channel 0
DN
AND Mask 0000
OR Mask 0003
Control ER
R6:22
If input word 12, bit 11 is set, bit 0 and bit 1 of the OR Channel Status
mask is set to SET (ON) the DTR and RTS lines.
Channel status will display a 001F.
7KHHUURUELW(5LVVHWGXULQJWKHH[HFXWLRQRIWKHLQVWUXFWLRQLIWKH

LQVWUXFWLRQLVDERUWHGGXHWRSURFHVVRUPRGHFKDQJH
ASCII Integer to String (AIC)
Description: 8VHWKH$,&LQVWUXFWLRQWRFRQYHUWDQLQWHJHUYDOXHEHWZHHQ±

AIC
DQGWRDQ$6&,,VWULQJ7KHVRXUFHFDQEHDFRQVWDQWRUDQ
INTEGER TO STRING LQWHJHUDGGUHVV
Source
Destination
Example:
I:012 AIC
[
[ INTEGER TO STRING
10 Source 867
Destination ST38:42
If input word 12, bit 10 is set, convert the value
867 to a string and store the result in ST38:42.
1785-6.1 November 1998

ASCII Read Characters (ARD)
Description: 8VHWKH$5'LQVWUXFWLRQWRUHDGFKDUDFWHUVIURPWKHEXIIHUDQGVWRUH
WKHPLQDVWULQJ7RUHSHDWWKHRSHUDWLRQWKHUXQJPXVWJRIURPIDOVH
ARD
ASCII READ EN WRWUXH7KHVHULDOSRUWPXVWEHLQ8VHUPRGH
Channel
Destination DN
Control Entering Parameters
String Length
ER
Characters Read
7RXVHWKH$5'LQVWUXFWLRQSURYLGHWKHIROORZLQJLQIRUPDWLRQ
Control the control file element used for the control status bits.
Destination the string element where you want the characters stored.
String Length the number of characters you want to read from the buffer. The
maximum is 82 characters. If you specify a length larger than 82,
only 82 characters will be read. (If you specify 0, the string length
defaults to 82.)
Characters Read the number of characters that the processor moved from the buffer
to the string (0 to 82). This field is display only.
Example:
ARD
I:012 EN
[
[ ASCII READ
10 Channel 0
Destination ST52:76 DN
If input word 12, bit 10 is set, read 50 characters Control R6:23
from the buffer and move them to ST52:76. String Length 50 ER
Characters Read
2QFHWKHUHTXHVWHGQXPEHURIFKDUDFWHUVDUHLQWKHEXIIHUWKH
FKDUDFWHUVDUHPRYHGWRWKHGHVWLQDWLRQVWULQJ7KHQXPEHURI
FKDUDFWHUVPRYHGLVSXWLQWKHSRVLWLRQZRUGRIWKHFRQWUROHOHPHQW
DQGWKHGRQHELWLVVHW
<RXFDQXVHWKH8/ELWWRWHUPLQDWHDQ$5'LQVWUXFWLRQEHIRUHLW
FRPSOHWHVIRUH[DPSOH\RXPD\ZDQWWRWHUPLQDWHWKHLQVWUXFWLRQLI
\RXNQRZWKDWWKH$6&,,GHYLFHFRQQHFWHGWRWKHSRUWLVQRWVHQGLQJ
GDWDRULIWKHFRQQHFWLRQEUHDNVDIWHUWKHLQVWUXFWLRQVWDUWVH[HFXWLQJ
6HWWKH8/ELWLQWKHFRQWUROVWUXFWXUHWKH(5ELWLVWKHQVHW
1785-6.1 November 1998

,PSRUWDQW :KHQ\RXVHWWKH8/ELWWKHLQVWUXFWLRQGRHVQRW
WHUPLQDWHLPPHGLDWHO\LWPD\WDNHVHYHUDOVHFRQGV
,IDQ$5'LQVWUXFWLRQVWDUWVH[HFXWLQJZLWKWKH8/ELWDOUHDG\VHWDQG
WKHUHDUHQRFKDUDFWHUVLQWKHEXIIHUWKHLQVWUXFWLRQWHUPLQDWHV,IDQ
$5'LQVWUXFWLRQVWDUWVH[HFXWLQJZLWKWKH8/ELWDOUHDG\VHWDQG
WKHUHDUHFKDUDFWHUVLQWKHEXIIHUWKHLQVWUXFWLRQSURFHHGVWR
QRUPDO FRPSOHWLRQ
ZKHQXVLQJDPRGHPWKHPRGHPLVGLVFRQQHFWHG
Figure 17.1
Example ARD Timing Diagram
Rung Condition ON
OFF
ON
Enable Bit (.EN) OFF
Queue Bit (.EU) ON

OFF
Done Bit
Error Bit ON
(.DN or. ER) OFF
Synchronous Done Bit (.EM) ON

OFF
1 2 3 4 5 1 5 2 3 4
1 - rung goes true
2 - instruction successfully queued
3 - instruction execution complete
4 - instruction scanned for the first time after execution is complete
5 - rung goes false
1785-6.1 November 1998

ASCII Read Line (ARL)
Description: 8VHWKH$5/LQVWUXFWLRQWRUHDGFKDUDFWHUVIURPWKHEXIIHUXSWRDQG
ARL
LQFOXGLQJWKHHQGRIOLQHWHUPLQDWLRQFKDUDFWHUVDQGVWRUHWKHPLQD
ASCII READ LINE EN VWULQJ7KHHQGRIOLQHFKDUDFWHUVDUHVSHFLILHGRQWKH&KDQQHO
Channel
Destination
&RQILJXUDWLRQVFUHHQWKHGHIDXOWLVDFDUULDJHUHWXUQ)RUPRUH
DN
Control
String Length
LQIRUPDWLRQRQFKDQQHOFRQILJXUDWLRQVHH\RXUVRIWZDUHXVHUPDQXDO
Characters Read ER 7KHVHULDOSRUWPXVWEHLQ8VHUPRGH
Entering Parameters
7RXVHWKH$5/LQVWUXFWLRQ\RXPXVWSURYLGHWKLVLQIRUPDWLRQ
Control the address of the control file element used for the control status bits.
Destination the string element where you want the string stored.
String Length the number of characters (maximum 82) you want to read from the
buffer. If the processor finds the end-of-line characters before
reading the number of characters you specified, only those
characters read and the end-of-line are moved to the destination.
Characters the number of characters that the processor moved from the buffer
Read to the string (0 to 82). This field is display only.
Example:
ARL
I:012
ASCII READ LINE EN
[ [
10 Channel 0
Destination ST52:72 DN
If input word 12, bit 10 is set, read 18 characters Control R6:23
(or until end-of-line) from the buffer and move String Length 18
them to ST52:72. ER
Characters Read
2QFHWKHUHTXHVWHGQXPEHURIFKDUDFWHUVRUWKHHQGRIOLQH
FKDUDFWHUVDUHLQWKHEXIIHUDOOFKDUDFWHUVLQFOXGLQJWKHHQGRIOLQH
FKDUDFWHUVDUHPRYHGWRWKHGHVWLQDWLRQVWULQJ7KHQXPEHURI
FKDUDFWHUVPRYHGLVVWRUHGLQWKHSRVLWLRQZRUGRIWKHFRQWUROHOHPHQW
DQGWKHGRQHELWLVVHW
1785-6.1 November 1998

<RXFDQXVHWKH8/ELWWRWHUPLQDWHDQ$5/LQVWUXFWLRQEHIRUHLW
\RXNQRZWKDWWKH$6&,,GHYLFHFRQQHFWHGWRWKHSRUWLVQRWVHQGLQJ
,IDQ$5/LQVWUXFWLRQVWDUWVH[HFXWLQJZLWKWKH8/ELWDOUHDG\VHWDQG
WKHUHDUHQRFKDUDFWHUVLQWKHEXIIHUWKHLQVWUXFWLRQWHUPLQDWHV,IDQ
$5/LQVWUXFWLRQVWDUWVH[HFXWLQJZLWKWKH8/ELWDOUHDG\VHWDQG
WKHUHDUHFKDUDFWHUVLQWKHEXIIHUWKHLQVWUXFWLRQSURFHHGVWR
QRUPDO FRPSOHWLRQ
FKDQQHOLVLQV\VWHPPRGHRUVZLWFKHVWRV\VWHPPRGHWKH
SURFHVVRUVZLWFKHVWRSURJUDPWHVWPRGHRULIWKHPRGHPLVORVW
ZKHQXVLQJPRGHPFRQWURO
Figure 17.2
Example ARL Timing Diagram
Rung Condition ON
OFF
Enable Bit (.EN) ON

OFF
Queue Bit (.EU) ON

OFF
Done Bit
Error Bit ON
(.DN or. ER) OFF
ON
Empty Bit (.EM) OFF
1 - rung goes true 1 2 3 4 5 1 5 2 3 4

5 - rung goes false
1785-6.1 November 1998

ASCII String Search (ASC)
Description: 8VHWKH$6&LQVWUXFWLRQWRVHDUFKDQH[LVWLQJVWULQJVHDUFKVWULQJ

ASC IRUDQRFFXUUHQFHRIWKHVRXUFHVWULQJ
STRING SEARCH
Source Entering Parameters
Index
Search
Result 7RXVHWKH$6&LQVWUXFWLRQ\RXPXVWSURYLGHWKLVLQIRUPDWLRQ
Search the string you want to examine.
Source the string you want to find when examining the search string.
Index the starting position (from 1 to 82) of the portion of the search string you
want to search. An index of 1 indicates the left-most character.
Result an integer address where the processor stores the position of the search
string where the source string begins. If no match is found, 0 is stored in
the result.
Example:
I:012 ASC
[
[
STRING SEARCH
10 Source ST38:40
Index 35
Search ST52:80
If input word 12, bit 10 is set, search the string in ST52:80 Result N10:0
starring at the 35th character, for the string found in
ST38:40. In this example, the result is stored in N10:0.
7KHIROORZLQJFRQGLWLRQVFDXVHWKHSURFHVVRUWRVHWWKHIDXOW
ELW6
LQYDOLGVWULQJOHQJWKRUVWULQJOHQJWKRI]HUR
LQGH[YDOXHVRXWVLGHRIUDQJH
LQGH[YDOXHJUHDWHUWKDQWKHOHQJWKRIWKHVRXUFHVWULQJ
7KHUHVXOWLVVHWWR]HURLQDQ\RIWKHDERYHLQVWDQFHV
1785-6.1 November 1998

ASCII String Compare (ASR)
Description: 8VHWKH$65LQVWUXFWLRQWRFRPSDUHWZR$6&,,VWULQJV7KHV\VWHP
ORRNVIRUDPDWFKLQOHQJWKDQGXSSHUORZHUFDVH,IWKHWZRVWULQJV
DUHLGHQWLFDOWKHUXQJLVWUXHLIWKHUHDUHDQ\GLIIHUHQFHVWKHUXQJ
LVIDOVH
Example:
ASR O:013
ASCII STRING COMPARE
Source A ST37:42 01
Source B ST38:90
If the string in ST37:42 is identical to the
string in ST38:90, set output bit O:013/01.
$QLQYDOLGVWULQJOHQJWKFDXVHVWKHSURFHVVRUWRVHWWKHIDXOWELW
6DQGWKHUXQJLVIDOVH
ASCII Write with Append (AWA)
Description: 8VHWKH$:$LQVWUXFWLRQWRZULWHFKDUDFWHUVIURPWKHVRXUFHWRD
GLVSOD\GHYLFH7KLVDSSHQGLQVWUXFWLRQDGGVRUFKDUDFWHUVZKLFK
AWA
ASCII WRITE APPEND EN \RXFRQILJXUHLQWKH&KDQQHO&RQILJXUDWLRQ7KHGHIDXOWLVDFDUULDJH
Channel
Source
UHWXUQDQGOLQHIHHGDSSHQGHGWRWKHHQGRIWKHVWULQJ<RXFDQXVH
Control
String Length
DN
WKLVLQVWUXFWLRQZLWKWKHVHULDOSRUWLQ8VHURU6\VWHPPRGH
Characters Sent ER
Entering Parameters
7RXVHWKH$:$LQVWUXFWLRQ\RXPXVWSURYLGHWKLVLQIRUPDWLRQ
Source the string you want to write.
Control the address of the control file element used for the control status bits.
String Length the maximum number of characters you want to write from the
source string (0 to 82). If you enter 0, the entire string will be written.
Characters Sent the number of characters that the processor sent to the display area
(0 to 82). Only after the entire string is sent is this field updated
(no running total for each character sent is stored). This field is
display only.
1785-6.1 November 1998

Example:
I:012 AWA
EN
[
[ ASCII WRITE APPEND
10 Channel 0
Source ST37:42 DN
Control R6:23
If input word 12, bit 10 is set, read 25 characters from String Length 25 ER
ST37:42 and write it to the display device. Then write Characters Sent
a carriage return and line feed (default).
7ZHQW\ILYHFKDUDFWHUVIURPWKHVWDUWRIVWULQJ67DUHVHQWWRWKH
GLVSOD\GHYLFHDQGWKHQXVHUFRQILJXUHGDSSHQGFKDUDFWHUVDUHVHQW
7KHGRQHELWLVVHWDQGDYDOXHRILVVHQWWRWKHSRVLWLRQZRUG
SURFHVVRUWKHQVHWVWKH(0ELWWRDFWDVDVHFRQGDU\GRQHELW
FRUUHVSRQGLQJWRWKHSURJUDPVFDQ
<RXFDQXVHWKH8/ELWWRWHUPLQDWHDQ$:$LQVWUXFWLRQEHIRUHLW
\RXNQRZWKDWWKH$6&,,GHYLFHFRQQHFWHGWRWKHSRUWFDQQRWDFFHSW
,IDQ$:$LQVWUXFWLRQVWDUWVH[HFXWLQJZLWKWKH8/ELWDOUHDG\VHW
WKHLQVWUXFWLRQDERUWVLPPHGLDWHO\
LQVWUXFWLRQLVDERUWHGGXHWRSURFHVVRUPRGHFKDQJHRULIWKHPRGHP
EHFRPHVORVWZKHQXVLQJPRGHPFRQWURO,IWKHPRGHPZDVDOUHDG\
ORVWWKHLQVWUXFWLRQVWLOOH[HFXWHV
1785-6.1 November 1998

Figure 17.3
Example AWA Timing Diagram
Rung Condition ON
OFF
ON
Enable Bit (.EN)
OFF
ON
Queue Bit (.EU)
OFF
Done Bit ON
Error Bit OFF
(.DN or. ER)
ON
Empty Bit (.EM)
OFF
1 2 3 4 5 1 5 2 3 4
1 - rung goes true
5 - rung goes false
ASCII Write (AWT)
Description: 8VHWKH$:7LQVWUXFWLRQWRZULWHFKDUDFWHUVIURPWKHVRXUFHWRD
AWT
GLVSOD\GHYLFH7RUHSHDWWKHLQVWUXFWLRQWKHUXQJPXVWJRIURP
ASCII WRITE IDOVHWRWUXH<RXFDQXVHWKLVLQVWUXFWLRQZLWKWKHSRUWLQ6\VWHPRU
EN
Channel 8VHUPRGH
Source
Control DN
String Length
Characters Sent ER Entering Parameters
7RXVHWKH$:7LQVWUXFWLRQ\RXPXVWSURYLGHWKLVLQIRUPDWLRQ
Parameters: Definition:
Source the string you want to write.
Control the address of the control file element used for the control status file.
String Length the maximum number of characters you want to write from the
source string (0 to 82). If you enter 0, the entire string will be written.
Characters Sent the number of characters that the processor sent to the display area
(0 to 82). Only after the entire string is sent is this field updated
(no running total for each character sent is stored). This field is
display only.
1785-6.1 November 1998

Example:
I:012 AWT
[
[ ASCII WRITE EN
10 Channel 0
Source ST37:20 DN
Control R6:23
If input word 12, bit 10 is set, write 40 characters String Length 40
from ST37:20 and write it to the display device. Characters Sent ER
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1785-6.1 November 1998

Figure 17.4
Example AWT Timing Diagram
ON
Rung Condition OFF
ON
Enable Bit (.EN) OFF
ON
Queue Bit (.EU) OFF
Done Bit ON
Error Bit
(.DN or. ER) OFF
ON
Empty Bit (.EM)
OFF
1 2 3 4 5 1 5 2 3 4
1 - rung goes true
5 - rung goes false
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Chapter 18
Custom Application Routine
Instructions SDS, DFA
Chapter Objectives 7KLVFKDSWHULQWURGXFHVWKH&XVWRP$SSOLFDWLRQ5RXWLQH&$5
LQVWUXFWLRQV6'6DQG')$IRU3/&SURJUDPPLQJVRIWZDUH<RX
QHHGWKH&XVWRP$SSOLFDWLRQ5RXWLQH&$5VRIWZDUHLQRUGHUWRXVH
WKHVHLQVWUXFWLRQV
For Information About: See:
SDS or DFA CAR utilities Distributed Diagnostic and Machine Control User Manual
AGA3 PLC-5 AGA Mass Flow Custom Application Routine

Programming Manual
AGA7 PLC-5 Volumetric Flow CARs for Turbine and Displacement

Metering User Manual
NX19 PLC-5 Volumetric Flow CARs for Orifice Metering User

Manual
API PLC-5 Volumetric Flow CARs for Turbine and Displacement

Metering User Manual
$SSHQGL[&
1785-6.1 November 1998

18-2 Custom Application Routine Instructions SDS, DFA
Smart Directed Sequencer (SDS) 7KH6PDUW'LUHFWHG6HTXHQFHU6'6LQVWUXFWLRQSURYLGHVVWDWH

Overview FRQWUROWKDWFDQEHXVHGWRFKDUDFWHUL]HQRUPDODQGDEQRUPDO
SDS FRQGLWLRQV
SMART DIRECTED SEQUENCER
EN
Control File
Step Desc. File
ST
7KH6'6LQVWUXFWLRQDOORZVWZREDVLFW\SHVRIORJLFHTXDWLRQV
Length
No. of Steps
Position/Step: ER WUDQVLWLRQDO
No. of I/O
Prog file number ES
FRPELQDWRULDO
This Type of
Logic Equation: Does this:
Transitional provides traditional state-based control. This type of SDS instruction

is built around the state transition concept, where each input
transition directs the instruction to a unique next state using a logical
OR structure. One input change directs the instruction to step A,
another to step B, etc.
Combinatorial provides for the ANDing of inputs in addition to the OR function used
in transition equations. This allows complex combinations to be
accommodated more easily within the SDS framework with a
minimum number of steps.
Programming the SDS Instruction

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,PSRUWDQW :KHQ\RXHQWHUWKHControl FileDQGStep Desc.

FileRSHUDQGVPDNHFHUWDLQWKHILOHQXPEHUVLH
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1785-6.1 November 1998

Custom Application Routine Instructions SDS, DFA 18-3
Diagnostic Fault Annunciator (DFA) 7KH'LDJQRVWLF)DXOW$QQXQFLDWRU')$LQVWUXFWLRQPRQLWRUVLQSXWV

Overview \RXGHILQHEXWLWFDQQRWFRQWURORXWSXWV9DOLGLQSXWVFDQEH
DFA VWRUDJHSRLQWVVXFKDVELQDU\ELWV
EN
DIAGNOSTIC FAULT ANNUNCIATOR
Control File ER FRXQWHUWLPHUGRQHELWV
No. of I/O
Program file number RXWSXWVUHDORUORJLFDO
DQ\YDOLGELWDGGUHVV
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GLDJQRVWLFPHVVDJHVZLWKWKH')$LQVWUXFWLRQVXFKDVWRROFKDQJH
PHVVDJHVDQGRSHUDWLQJLQVWUXFWLRQV
Programming the DFA Instruction

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1785-6.1 November 1998

18-4 Custom Application Routine Instructions SDS, DFA
1RWHV
1785-6.1 November 1998

Appendix A
Instruction Timing and
Memory Requirements
Instruction Timing and Memory 7KHWLPHLWWDNHVIRUDSURFHVVRUWRVFDQDQLQVWUXFWLRQGHSHQGVRQWKH
Requirements W\SHRILQVWUXFWLRQWKHW\SHRIDGGUHVVLQJWKHW\SHRIGDWDZKHWKHU
WKHLQVWUXFWLRQKDVWRFRQYHUWGDWDDQGZKHWKHUWKHLQVWUXFWLRQLVWUXH
RUIDOVH
7KHWLPLQJDQGPHPRU\UHTXLUHPHQWVHVWLPDWHVLQWKLVFKDSWHUKDYH
WKHIROORZLQJDVVXPSWLRQV
GLUHFWDGGUHVVLQJ
LQWHJHUGDWDH[FHSWZKHUHQRWHG
QRGDWDW\SHFRQYHUVLRQV
DGGUHVVHVZLWKLQILUVWZRUGVRIWKHGDWDWDEOHIRU&ODVVLF
3/&SURFHVVRUVDGGUHVVHVZLWKLQILUVWZRUGVIRU
H[HFXWLRQWLPHVVKRZQLQµV
0HPRU\UHTXLUHPHQWVUHIHUWRWKHQXPEHURIZRUGVWKHLQVWUXFWLRQ
XVHV,QVRPHFDVHVDQLQVWUXFWLRQPD\KDYHDUDQJHRIPHPRU\
UHTXLUHPHQWV7KHUDQJHRIZRUGVH[LVWVEHFDXVHWKHLQVWUXFWLRQFDQ
XVHGLIIHUHQWW\SHVRIGDWDDQGDGGUHVVLQJPRGHV
7KHWDEOHVDUHGLYLGHGLQWRLQVWUXFWLRQWLPHVDQGPHPRU\
UHTXLUHPHQWVWKDWDUHVSHFLILFWRHDFKSURFHVVRU
If You Are Using this Processor: See Page:
Enhanced PLC-5, series C

Bit and Word Instructions A-2
File Instructions A-5
Classic PLC-5 (all series):

Bit and Word Instructions A-10
File Instructions A-13
1785-6.1 November 1998

A-2 Instruction Timing and Memory Requirements
Timing for Enhanced PLC-5 Bit and Word Instructions

Processors 7DEOH$$VKRZVWLPLQJDQGPHPRU\UHTXLUHPHQWVIRUELWDQGZRUG
LQVWUXFWLRQVIRU(QKDQFHG3/&SURFHVVRUV
Table A.A
Timing and Memory Requirements for Bit and Word Instructions
(Enhanced PLC-5 Processors)
Execution Time Execution Time (µs)

(µs) integer floating point Words of
Category Code Title
Memory1
True False True False
Relay XIC examine if closed .32 .16 12
XIO examine if open .32 .16 12
OTL output latch .48 .16 12
OTU output unlatch .48 .16 12
OTE output energize .48 .48 12
Branch branch end .16 .16 1
next branch .16 .16 1
branch start .16 .16 1
Timer and Counter TON timer on (0.01 base) 3.8 2.6 2-3
(1.0 base) 4.1 2.5
TOF timer off (0.01 base) 2.6 3.2 2-3

(1.0 base) 2.6 3.2
RTO retentive timer on 2-3

(0.01 base) 3.8 2.4
(1.0 base) 4.1 2.3
CTU count up 3.4 3.4 2-3
CTD count down 3.3 3.4 2-3
RES reset 2.2 1.0 2-3
(Continued)
Use the larger number for addresses beyond 2048 words in the processor’s data table.
)or every bit address above the first 256 words of memory in the data table, add 0.16 ms and 1 word of memory.
1785-6.1 November 1998

Instruction Timing and Memory Requirements A-3
Execution Time (µs) Execution Time (µs)

integer floating point Words of
Category Code Title
Memory1
Arithmetic ADD add 6.1 1.4 14.9 1.4 4-7
SUB subtract 6.2 1.4 15.6 1.4 4-7
MUL multiply 9.9 1.4 18.2 1.4 4-7
DIV divides 12.2 1.4 23.4 1.4 4-7
SQR square root 9.9 1.3 35.6 1.3 3-5
NEG negate 4.8 1.3 6.0 1.3 3-5
CLR clear 3.4 1.1 3.9 1.1 2-3
AVE average file 152+E25.8 30 162+E22.9 36 4-7
STD standard deviation 321+E84.3 34 329+E77.5 34 4-7
TOD convert to BCD 7.8 1.3 3-5
FRD convert from BCD 8.1 1.3 3-5
RAD radian 57.4 1.4 50.1 1.4 3-5
DEG degree 55.9 1.4 50.7 1.4 3-5
SIN sine 414 1.4 3-5
COS cosine 404 1.4 3-5
TAN tangent 504 1.4 3-5
ASN inverse sine 426 1.4 3-5
ACS inverse cosine 436 1.4 3-5
ATN inverse tangent 375 1.4 3-5
LN natural log 409 1.4 403 1.4 3-5
LOG log 411 1.4 403 1.4 3-5
XPY X to the power of Y 897 1.5 897 1.5 4-7
SRT sort file 3-5

(5/11, -5/20) 276 + 12[E**1.34] 227 278 + 16[E**1.35] 227
(-5/30, -5/40, -5/60, 224 + 25[E**1.34] 189 230 + 33[E**1.35] 189
-5/80)
(Continued)
1.Use the larger number for addresses beyond 2048 words in the processor’s data table.
E = number of elements acted on per scan
SRT true is only an approximation. Actual time depends on the randomness of the numbers.
1785-6.1 November 1998


Category Code Title
Memory1
Logic AND and 5.9 1.4 4-7
OR or 5.9 1.4 4-7
XOR exclusive or 5.9 1.4 4-7
NOT not 4.6 1.3 3-5
Move MOV move 4.5 1.3 5.6 1.3 3-5
MVM masked move 6.2 1.4 4-7
BTD bit distributor 10.0 1.7 6-9
Comparison EQU equal 3.8 1.0 4.6 1.0 3-5
NEQ not equal 3.8 1.0 4.5 1.0 3-5
LES less than 4.0 1.0 5.1 1.0 3-5
LEQ less than or equal 4.0 1.0 5.1 1.0 3-5
GRT greater than 4.0 1.0 5.1 1.0 3-5
GEQ greater than or 4.0 1.0 5.1 1.0 3-5

equal
LIM limit test 6.1 1.1 8.4 1.1 4-7
MEQ mask compare 5.1 1.1 4-7

if equal
Compare CMP all 2.48 + (Σ[0.8 + i]) 2.16 + Wi[0.56] 2.48 + (Σ[0.8 + i]) 2.16 + Wi[0.56] 2+Wi
Compute CPT all 2.48.+ (Σ[0.8 + i]) 2.16 + Wi[0.56] 2.48.+ (Σ[0.8 + i]) 2.16 + Wi[0.56] 2+Wi
i = execution time of each instruction (operation, e.g. ADD, SUB, etc.) used within the CMP or the CPT expression
Wi = number of words of memory used by the instruction (operation, e.g. ADD, SUB, etc) within the CMP or CPT expression
CMP or CPT instructions are calculated with short direct addressing
1785-6.1 November 1998

File Instructions
5HIHUWR7DEOH$%IRUWKHLQVWUXFWLRQWLPLQJIRUILOHLQVWUXFWLRQV
Table A.B
Timing and Memory Requirements for File, Program Control, and ASCII
Instructions (Enhanced PLC-5 Processors)
Time (µs) Time (µs)

Words of
Category Code Title integer floating point
Memory1
File FAL all 11 + (Σ[2.3 + i])E 6.16 + Wi[0.16] 11 + (Σ[2.3 + i])E 6.16 + Wi[0.16] 3-5 +Wi
Arithmetic
and Logic
File Search FSC all 11 + (Σ[2.3 + i])E 6.16 + Wi[0.16] 11 + (Σ[2.3 + i])E 6.16 + Wi[0.16] 3-5 +Wi
and
Compare
File COP copy 16.2+E[0.72] 1.4 17.8+E[1.44] 1.4 4-6
counter, timer, and 15.7+E[2.16] 1.4
control
FLL fill 15.7+E[0.64] 1.5 18.1+E[0.80] 1.5 4-6
counter, timer, and 15.1+E[1.60] 1.5
control
Shift BSL bit shift left 10.6+B[0.025] 5.2 4-7
Register
BSR bit shift right 11.1 + B[0.025] 5.2 4-7
FFL FIFO load 8.9 3.8 4-7
FFU FIFO unload 10.0+E[0.43] 3.8 4-7
LFL LIFO load 9.1 3.7 4-7
LFU LIFO unload 10.6 3.8 4-7
Diagnostic FBC 0 mismatch 15.4 + B[0.055] 2.9 6-11
1 mismatch 22.4 + B[0.055] 2.9
2 mismatches 29.9+ B[0.055] 2.9
DDT 0 mismatch 15.4 + B[0.055] 2.9 6-11
1 mismatch 24.5 + B[0.055] 2.9
2 mismatches 34.2 + B[0.055] 2.9
DTR data transitional 5.3 5.3 4-7
(Continued)
i = execution time of each instruction (operation, e.g. ADD, SUB, etc.) used within the FAL or the FSC expression
E = number of elements acted on per scan
B = number of bits acted on per scan
Wi = number of words of memory used by the instruction (operation, e.g. ADD, SUB, etc.) within the FAL or FSC expression
FAL or FSC instructions are calculated with short direct addressing
1785-6.1 November 1998


Words of
Memory1
Sequencer SQI sequencer input 7.9 1.3 5-9

SQL sequencer load 7.9 3.5 4-7
SQO sequencer output 9.7 3.7 5-9
Immediate IIN immediate input 1.1 2
I/O2 (-5/11, -5/20) 357
(-5/30, -5/40, -5/60, 307
-5/80)
IOT immediate output 1.1 2
(-5/11, -5/20) 361
(-5/30, -5/40, -5/60, 301
-5/80)
IDI immediate data input 1.1 4-7
(-5/20C) 200 + 1.4 (for
each word)
(-5/40C, -5/60C, and 200 + 1.4 (for
-5/80C) each word)
IDO immediate data output 1.1 4-7
(-5/20C) 230 + 1.4 (for
– each word)
(-5/40C, -5/60C, and 250 + 1.7 (for
-5/80C) each word)
Zone MCR master control 0.16 0.16 1
Control
Program JMP jump 8.9 + (file number 1.4 + (file number 2
Control − 2) ∗ 0.96 − 2) ∗ 0.96
LBL label 0.32 0.32 2+position
in label table
JSR3/ jump to subroutine/ 3+
RET return parameters/
PLC-5/11, -5/20, JSR
-5/30, -5/40, -5/40L, 1+
-5/60, -5/60L, -5/20E, parameters/
-5/40E RET
– 0 parameters 12.3 1.0 n/a n/a
– 1 parameter 16.1 1.0 17.3 1.0
– increase/parameter 3.8 n/a 5.0 n/a
PLC-5/80
– 0 parameters 315 1.0
– 1 parameter 340 1.0 349
– increase/parameter 31 n/a 33 1.0
(Continued)
2.Timing for immediate I/O instructions is the time for the instruction to queue-up for processing
3.Calculate execution times as follows: (time) + (quantity of additional parameters)(time/parameter). For example, if you are passing 3 integer parameters in a JSR
within a PLC-5/11 processor, the execution time =16.1 + (2)(3.8)=23.7µs.
B = number of bits acted on per scan
1785-6.1 November 1998


Words of
Memory1
Program SBR 0 parameters 12.3 1.0 1+

Control parameters
1 parameter 16.1 1.0 17.3 1.0
increase/ 3.8 5.0
parameter
END end negligible 1
TND temporary end 1
EOT end of transition 1
AFI always false 0.16 0.16 1
ONS one shot 3.0 3.0 2-3
OSR one shot rising 6.2 6.0 4-6
OSF one shot falling 6.2 5.8 4-6
FOR/ for next loop 8.1+ L[15.9] 5.3 + N[0.75] FOR 5-9
NXT (PLC-5/80) (151+L[277]) (152+N[6.1]) NXT 2
BRK break 11.3 + N[0.75] 0.9 1
UID user interrupt disable 1.0 1
(-5/11, -5/20) 175
(-5/30, -5/40, -5/60, 119
-5/80)
UIE user interrupt enable 1.0 1
(-5/11, -5/20) 170
(-5/30, -5/40, -5/60, 100
-5/80)
(Continued)
L = number of FOR/NXT loops
N = number of words in memory between FOR/NXT or BRK/NXT
1785-6.1 November 1998


Words of
Memory1
Process PID PID loop control 5-9

Control
Gains Independent 3.0 882 58
(-5/11, -5/20, -5/20E, 462
-5/20C)
(-5/30, -5/40, -5/40E, 655
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
ISA 1142
(-5/11, -5/20, -5/20E, 560
-5/20C)
(-5/30, -5/40, -5/40E, 895
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
Modes Manual 900
(-5/11, -5/20, -5/20E, 372
-5/20C)
(-5/30, -5/40, -5/40E, 420
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
Set Output 882
(-5/11, -5/20, -5/20E, 380
-5/20C)
(-5/30, -5/40, -5/40E, 440
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
Cascade Slave 1286
Master 840
ASCII2 ABL2 test buffer for line 3-5
(-5/11, -5/20) 316 214
(-5/30, -5/40, -5/60, 388 150
-5/80)
ACB 2 no. of characters in 3-5
buffer
(-5/11, -5/20) 316 214
(-5/30, -5/40, -5/60, 389 150
-5/80)
ACI string to integer 1.4 3-5
(-5/11, -5/20) 220 + C[11]
(-5/30, -5/40, -5/60, 140 + C[21.4]
-5/80)
(Continued)
2.Timing for ASCII instructions is the time for the instruction to queue-up for processing in channel 0.
1785-6.1 November 1998


Words of
Memory1
ASCII2 ACN string concatenate 1.9 4-7

(-5/11, -5/20) 237 + C[2.6]
(-5/30, -5/40, -5/60, 179 + C[5.5]
-5/80)
AEX string extract 1.9 5-9
(-5/11, -5/20) 226 + C[1.1]
(-5/30, -5/40, -5/60, 159 + C[2.2]
-5/80)
AHL2 set or reset lines 5-9
(-5/11, -5/20) 318 213
(-5/30, -5/40, -5/60, 526 157
-5/80)
AIC integer to string 1.4 3-5
(-5/11, -5/20) 260
(-5/30, -5/40, -5/60, 270
-5/80)
ARD2 read characters 4-7
(-5/11, -5/20) 315 214
(-5/30, -5/40, -5/60, 380 149
-5/80)
ARL2 read line 4-7
(-5/11, -5/20) 316 214
(-5/30, -5/40, -5/60, 388 151
-5/80)
ASC string search 1.9 5-9
(-5/11, -5/20) 222 + C[1.7]
(-5/30, -5/40, -5/60, 151 + C[3.0]
-5/80)
ASR string compare 3-5
(-5/11, -5/20) 234 + C[1.3] 202
(-5/30, -5/40, -5/60, 169 + C[2.4] 119
-5/80)
AWA2 write with append 4-7
(-5/11, -5/20) 319 215
(-5/30, -5/40, -5/60, 345 154
-5/80)
AWT2 write 4-7
(-5/11, -5/20) 318 215
(-5/30, -5/40, -5/60, 344 151
-5/80)
2.Timing for ASCII instructions is the time for the instruction to queue-up for processing in channel 0.
C = number of ASCII characters
1785-6.1 November 1998

Timing for Classic PLC-5 Bit and Word Instructions

Processors 7DEOH$&VKRZVWLPLQJDQGPHPRU\UHTXLUHPHQWVIRUELWDQGZRUG
LQVWUXFWLRQVIRU&ODVVLF3/&SURFHVVRUV
Table A.C
Timing and Memory Requirements for Bit and Word Instructions
(Classic PLC-5 Processors)

integer floating point
Category Code Title Words of Memory1
Relay XIC examine if closed 1.3 0.8 12
XIO examine if open 1.3 0.8 12
OTL output latch 1.6 0.8 12
OTU output unlatch 1.6 0.8 11
OTE output energize 1.6 1.6 12
Branch branch end 0.8 0.8 1
next branch 0.8 0.8 1
branch start 0.8 0.8 1
Timer and Counter TON timer on (0.01 base) 39 27 2-3

(1.0 base) 44 28
TOF timer off (0.01 base) 30 43 2-3

(1.0 base) 30 51
RTO retentive timer on 2-3

(0.01 base) 39 24
(1.0 base) 44 24
CTU count up 32 34 2-3
CTD count down 34 34 2-3
RES reset 30 14 2-3

1
Use the smaller number if all addresses are below word 4096; use the larger number if all addresses are above 4096.
2
For every bit address above the first 256 words of memory in the data table, add 0.8 µs to the execution time and 1 word of memory to the requirements.
(Continued)
1785-6.1 November 1998


Arithmetic ADD add 36 14 92 14 4-7
SUB subtract 36 14 92 14 4-7
MUL multiply 41 14 98 14 4-7
DIV divide 49 14 172 14 4-7
SQR square root 82 14 212 14 3-5
NEG negate 28 14 36 14 3-5
CLE clear 18 14 23 14 2-3
TOD convert to BCD 52 14 3-5
FRD convert from BCD 44 14 3-5
Logic AND and 36 14 4-7
OR or 36 14 4-7
XOR exclusive or 36 14 4-7
NOT not 27 14 3-5
Move MOV move 26 14 35 14 3-5
MVM masked move 55 14 6-9
Comparison EQU equal 32 14 42 14 3-5
NEQ not equal 32 14 42 14 3-5
LES less than 32 14 42 14 3-5
LEQ less than or equal 32 14 42 14 3-5
GRT greater than 32 14 42 14 3-5
GEQ greater than or equal 32 14 42 14 3-5
LIM limit test 42 14 60 14 4-7
MEQ mask compare if equal 41 14 4-7

1
(Continued)
1785-6.1 November 1998


Compute CPT add 67 34 124 34 6-9
subtract 67 34 124 34 6-9
multiply 73 34 130 34 6-9
divide 80 34 204 34 6-9
square root 113 33 244 34 5-7
negate 59 33 68 34 5-7
clear 49 30 55 34 4-5
move 58 33 5-7
convert to BCD 84 33 5-7
convert from BCD 75 33 5-7
AND 68 34 6-9
OR 68 34 6-9
XOR 68 34 6-9
NOT 59 34 5-7
Compare CMP equal 63 34 73 34 5-7
not equal 63 34 73 34 5-7
less than 63 34 73 34 5-7
less than or equal 63 34 73 34 5-7
greater than 63 34 73 34 5-7
greater than or equal 63 34 73 34 5-7

1
1785-6.1 November 1998

File Instructions
7KHLQVWUXFWLRQWLPLQJIRUILOHLQVWUXFWLRQVGHSHQGVRQWKHGDWDW\SH
QXPEHURIILOHVDFWHGRQSHUVFDQQXPEHURIHOHPHQWVDFWHGRQSHU
VFDQDQGZKHWKHUWKHLQVWUXFWLRQFRQYHUWVGDWDEHWZHHQLQWHJHUDQG
IORDWLQJSRLQWIRUPDWV
IRULQWHJHUWRIORDWLQJSRLQWFRQYHUVLRQDGG
µVIRUHDFKHOHPHQWDGGUHVV
µVIRUHDFKILOHDGGUHVVSUHIL[
IRUIORDWLQJSRLQWWRLQWHJHUFRQYHUVLRQDGG
µVIRUHDFKHOHPHQWDGGUHVV
µVIRUHDFKILOHDGGUHVVSUHIL[
Table A.D
Timing and Memory Requirements for File Instructions
Time (µs)
integer or
Category Code Title floating point
Memory1
True True False
File Arithmetic and Logic FAL add 98 + W[36.7 + N] 98 + W[95.1 + N] 54 7-12
subtract 98 + W[36.7 + N] 98 + W[95.1 + N] 54 7-12
multiply 98 + W[42.5 + N] 98 + W[101.2 + N] 54 7-12
divide 98 + W[51.1 + N] 98 + W[180.3 + N] 54 7-12
square root 98 + W[84.7 + N] 98 + W[220.5 + N] 54 6-10
negate 98 + W[29.2 + N] 98 + W[37.2 + N] 54 6-10
clear 98 + W[18.4 + N] 98 + W[24.0 + N] 54 5-8
move 98 + W[27.3 + N] 98 + W[36.2 + N] 54 6-10
convert to BCD 98 + W[54.3 + N] 54 6-10
convert from BCD 98 + W[45.4 + N] 54 6-10

1
W = number of elements acted on per scan
N = 2 × (number of integer file addresses) + 8 × (number of floating-point file addresses) + 6 × (number of timer, counter, or control file addresses) + (
number of
conversions between integer and floating point formats)
(Continued)
1785-6.1 November 1998

Time (µs)
integer or
Memory1
True True False
File Arithmetic and Logic AND 98 + W[37.2 + N] 54 7-12
OR 98 + W[37.2 + N] 54 7-12
XOR 98 + W[37.2 + N] 54 7-12
NOT 98 + W[28.2 + N] 54 6-10
File Search and Compare FSC all comparisons 93 + W[32.7 +N] 93 + W[43.3 +N] 54 6-10
File COP copy 88 + 2.7W 104 + 3.8W 20 4-7
counter, timer, and 98 + 5.8W

control
FLL fill 81 + 2/.1 W 100 + 3.1W 15 4-7
counter, timer, and 97 + 4.4W

control
Shift Register BSL bit shift left 74 + 3.4W 57 4-7
BSR bit shift right 78 + 3.0W 57 4-7
FFL FIFO load 54 44 4-7
FFU FIFO unload 68 + 3.2W 46 4-7
Diagnostic FBC file bit compare 6-11
0 mismatch 75 + 6W 31
2 mismatches 151 + 6W 31
DDT diagnostic detect 6-11
2 mismatches 161 + 6W
1
W = number of elements acted on per scan
N = 2 × (number of integer file addresses) + 8 × (number of floating-point file addresses) + 6 × (number of timer, counter, or control file addresses) + (
number of
conversions between integer and floating point formats)
(Continued)
1785-6.1 November 1998

Time (µs)
integer or
Memory1
True True False
Zone Control MCR master control 12 18 1
Immediate I/O IIN immediate input 2-3
local 196 16
remote 204 16
IOT immediate output 2-3
local 202 16
remote 166 16
Sequencer SQI sequencer input 57 14 5-9
SQL sequencer load 55 42 4-7
SQO sequencer output 77 42 5-9
Jump and Subroutine JMP jump 45 15 2-3
JSR jump to subroutine
SBR 0 parameters 56 15 2-3
1 parameter 91 15 3-5
add per parameter 21
RET return from sub.
0 parameters 48 13 1
1 parameter 70 13 2-3
add per parameter 21
LBL label 12 12 3
1
(Continued)
1785-6.1 November 1998

Time (µs)
integer or
Memory1
True True False
Miscellaneous END end negligible negligible 1
TND temporary end negligible 15 1
AFI always false 15 13 1
ONS one shot 28 30 2-3
DTR data transitional 41 41 4-7
BTD bit distributor 77 14 6-11
PID PID loop control 608 34 5-9
BTR block transfer read See chapter 15
BTW block transfer write
MSG message See chapter 16

1Use the smaller number if all addresses are below word 4096; use the larger number if all addresses are above 4096.
1785-6.1 November 1998

Program Constants 8VHSURJUDPFRQVWDQWVLQFRPSDUHFRPSXWHDQGILOHLQVWUXFWLRQVWR

LPSURYHLQVWUXFWLRQH[HFXWLRQWLPHV,QWHJHUFRQVWDQWVDQG
IORDWLQJSRLQWFRQVWDQWVH[HFXWHLQOHVVWKDQµV
Direct and Indirect Elements – $GGLWLRQDOH[HFXWLRQWLPHIRUGLUHFWO\DQGLQGLUHFWO\DGGUHVVHG

Enhanced PLC-5 Processors HOHPHQWVGHSHQGVRQORFDWLRQLQPHPRU\UHIHUHQFHWRWKHEHJLQQLQJ
RIDOOGDWDILOHVRXWSXWILOHZRUGZKHWKHUGDWDLVVWRUHGDWWKH
VRXUFHRUGHVWLQDWLRQDGGUHVVDQGZKHWKHUWKHLQVWUXFWLRQFRQYHUWV
GDWD7DEOH$(OLVWVWLPHVWRDGGWRLQVWUXFWLRQH[HFXWLRQWLPHV
Table A.E
Additional Execution Time (Enhanced PLC-5 Processors)
Modifier in µsec
Addressing Mode Data Type (add for each
operand)
Direct Integer 0
Float 0
Index Integer 1.1

Float 1.8
Counter-Timer-Control 2.4
Immediate Integer 0.24

Float 1.0
Indirect 6.6 + W[0.09]
Float-to-integer 5.6
Integer-to-float 8.4
1785-6.1 November 1998

Direct and Indirect Elements – $GGLWLRQDOH[HFXWLRQWLPHIRUGLUHFWO\DGGUHVVHGHOHPHQWVGHSHQGVRQ

Classic PLC-5 Processors ORFDWLRQLQPHPRU\UHIHUHQFHWRWKHEHJLQQLQJRIDOOGDWDILOHVRXWSXW
ILOHZRUGZKHWKHUGDWDLVVWRUHGDWWKHVRXUFHRUGHVWLQDWLRQ
DGGUHVVDQGZKHWKHUWKHLQVWUXFWLRQFRQYHUWVGDWD7DEOH$)OLVWV
WLPHVWRDGGWRLQVWUXFWLRQH[HFXWLRQWLPHV
Table A.F
Additional Execution Time Based on Source and Destination Addresses
Source Destination
(integer to floating point) (floating point to integer)
Data Type
0-2K 2-4K 4K+ 0-2K 2-4K 4K+
integer 0 1 2 0 1 2
floating point 0 3 4 0 3 4
data conversion 8 9 10 33 34 35
:KHQILOHDGGUHVVHVSUHIL[LQWKHH[SUHVVLRQRUGHVWLQDWLRQ

DGGUHVVFRQWDLQLQGLUHFWDGGUHVVHVIRUILOHQXPEHUVDGG
µV ZKHQWKHLQGLUHFWDGGUHVVLVLQWHJHUW\SH
µV ZKHQWKHLQGLUHFWDGGUHVVLVIORDWLQJSRLQWW\SH
µV ZKHQWKHLQGLUHFWDGGUHVVLVWLPHUFRXQWHURU
FRQWUROW\SH
:KHQILOHDGGUHVVHVLQWKHH[SUHVVLRQRUGHVWLQDWLRQFRQWDLQLQGLUHFW
DGGUHVVHVIRUHOHPHQWQXPEHUVDGG
µV ZKHQWKHLQGLUHFWDGGUHVVLVLQWHJHUW\SH
µV ZKHQWKHLQGLUHFWDGGUHVVLVIORDWLQJSRLQWW\SH
µV ZKHQWKHLQGLUHFWDGGUHVVLVWLPHUFRXQWHURU
FRQWUROW\SH
,IWKHILOHDGGUHVVFRQWDLQVWZRLQGLUHFWDGGUHVVHVDGGRQO\RQHYDOXH
WKHODUJHVW)RUH[DPSOHIRU)>1@>1@DGGµVLQGLUHFW
IORDWLQJSRLQWILOHDGGUHVV
1785-6.1 November 1998

0XOWLSO\WKHDGGLWLRQDOWLPHE\WKHQXPEHURIHOHPHQWVLQWKHILOHIRU
DQ\W\SHRIILOHRUILOHDGGUHVV)RUH[DPSOH
([SUHVVLRQ1>1@ )
DGGIRUFRQYHUWLQJWRIORDWLQJSRLQW
DGGIRULQGLUHFWDGGUHVV
'HVWLQDWLRQ1
DGGIRUFRQYHUWLQJWRLQWHJHU
)$/PXOWLSO\:>1LQGLUHFWDGGUHVVLQJ@
1
:
([HFXWLRQWLPHLQ$//PRGH
>@
µV
Indirect Bit or Elements Addresses $GGLWLRQDOH[HFXWLRQWLPHVIRULQGLUHFWO\DGGUHVVHGELWVDQGHOHPHQWV

– Classic PLC-5 Processors GHSHQGVRQWKHQXPEHURILQGLUHFWDGGUHVVHVLQWKHRYHUDOODGGUHVV
7DEOH$*OLVWVWKHDGGLWLRQDOWLPHV
Table A.G
Additional Execution Times for Indirectly Addressed Bits and Elements
Classic PLC-5 Processors
Time (µs) for Time (µs) for

Data Type Variable File or Variable File and
Element Element
Bit in binary file 57 60
Bit in integer file 60 63
Bit in timer, counter, or control file 64 66
Integer (N) 42 42
Timer (T), counter (C), or control 43 44

(R) file
Floating point (F) 61 64
Converting integer to floating point 71 77
Converting timer, counter, or control 85 81

to floating point
1785-6.1 November 1998

Additional Timing Considerations – 7DEOH$+OLVWVDGGLWLRQDOWLPLQJFRQVLGHUDWLRQV

Classic PLC-5 Processors Table A.H
Additional Timing Considerations (Classic PLC-5 Processors)
Tasks Time (milliseconds)
Housekeeping 4.5 max
Resident Local I/O scan 1 per assigned rack number
Remote I/O scan 10 per assigned rack number at 57.6 Kb
1785-6.1 November 1998

Appendix B
SFC Reference
Appendix Objectives 8VHWKLVDSSHQGL[WRPDNHVXUH\RXU6)&PHHWV\RXUSURFHVVRU¶V
UHTXLUHPHQWVDQGWRPDNHVXUH\RXU6)&UXQVWKHZD\\RXH[SHFW
7KLVDSSHQGL[GLVFXVVHV
6)&VWDWXVLQIRUPDWLRQLQWKH3URFHVVRU6WDWXVILOH
PHPRU\DOORFDWLRQ
G\QDPLFFRQVWUDLQWV
VFDQQLQJVHTXHQFHV
UXQWLPHV
SFC Status Information in the 7DEOH%$OLVWVWKHZRUGVDQGELWVLQWKHSURFHVVRUVWDWXVILOH6WKDW

Processor Status File FRQWDLQ6)&LQIRUPDWLRQ
Table B.A
SFC Status Words
Word: Title: Description:
S:1/15 First pass Set: Processor began first program scan of

the next active step in the SFC
Reset: Processor completed scanning the
currently active step
S:8 Current program The time for the processor to scan through all active
scan time steps one time
If you are using multiple main control programs on

a Enhanced PLC-5 processor, this time is the
current total of one scan of all main control
programs.
S:9 Maximum program The maximum time for the processor to scan
scan time through all active steps one time (word S:8)

an Enhanced PLC-5 processor, this time is the
maximum of all previous totals. This value is
maintained until user resets it.
S:11/3 SFC fault Set: Processor detected an SFC fault and

stored a fault code in word 12
Reset: No SFC fault
S:11/5 Start up fault Set: Processor detected a start-up protection

fault (see word 26 bit 1)
Reset: No fault, start up allowed
(Continued)
1785-6.1 November 1998

B-2 SFC Reference
Word: Title: Description:
S:12 Fault codes 74 Fault in SFC file

75 SFC has more than 24 active steps
77 Missing file or file of wrong type for step,
action or transition
78 SFC execution cannot continue after
interruption
79 Cannot run SFC because PLC-5 is
incompatible
S:13 Faulted File Contains the file number if an SFC fault occurred
Number
S:14 Faulted Rung Contains the faulted rung number

Number
S:26/0 * Restart/continue Set: Processor restarts SFC at the active

steps where it left off due to power loss
or processor mode change
Reset: Processor restarts SFC at first step
S:26/1 * Start-up protection Set: Protection enabled; processor goes to

after power loss fault routine at power up and processor
sets word 11, bit 5
Reset: Protection disabled; processor powers
up in run mode
S:28 * Program Maximum time (milliseconds) for scanning a single

watchdog setpoint pass through all active steps

an Enhanced PLC-5 processor this time is the total
of one scan of all main control programs.
S:79 * MCP inhibit, file Information on the individual multiple main control
(except number and scan programs.
for scan time
time) – Enhanced PLC-5 processors only.
S:127
* You enter values for these words/bits
1785-6.1 November 1998

SFC Reference B-3
Memory Allocation 7KHPHPRU\UHTXLUHPHQWVIRU\RXU6)&GHSHQGRQWKHVWUXFWXUHV\RX

XVH7DEOH%%VKRZVHVWLPDWHGZRUGXVDJHIRU6)&VWUXFWXUHV
Table B.B
SFC Memory Usage
Uses this Amount of Memory:

This Structure:
Classic PLC-5 Processor Enhanced PLC-5 Processor
start and end of program 2 words 19 words
each step /transition pair 8 words 16 + 6a words

a = number of actions in step
6 words
each action
each selection branch 5n + 5 words 11 + 6a + 7n

n = number of a = number of actions in step
branches n = number of paths
each simultaneous n + 1 word 3n + 1

branch, diverging n = number of n = number of paths
branches
each simultaneous n2 + 6n + 3 words 5 + 11n + 6a

branch, converging n = number of a = number of actions in all
branches converging
steps for that simultaneous
branch
n = number of paths
each label or 1 word 1 word

GOTO statement
each chart compression 3 words 3 words
)LJXUH%VKRZVDVDPSOH6)&DQGWKHHVWLPDWHGPHPRU\
UHTXLUHPHQWVIRUWKH6)&
1785-6.1 November 1998

B-4 SFC Reference
Figure B.1
Sample SFC and Memory Requirements
Classic PLC-5 Processors Enhanced PLC-5 Processors
one action/step
step/transition pair a=1
8 words 16 + 6a=22 words
simultaneous diverge simultaneous diverge
n=2 n=2
n +1 = 3 words 3n +1 = 7 words
selection branch selection branch

n=3 n=3 a=1
5n + 5 = 20 11 + 6a + 7n = 38 words
3 step/transition pairs 3 step/transition pairs a =1

3 x 8 = 24 words 3 (16 + 6a) = 66 words
simultaneous converge simultaneous converge

n=2 n=2 a=2
n2 + 6n + 3 = 19 words 5 + 11n + 6a = 39 words
step/transition one action/step a = 1

8 words 16 + 6a = 22 words
194 words (sub total)

+ 18 words (start and end of program)
82 words (sub total) (8 actions * 6 words – assumes
+ 2 words (start and end of program) 1 unique action per step)
84 words total for SFC 260 words total for SFC
1785-6.1 November 1998

SFC Reference B-5
Dynamic Constraints – Classic ,I\RXDUHXVLQJD&ODVVLF3/&SURFHVVRUDQG\RXU6)&KDVPRUH

PLC-5 Processors Only WKDQSDUDOOHOSDWKV\RXQHHGWRGHWHUPLQHWKHQXPEHURISDUDOOHO
SDWKVWKDWFRXOGEHDFWLYHDWRQHWLPH7KHG\QDPLFOLPLWLVSDUDOOHO
SDWKVDFWLYHDWWKHVDPHWLPHIRUD&ODVVLF3/&SURFHVVRU
:KHQDWUDQVLWLRQJRHVWUXHPRPHQWDULO\ERWKWKHSUHYLRXVO\DFWLYH
VWHSVQRZZDLWLQJIRUSRVWVFDQDQGWKHQHZO\DFWLYHVWHSVDUHRQ
WKHH[HFXWLRQTXHXHWRJHWKHU<RXFDQKDYHXSWRSDUDOOHODFWLYH
VWHSVDVORQJDV\RXFDQJXDUDQWHHWKDWQRPRUHWKDQRQHWUDQVLWLRQ
JRHVWUXHDWRQHWLPH
'HWHUPLQHWKHQXPEHURIDFWLYHVWHSVE\FRXQWLQJWKHVWHSVRQHDFK
VLGHRIWKHWUDQVLWLRQVWKDWFRQWUROWKHZLGHVWDUHDRIWKH6)&)RU
H[DPSOHWUDQVLWLRQVWKDWDUHWUXHDWWKHVDPHWLPHDFFRXQWIRUDW
OHDVWVLPXOWDQHRXVDFWLYHVWHSV,IDQ\QHZVLPXOWDQHRXV
GLYHUJHQFHVIROORZRQHRIWKHVHWUDQVLWLRQVWKHPD[LPXPRI
DFWLYHSDWKVLVH[FHHGHG
,IWKHIXQFWLRQFKDUWLQ)LJXUH%LVDWWKHSRLQWZKHUHDOOVKDGHG
VWHSVDUHDFWLYHDQGDOORIWKHWUDQVLWLRQVIROORZLQJWKRVHVWHSV
EHFRPHWUXHDWWKHVDPHWLPHWKHV\VWHPDWWHPSWVWRKDYHDFWLYH
VWHSVIRUSRVWVFDQIRUILUVWVFDQDQGWKHSURFHVVRUZLOOIDXOW
1785-6.1 November 1998

B-6 SFC Reference
Figure B.2
Dynamic Limit of Active Steps Could Be Exceeded
1785-6.1 November 1998

SFC Reference B-7
Scanning Sequences 7KHSURFHVVRUVFDQVWKH6)&IURPWRSWRERWWRPOHIWWRULJKW:KHQ

WKHVFDQHQFRXQWHUVDFWLYHSDUDOOHOVWHSVWKHSURFHVVRUUXQVWKHODGGHU
ORJLFLQWKHOHIWPRVWVWHSILUVWWKHQPRYHVWRWKHODGGHUORJLFLQWKH
QH[WSDUDOOHOVWHSXQWLODOODFWLYHVWHSVDUHUXQ7KHSURFHVVRU
UHFRJQL]HVSDUDOOHOVWHSVE\WKHLUSRVLWLRQZLWKUHVSHFWWRWKHLU
FRPPRQGLYHUJHQFHQRWQHFHVVDULO\E\WKHLUSRVLWLRQRQWKHVFUHHQ
Step and Transition Scanning

,QJHQHUDOWKHSURFHVVRUVFDQVDQDFWLYHVWHSWKHQVFDQVWKH,2DQG
FRQWLQXHVWKLVF\FOHXQWLOWKHWUDQVLWLRQORJLFLVWUXH6FDQQLQJWKHVWHS
LQFOXGHVHYDOXDWLQJDOOVWHSDFWLRQTXDOLILHUVDQGVFDQQLQJDOO
DSSURSULDWHDFWLRQV:KHQWKHWUDQVLWLRQLVWUXHWKHSURFHVVRUVFDQV
WKHFXUUHQWVWHSRQHPRUHWLPHSRVWVFDQ'XULQJSRVWVFDQWKH
SURFHVVRUIRUFHVDOOUXQJVLQWKHVWHSIDOVHDQGUHVHWVUXQJORJLF7KH
SURFHVVRUGRHVQRWXSGDWH,2EHWZHHQDSRVWVFDQDQGWKHVFDQRIWKH
QH[WDFWLYHVWHS)LJXUH%VKRZVWKHVFDQVHTXHQFHIRUDVWHS
WUDQVLWLRQDQGSRVWVFDQ,I\RXDUHXVLQJ(QKDQFHG3/&SURFHVVRUV
\RXFDQFRQILJXUHWKHVFDQDQGSRVWVFDQRSHUDWLRQV)RUPRUH
LQIRUPDWLRQVHH\RXUSURJUDPPLQJPDQXDO
,PSRUWDQW 6XEFKDUWVDFWLYDWHGE\DFKDUWDUHVFDQQHGMXVWSULRUWR
V\VWHPKRXVHNHHSLQJ
Figure B.3
Scan Sequence for a Step, Transition, and Postscan
A scan of step A
A pA postcan of step A
X0 I/O I/O scan

hk housekeeping
B
Xn transition scan
X1 F false
T true
F hk
A I/O X0 F hk
T hk pA B I/O X1
T hk pB
15556
1785-6.1 November 1998

B-8 SFC Reference
Selected Branch Scanning

7KHSURFHVVRUVHOHFWVRQHSDWKRIPXOWLSOHSDUDOOHOSDWKVLQDVHOHFWHG
EUDQFK)LJXUH%7KHSURFHVVRUWHVWVWUDQVLWLRQV;WKURXJK;Q
IURPOHIWWRULJKWXQWLORQHRIWKHWUDQVLWLRQVEHFRPHWUXH7KHSDWK
ZLWKWKHILUVWWUXHWUDQVLWLRQLVWKHDFWLYHSDWK
Figure B.4
Selected Branch – Divergence
//
X0 X1 X2 X7
%HFDXVHRQO\RQHSDWKLVDFWLYHWKHVFDQVHTXHQFHIRUWKH
FRQYHUJHQFHLVWKHVDPHDVIRUDVWHSDQGWUDQVLWLRQ)LJXUH%
VKRZVWKHVFDQVHTXHQFHIRUWKHGLYHUJHQFHDQGFRQYHUJHQFHRID
VHOHFWHGEUDQFK
1785-6.1 November 1998

SFC Reference B-9
Figure B.5
Scan Sequence for a Selected Branch - Divergence and Convergence
A scan of step A A
pA postcan of step A
I/O I/O scan X0 X1

hk housekeeping
B C n
oh overhead
X2 X3
Xn transition scan
F false
T true Classic PLC-5 Processors: maximum of 7 selections
n transition number
Enhanced PLC-5 Processors: maximum of 16 selections
F hk
F oh X1 F hk
T hk pA C I/O X3
T hk pC
A I/O X0
F hk
T hk pA B I/O X2
T hk pB
15557
Simultaneous Branch Scanning

7KHSURFHVVRUVFDQVDOOSDUDOOHOSDWKVLQDVLPXOWDQHRXVEUDQFK
)LJXUH%2QWKHILUVWVFDQWKHSURFHVVRUVFDQVVWHS%WKHQVWHS
&XQWLOWKHSURFHVVRUVFDQVDOOWKHVWHSVRQWKHGLYHUJHQFH
Figure B.6
Simultaneous Branch – Divergence
//
B C D N
2QVXEVHTXHQWVFDQVWKHSURFHVVRUVFDQVLQWKHRUGHURIVWHS,2DQG
WUDQVLWLRQIRUHDFKSDWKVWDUWLQJIURPWKHOHIW
1785-6.1 November 1998

B-10 SFC Reference
7KHYHUWLFDOSURJUHVVLRQIURPVWHSWRVWHSLVLQGHSHQGHQWRIWKHDFWLYH
VWHSVRQWKHRWKHUSDUDOOHOSDWKV)LJXUH%
Figure B.7
Simultaneous Branch - Convergence
//
7KHFRPPRQWUDQVLWLRQFDQQRWJRWUXHXQWLOWKHSURFHVVRUVFDQVDOOWKH
VWHSVLQWKHVLPXOWDQHRXVEUDQFKDWOHDVWRQFH2QFHWKHWUDQVLWLRQ
JRHVWUXHWKHSURFHVVRUGRHVQRWVFDQWKHUHPDLQLQJSDWKVLQWKH
EUDQFKWKHSURFHVVRUSRVWVFDQVHDFKVWHSLQWKHEUDQFK)LJXUH%
VKRZVWKHVFDQVHTXHQFHIRUWKHGLYHUJHQFHDQGFRQYHUJHQFHRID
VHOHFWHGEUDQFK
Figure B.8
Scan Sequence for a Simultaneous Branch – Divergence and
Convergence
A
A scan of step A
X0 pA postcan of step A
I/O I/O scan

hk housekeeping**
B C n
Xn transition scan
F false
X1 T true
Classic Processors: maximum of 7 selections oc convergence overhead
Enhanced PLC-5 Processors: maximum of 16 selections od divergence overhead
F hk
X1
F C I/O
F hk
T hk pB oc pC
X1
A I/O X0 F hk B I/O
* T hk pB oc pC
T hk pA B od C I/O X1
T hk pB oc pC
15558
* In an Enhanced PLC-5 Processors, these states do not occur if scan
configuration is set to ADVANCED mode.
** Any subcharts tied to this MCP execute now, followed by execution

of subsequent MCPs. If this chart is MCP B and has active subchart
actions while MCP A and C have ladder programs the sequence is:
MCP A, Chart in MCP B, MCP B's subcharts, MCP C
1785-6.1 November 1998

SFC Reference B-11
SFC Example and Scan Sequence

)LJXUH%VKRZVDQH[DPSOH6)&)LJXUH%VKRZVWKHVFDQ
VHTXHQFHIRUWKHH[DPSOH6)&8VHWKLVH[DPSOH6)&DQGVFDQ
VHTXHQFHDVDJXLGH7KHVHILJXUHVPD\QRWDSSO\WR\RXUV\VWHP
Figure B.9
Example SFC for Scan Sequence Example
start
X0 X1 X2
B C D
X3 X4 X5
E X6 G
J
X7
X9
I
X8
X10
end
1785-6.1 November 1998

B-12 SFC Reference
Figure B.10
Scan Sequence Example for the Example SFC
F hk
F oh X2
F hk
T h k p A D I /O X5 F hk
T h k p D J I /O X9
F oh X1
T hk pJ
F hk
T hk p A C I/O X4 F hk
T hk p C K I/O X 10
A I /O X0 T hk pK
F hk F hk
T h k p A B I/O F F G I /O X7
X3
F o d G I /O h k E I /O F I /O X6 F H I /O X7 T
T hk pB E od F T F h k E I/O X7 * T
X6 * T
A = step scan (A - K)
pA = post scan (A - K) T o d G I /O h k E I /O p F H I /O G I /O X7
I/O = I/O scan
XN = transition (1 - 10)
T=true F hk
F=false X8
T hk pE oc pH oc pG I I /O
oh = overhead
oc = convergence overhead T hk pI
od = divergence overhead * In an Enhanced PLC-5 Processor, these states do not occur if
hk = housekeeping scan configuration is set to ADVANCED mode. 15303
Run Times – Classic PLC-5 7RGHWHUPLQHWKHUXQWLPHRI\RXUSURFHVVRUPHPRU\ILOHRQD&ODVVLF

Processors 3/&SURFHVVRU\RXDGGWKHUXQWLPHIRUODGGHUORJLFDQGWKHUXQ
WLPHIRUWKH6)&)RULQIRUPDWLRQDERXWUXQWLPHVIRUODGGHUORJLF
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1785-6.1 November 1998

SFC Reference B-13
Using Sequence Diagrams to Determine Run Time

7DEOH%&OLVWVWKHUXQWLPHVWRDGGEDVHGRQWKHVHTXHQFHGLDJUDP
IRU\RXU6)&
Table B.C
Run Times for Sequence Diagram Sections – Classic PLC-5 Processors
Takes this Amount of Time

This Event:
(in milliseconds):
A time to execute logic of step A + 0.1 ms
pA time to scan logic of step A with rungs false + 0.1 ms
XN transition N false (F): time to scan logic + 0.1 ms

transition N true (T): time to scan logic + .25 ms
I/O (I/O scan) 0.6 ms
hk (housekeeping) 0.7 ms (increases with increasing DH+ traffic)
oh (overhead) 0.02 ms
od (divergence overhead) 0.3 ms
oc (convergence overhead) 0.2 ms
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1785-6.1 November 1998

B-14 SFC Reference
Figure B.11
Minimum Scan Time for a Step and Transition Pair
X0
X1
1.6 ms
F hk 1.6 ms
A I/O X0 F hk
T hk pA B I/O X1
T hk pB
1.9 ms 1.9 ms
14271
Using Equations to Determine Run Time

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DUHIDOVH8VHWKLVHTXDWLRQ7DEOH%'
Tmilliseconds = 0.8a + 0.7 + Tscan
Table B.D
Variables for Steady-State Scan Time
Where: Is:
Tmilliseconds steady-state scan time in milliseconds
a number of active steps
Tscan total time to scan logic in all active steps and associated false transitions
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1785-6.1 November 1998

SFC Reference B-15
)RUDVHOHFWHGSDWKGLYHUJHQFHWKHEHVWFDVHLVZKHQWKHWUDQVLWLRQ
JRHVWUXHMXVWEHIRUHWKH,2VFDQ8VHWKLVHTXDWLRQ7DEOH%(
A
//
X0 X1 X2 Xn
B C D N
Tmilliseconds = TX + pA + TS + 0.02(n±1) + 1.55 + 0.8a + T0
Table B.E
Variables for Selected-Path Divergent Scan Time
Where: Is:
Tmilliseconds transition scan time in milliseconds from step A to the first step in
selected path N
TX sum of scan times of logic of transitions X0, X1, . . . , Xn in the

divergence, up to and including the selected transition
pA postscan time for the step (step A) preceding the divergence
TS scan time for logic in the new step (step N)
n path number selected (1-7, from left to right)
a number of active steps outside the divergence
T0 sum of scan times of logic in all other active steps and transitions
parallel to the divergence, but outside of the divergence
1785-6.1 November 1998

B-16 SFC Reference
)RUDVLPXOWDQHRXVGLYHUJHQFHWKHEHVWFDVHLVZKHQWKHWUDQVLWLRQ
JRHVWUXHMXVWEHIRUHWKH,2VFDQ8VHWKLVHTXDWLRQ7DEOH%)
A
X0
//
B C D N
Tmilliseconds = TX0 + pA + TS + 0.3(n±1) + 1.97 + 0.8a + T0
Table B.F
Variables for Simultaneous-Path Divergent Scan Time
Where: Is:
Tmilliseconds transition time in milliseconds from when transition X0 goes true

until the processor finishes scanning the last simultaneous step
(step N) in the divergence
TX0 scan time of logic in transition X0
pA time to do a post-scan of step A
TS sum of scan times of logic in new steps (step B, step C, . . . , step N)
n number of simultaneous active steps in the divergence
a number of parallel active steps outside the divergence
parallel to the divergence, but outside of the divergence
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1785-6.1 November 1998

SFC Reference B-17
&RQYHUJHQW6FDQ7LPHLVZKHQDVLPXOWDQHRXVEUDQFKHQGV7KH
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WKLVHTXDWLRQ7DEOH%*
F G H N
//
X1
Tmilliseconds = TX1 + Tp + TZ + 0.2(n±1) + 1.5 + 0.8a + T0
Table B.G
Variables for Simultaneous-Path Convergent Scan Time
Where: Is:
Tmilliseconds transition time in milliseconds from when transition X1 goes true

until the processor finishes scanning step Z
TX1 scan time of logic in transition X1
Tp sum of postscan times of steps F, G, . . . , N
TZ scan time of logic in step Z
n number of simultaneous active steps in the convergence
a number of parallel active steps outside of the convergence
parallel to the convergence, but outside of the convergence
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1785-6.1 November 1998

B-18 SFC Reference
1RWHV
1785-6.1 November 1998

Appendix C
Valid Data Types for
Instruction Operands
Appendix Objectives 7KLVDSSHQGL[OLVWVDOORIWKHDYDLODEOHLQVWUXFWLRQVDQGWKHLURSHUDQGV
DQGWKHGDWDW\SHVYDOXHVWKDWDUHYDOLGIRUHDFKRSHUDQG
7KHIROORZLQJWDEOHH[SODLQVHDFKYDOLGGDWDW\SHYDOXH
This Data
Accepts:
Type/Value:
immediate any value between –32,768 and 32,767

(program constant)
integer any integer data type: integer, timer, counter, status, bit, input,
output, ASCII, BCD, control (e.g., N7:0, C4:0, etc.)
float any floating point data type with 7-digit precision (valid range is
±1.1754944e–38 to ±3.4028237e+38).
block transfer any block transfer data type (e.g., BT14:0)
ControlNet transfer any CT data type (e.g., CT14:0)
message any message data type (e.g., MG15:0)
PID any PID data type (e.g., PD16:0) or integer data type
(e.g., N7:0)
string any string data type (e.g., ST12:0)
SFC status any SFC status data type (e.g., SC17:0)
Instruction Operands and Valid 7DEOH&$VKRZVWKHSURJUDPPLQJLQVWUXFWLRQV\RXFDQXVHDQGWKH

Data Types RSHUDQGVIRUWKRVHLQVWUXFWLRQV<RXFDQDOVRXVHWKLVWDEOHWRIRUPDW
LQVWUXFWLRQVLQ$6&,,IRULPSRUWLQJ)RUPRUHLQIRUPDWLRQRQ
LPSRUWLQJVHH\RXUSURJUDPPLQJPDQXDO
,QVWUXFWLRQVPDUNHGZLWKDQDVWHULVN DUHRQO\VXSSRUWHGE\
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7DEOH&$
HQFORVHDOORIWKHRSHUDQGVLQSDUHQWKHVHV
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1785-6.1 November 1998

C-2 Valid Data Types for Instruction Operands
Table C.A
Programming Instructions and Operands
Require
Instruction Description Operand Valid Value False-to-True
Transition
ABL * ASCII Test Buffer for Line channel immediate, 0-4 integer yes
control control
ACB * ASCII Number of Characters channel immediate, integer yes

in Buffer
control control
ACI * ASCII String to Integer source string no
destination integer
ACN * ASCII String Concatenate source A string no
source B string
destination string
ACS * Arc Cosine source immediate, float (in radians), no

integer
destination float (in radians), integer
ACT * SFC action action number immediate N/A

(only for ASCII import/export)
file number 0 - 999
destination string
ADD ADD source A immediate, integer, float no
source B immediate, integer, float
destination integer, float
AEX * String Extract source string no
index immediate, 0-82 integer
number immediate, 0-82 integer
destination string
AFI Always False none no
AHL * ASCII Set/Reset channel immediate, 0-4 integer yes

Handshake Lines
handshake AND mask immediate, Hex integer yes
handshake OR mask immediate, Hex integer
control control
AIC * ASCII Integer to String source immediate, integer no
destination string
1785-6.1 November 1998

Valid Data Types for Instruction Operands C-3
Require
Transition
AND Logical AND source A integer no
source B integer
destination integer
ARD * ASCII Read Characters channel immediate, 0-4 integer yes
destination string
control control
string length 0 - 82
ARL * ASCII Read Line channel immediate, 0-4 integer yes
destination string
control control
ASC * ASCII String Search source string no
index immediate, 0-4 integer
search string
result integer
ASN * Arc Sine source immediate, float (in radians) no
destination float (in radians)
ASR * ASCII String Compare source A string no
source B string
ATN * Arc Tangent source immediate, float (in radians) no
AVE * Average File file integer, float yes
control control
length 1 - 1000
position 0 - 999
AWA * ASCII Write with Append channel immediate, 0-4 integer yes
source string
control control
1785-6.1 November 1998

Require
Transition
AWT * ASCII Write channel immediate, integer yes
source string
control control
length 0 - 82 yes
BRK Break none no
BSL Bit Shift Left file binary yes
control control
bit address bit
length 1 - 16000 (length in bits)
BSR Bit Shift Right file binary yes
control control
bit address bit
BTD Bit Distribute source immediate, integer no
source bit immediate, (0 - 15) integer
destination integer
destination bit immediate (0 - 15)
length immediate (1 - 16)
1785-6.1 November 1998

Require
Transition
BTR1 Block Transfer Read rack 00-277 octal yes
group 0-7
module 0-1
control block block, integer
data file integer
length 0, 1-64
continuous YES, NO
1
BTW Block Transfer Write rack 00-277 octal yes
group 0-7
module 0-1
control block block, integer
data file integer
length 0, 1-64
continuous YES, NO
CIO ControlNet I/O Transfer control block ControlNet transfer (1 - 64) yes
CIR Custom Input Routine program file number immediate (2 - 999) for all N/A
processors
input parameter list immediate, integer, float

(for use with CAR
applications only) return parameter list integer, float
CLR Clear destination integer, float no
CMP Compare expression, relative expression using values or no

expression, expression addresses with evaluators (for
a list, see chapter 3 in
this manual)
EXE mnemonic EXE

(end of expression)
only for ASCII import
COP File Copy source array no
destination array

1 In non-continuous mode, BTR and BTW ladder functions requires a false-to-true transition to execute. In continuous mode, once the rung goes
true, BTR and BTW functions continue to execute regardless of rung condition. See page 15-8 for more information.
1785-6.1 November 1998

Require
Transition
COR Custom Output Routine program file number immediate (2 - 999) for all no
processors

(for use with CAR
applications only) return parameter list integer, float
COS * Cosine source immediate, float (in radians) no
CPT Compute math expression expression using values or no

immediate integer float
addresses with evaluators
(for a list, see chapter 4 in
this manual)
EXE mnemonic EXE

only for ASCII import
relative expression addresses with evaluators (for

a list, see chapter 4 in
this manual)
CTD Count Down counter counter yes
PRE –32,768 - +32,767
ACC –32,768 - +32,767
CTU Count Up counter counter yes
PRE –32,768 - +32,767
ACC –32,768 - +32.767 yes
DDT Diagnostic Detect source array binary yes
reference array binary
result array integer
compare control control
position 0 - 15999
result control control
length 1 - 1000
position 0 - 999
DEG * Degree (convert radians source immediate, float (in radians) no

to degrees)
destination immediate, float (in degrees)
1785-6.1 November 1998

Require
Transition
DFA Diagnostic Fault Annunciator control file integer
number of I/O immediate (8, 16, 32)
program file number immediate (3-999)
DIV Divide source A immediate, integer, float no
DTR Data Transitional source immediate, integer no
mask immediate, integer
reference integer
EOC end of SFC compression only for ASCII N/A

(see SOC) import/export
EOR end of rung only for ASCII N/A

import/export
EOT end of transition none no
ESE end SFC selection branch only for ASCII N/A

(see SEL) import/export
EQU Equal source A immediate, integer, float no
EOP end of SFC program only for ASCII N/A

import/export
ERI error on an input instruction only in ASCII N/A

export files
ERO error on an output instruction only in ASCII N/A

export files
ESI end SFC simultaneous branch only for ASCII N/A

(see SIM) import/export
FAL File Arithmetic/Logical control control yes
length 1 - 1000
position 0 - 999
mode (INC, 1-1000, ALL)
math expression indexed math instruction
1785-6.1 November 1998

Require
Transition
FBC File Bit Compare source array binary yes
reference array binary
result array integer
compare control control
position 0 - 15999
result control control
length 1 - 1000
position 0 - 999
FFL FIFO Load source operand immediate, indexed, integer yes
FIFO array indexed, integer
FIFO control control
length 1 - 1000
position 0 - 999
FFU FIFO Unload FIFO array indexed, integer yes
destination indexed, integer
FIFO control control
length 1 - 1000
position 0 - 999
FLL Fill File source operand immediate, integer, float no
destination array array no
FOR For Loop LBL number integer no
index integer
initial value immediate, integer
terminal value immediate, integer
step size immediate, integer
FRD From BCD source immediate, integer no
destination integer
1785-6.1 November 1998

Require
Transition
FSC File Search and Compare control control yes
length 1 - 1000
position 0 - 999
mode immediate, integer (0, INC,

1-1000, ALL)
math expression indexed math instruction
GEQ Greater Than or Equal To source A immediate, integer, float no
GRT Greater Than source A immediate, integer, float no
IDI Immediate Data Input data file offset immediate (0-999), integer yes
length immediate (1-64), integer
destination integer
IDO Immediate Data Output data file offset immediate (0-999), integer yes
length immediate (1-64), integer
source integer
IIN Immediate Input I (input) word immediate, integer no

PLC-5/10, 11, 12 15, 20, 25,
30: 000-077
PLC-5/40, 40L: 000-157
PLC-5/60, 60L, 80, :000-237
IOT Immediate Output O (output) word immediate, integer no

PLC-5/10, 11, 12, 15, 20, 25,
30: 000-077
PLC-5/40, 40L: 000-157
PLC-5/60, 60L, 80: 000-237
JMP Jump label number immediate no

Classic PLC-5 processors:
0-31
Enhanced PLC-5 processors:
0-255
JSR Jump to Subroutine ladder program immediate (2 - 999) no

number
return parameter list integer float no
LAB SFC label (import/export only) file number immediate N/A

0-31
0-255
1785-6.1 November 1998

Require
Transition
LBL LBL (ladder program label) label number immediate no

0-31
0-255
LEQ Less Than or Equal To source A immediate, integer, float no
LES Less Than source A immediate, integer, float no
LFL * LIFO Load source operand immediate, indexed, integer yes
LIFO array indexed, integer
LIFO control control
length 1 - 1000
position 0 - 999
LFU * LIFO Unload LIFO array indexed, integer yes
LIFO control control
length 1 - 1000
position 0 - 999
LIM Limit low limit immediate, integer, float no
test immediate, integer, float
high limit immediate, integer, float
LN * Natural Log source immediate, integer, float no
destination float
LOG * Log to the Base 10 source immediate, integer, float no
destination float no
MCR Master Control Relay no
MEQ Mask Compare Equal To source operand immediate, integer no
source mask immediate, integer
compare operand immediate, integer
MOV Move source immediate, integer, float no
MSG Message control block message, integer yes
1785-6.1 November 1998

Require
Transition
MUL Multiply source A immediate, integer, float no
MVM Masked Move source operand immediate, integer no
source mask immediate, Hex integer
destination integer
NEG Negate source immediate, integer, float no
NEQ Not Equal To source A immediate, integer, float no
NOT Logical NOT source immediate, integer no
destination integer
NSE SFC next selection branch only for ASCII N/A

import/export
NSI SFC next simultaneous branch only for ASCII N/A

import/export
NXT Next (FOR Loop) for label number immediate no

0-31
0-255
OR Logical OR source A immediate, bits integer yes
source B immediate, bits integer
destination integer
OSF * One Shot Falling storage bit bit yes; requires a

true-to-false
output bit immediate (0 - 15) transition to
execute
output word integer
ONS One Shot source bit bit yes
OSR * One Shot Rising storage bit bit yes
output bit immediate (0 - 15)
output word integer
OTE Output Energize destination bit bit no
OTL Output Latch destination bit bit no
OTU Output Unlatch destination bit bit no
1785-6.1 November 1998

Require
Transition
PID PID control block PD no
control block integer yes
pv value integer
tieback value immediate, integer
cv value integer
RAD * Radian (convert degrees source immediate, float (in degrees) no

to radians)
REF SFC reference (see LAB) label number immediate (0 - 255) N/A
(ASCII import/export only)
RES Timer/Counter Reset timer, counter, control no
RET Return return parameter list immediate, integer, float no
RTO2 Retentive Timer On timer timer yes
time base immediate (0.01, 1.0)
PRE 0 - 32767
ACC 0 - 32767
SBR Subroutine input parameter list integer, float no
SDS Smart Directed Sequencer control file integer no
number of I/O immediate (8, 16, 32)
program file number immediate (3-999)
SDZ start of delete zone, only in ASCII N/A

unassembled edits export files
SEL SFC selection branch only for ASCII N/A

import/export
SFR* SFC reset SFC file number immediate (1 - 999) no
restart at step immediate, integer
SIM SFC simultaneous branch only for ASCII import N/A

2
This instruction requires periodic scans to be updated. See page 2-13 in this manual or your Structured Text User Manual for more information.
1785-6.1 November 1998

Require
Transition
SIN * Sine source immediate, float (in radians) no
SIZ start of insert zone, only in ASCII N/A

unassembled edits export files
SOC start of compression only for ASCII N/A

import/export
SOP SFC start of program only for ASCII N/A

import/export
SOR start of rung only for ASCII N/A

import/export
SQI Sequencer Input file integer, indexed no
mask immediate, Hex indexed,

integer
source immediate, indexed, integer
control control
length 1 - 1000
position 0 - 999
SQL Sequencer Load file integer, indexed yes
source immediate, indexed, integer
control control
length 1 - 1000
position 0 - 999
SQO Sequencer Output file integer, indexed yes
destination mask immediate, indexed, integer
control control
length 1 - 1000
position 0 - 999
SQR Square Root source immediate, integer, float no
SRT * Sort sort file integer, float yes
file control control
length 1 - 1000
position 0 - 999
1785-6.1 November 1998

Require
Transition
SRZ start of replace zone, only in ASCII export N/A

unassembled edits files
STP SFC step (Classic file number 2 - 999 N/A

PLC-5 Processors)
STP * SFC step step timer file number 2 - 9999 N/A

(Enhanced PLC-5 Processors)
(ASCII import/export only) time base immediate (0.01, 1.0)
qualifier N, S, R, L, D, P1, P0, SL,

SD, DS
action number immediate

(from ACT)
timer file number timer
STD * Standard Deviation standard deviation file integer, float yes
file control control
length 1 - 1000
position 0 - 999
SUB Subtract source A immediate, integer, float no
TAN * Tangent source immediate, float (in radians) no
TID * Token ID token ID number immediate N/A

(ASCII import/export only) (must be unique per
SFC file)
TND Temporary End no
TOD To BCD source immediate, integer no
destination integer
1785-6.1 November 1998

Require
Transition
TOF 2 Timer Off Delay timer timer yes: requires

true-to-false
transition to
execute
TOF 2 Timer Off Delay time base immediate (0.01, 1.0) yes: requires
true-to-false
PRE 0 - 32767 transition to
execute
ACC 0 - 32767
TON 3 Timer On Delay timer timer yes
PRE 0 - 32767
ACC 0 - 32767
TRC SFC transition file number 2 - 999 for all processors N/A
UID * User Interrupt Disable no
UIE * User Interrupt Enable no
XIC Examine On source bit bit no
XIO Examine Off source bit bit no
XOR Exclusive Or source A immediate, bits integer no
source B immediate, bits integer
destination integer
XPY * X to the Power of Y source A immediate, integer no
source B immediate, integer
destination integer
2
This instruction requires periodic scans to be updated. See page 2-9 in this manual or page 2-10 in the Structured Text User Manual for more
information.
3
This instruction requires periodic scans to be updated. See page 1-14 in this manual or your Structured Text User Manual for more information.
1785-6.1 November 1998

1RWHV
1785-6.1 November 1998

Index
A ASCII
ABL instruction 17-4 ABL 17-4
ACB 17-5
ACB instruction 17-5
ACI 17-6
ACI instruction 17-6 ACN 17-7
ACN instruction 17-7 AEX 17-7
ACS instruction 4-11 AHL 17-8
AIC 17-9
ADD instruction 4-12
ARD 17-10
Addition instruction ARL 17-12
ADD 4-12 ASC 17-14
AEX instruction 17-7 ASR 17-15
AFI instruction 13-13 AWA 17-15
AWT 17-17
AHL instruction 17-8
ASCII instructions, strings 17-3
AIC instruction 17-9
ASCII Integer to String instruction 17-9
Always False instruction 13-13
ASCII Read Characters instruction 17-10
AND instruction 5-2
ASCII Read Line instruction 17-12
AND Operation instruction
AND 5-2 ASCII Set Handshake Lines instruction 17-8
Arc Cosine instruction ASCII String Compare instruction 17-15
ACS 4-11 ASCII String Concatenate instruction 17-7
Arc Sine instruction ASCII String Extract instruction 17-7
ASN 4-13 ASCII String Search instruction 17-14
Arc Tangent instruction ASCII String to Integer instruction 17-6
ATN 4-14
ASCII Write Append instruction 17-15
ARD instruction 17-10
ASCII Write instruction 17-17
ARL instruction 17-12
ASN instruction 4-13
ASC instruction 17-14
ASR instruction 17-15
ATN instruction 4-14
1785-6.1 November 1998

I–2 Index
Attention B
32- to 16-bit conversion 4-10 Bit Distribute instruction
AVE indexed address 4-16 BTD 7-2
change index value 13-6
Bit Shift Left (BSL) instruction 11-2
control structure addressing 10-4
DTR online programming 10-8 Bit Shift Right (BSR) instruction 11-2
entering input addresses 1-6 block transfer
entering output addresses 1-7 BTR instruction 15-3
FAL indexed address 9-2 BTW instruction 15-3
FOR and NXT with output branches 13-5 direct communication mode 15-2
FOR and NXT within branches 13-5 I/O scan mode 15-1
indexed addressing 8-2 instructions 15-1
jumped timers and counters 13-4 programming examples 15-15
MCR zones timing 15-13, 15-14
overlapping or nesting 13-2 Block Transfer Read instruction
timers and counters 13-2 BTR 15-3
modify status bits of BTR/BTW 15-6
Block Transfer Write instruction
MSG
BTW 15-3
status bits .ST and .EW 15-24
online programming with ONS 13-14 Break (BRK) instruction 13-5
pairing stack instructions 11-6 BRK instruction 13-5
PID BSL instruction 11-2
change engineering unit max 14-22
BSR instruction 11-2
change engineering unit min 14-22
change inputs or units 14-19 BTD instruction 7-2
changing scaling 14-6 BTR instruction 15-3
resume last state 14-10 BTW instruction 15-3
setting temperature limits 14-28
update time 14-21
placement of critical counters 2-15, 2-17 C
resetting TON and TOF 2-8, 2-20 CAR utility 18-1
SRT indexed address 4-27 CIO instruction 15-22
status of BTR/BTW bits 15-7 monitoring 15-24
STD indexed address 4-30 status bits 15-24
use of control address 12-3 using 15-23
using control addresses 8-2 Classic PLC5 processors 1
using control addresses for instructions 11-2
Clear instruction
AVE instruction 4-15 CLR 4-17
Average File instruction CLR instruction 4-17
AVE 4-15
CMP
AWA instruction 17-15 instruction 3-2
AWT instruction 17-17
1785-6.1 November 1998

Index I–3
compare control file

EQU 3-5 example 8-2
expression 3-2 ControlNet I/O transfer
GEQ 3-5, 3-6 instruction 15-22
instructions 3-2
ControlNet PLC5 processors 1
length of expressions 3-3
LEQ 3-6 convergent
LES 3-7 scan time B-14
NEQ 3-10 conversion
compute BCD 6-2
ACS 4-11 FRD 6-2
ADD 4-12 Convert from BCD instruction
ASN 4-13 FRD 6-2
ATN 4-14 Convert to BCD instruction
AVE 4-15 TOD 6-2
CLR 4-17
COP instruction 9-19
COS 4-18
CPT 4-5 COS instruction 4-18
DEG 6-3 Cosine instruction
DIV 4-19 COS 4-18
EOT 13-18 Count Down instruction 2-17
expression 4-5
Count Up instruction 2-15
FSC 9-14
functions 4-9 counter
IOT 1-7 CTD 2-17
length of expressions 4-7 CTU 2-15
LN 4-20 RES 2-20
LOG 4-21 counters
MUL 4-22 instructions 2-13
NEG 4-23 CPT instruction 4-5
ONS 13-14
CTD instruction 2-17
order of operation 4-8
RAD 6-4 CTU instruction 2-15
SIN 4-24 custom application routine 18-1
SQR 4-25
SRT 4-26 D
STD 4-28
data files
SUB 4-31
manipulating 8-3
TAN 4-32
range of values C-1
XPY 4-33
data storage
Compute instruction
I/O image files 1-2
CPT 4-5
Data Transitional instruction
connecting to Ethernet PLC5 processors using
hostnames 16-6 DTR 10-8
1785-6.1 November 1998

I–4 Index
DDT instruction 10-2 Equal To instruction 3-5

DEG instruction 6-3 Ethernet PLC5 processors 1
Degree instruction Examine Off instruction 1-3
DEG 6-3 Examine On instruction 1-3
derivative smoothing 14-4 expression
DFA instruction 18-1 determining the length of 3-3, 4-7
diagnostic
DDT 10-2 F
DTR 10-8
FAL logical instruction 9-12
FBC 10-2
parameters 10-4, 10-8 FBC instruction 10-2
search mode 10-2 FFL instruction 11-5
status 10-5 FFU instruction 11-5
Diagnostic Detect instruction FIFO Load (FFL) instruction 11-5
DDT 10-2 FIFO Unload (FFU) instruction 11-5
Diagnostic Fault Annunciator Instruction 18-1 file
diagnostic instructions 10-1 search and compare operations 9-17
direct communication File Arithmetic and Logic instruction
block transfer 15-2 FAL 9-2
DIV instruction 4-19 File Bit Comparison instruction
divergent FBC 10-2
scan time B-14 file concepts
Divide instruction control structure 8-2
DIV 4-19 manipulating data 8-3
DTR instruction 10-8 modes of operation 8-5
File Copy instruction
COP 9-19
E
File Fill instruction
element manipulation
FLL 9-20
LIM 3-7
MEQ 3-9 file instructions
MOV 7-3 logical 9-12
MVM 7-4 File Search and Compare instruction
End of Transmission instruction FSC 9-14
EOT 13-18
engineering units
scaling 14-5
Enhanced PLC5 processors 1
EOT instruction 13-18
EQU instruction 3-5
1785-6.1 November 1998

Index I–5
files instruction
arithmetic operations 9-7 ControlNet I/O transfer 15-22
copy operations 9-5 immediate data input 1-8
functions 9-14 immediate data output 1-8
instruction instructions
COP 9-19 ASCII 17-1
FLL 9-20 block transfer 15-1
logical operations 9-12 CIO
operation modes 8-5 monitoring 15-24
FLL instruction 9-20 compare 3-2
floating point diagnostic 10-1
valid value range C-1 memory requirements A-1
message 16-1
For (FOR) instruction 13-5
operands C-1
FOR instruction 13-5 program flow 13-1
FRD instruction 6-2 relay-type 1-1, 2-1
FSC instruction 9-14 sequencer 12-1
shift register 11-1
timer 2-1
G timing A-1
gain constants 14-3 INVALID OPERAND
GEQ instruction 3-5, 3-6 error message 4-4
Greater Than or Equal To instruction 3-5, 3-6 IOT instruction 1-7
I J
I/O image files 1-2 JMP instruction 13-3
I/O scan mode JSR instruction 13-8
block transfer 15-1 Jump instruction 13-3
IDI instruction 1-8 Jump to Subroutine instruction 13-8
using 1-9
IDO instruction 1-8
L
using 1-9
Label (LBL) instruction 13-5
IIN instruction 1-6
Label instruction 13-3
Immediate Data Input
instruction 1-8 LBL instruction 13-3, 13-5
Immediate Data Output LEQ instruction 3-6
instruction 1-8 LES instruction 3-7
Immediate Input instruction 1-6 Less Than instruction 3-7
Immediate Output instruction Less Than or Equal To instruction 3-6
IOT 1-7 LFL instruction 11-5
incremental mode 8-7 LFU instruction 11-5
1785-6.1 November 1998

I–6 Index
LIFO Load (LFL) instruction 11-5 MUL instruction 4-22

LIFO Unload (LFU) instruction 11-5 Multiply instruction
LIM instruction 3-7 MUL 4-22
Limit Test instruction 3-7 MVM instruction 7-4
LN instruction 4-20
LOG N
instruction 4-21 Natural Log instruction
Log to the base 10 instruction LN 4-20
LOG 4-21 NEG instruction 4-23
logical Negate instruction
AND 5-2 NEG 4-23
NOT 5-3 NEQ instruction 3-10
OR 5-4
Next (NXT) instruction 13-5
XOR 5-5
Not Equal To instruction 3-10
NOT instruction 5-3
M
NOT Operation instruction
manipulating
NOT 5-3
file data 8-3
Number of Char in Buffer instruction 17-5
Masked Comparison for Equal instruction 3-9
NXT instruction 13-5
Masked Move instruction 7-4
Master Control Reset instruction 13-2
O
MCR instruction 13-2
One Shot Falling (OSF) instruction 13-16
memory
instruction requirements A-1 One Shot instruction
SFC requirements B-3 ONS 13-14
MEQ instruction 3-9 One Shot Rising (OSR) instruction 13-15
message ONS instruction 13-14
instruction 16-1 operands
modes instructions C-1
file operation 8-5 OR instruction 5-4
monitoring OR Operation instruction
CIO instructions 15-24 OR 5-4
MOV instruction 7-3 order of operation 4-8
Move instruction OSF instruction 13-16
MOV 7-3 OSR instruction 13-15
MSG OTE instruction 1-4
instruction entry 16-10 OTL instruction 1-4
MSG instruction 16-1 OTU instruction 1-5
using 16-10
1785-6.1 November 1998

Index I–7
Output Energize instruction 1-4 program flow instruction

Output Latch instruction 1-4 FOR, BRK, LBL, and RET 13-5
OSF 13-16
Output Unlatch instruction 1-5
OSR 13-15
SFR 13-17
P program flow instructions 13-1
PID Programming
biasing 14-9 SDS instruction 18-2
equations 14-2
programming
examples 14-29
instructions
instruction 14-10
operands C-1
integer examples 14-29
PD examples 14-33 Proportional, Integral, and Derivative instruction
selecting derivative term 14-7 14-10
setting output alarms 14-7
using manual mode 14-8 R
using output limiting 14-7
RAD instruction 6-4
PID instruction 14-1
Radian instruction
PLC2 compatibility file 16-15 RAD 6-4
process control relay-type
biasing 14-9 IIN 1-6
derivative smoothing 14-4 OTE 1-4
equations 14-2 OTL 1-4
gain constants 14-3 OTU 1-5
integer PID examples 14-29 XIC 1-3
PD PID examples 14-33 XIO 1-3
PID 14-10
RES instruction 2-20
PID examples 14-29
PID instruction 14-1 Reset instruction 2-20
selecting derivative term 14-7 RET instruction 13-8
setting output alarms 14-7 Retentive Timer On instruction 2-10
using manual mode 14-8
Return instruction 13-8
using output limiting 14-7
RTO instruction 2-10
program constant
valid value range C-1 run times
determining B-12
program constants 3-2, 4-5
program flow
AFI 13-13
JMP and LBL 13-3
JSR, SBR, and RET 13-8
MCR 13-2
UID 13-19
UIE 13-20
1785-6.1 November 1998

I–8 Index
S shift register instruction

SBR instruction 13-8 applying 11-1
BSL and BSR 11-2
scaling
FFL and FFU 11-5
to engineering units 14-5
LFL and LFU 11-5
scan sequence
simultaneous branch
SFC B-7
scanning sequence B-9
scan time
SIN instruction 4-24
convergent B-14
divergent B-14 Sine instruction
steady–state B-14 SIN 4-24
scanner mode Smart Directed Sequencer (SDS) Instruction
configuring 15-13, 15-14 overview 18-2
programming 18-2
SDS instruction 18-1
Smart Directed Sequencer Instruction 18-1
selection branch
scanning sequence B-8 Sort File instruction
SRT 4-26
sequencer
applying 12-1 SQI instruction 12-2
instructions 12-1 SQL instruction 12-2
SQI 12-2 SQO instruction 12-2
SQL 12-2
SQR instruction 4-25
SQO 12-2
Square Root instruction
Sequencer Input instruction 12-2
SQR 4-25
Sequencer Load instruction 12-2
SRT instruction 4-26
Sequencer Output instruction 12-2
Standard Deviation instruction
Sequential Function Chart Reset STD 4-28
instruction 13-17
status bits
SFC CIO instruction 15-24
constraints B-5
status information
example
SFC B-1
memory requirements B-3 STD instruction 4-28
scanning sequence steady-state
example B-11 scan time B-14
selection branch B-8 step
simultaneous branch B-9 scanning sequence B-7
scanning sequences
SUB instruction 4-31
step/transition B-7
status information B-1 Subroutine Header instruction 13-8
SFR instruction 13-17 Subtract instruction
SUB 4-31
1785-6.1 November 1998

Index I–9
T U
TAN instruction 4-32 units, engineering
Tangent instruction scaling 14-5
TAN 4-32 User Interrupt Disable
Temporary End UID 13-19
instruction 13-13 User Interrupt Enable
Temporary End instruction 13-20 UIE 13-20
Test Buffer For Line instruction 17-4 using
CIO instruction 15-23
timer
IDI instruction 1-9
accuracy 2-3
IDO instruction 1-9
instruction parameters 2-2, 2-13
MSG instruction 16-10
RES 2-20
RTO 2-10
TOF 2-7 X
TON instruction 2-4 X to the Power of Y instruction
Timer Off Delay instruction 2-7 XPY 4-33
Timer On Delay instruction 2-4 XIC instruction 1-3
timers 2-1 XIO instruction 1-3
timing XOR instruction 5-5
block transfer 15-13, 15-14 XOR Operation instruction
instructions A-1 XOR 5-5
tip XPY instruction 4-33
connecting to Ethernet PLC5 processors
using hostnames 16-6
TND
instruction 13-13
TND instruction 13-19, 13-20
TOD instruction 6-2
TOF instruction 2-7
TON instruction 2-4
transition
1785-6.1 November 1998

I–10 Index
1RWHV
1785-6.1 November 1998

Allen-Bradley
Publication Problem Report
If you find a problem with our documentation, please complete and return this form
Pub. Name PLC-5 Programmable Controllers Instruction Set Reference
Cat. No. 1785 series Pub. No. 1785-6.1 Pub. Date November 1998 Part No. 955133-83
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Technical Accuracy text illustration
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1785-6.1 November 1998

1785-6.1 November 1998 PN 955133-83
Supersedes 1785-6.1 Feburary 1996 © 1998 Rockwell International Corporation. Printed in USA

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PLC-5 Instruction Set Alphabetical Listing

ABL 17-51 CMP 3-3 JSR 13-12 RES 2-25

ACB 17-71 COP 9-20 LBL 13-5 RET 13-12

ACI 17-91 COS 4-211 LEQ 3-9 RTO 2-13

ACN 17-101 CPT 4-5 LES 3-10 SBR 13-12

ACS 4-131 CTD 2-20 LFL 11-51 SDS 18-2

ADD 4-14 CTU 2-18 LFU 11-51 SFR 13-231

AEX 17-111 DDT 10-2 LIM 3-11 SIN 4-271

AFI 13-19 DEG 6-51 LN 4-231 SQI 12-2

AIC 17-141 DIV 4-22 MCR 13-3 SQO 12-2

AND 5-2 DTR 10-8 MEQ 3-13 SQR 4-28

ARD 17-151 EOT 13-24 MOV 7-4 SRT 4-291

ARL 17-181 EQU 3-6 MSG 16-2 STD 4-311

ASC 17-211 FAL 9-2 MUL 4-25 SUB 4-34

ASN 4-151 FBC 10-2 MVM 7-5 TAN 4-351

ASR 17-221 FFL 11-5 NEG 4-26 TND 13-19

ATN 4-161 FFU 11-5 NEQ 3-15 TOD 6-3

AVE 4-171 FLL 9-21 NOT 5-4 TOF 2-9

AWA 17-231 FOR 13-8 NXT 13-8 TON 2-5

AWT 17-261 FRD 6-4 ONS 13-20 UID 13-251

BRK 13-8 FSC 9-15 OR 5-6 UIE 13-261

BSL 11-2 GEQ 3-7 OSF 13-221 XIC 1-3

BSR 11-2 GRT 3-8 OSR 13-211 XIO 1-4

BTD 7-2 IDI 1-102 OTE 1-5 XOR 5-8

1785-6.1 November 1998

If You Want to Perform Use this Instruction Category:

examine, check or control 2-state device or condition bit level

move, copy, change, analog values, codes element level

convert conversion instructions

time or delay timer

shift or track bit shift

message sending/receiving message

transfer data to/from modules block transfer or ControlNet transfer

diagnostics, fault handling diagnostics

control the flow of your program program control

If Your Application Calls for Operations such as: Use:

detecting when a limit switch closes bit level

changing the temperature preset element level

transfer analog data block transfer

turn on a motor 10 seconds after a pump is activated timing

move 1 of 3 recipes into a work area multi-element

keep track of parts as they move from station to station shifting

keep track of total parts in a bin counting

1785-6.1 November 1998

For this Update Information: See Chapter:

Converting non-decimal numbers with the FRD instruction 6

How non-existing, indirect addresses affect the COP and 9

How the .POS value operates in sequencer instructions 12

Using a RET instruction 13

Using the PID bias term 14

Using the no zero crossing (.NOZC) and no back calculation 14

Clarification to error code 89 for MSG instruction 16

Ethernet PLC-5 processors now support SLC Typed Read and 16

Configuring a multihop MSG instruction over Ethernet or 16

Monitoring the status of the .EN bit in a continuous 16

1785-6.1 November 1998

1785-6.1 November 1998

References to: Include these Allen-Bradley Processors:

Enhanced PLC-5 processors PLC-5/11™, -5/20™, -5/30™, -5/40™, -5/40L™, -5/60™,

Ethernet PLC-5 processors PLC-5/20E™, -5/40E™, and -5/80E™ processors.

ControlNet PLC-5 processors PLC-5/20C™, -5/40C™, -5/46C™, and -5/80C™ processors.

Protected PLC-5 processors 1 PLC-5/26™, -5/46™, and -5/86™ processors.

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