You are on page 1of 4

The Performance Degradation of Folded-Cascode CMOS Op-Amp

due to Hot-Carrier Effects

Chong-Gun Yu, Hyun-Joong Kim, Woon-Dal Jeong and Jong-Tae Park
Department of Electronics Engineering
University of Inchon
177, Tohwa-dong, Namgu, Inchon, Korea

Abstract - This study presents the first 11. DESIGN AND J~~EASUREMENT
experimental data for the impact of CMOS hot-
carrier degradation on the performance of folded- Two types of folded-cascode op-amps have been
cascode op-amps. Two types of folded-cascode designed and fabricated using a 0.8pm LOCOS
op-amps have been designed and fabricated using a -isolated, double-metal CMOS process with LDD
0.8pm double-metal CMOS process. After high
voltage stress, the degradation of performance stsuctures. As shown in Fig.1, the first type has an
parameters such as open-loop voltage gain, offset NMOS input stage which will be denoted as an
voltage, unity-gain frequency and phase margin has N-type op-amp, and the second type has a PMOS
been analyzed and physically explained in terms of input stage which will be denoted as a P-type
hot-carrier degradation. op-amp. To reduce the systematic offset, the
device sizes of output transistors were appropriately
adjusted at the simulation stage, and the common
I. INTRODUCTION centroid technique was used in doing layout of the
input transistors to reduce the random offset. The
Recently, the use of the submicrometer-level device size of input transistors M1 and M2 is
CMOS transistors for analog circuits requires the (W/L)i,2=226.4/0.8, and the sizes of output
intensive study on the hot-carrier induced circuit transistors M7 and M9 are (W/L)7=84/1.6 and
performance degradation. It is known that the (W/L)g=177.5/1.6 for the N-type op-amp, and
hot-carrier induced device degradation impacts on (W/L)7=80/1.6 and (W/L)s=193/1.6 for the P-type
the performance of digital circuits and memory op-amp.
circuits such as CMOS logic circuits [ll, DRAM Performance parameters such as open-loop
[21 and SRAM circuits [31. However, there have voltage gain, offset voltage, unity-gain frequency
been a few efforts to study how much hot-carrier and phase margin were measured before and after
induced damage affects on analog circuit stress. The open-loop voltage gain (Av) was
performance [41,[51. They have studied the measured using the configuration shown in Fig2
performance degradation of CMOS subcircuits such and calculated using the following equation.
as differential input stages [61 and current mirrors
[71, and the drain output conductance degradation R1+R
for analog circuit applications [SI. It has also been
recognized that the performance degradation of
analog circuits due to hot-carrier effects is
R1 z ) [ ( l + $ ) vout
~ - ~ Ro 1'

sensitive to the circuit topology and operating where FL is the open-loop output resistance. The
conditions [61. Thus, the criteria for hot-carrier output resistance Ro is about 3.R\/IS for P-type
reliability should base on circuit and system op-amp and 2OMQ for the N-type op-amp before
performance requirements. stress.
This study presents the first experimental data The input offset voltage (Voff) was measured
for the impact of hot-carrier induced device using a resistor divider in the negative feedback
degradation on the performance of folded-cascode path. The unity-gain frequency (UGF) was
CMOS operational amplifiers. The hot-carrier determined as a frequency at which the input
degradation of the op-amp performance parameters voltage swing equals to the output voltage swing.
such as open-loop voltage gain, offset voltage, Finally, the phase margin (PM) was determined by
unity-gain frequency and phase margin was subtracting the phase difference between the input
measured and analyzed. signal and the output signal from 180" at the
unity-gain frequency. The measurement results for
This work has been supported in part by Electronics and two types of folded-cascode op-amps before stress
Telecommunications Research Institute. are shown in Table 1.

0-7803-3694-1/97/$10.00 @ 1997 IEEE 164


To easily evaluate the impact of the hot carrier decreases, and thus, the open-loop gain decreases.
degradation on the circuit performance, high supply There is a power law relation between the
voltages were applied. Stress voltages for VDDand open-loop voltage gain variation and the stress
Vss were in the range of 5.6V-6.6V and -5.6V- time as shown in Fig.4. It can also be found that
-6.6V, respectively. The stress time was up to 210 the voltage gain variation increases with stress
minutes. For an open-loop stress condition, the voltage.
positive input terminal was grounded, and a The hot-carrier induced offset voltage variation
sinusoidal signal (f =lkHz, Vp-p=2V)was applied at which is caused primarily by the degradation of the
the negative input terminal. input transistor M1 is shown in Fig.5. It has been
observed that the offset voltage of the P-type
op-amp shifts in the positive direction with stress
DEGRADATION time while the offset voltage of the N-type op-amp
shifts in the negative direction with stress time.
For the open-loop stress condition, input Therefore, the magnitude of the offset voltages for
transistor M1 and output transistors M7 and M9 both cases increases after all regardless of the
for both cases are degraded more significantly polarity of the initial offset voltage. The significant
compared to other transistors. Due to large voltage degradation of the offset voltages could become the
stress received by M7 of Fig.l(a) (M9 of Fig.l(b)) criteria for the determination of the circuit lifetime.
during the positive input swing and by M9 of From Fig.5, it is also found that the offset voltage
Fig.l(a) (M7 of Fig.l(b)) during the negative input variation increases with stress voltage.
swing, the circuit performance will be degraded. The unity-gain frequency variation is shown Fig.6.
During the negative input swing, M9 of Fig.l(a) In case of the N-type op-amp, the unity-gain
(M7 of F@.l(b)) is in the saturation region with frequency increases at the early sQge of stress but
low gate to source voltages, and M7 of Fig.l(a) becomes almost saturated as the stress time is
(M9 of Fig.l(b)) is also in the saturation region increased further. In case of the P-type op-amp,
during the positive input swing. When an NMOS is the unity-gain frequency decreases at the early
biased in the saturation region, as for most analog stage of stress such that its variation increases as
circuit purpose, acceptor-type interface states are shown in Fig.6(b) but also becomes saturated as
mostly unoccupied because of the lowered electron the stress time increases.
quasi-fermi level near the drain [91. As a result, It has also been observed that the phase margin
trapped hole charges lead to the increase of the of the N-type op-amp decreases, but the phase
transconductance ( g m ) and the drain output margin of the P-type op-amp increases with stress
conductance ( g d ) [41. When a PMOS is biased in time. Their variations versus stress time are shown
the saturation region, trapped electron charges lead in Fig.7. In case of the N-type op-amp, the
to the increase of the transconductance and the open-loop voltage gain increases, while the
decrease of drain output conductance 141. dominant pole (-l/R,tCd decreases. However, the
Fig.3 shows the measured frequency responses of increase rate of Av IS greater than the decrease
the open-loop voltage gain versus stress time. The rate of R,t by the factor of g,,-,i. Therefore, the
gain of the N-type op-amp increases after stress, unity-gain frequency, which is approximately same
but the gain of the P-type op-amp decreases. The as the product of the open-loop gain and the
open-loop voltage gain of a single-stage folded- dominant pole, increases and thus, the phase
cascode op-amp is defined as the product of the margin decreases. In case of the P-type op-amp,
transconductance o€ input transistors ( g d and the the same comment as above can be made to
resistance at the output node ( R d . explain the variation of the performance parameters.
&=gfmi Rout

In casc of the IY-type op-amp, the voltage gain In this paper the performance variation of two
shift is dominated by the degradation of the output types of CMOS folded-cascode op-amps due to
PMOS transistor ld7. The hot-carrier variation of hot-carrier effects has been measured and analyzed.
g d is usually much significant than that of gm. It can be concluded from the reliability point of
Since g d 7 decreases dominantly after stress, the view that the degradation of the open-loop voltage
output resistance %,t and thus, the voltage gain gain and offset voltage determines the circuit
Av increases as the stress time increases. The lifetime in case of the folded-cascode op-amp with
decrease of the voltage gain of the P-type op-amp a PMOS input stage, and the offset voltage and
can be explained by the dominant degradation of phase margin can be the major factors determining
the output NMOS transistor M7. Because of the the lifetime in case of the folded-cascode op-amp
dominant increase of $37, the output resistance &t, with an NMOS input stage.

111 W. Weber, L. Risch, W. Krautschneider, and Q. Wang, "Hot
carrier degradation of CMOS inverters," IEDM Tech Dig.,
pp. 208-211, 1988.
[21 Y . Huh, H. Lee, J. Ahn, D. Yang, and Y. Song, "Hot carrier
induced gate capacitance variation and its impact on DRAN
circuit functionality," IEDM Tech Dig., pp. 33-37, 1995.
[31 J. van der pol, and J. Koomen, "Relation between the hot
carrier lifetime of transistors and CMOS SRAM products,"
in Proc Ink Reliability Physics Symp., pp. 178-185, 1990.
[41 J. Chung, K. Quadex, C. Sodini, P. KO, and C. Hu, "The
effects of hot electron degradation on analog MOSFET
performance," IEDM Tech Dig., pp. 553-556,1990.
[51 S. Mohamedi, V. H. Chan, J. Park, F. Nouri, B. Schart, and
J. Chung, "Hot electron induced input offset voltage
degradation in CMOS differential amplifiers," in Proc Int.
Reliability Physics Symp., pp. 76-80, 1992. (b)
[6] V. Chan, J. E. Chung, "The impact of NMOSFET hot carrier Fig. 1. Circuit schematic of folded-cascode op-amps with (a) an
degradation on CMOS analog subcircuit perfomance," IEEE NMOS input stage (b) a PMOS input stage
J. of Solid State Circuits, vol. 30, no. 6, pp. 644-649, 1995.
[7l R. Thewes, K. F. Goser, and W. Weber, "Hot carrier induced R 3 (520k) V, R, (520k)
degradation of CMOS current mirrors and current sources,"
IEDM Tech Dig., pp. 885-888, 19%.
[SI R. Thewes, M. Brox, G. Tempel, and W. Weber, "Hot carrier
degradation of PMOSFET's in analog operation," IEDM
Tech Dig., pp. 531-533, 1992.
[91 B. Doyle, et. al., "The generabon and charactenzation of
electron and hole traps created by hole injection during low &
gate voltage hot carrier stressing of n-MOS transistors," Fig. 2. Configuration for measuring the low-frequency open-loop
IEEE Trans. Electron Devices, vol. 37. no. 8, pp. 1869-1876, voltage gain

Stress Voltage e IO-
Parameter N-type op-amp P-type op-amp V &V = t 6 W
A 30-
T 60-
Av(dB) 67.3 71.6
UGF(MHz) 3.1 2.5
PM(deg) 74 94
Voff(mV) 3.8 4.9

Stress Voltage
V &V = + 6 . W

101 102 103 1[)1 105
(b) Frequency W )

Fig. 3. Open-loop response characteristics before and after stress

(a) N-type op-amp (b) P-type op-amp

vDD 4 v

+ 6.W

100 . . I

103 lo"

103 104 105
1W 103 101 10s (b) Stress time (sec.)
(b) :Stress time (sec.)

Fig. 4. Open-loop voltage gain variation measured at lkHz Fig. 6. Unity-gain frequency variation versus stress time (a)
versus stress time (a) N-type op-amp (b) P-type op-amp N-type op-amp (b) P-type op-amp


' I h

c .


E .

102 103 101 105
(a) Stress time (sec.)

102, ."
v &V


8 101 E
G Ea i.
1001 . ...?..., . ....... . . ....-

Fig. 5. Offset voltage vwiation versus stress time (a) N-type Fig. 7. Phase margin variation (a) N-type op-amp (b) P-type
op-amp (b) P-type op-amp OP-amP