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VHDL

Lab File
SUBMITTED BY
Giric Goyal

A2305208361

Roll No. 514

5CS3 (Y)

B.TECH (CSE)

SESSION: 2008-2012

INDEX

S.No DESCRIPTION Date Signature

EXPERIMENT NO 2

AIM: To implement HALF ADDER in VHDL using dataflow,
behavioral and structural style of modeling.

Theory:
Half adder is the most basic digital arithmetic circuit. It is a logical circuit that
performs an addition operation on two binary digits. It is a combinational circuit
which produces a sum and a carry value, which are both binary digits.
A half adder has two inputs, generally labeled A and B, and two outputs, the
“sum” S and “carry flag” C.

S is the two-bit “XOR gate” of A and B, and C is the “AND gate” of A and B.

S= A xor B
C=A and B

Following is the truth table for a half adder is –
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Dataflow code for Half Adder

CODE: library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (a,b:in bit;
sum,carry:out bit);
end half_adder;
architecture E of half_adder is
begin
sum<= a xor b;
carry<=a and b;
end E;

OUTPUT WAVEFORM:

std_logic_1164. use ieee. end E.carry:out bit). carry<='0'. OUTPUT WAVEFORM: .all. entity half_adder is port (a.b: in bit. architecture E of half_adder is begin process(a. carry<='1'.Behavioral code for Half Adder CODE: library ieee. carry<='0'. begin q :=a & b.b) variable q: bit_vector(0 to 1). case q is when "00"=> sum<='0'. sum. carry<='0'. when "01"=> sum<='1'. when "11"=> sum<='0'. end process . end case. end half_adder. when "10"=> sum<='1'.

b:in bit.Structural code for Half Adder CODE: library ieee. end xorg. entity half_adderg is port (a1. entity andg is port (a. z:out bit). end E1. use ieee. entity xorg is port (a.b:in bit. end andg. end E2. z: out bit). architecture E of xorg is begin z<= a xor b. begin A3: xorg port map (a1.carry). end half_adderg.sum).b: in bit.all. end E.b. A2: andg port map (a1. end component. z: out bit).b: in bit. OUTPUT WAVEFORM: . architecture E2 of half_adderg is component xorg port (a.carry:out bit). z:out bit). end component.b. architecture E1 of andg is begin z<= a and b.b: in bit.std_logic_1164. component andg port (a. sum.

which are both binary digits. S= A xor B xor Cin Cout=A. A half adder has three inputs. EXPERIMENT NO 3 AIM: To implement FULL ADDER in VHDL using dataflow. and Cin. Theory: Full adder is a combinational circuit that performs an addition operation on three binary digits. B. generally labelled A. It produces a sum and a carry value. and Cin. B. behavioral and structural style of modeling. and two outputs. S is the two-bit “XOR gate” of A.B+ (A xor B) Cin Following is the truth table for a full adder is- A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 . the “sum” S and “carry flag” Cout.

all.b.c:in bit.1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Dataflow code for Full Adder CODE library ieee. sum. architecture e1 of full_adder1 is begin carry<=(a and b) or (b and c) or (c and a). OUTPUT WAVEFORM: . sum<=a xor b xor c. use ieee.carry:out bit). entity full_adder1 is port (a.std_logic_1164. end e1. end full_adder1.

architecture e1 of fulladder is begin P1:process(a) begin case a is when "000"=>sum<='0'.all. end case. end fulladder. when "011"=>sum<='0'.carry<='0'. when "001"=>sum<='1'.Behavioral code for full adder CODE: library ieee.carry<='1'.carry<='1'.std_logic_1164. when "110"=>sum<='0'. entity fulladder is port(a:in bit_vector(0 to 2).carry<='0'. when "100"=>sum<='1'.carry<='0'.carry<='1'. OUTPUT WAVEFORM: . when "010"=>sum<='1'. when "101"=>sum<='0'. when "111"=>sum<='1'.carry:out bit). sum. use ieee.carry<='0'.carry<='1'. end process p1.

use ieee.b. end E2. end E1. end andg.all.Structural code for full adder CODE: library ieee. architecture E1 of org is begin z<=a or b or c.c:in bit. architecture E2 of xorg is begin z<=a xor b xor c. end org. sum. z:out bit).b.c: in bit.carry:out bit). entity andg is port (a. architecture E of andg is begin z<= a and b. entity xorg is port(a. z: out bit).b. entity full_adderg is port (a1. . end E.std_logic_1164.c:in bit. end xorg. end full_adderg.b:in bit. z:out bit). entity org is port (a.

end E3.x1).b. end component.x2.b.architecture E3 of full_adderg is component andg port (a. OR1: org port map (x1. component xorg port(a.c. end component.c.x2).b:in bit.x2.x3:bit. component org port (a.c. begin A4: andg port map (a1. z: out bit). z:out bit). z:out bit).b. end component.c:in bit. signal x1. A3: andg port map (a1.c: in bit.b.x3. XOR1: xorg port map (a1.carry). OUTPUT WAVEFORM: . A2: andg port map (b.x3).sum).

end mux41.std_logic_1164.all. architecture e1 of mux41 is begin z<=(((not s1) and (not s2) and a) or ((not s1) and (s2) and b) or ((s1) and (not s2) and c) or ((s1) and (s2) and d)). behavioral and structural style of modeling. Datafllow code for 4 to 1 multiplexer: FUNCTION:Y=((d0 and (not s0) and (not s1)) or (d1 and (not s1) and s0) or (d2 and s1 and (not s0)) or (d3 and s0 and s1)) CODE: library ieee.s1. entity mux41 is port (a.b.c. end e1.d. EXPERIMENT NO 4 AIM: To implement a 4X1 multiplexer in VHDL using dataflow. z:out bit). OUTPUT WAVEFORM .s2:in bit. use ieee.

d.Behavioral code for 4 to 1 multiplexer TRUTH TABLE: I/P O/P S0 S1 Y 0 0 D0 0 1 D1 1 0 D2 1 1 D3 CODE: library ieee.s2:in bit. architecture e1 of mux4 is begin process(a.c. elsif s1&s2="01" then z<=b. elsif s1&s2="10" .s2) begin if s1&s2="00" then z<=a.std_logic_1164.d. use ieee. z:out bit).s1.all.s1.c. entity mux4 is port(a.b. end mux4.b.

x5).std_logic_1164. else z<=d.d:in std_logic.c. signal x1. end component. end mux4str.d1. end component.b.x5. use ieee.s1.s0. u2:and3 port map(x1.d3. component or4 port(a.d2.y:out std_logic).s1.b. begin u0:not1 port map(s0. end e1.x3).d2.s1:in std_logic.all.d1.then z<=c. OUTPUT WAVEFORM: Structural code for 4X1 multiplexer: CODE: library ieee.x6:std_logic. u1:not1 port map(s1.y:out std_logic). entity mux4str is port(d0. component and3 port(a. architecture gate of mux4str is component not1 port(a:in std_logic.x1).x6). end component.x2).x3.x4).y:out std_logic). u5:and3 port map(s0. u4:and3 port map(x2. end process. .s0.x4.c:in std_logic.d3.y:out std_logic).x2.d0. end if. u3:and3 port map(x1.x2.

n-to-2n. behavioral and structural style of modeling. binary-coded decimal decoders. In digital electronics. where the input and output codes are different. OUTPUT WAVEFORM: EXPERIMENT NO 5 AIM: To implement a 3X8 decoder in VHDL using dataflow.y). Enable inputs must be on for the decoder to function. e. 7 segment display and memory address decoding.g. end gate. a decoder can take the form of a multiple-input. undoing the encoding so that the original information can be retrieved. u6:or4 port map(x3. Dataflow code for 3:8 decoder: . Decoding is necessary in applications such as data multiplexing.x6.x4.x5. Theory: A decoder is a device which does the reverse of an encoder. otherwise its outputs assume a single "disabled" output code word. The same method used to encode is usually just reversed in order to decode. multiple- output logic circuit that converts coded inputs into coded outputs.

b. architecture e1 of notg is begin b<= not a.c.CODE: library ieee. use ieee.enable:in bit. end andg.b.c:in bit.z.a.e.all. b<=((not x)and (not y)and z). h<=(x and y and z). architecture deco1 of decoder is begin a<=((not x)and (not y)and (not z)). end deco1. entity notg is port(a:in bit. use ieee. e<=(x and (not y)and (not z)). d<=((not x)and y and z).all. OUTPUT WAVEFORM Structural code for 3:8 decoder: CODE: library ieee.g.std_logic_1164. entity andg is port(a. . b: out bit).y.f.h:out bit). architecture e2 of andg is begin d<= a and b and c. end notg. entity decoder is port(x. g<=(x and y and (not z)). end architecture. f<=(x and (not y)and z).std_logic_1164. c<=((not x)and y and (not z)).d. end decoder. d: out bit).

d(4)). end main. x6:andg port map(x. x5:andg port map(x.a(1). x10:andg port map(a(0). signal x. x9:andg port map(a(0).a(2).z. begin x1:notg port map(a(0). b: out bit).z.a(2).a(1).y. architecture main of main is component notg is port(a:in bit. x11:andg port map(a(0).a(2).z).b.y). end component. end architecture. d: out bit_vector(0 to 7)).x). component andg is port(a.z.d(3)).y. OUTPUT WAVEFORM .a(1).a(2).d(2)). end architecture.d(5)).d(0)).a(1). x8:andg port map(a(0).y. end component.y. x2:notg port map(a(1).y.c:in bit.d(6)). x3:notg port map(a(2).z.d(1)).d(7)). x4:andg port map(x. x7:andg port map(x. d: out bit).z:bit. entity main is port( a: in bit_vector(0 to 2).

all. .std_logic_1164. when "001" => s<="01000000". a:in bit_vector(0 to 2)). end decoder. use ieee. architecture behaviour of decoder is begin process(a) begin case a is when "000" => s<="10000000".Behavioral code for 3:8 decoder: CODE: library ieee. entity decoder is port (s:out bit_vector(0 to 7).

when "011" => s<="00010000". [7] It is called the D flip-flop for this reason. when "010" => s<="00100000". end behaviour. OUTPUT WAVEFORM EXPERIMENT NO 6 AIM: To implement a D. Theory: D FLIP FLOP : The Q output always takes on the state of the D input at the moment of a rising clock edge (or falling edge if the clock input is active low). T. end process. when "110" => s<="00000010". since the output takes the value of . J-K Flip Flop using behavioural style of modeling. end case. when "100" => s<="00001000". S-R. when "111" => s<="00000001". when "101" => s<="00000100".

zero-order hold. end diff. .clk:in bit.qbar:inout bit). library ieee. entity diff is port(d. q.all.all.std_logic_1164. use ieee.the D input or Data input. and Delays it by one clock count. use ieee. The D flip-flop can be interpreted as a primitive memory cell. or delay line. Truth table: Clock D Q Qprev Rising 0 0 X edge Rising 1 1 X edge Non-Rising X Qprev Behavioral code for D flip flop: CODE: library ieee.std_logic_1164.

qbar<= not d. This behavior is described by the characteristic equation: (or. end process. the equivalent: ) . OUTPUT WAVEFORM T FLIP FLOP : If the T input is high. the T flip-flop changes state ("toggles") whenever the clock input is strobed. the flip-flop holds the previous value.clk) begin if clk='1' and clk' event then q<= d. without benefit of the XOR operator. end if. architecture behav of diff is begin process(d. If the T input is low. end behav.

std_logic_1164.all. and can be described in a truth table: T Flip-Flop operation [6] Characteristic table Excitation table T Q Qnext Comment Q Qnext T Comment 0 0 0 hold state (no clk) 0 0 0 No change 0 1 1 hold state (no clk) 1 1 0 No change 1 0 1 toggle 0 1 1 Complement 1 1 0 toggle 1 0 1 Complement Behavioral code for T flip flop: CODE: library ieee. . use ieee.

clk:in bit. end tiff. entity tiff is port(t.qbar:inout bit). end process. OUTPUT WAVEFORM SR FLIP FLOP : . end behav.clk) begin if clk='1' and clk' event then q<=not t. q. qbar<=t. architecture behav of tiff is begin process(t. end if.

The fundamental latch is the simple SR flip-flop. the S and R inputs are both low. If S is pulsed high while R is held low. where S and R stand for set and reset. in storage mode. then the Q output is forced low. respectively. meaning the signal is irrelevant) . It can be constructed from a pair of cross- coupled NAND or NORlogic gates. with Q the complement of Q. then the Q output is forced high. and stays low even after R returns low. similarly. Normally. and stays high even after S returns low. SR Flip-Flop operation (BUILT WITH NOR GATES) [6] Characteristic table Excitation table SR Action Q(t) Q(t+1) S R Action 0 0 Keep state 0 0 0 X No change 0 1 Q=0 0 1 1 0 reset 1 0 Q=1 1 0 0 1 set 1 1 Unstable combination 1 1 X 0 race condition ('X' denotes a Don't care condition. if R is pulsed high while S is held low. and feedback maintains the Q and Q outputs in a constant state. The stored bit is present on the output marked Q.

OUTPUT WAVEFORM . if clk='1' and clk' event then case g is when "00"=> null. architecture behav of srff is begin process(s. end process.clk:in bit. end behav. entity srff is port(s.Behavioral code for SR flip flop: CODE: library ieee.r. when "10"=> q<='1'.qbar:inout bit). end if. when "11"=> assert r/='1' and s/='1'report "invalid condition" severity error. end srff. qbar<='1'. q. use ieee. begin g:= s&r. qbar<='0'. end case.clk) variable g: bit_vector(0 to 1).r.std_logic_1164.all. when "01"=> q<='0'.

the combination J = 0.e. The JK flip-flop is therefore a universal flip-flop. K = 1 is a command to reset the flip-flop. because it can be configured to work as an SR flip-flop. a D flip-flop. The characteristic equation of the JK flip-flop is: and the corresponding truth table is: JK Flip Flop operation Characteristic table Excitation table J K Qnext Comment Q Qnext J K Comment 0 0 Qprev hold state 0 0 0 X No change 0 1 0 reset 0 1 1 X Set 1 0 1 set 1 0 X 1 Reset 1 1 Qprev toggle 1 1 X 0 No change . will hold the current state. Setting J = K = 0 does NOT result in a D flip-flop. i. or a T flip-flop.. K = 0 is a command to set the flip-flop. and the combination J = K = 1 is a command to toggle the flip-flop. Specifically. K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. To synthesize a D flip-flop. simply set K equal to the complement of J. change its output to the logical complement of its current value.JK FLIP FLOP : The JK flip-flop augments the behavior of the SR flip-flop (J=Set. the combination J = 1. but rather.

qbar:inout bit). architecture behav of jkff is begin process(j. entity jkff is port(j.std_logic_1164. OUTPUT WAVEFORM . when "11"=> q<=not q. begin s:= j&k.k.k. if clk='1' and clk' event then case s is when "00"=> null. use ieee.clk) variable s: bit_vector(0 to 1). qbar<=q.Behavioral code for JK flip flop: CODE: library ieee. end case. end process. end jkff. when "10"=> q<='1'. qbar<='1'.all.clk:in bit. when "01"=> q<='0'. qbar<='0'. end behav. end if. q.

0 (in that order. we would get exactly what was put in. This is called clocking or strobing) to the register.e. The left hand column corresponds to the left-most flip-flop's output pin. As 'Data In' 0 1 1 0 presents 1.0. At each advance. with a pulse at 'Data Advance' 0 0 1 1 each time.0.e.1. The bit on the far right (i. Theory: These are the simplest kind of shift registers. at any time. so there are four storage 'slots' available in this arrangement. 'Data Out') is shifted out and lost. and is shifted right one stage each time 'Data Advance' is brought high. but offset by four 'Data Advance' cycles. this is the 0 0 0 1 result.1. 0 0 0 0 So the serial output of the entire register is 10110000 (). Also. the bit on the far left (i. and so on. 1 0 0 0 0 1 0 0 The data are stored after each flip-flop on the 'Q' output.each datum is lost once it been shifted out of the right-most bit. the whole register can be set to zero by bringing the reset (R) pins high.0. This arrangement is the hardware equivalent of a queue. 'Data In') is shifted into the 0 0 0 0 first flip-flop's output. imagine that the 1 1 0 1 register holds 0000 (so all storage slots are empty). This arrangement performs destructive readout . As you can see if we were to continue to input data. To give an idea of the shifting pattern. EXPERIMENT NO 7 AIM: To design shift registers in VHDL using structural. The data string is presented at 'Data In'.0. . hence it is a 4-Bit 1 0 1 0 Register.

q:out bit).clk:in bit. signal q0. end e1. end if.clk:in bit.all.clk.Structural code for SISO: CODE: library ieee. architecture e1 of dff is begin process(d. end e1.clk:in bit. end dff.qout). q:out bit). qout:out bit).clk.q0). clk) begin if clk='1' and clk'event then q<=d. end siso. n3:dff port map(q1. n2:dff port map(q0.q1.q1). n4:dff port map(q2. end component.clk.q2:bit. entity siso is port( input. end process. architecture e1 of siso is component dff port(d.std_logic_1164. entity dff is port(d. use ieee.clk. OUTPUT WAVEFORM .q2). begin n1:dff port map(input.

clk.all. end component.q2). architecture e1 of pipo is component dff port (d.b. use ieee. end pipo.PIPO: The PARALLEL IN/PARALLEL OUT shift register is loaded with four bits simultaneously.clk. q0. in parallel. end e1. entity dff is port (d. .They are also clocked out simultaneously. q.c. begin N1: dff port map (a. N2: dff port map (b. end dff. Structural code for PIPO: CODE: library ieee. in parallel.clk:in bit.q2. q. qbar<=not d.clk.qbar:out bit). end process.qbar:out bit).q0). architecture behav of dff is begin process (d.d.q1.q3:out bit). end if. N4: dff port map (d.q1).clk:in bit. entity pipo is port (a.clk.clk) begin if clk = '1' and clk'event then q<=d. end behav.clk:in bit. N3: dff port map (c.std_logic_1164.q3).

the Write/Shift control line must be held LOW. Structural code for PIPO: CODE: library ieee. the W/S control line is brought HIGH and the registers are clocked. end e1. will be the parallel data read off in order.x. The arrangement now acts as a SISO shift register.clk:in bit. end process.clk) . Q. end dff. with D1 as the Data Input. entity dff is port (d. architecture e1 of ctrl is begin process(x. inpf2:out bit). architecture behav of dff is begin process (d. q.control:in bit.outf1) begin if control='1' then inpf2<=x. use ieee. To shift the data. end ctrl. entity ctrl is port(outf1.OUTPUT WAVEFORM PISO: This configuration has the data input on lines D1 through D4 in parallel format. However. the Data Output.std_logic_1164. else inpf2<=outf1.qbar:out bit).all. as long as the number of clock cycles is not more than the length of the data-string.control. end if. To write the data to the register.

x. N4: ctrl port map (q1.control.d. component ctrl port(outf1. architecture e2 of piso is component dff port (d. N6: ctrl port map (q2.c. N3: dff port map (d1.d3:inout bit.clk.q0).q2.clk:in bit. entity piso is port(a. end piso. OUTPUT WAVEFORM . q0.q3).d0.clk.control.qbar:out bit).d3).b.d2.d1). end component. control. N7: dff port map (d3. begin if clk = '1' and clk'event then q<=d. N2: ctrl port map (q0.control. end e2.control:in bit. end process. q.c.q3:inout bit. N5: dff port map (d2.b. end component. end behav. end if.c.clk. qbar<=not d.clk.q2).q1). begin d0<=a.d1. N1: dff port map (a. inpf2:out bit).clk:in bit).q1.d2).

it may be either read off at each output simultaneously. architecture e1 of sipo is .std_logic_1164. end dff. entity dff is port (d.clk:in bit.qbar:out bit). Once the data has been input. end if.q3:inout bit).clk) begin if clk = '1' and clk'event then q<=d. end behav. or it can be shifted out and replaced. Data is input serially. use ieee. qbar<=not d. q0. end process.clk:in bit. Structural code for PIPO: CODE: library ieee. as described in the SISO section above. entity sipo is port (input.q2. q. architecture behav of dff is begin process (d.all.SIPO: This configuration allows conversion from serial to parallel format.q1. end sipo.

.qbar:out bit). N2: dff port map (q0. ENTITY binary_counter IS port( clk. USE ieee.clk:in bit.q2). use ieee.std_logic_1164.q1). USE ieee. N4: dff port map (q2.std_logic_unsigned. there are two types of counters: • Up counters. which increase (increment) in value • Down counters. often in relationship to a clock signal. component dff port (d. begin N1: dff port map (input.q0). OUTPUT WAVEFORM EXPERIMENT NO 9 AIM: Design a mod 5 counter Theory: In digital logic and computing.clk.all.std_logic_arith. N3: dff port map (q1.all. which decrease (decrement) in value A mod 5 counter counts till binary four and in fifth clock pulse it counts back to zero. reset:in bit. end e1. In practice. count:out std_logic_vector( 0 to 2)). a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred.clk.clk.q3). end component. q.clk.all. Behavioral code for mod 5 counter: CODE: library ieee.

reset) begin if reset='1' then temp<="000". end if. count<= temp. OUTPUT WAVEFORM . ARCHITECTURE binary OF binary_counter IS signal temp: std_logic_vector( 0 to 2):="000". BEGIN process ( clk. else if clk='1' and clk'event then temp<= temp+ 1. END ENTITY binary_counter. END ARCHITECTURE binary. end process. end if.

often in relationship to a clock signal. a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred. Behavioral code for binary counter: . In practice. which decrease (decrement) in value binary counter is a machine (like a computer) which counts in binary. there are two types of counters: • Up counters. which increase (increment) in value • Down counters. EXPERIMENT NO 8 AIM: Design a binary counter Theory: In digital logic and computing.

std_logic_arith.all.all. ENTITY binary_counter IS port( clk. end if. END ARCHITECTURE binary. USE ieee. ARCHITECTURE binary OF binary_counter IS signal temp: std_logic_vector( 0 to 2):="000". reset:in bit.std_logic_1164. END ENTITY binary_counter. use ieee. count:out std_logic_vector( 0 to 2)). count<= temp.std_logic_unsigned. USE ieee.CODE: library ieee. end if. BEGIN process ( clk. OUTPUT WAVEFORM . reset) begin if reset='1' then temp<="000".all. end process. else if clk='1' and clk'event then temp<= temp+ 1.

The ALU is a fundamental building block of the central processing unit (CPU) of a computer. a single component may contain a number of ALUs. The processors found inside modern CPUs and graphics processing units accommodate very powerful and very complex ALUs. and even the simplest microprocessors contain one for purposes such as maintaining timers. . EXPERIMENT NO 10 AIM: Design simple ALU Theory: An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations.

when"1111"=> y<= not ( a xor b).Behavioral code forALU: CODE: library ieee. when"1110"=> y<= a xor b.b:in std_logic_vector(2 downto 0). END ARCHITECTURE alu. when"0100"=> y<=b+1. when"0001"=> y<=a+1.std_logic_unsigned. USE ieee. y:out std_logic_vector( 2 downto 0)). when others=> null. use ieee.std_logic_1164. when"0011"=> y<=b.b. when"0111"=> y<=a+b+cin. USE ieee.sel) begin case sel is --arithmetic unit when"0000"=> y<=a. when"1100"=> y<= a nand b.logic unit when"1000"=> y<= not a. END ENTITY alu. when"0010"=> y<=a-1. when"0101"=> y<=b-1. when"1010"=> y<= a and b. when"1101"=> y<= a nor b. ARCHITECTURE alu OF alu IS BEGIN process( a. OUTPUT WAVEFORM . ENTITY alu IS port( a. cin: in std_logic. sel: in std_logic_vector(3 downto 0). -.all. when"1011"=> y<= a or b.all. when"1001"=> y<= not b.all. when"0110"=> y<=a+b.std_logic_arith. end process. end case.

it behaves according to the truth table to the right. A HIGH output (1) results if one . EXPERIMENT NO 1 AIM: To implement logic gates Theory: OR GATE The OR gate is a digital logic gate that implements logical disjunction .

all.or both the inputs to the gate are HIGH (1). x:out bit). entity orgate is port(a.b:in bit. If neither input is HIGH. . use ieee. a LOW output (0) results. end orgate.std_logic_1164. INPUT OUTPUT A B A+B 0 0 0 0 1 1 1 0 1 1 1 1 Behavioral code for OR gate: CODE: library ieee.

end if. end process p1. elsif a='0' and b='1' then x<='1'. architecture behav of orgate is begin p1:process(a. OUTPUT WAVEFORM NOR GATE: The NOR gate is a digital logic gate that implements logical NOR . elsif a='1' and b='0' then x<='1'. A HIGH output (1) results if both the . end behav.it behaves according to the truth table to the right.b) begin if a='0' and b='0' then x<='0'. else x<='1'.

By contrast.all. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation -. a LOW output (0) results. If one or both input is HIGH (1).combinations of NOR gates can be combined to generate any other logical function. . the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.std_logic_1164. use ieee.inputs to the gate are LOW (0). INPUT OUTPUT A B A NOR B 0 0 1 0 1 0 1 0 0 1 1 0 Behavioral code for NOR gate: CODE: library ieee.

OUTPUT WAVEFORM XOR GATE: . end behav. end process p1. end if.b) begin if a='0' and b='0' then x<='1'. entity norgate is port(a.b:in bit. end norgate. elsif a='1' and b='0' then x<='0'. x:out bit). else x<='0'. architecture behav of norgate is begin p1:process(a. elsif a='0' and b='1' then x<='0'.

a LOW output (0) results. end x1.b) variable c: bit_vector(0 to 1). end case. architecture x1 of exor is begin process(a. end process. If both inputs are LOW (0) or both are HIGH (1). case c is when "00" => z<='0'." INPUT OUTPUT A B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0 Behavioral code for XOR gate: CODE: library ieee. end exor. XOR gate is short for exclusive OR. A way to remember XOR is "one or the other but not both. A HIGH output (1) results if one. This means that precisely one input must be 1 (true) for the output to be 1 (true). entity exor is port( a.std_logic_1164.all.The XOR gate (sometimes EOR gate) is a digital logic gate that implements exclusive disjunction . and only one.it behaves according to the truth table above. z: out bit). when "10" => z<='1'. . use ieee. when "01" => z<='1'. of the inputs to the gate is HIGH (1). begin c:= a&b. when "11" => z<='0'.b: in bit.

OUTPUT WAVEFORM .

a LOW output (0) results. end if. elsif a='1' and b='0' then x<='0'.XNOR GATE: The XNOR gate (sometimes spelled "exnor" or "enor") is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. entity norgate is port(a.b) begin if a='0' and b='0' then x<='1'. OUTPUT WAVEFORM . If one but not both inputs are HIGH (1). behaving according to the truth table to the right. x:out bit). elsif a='0' and b='1' then x<='0'.b:in bit. end process p1. end behav.std_logic_1164. architecture behav of norgate is begin p1:process(a. A HIGH output (1) results if both of the inputs to the gate are the same. end norgate. Behavioral code for XOR gate: CODE: library ieee. use ieee. The two-input version implements logical equality.all. else x<='0'.

Behavioral code for XOR gate: CODE: library ieee. when "01"=>z<='1'. begin t:=a & b. end process. end a1. end nandg.all.b) variable t:bit_vector(0 to 1).z:out bit). OUTPUT WAVEFORM . Due to this property. case t is when "00"=>z<='1'. begin process(a. contrary to popular belief. EDA tools are used to convert the description of a logical circuit to a netlist of complex gates (standard cells). entity nandg is port(a. However. end case. modern integrated circuits are not constructed exclusively from a single type of gate. Instead.std_logic_1164. when "10"=>z<='1'. when "11"=>z<='0'. architecture a1 of nandg is constant nandg_delay: time := 10 ns.NAND GATE: NAND gates are one of the two basic logic gates (along with NOR gates) from which any other logic gates can be built.b:in bit. NAND and NOR gates are sometimes called "universal gates". use ieee.