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CAT28C64B

64K-Bit CMOS PARALLEL E2PROM

FEATURES
■ Fast Read Access Times: ■ Commercial, Industrial and Automotive
– 120/150ns Temperature Ranges
■ Low Power CMOS Dissipation: ■ Automatic Page Write Operation:
– Active: 25 mA Max. – 1 to 32 Bytes in 5ms
– Standby: 100 µA Max. – Page Load Timer
■ Simple Write Operation: ■ End of Write Detection:
– On-Chip Address and Data Latches – Toggle Bit
– Self-Timed Write Cycle with Auto-Clear – DATA Polling
■ Fast Write Cycle Time: ■ 100,000 Program/Erase Cycles
– 5ms Max.
■ 100 Year Data Retention
■ CMOS and TTL Compatible I/O
■ Hardware and Software Write Protection

DESCRIPTION
The CAT28C64B is a fast, low power, 5V-only CMOS The CAT28C64B is manufactured using Catalyst’s ad-
Parallel E2PROM organized as 8K x 8-bits. It requires a vanced CMOS floating gate technology. It is designed to
simple interface for in-system programming. On-chip endure 100,000 program/erase cycles and has a data
address and data latches, self-timed write cycle with retention of 100 years. The device is available in JEDEC-
auto-clear and VCC power up/down write protection approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32-
eliminate additional timing and protection hardware. pin PLCC package .
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write pro-
tection.

BLOCK DIAGRAM
ROW 8,192 x 8
A5–A12 ADDR. BUFFER
DECODER E2PROM
& LATCHES
ARRAY

INADVERTENT HIGH VOLTAGE
VCC 32 BYTE PAGE
WRITE GENERATOR
REGISTER
PROTECTION

CE
OE CONTROL
WE LOGIC
I/O BUFFERS
DATA POLLING
TIMER AND
TOGGLE BIT I/O0–I/O7

ADDR. BUFFER
A0–A4 COLUMN
& LATCHES
DECODER

5094 FHD F02

© 1999 by Catalyst Semiconductor, Inc. Doc. No. 25006-0A 2/98 P-1
Characteristics subject to change without notice 1

25006-0A 2/98 P-1 2 .4mm) (T13) VCC A12 WE NC NC NC A7 OE 1 28 A10 4 3 2 1 32 31 30 A11 2 27 CE A6 5 29 A8 A9 3 26 I/O7 A5 6 28 A9 A8 4 25 I/O6 NC 5 24 I/O5 A4 7 27 A11 WE 6 23 I/O4 A3 8 26 NC VCC 7 22 I/O3 9 25 NC 8 21 GND A2 TOP VIEW OE A12 9 20 I/O2 A1 10 24 A10 A7 10 19 I/O1 A0 11 23 CE A6 11 18 I/O0 A5 12 17 A0 NC 12 22 I/O7 A4 13 16 A1 I/O0 13 21 I/O6 A3 14 15 A2 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 28C64B F03 5094 FHD F01 PIN FUNCTIONS Pin Name Function Pin Name Function A0–A12 Address Inputs WE Write Enable I/O0–I/O7 Data Inputs/Outputs VCC 5 V Supply CE Chip Enable VSS Ground OE Output Enable NC No Connect Doc. No. K) NC 1 28 VCC NC 1 28 VCC A12 2 27 WE A12 2 27 WE A7 3 26 NC A7 3 26 NC A6 4 25 A8 A6 4 25 A8 A5 5 24 A9 A5 5 24 A9 A4 6 23 A11 A4 6 23 A11 A3 7 22 OE A3 7 22 OE A2 8 21 A10 A2 8 21 A10 A1 9 20 CE A1 9 20 CE A0 10 19 I/O7 A0 10 19 I/O7 I/O0 11 18 I/O6 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O1 12 17 I/O5 I/O2 13 16 I/O4 I/O2 13 16 I/O4 VSS 14 15 I/O3 VSS 14 15 I/O3 PLCC Package (N) TSOP Package (8mm x 13.CAT28C64B PIN CONFIGURATION DIP Package (P) SOIC Package (J.

....... Doc......... CAT28C64B ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias .. No more than one output shorted at a time......... Units Test Method NEND(1) Endurance 105 Cycles/Byte MIL-STD-883... During transitions......0V to +VCC + 2. (2) The minimum DC input voltage is –0.... f = 1.. Test Method 1008 VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883.5V. Exposure to any absolute maximum Package Power Dissipation rating for extended periods may affect device perfor- Capability (Ta = 25°C) ... 25006-0A 2/98 P-1 3 .. 1... 300°C Output Short Circuit Current(3) ... –65°C to +150°C These are stress ratings only............. Max....... Units Conditions CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.....5V.0V for periods of less than 20 ns.. Storage Temperature . inputs may undershoot to –2........ and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE CAPACITANCE TA = 25°C. Lead Soldering Temperature (10 secs) ..... Test Method 3015 ILTH (1)(4) Latch-Up 100 mA JEDEC Standard 17 MODE SELECTION Mode CE WE OE I/O Power Read L H L DOUT ACTIVE Byte Write (WE Controlled) L H DIN ACTIVE Byte Write (CE Controlled) L H DIN ACTIVE Standby.. –2. Test Method 1033 TDR (1) Data Retention 100 Years MIL-STD-883..........0V those listed in the operational sections of this specifica- VCC with Respect to Ground ....... VCC = 5V Symbol Test Max...0V tion is not implied.0V to +7.... (3) Output shorted for no more than one second...0V for periods of less than 20 ns.... (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. No...0W mance and reliability... Maximum DC voltage on output pins is VCC +0.......... 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min...0 MHz...... –2... –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device..... which may overshoot to VCC +2. and functional operation Voltage on Any Pin with of the device at these or any other conditions outside of Respect to Ground(2) ...

No.5 V Note: (1) VILC = –0.3V. All I/O’s Open ISB VCC Current (Standby. f = 1/tRC min.4 V IOL = 2. All I/O’s Open ILI Input Leakage Current –10 10 µA VIN = GND to VCC ILO Output Leakage Current –10 10 µA VOUT = GND to VCC.3 0. 25006-0A 2/98 P-1 4 .CAT28C64B D. Doc. Limits Symbol Parameter Min. Max.4 V IOH = –400µA VOL Low Level Output Voltage 0.3 V VIL(1) Low Level Input Voltage –0. unless otherwise specified.1mA VWI Write Inhibit Voltage 3. OPERATING CHARACTERISTICS VCC = 5V ±10%. (2) VIHC = VCC –0. All I/O’s Open ICCC(1) VCC Current (Operating. CE = VIH VIH(2) High Level Input Voltage 2 VCC +0. TTL) 30 mA CE = OE = VIL. Units Test Conditions ICC VCC Current (Operating. CMOS) 100 µA CE = VIHC. f = 1/tRC min.8 V VOH High Level Output Voltage 2.3V to +0. CMOS) 25 mA CE = OE = VILC.3V to VCC +0.C. All I/O’s Open ISBC(2) VCC Current (Standby. TTL) 1 mA CE = VIH.3V. Typ.

C. Read Cycle VCC = 5V ±10%. (3) Input rise and fall times (10% and 90%) < 10 ns. Doc. CHARACTERISTICS. unless otherwise specified. Testing Input/Output Waveform(3) 2. Testing Load Circuit (example) 1. Min. 28C64B-12 28C64B-15 Symbol Parameter Min.3K DEVICE UNDER OUT TEST CL = 100 pF CL INCLUDES JIG CAPACITANCE 5096 FHD F04 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.C. A.8 V 0. Max. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. Units tRC Read Cycle Time 120 150 ns tCE CE Access Time 120 150 ns tAA Address Access Time 120 150 ns tOE OE Access Time 60 70 ns tLZ(1) CE Low to Active Output 0 0 ns tOLZ(1) OE Low to Active Output 0 0 ns tHZ(1)(2) CE High to High-Z Output 50 50 ns tOHZ(1)(2) OE High to High-Z Output 50 50 ns tOH(1) Output Hold from Address Change 0 0 ns Figure 1. Max. 25006-0A 2/98 P-1 5 .0 V INPUT PULSE LEVELS REFERENCE POINTS 0. No. A.3V 1N914 3.4 V 2. CAT28C64B A.C.45 V 5096 FHD F03 Figure 2.

No. 25006-0A 2/98 P-1 6 . unless otherwise specified. (3) A timer of duration tBLC max.05 100 . Write Cycle VCC = 5V ±10%.C. a page or byte write will begin. If allowed to time out. CHARACTERISTICS. stops the timer.05 100 µs Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Min. Units tWC Write Cycle Time 5 5 ms tAS Address Setup Time 0 0 ns tAH Address Hold Time 100 100 ns tCS CE Setup Time 0 0 ns tCH CE Hold Time 0 0 ns tCW(2) CE Pulse Time 110 110 ns tOES OE Setup Time 0 0 ns tOEH OE Hold Time 0 0 ns tWP(2) WE Pulse Width 110 110 ns tDS Data Setup Time 60 60 ns tDH Data Hold Time 0 0 ns tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 ms tBLC(1)(3) Byte Load Cycle Time . (2) A write pulse of less than 20ns duration will not initiate a write cycle. Max. begins with every LOW to HIGH transition of WE. 28C64B-12 28C64B-15 Symbol Parameter Min. however a transition from HIGH to LOW within tBLC max.CAT28C64B A. Doc. Max.

Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOHZ tOLZ tOH tHZ HIGH-Z DATA OUT DATA VALID DATA VALID tAA 28C64B F06 Figure 4. low. Once initiated. Figure 3. 25006-0A 2/98 P-1 7 . CAT28C64B DEVICE OPERATION Byte Write A write cycle is executed when both CE and WE are low. Byte Write Cycle [WE Controlled] tWC ADDRESS tAS tAH tCS tCH CE OE tOES tWP tOEH WE tBLC HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH 5096 FHD F06 Doc. This 2-line control architec. with the address input being latched on the bus when WE is held high. Write cycles can be initiated using either Data stored in the CAT28C64B is transferred to the data WE or CE. whichever occurs first. either CE or OE goes high. Data. is latched on the rising edge of WE or CE. No. Read and OE is high. and both OE and CE are held falling edge of WE or CE. data is written within 5 ms. The data bus is set to a high impedance state when conversely. a byte write cycle ture can be used to eliminate bus contention in a system automatically erases the addressed byte and the new environment. whichever occurs last.

Each successive byte load extended BYTE WRITE mode) allows from 1 to 32 bytes cycle must begin within tBLC MAX of the rising edge of the of data to be programmed within a single E2PROM write preceding WE pulse. factor of 32. which erases any data and data bytes into a 32 byte temporary buffer. for stay high a minimum of tBLC MAX for the internal auto- tWP. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tBLC tCW CE tOEH OE tOES tCS tCH WE HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH 5094 FHD F07 Figure 6. No. address where data is to be written. is latched on the last falling edge of WE. and a write cycle. Figure 5. WE must Following an initial WRITE operation (WE pulsed low. which load the address cycle consists of an erase cycle. and then high) the page write mode can begin by matic program cycle to commence. This programming issuing sequential WE pulses. This effectively reduces the byte-write time by a limitation as long as WE is pulsed low within tBLC MAX. A page write will to A12. There is no page write window cycle. specified by bits A5 which writes new data back into the cell. The page that existed in each addressed cell. 25006-0A 2/98 P-1 8 . Each only write data to the locations that were addressed and byte within the page is defined by address bits A0 to A4 will not rewrite the entire page. Upon completion of the page write sequence. Page Mode Write Cycle OE CE t WP t BLC WE ADDRESS t WC I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 5096 FHD F10 Doc.CAT28C64B Page Write (which can be loaded in any order) during the first and The page write mode of the CAT28C64B (essentially an subsequent write cycles.

once the write is complete. all stops toggling and valid data can be read from the I/O’s will output true data during a read cycle. Doc. the device offers write cycle. While a write cycle is in progress. attempting to read the last byte written will a write cycle. 25006-0A 2/98 P-1 9 . Once a byte write or page write cycle is an additional method for determining the completion of initiated. Toggle Bit WE CE tOEH tOES tOE OE I/O6 (1) (1) tWC 28C64B F11 Note: (1) Beginning and ending state of I/O6 is indeterminate. However. Figure 7. one and zero. CAT28C64B DATA Polling Toggle Bit DATA polling is provided to indicate the completion of In addition to the DATA Polling feature. No. I/O6 plete. reading output the complement of that data on I/O7 (I/O0–I/O6 data from the device will result in I/O6 toggling between are indeterminate) until the programming cycle is com. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X DOUT = X 28C64B F10 Figure 8. Upon completion of the self-timed write cycle. device.

in the standard operating mode). Write Sequence for Deactivating Data Protection Software Data Protection WRITE DATA: AA WRITE DATA: AA ADDRESS: 1555 ADDRESS: 1555 WRITE DATA: 55 WRITE DATA: 55 ADDRESS: 0AAA ADDRESS: 0AAA WRITE DATA: A0 WRITE DATA: 80 ADDRESS: 1555 ADDRESS: 1555 SOFTWARE DATA WRITE DATA: AA (1) PROTECTION ACTIVATED ADDRESS: 1555 WRITE DATA: XX WRITE DATA: 55 TO ANY ADDRESS ADDRESS: 0AAA WRITE LAST BYTE WRITE DATA: 20 TO LAST ADDRESS ADDRESS: 1555 28C64B F12 5094 FHD F09 Note: (1) Write protection is activated at this point whether or not any more writes are completed.5V min. performed. Figure 9. CE high or WE high. Doc. SOFTWARE DATA PROTECTION (1) VCC sense provides for write protection when VCC The CAT28C64B features a software controlled data falls below 3. Writing to addresses must occur within tBLC Max. inputs will not result in a write cycle. requires a data algorithm to be issued to the device before a write can be (2) A power on delay mechanism.CAT28C64B HARDWARE DATA PROTECTION (4) Noise pulses of less than 20 ns on the WE or CE The following is a list of hardware data protection fea. 25006-0A 2/98 P-1 10 .5V min. after SDP activation. tures that are incorporated into the CAT28C64B. protection scheme which. (3) Write inhibit is activated by holding any one of OE low. The device is shipped from Catalyst with the teristics). after VCC has reached 3. once enabled. provides a 5 to 10 ms delay before a write software protection NOT ENABLED (the CAT28C64B is sequence. tINIT (see AC charac.. No. Write Sequence for Activating Software Figure 10.

reset the internal protection circuitry. and the device will all subsequent byte or page writes to the device must be return to standard operating mode (Figure 12 provides preceded by this same set of write commands. tions. 150 ns Access Time. The six step algorithm (Figure 10) will write timing specifications (Figure 11). This sequence of commands is a software command sequence for deactivating the (along with subsequent writes) must adhere to the page data protection. Doc. The data reset timing). CAT28C64B To activate the software data protection. After the sixth byte of this reset sequence protection mechanism is activated until a deactivate has been issued. Tape & Reel). 25006-0A 2/98 P-1 11 . the device must To allow the user the ability to program the device with be sent three write commands to specific addresses with an E2PROM programmer (or for testing purposes) there specific data (Figure 9). Software Data Protection Timing DATA AA 55 A0 tWC ADDRESS 1555 0AAA 1555 BYTE OR CE PAGE WRITES tWP tBLC ENABLED WE 5094 FHD F13 Figure 12. Figure 11. Industrial temperature. No. commence. Once this is done. This gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided.4mm) * -40˚C to +125˚C is available upon request 28C64B F15 Notes: (1) The device used in the above example is a CAT28C64BNI-15T (PLCC. standard byte or page writing can sequence is issued regardless of power on/off transi. Resetting Software Data Protection Timing DATA AA 55 80 AA 55 20 tWC SDP ADDRESS 1555 0AAA 1555 1555 0AAA 1555 RESET CE DEVICE UNPROTECTED WE 5094 FHD F14 ORDERING INFORMATION Prefix Device # Suffix CAT 28C64B N I -15 T Product Temperature Range Tape & Reel Number Blank = Commercial (0˚C to +70˚C) T: 500/Reel I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* Package Optional P: PDIP Speed Company J: SOIC (JEDEC) 12: 120ns ID K: SOIC (EIAJ) 15: 150ns N: PLCC T13: TSOP (8mmx13.

25006-0A 2/98 P-1 12 .CAT28C64B Doc. No.