PRE-SYNOPSIS REPORT

PROJECT TITLE:- Simulation & Analysis Of LC-VCO(Voltage Controlled Oscillator)

using CMOS technology.
AREA OF WORK: VLSI
TYPE OF MODEL:-Software (TSpice 16.0)
PROJECT/IDEA CONCEPT:- With the tremendous growth of wireless communication
technologies there is a continuous demand for low cost, low power and high integration on-chip
solutions.It keeps pushing CMOS integrated wireless systems to support much more
communication standards(WLAN,GSM,Bluetooth and Wireless sensor area network).VCO is a
important Component in radio transceiver and it has specifications like low noise,low power
consumption,high packaging density,high frequency and wide tuning range.
LC based VCO is been used because of its high frequency stability and spectral
purity.And are widely used in RF transceivers because of its easier implementation and low
phase noise performance.

PROJECT OBJECTIVE/AIM:-

AIM:-The basic aim of this project is to simulate and compare the parameters of NMOS cross
coupled LC VCO(Voltage Controlled Oscillator) with its previous work using modern CMOS
technology and then design its physical layout.

Following steps are needed to be followed to accomplish different objectives:-

1. Circuit Of VCO using Cross Coupled NMOS topology a varactor circuit is implemented
with help of 4 transistors to tune O/P frequency of VCO.
2. The VCO is implemented using TMSC 130nm CMOS and simulations are carried out
using ADS(Advanced design System) tool
3. Comparison between different parameters of previous LC VCO and proposed LC VCO
4. The parameters are (Supply voltage,frequency,wide tuning range,power dissipation and
phase noise.
5. FOM(figure of Merit) is calculated and performance of VCO is analysed with previous
work
6. Design a physical layout of proposed LC VCO with verification using DRC(Design Rule
Check) and LVS(layout versus schematics) techniques.

BLOCK DIAGRAMS:-
 Fig.1 Schematic Diagram Of Cross Coupled NMOS LC-VCO

Design Specification Layout

Design rule Check(DRC)

Schematic Capture

Extraction
Create Symbol

Layout versus Schematic Check

Simulation

Post Layout Simulation

Fig.2. Block Diagram Of Design Flow

Applications:-

References:-
1. Sherif A. Mohamed and Yiannos Manoli, “Design of Low-Power and Low-Phase
Noise VCO in Standard 0.13μm CMOS”, IEEE International Symposium on Circuits
and Systems (ISCAS), May 2015.
2. Gaurav Haramkar,Prof. Rohita P. Patil and Renuka Andankar,” A 2.4 GHZ FULLY
INTEGRATED LC VCO DESIGN USING 130 NM CMOS TECHNOLOGY”,
International Journal of Microelectronics Engineering (IJME), Vol.2, No.4, October
2016.

Name of Team Members:

1. Abhijeet Srivastava (1612231002)
2. Harshit Jain (1612231042)
3. Kshitiz Mishra (1612231054)